Update copyright years.

[thirdparty/gcc.git] / libgcc / config / nds32 / isr-library / save_partial.inc

diff --git a/libgcc/config/nds32/isr-library/save_partial.inc b/libgcc/config/nds32/isr-library/save_partial.inc
index 61df3966d1e09535cca7df70c547fac25555338c..c93341fb36f66602a4b47f796ff36ffb0cb954d1 100644 (file)
--- a/libgcc/config/nds32/isr-library/save_partial.inc
+++ b/libgcc/config/nds32/isr-library/save_partial.inc
@@ -1,5 +1,5 @@
 /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
-   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Copyright (C) 2012-2023 Free Software Foundation, Inc.
    Contributed by Andes Technology Corporation.
 
    This file is part of GCC.
@@ -23,20 +23,20 @@
    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    <http://www.gnu.org/licenses/>.  */
 
-.macro SAVE_PARTIAL_4B
-#ifdef __NDS32_REDUCED_REGS__
+#if __NDS32_ISR_VECTOR_SIZE_4__
+
+/* If vector size is 4-byte, we have to save registers
+   in the macro implementation.  */
+.macro SAVE_PARTIAL
+#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
        smw.adm $r15, [$sp], $r15, #0x2
-#else /* not __NDS32_REDUCED_REGS__ */
+#else
        smw.adm $r15, [$sp], $r27, #0x2
-#endif /* not __NDS32_REDUCED_REGS__ */
-       smw.adm $r0, [$sp], $r5, #0x0
-#ifdef NDS32_EXT_IFC
-       mfusr   $r1, $IFC_LP
-       smw.adm $r1, [$sp], $r2, #0x0   /* Save extra $r2 to keep
-                                          stack 8-byte alignment.  */
 #endif
-       SAVE_MAC_REGS
-       SAVE_FPU_REGS
+       smw.adm $r0, [$sp], $r5, #0x0
+  SAVE_USR_REGS
+  SAVE_MAC_REGS
+  SAVE_FPU_REGS
 #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
        mfsr    $r1, $IPC       /* Get IPC.  */
        mfsr    $r2, $IPSW      /* Get IPSW.  */
@@ -44,26 +44,24 @@
 #endif
        mfsr    $r0, $ITYPE     /* Get VID to $r0.  */
        srli    $r0, $r0, #5
-#ifdef __NDS32_ISA_V2__
        andi    $r0, $r0, #127
-#else
-       fexti33 $r0, #6
-#endif
 .endm
 
+#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
+
+/* If vector size is 16-byte, some works can be done in
+   the vector section generated by compiler, so that we
+   can implement less in the macro.  */
+
 .macro SAVE_PARTIAL
-/* SAVE_CALLER_REGS code has been moved to
-   vector table generated by compiler.  */
-#ifdef NDS32_EXT_IFC
-       mfusr   $r1, $IFC_LP
-       smw.adm $r1, [$sp], $r2, #0x0   /* Save extra $r2 to keep
-                                          stack 8-byte alignment.  */
-#endif
-       SAVE_MAC_REGS
-       SAVE_FPU_REGS
+  SAVE_USR_REGS
+  SAVE_MAC_REGS
+  SAVE_FPU_REGS
 #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
        mfsr    $r1, $IPC       /* Get IPC.  */
        mfsr    $r2, $IPSW      /* Get IPSW.  */
        smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
 #endif
 .endm
+
+#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */