Update copyright dates with scripts/update-copyrights.

[thirdparty/glibc.git] / sysdeps / powerpc / fpu_control.h

diff --git a/sysdeps/powerpc/fpu_control.h b/sysdeps/powerpc/fpu_control.h
index 159543beed27116be2d512ab6fe3bcaeba2cafe7..8f40b1ae798efca3093c6e24dd1c49f7380e88fe 100644 (file)
--- a/sysdeps/powerpc/fpu_control.h
+++ b/sysdeps/powerpc/fpu_control.h
@@ -1,5 +1,5 @@
 /* FPU control word definitions.  PowerPC version.
-   Copyright (C) 1996-2013 Free Software Foundation, Inc.
+   Copyright (C) 1996-2020 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -14,12 +14,16 @@
 
    You should have received a copy of the GNU Lesser General Public
    License along with the GNU C Library; if not, see
-   <http://www.gnu.org/licenses/>.  */
+   <https://www.gnu.org/licenses/>.  */
 
 #ifndef _FPU_CONTROL_H
 #define _FPU_CONTROL_H
 
-#if defined _SOFT_FLOAT || defined __NO_FPRS__
+#if defined __SPE__ || (defined __NO_FPRS__ && !defined _SOFT_FLOAT)
+# error "SPE/e500 is no longer supported"
+#endif
+
+#ifdef _SOFT_FLOAT
 
 # define _FPU_RESERVED 0xffffffff
 # define _FPU_DEFAULT  0x00000000 /* Default value.  */
@@ -36,6 +40,8 @@ extern fpu_control_t __fpu_control;
 # define _FPU_RC_UP      0x02
 # define _FPU_RC_ZERO    0x01
 
+# define _FPU_MASK_RC (_FPU_RC_NEAREST|_FPU_RC_DOWN|_FPU_RC_UP|_FPU_RC_ZERO)
+
 # define _FPU_MASK_NI  0x04 /* non-ieee mode */
 
 /* masking of interrupts */
@@ -56,22 +62,49 @@ extern fpu_control_t __fpu_control;
 # define _FPU_IEEE     0x000000f0
 
 /* Type of the control word.  */
-typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
+typedef unsigned int fpu_control_t;
 
 /* Macros for accessing the hardware control word.  */
-# define _FPU_GETCW(__cw) ( { \
-  union { double d; fpu_control_t cw[2]; } \
-    tmp __attribute__ ((__aligned__(8))); \
-  __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
-  (__cw)=tmp.cw[1]; \
-  tmp.cw[1]; } )
-# define _FPU_SETCW(__cw) { \
-  union { double d; fpu_control_t cw[2]; } \
-    tmp __attribute__ ((__aligned__(8))); \
-  tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \
-  tmp.cw[1] = __cw; \
-  __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
-}
+# define _FPU_GETCW(cw)                                                \
+  ({union { double __d; unsigned long long __ll; } __u;                \
+    __asm__ __volatile__("mffs %0" : "=f" (__u.__d));          \
+    (cw) = (fpu_control_t) __u.__ll;                           \
+    (fpu_control_t) __u.__ll;                                  \
+  })
+
+# define _FPU_GET_RC_ISA300()                                          \
+  ({union { double __d; unsigned long long __ll; } __u;                        \
+    __asm__ __volatile__(                                              \
+      ".machine push; .machine \"power9\"; mffsl %0; .machine pop"     \
+      : "=f" (__u.__d));                                               \
+    (fpu_control_t) (__u.__ll & _FPU_MASK_RC);                         \
+  })
+
+# ifdef _ARCH_PWR9
+#  define _FPU_GET_RC() _FPU_GET_RC_ISA300()
+# elif defined __BUILTIN_CPU_SUPPORTS__
+#  define _FPU_GET_RC()                                                        \
+  ({fpu_control_t __rc;                                                        \
+    __rc = __glibc_likely (__builtin_cpu_supports ("arch_3_00"))       \
+      ? _FPU_GET_RC_ISA300 ()                                          \
+      : _FPU_GETCW (__rc) & _FPU_MASK_RC;                              \
+    __rc;                                                              \
+  })
+# else
+#  define _FPU_GET_RC()                                                \
+  ({fpu_control_t __rc = _FPU_GETCW (__rc) & _FPU_MASK_RC;     \
+    __rc;                                                      \
+  })
+# endif
+
+# define _FPU_SETCW(cw)                                                \
+  { union { double __d; unsigned long long __ll; } __u;                \
+    register double __fr;                                      \
+    __u.__ll = 0xfff80000LL << 32; /* This is a QNaN.  */      \
+    __u.__ll |= (cw) & 0xffffffffLL;                           \
+    __fr = __u.__d;                                            \
+    __asm__ __volatile__("mtfsf 255,%0" : : "f" (__fr));       \
+  }
 
 /* Default control word set at startup.  */
 extern fpu_control_t __fpu_control;