(CFLAGS-tst-align.c): Add -mpreferred-stack-boundary=4.

[thirdparty/glibc.git] / sysdeps / powerpc / powerpc32 / bits / atomic.h

diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h
index 6fcc669fb1f97e7c7a5d0ad841fb2833e4f3f261..0f1a72335f34fdd1ec4054414a7260a8f118eb5e 100644 (file)
--- a/sysdeps/powerpc/powerpc32/bits/atomic.h
+++ b/sysdeps/powerpc/powerpc32/bits/atomic.h
@@ -89,27 +89,12 @@
 # define __arch_atomic_decrement_if_positive_64(mem) \
     ({ abort (); (*mem)--; })
 
-#ifdef _ARCH_PWR4
-/*
- * Newer powerpc64 processors support the new "light weight" sync (lwsync)
- * So if the build is using -mcpu=[power4,power5,power5+,970] we can
- * safely use lwsync.
- */
-# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
-/*
- * "light weight" sync can also be used for the release barrier.
- */
-# ifndef UP
-#  define __ARCH_REL_INSTR     "lwsync"
-# endif
-#else
 /*
  * Older powerpc32 processors don't support the new "light weight"
  * sync (lwsync).  So the only safe option is to use normal sync
  * for all powerpc32 applications.
  */
 # define atomic_read_barrier() __asm ("sync" ::: "memory")
-#endif
 
 /*
  * Include the rest of the atomic ops macros which are common to both