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armv8/ls2080ardb: Update DDR timing to support more UDIMMs
authorShengzhou Liu <Shengzhou.Liu@nxp.com>
Thu, 7 Apr 2016 06:41:30 +0000 (14:41 +0800)
committerYork Sun <york.sun@nxp.com>
Tue, 17 May 2016 16:26:59 +0000 (09:26 -0700)
commitaa7a2226b5a7829915d189d727ee9320dc3a198b
tree8df0a56bc5c981aa458339daf53571ca86adbd29tree | snapshot
parent5fc62fe57097e195a8047859cd3c278a5d6790b6commit | diff
armv8/ls2080ardb: Update DDR timing to support more UDIMMs

Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.

Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
 - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
 - Apacer UDIMM: 78.C1GM4.AF10B
 - Transcend UDIMM: TS1GLH72V1H

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
board/freescale/ls2080ardb/ddr.h diff | blob | blame | history
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