}
#endif /* CONFIG_MISC_INIT_R */
+#if defined(CONFIG_BFIN_MAC)
+
+extern int bfin_EMAC_initialize(bd_t *bis);
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
#ifdef CONFIG_POST
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
return val;
}
+
+extern int uli526x_initialize(bd_t *);
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_ULI526)
+ uli526x_initialize(bis);
+#endif
+ return 0;
+}
{
pci_mpc824x_init(&hose);
}
+
+extern int skge_initialize(bd_t *bis);
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#if defined(CONFIG_SK98)
+ rc = skge_initialize(bis);
+#endif
+ return rc;
+}
+
U_BOOT_CMD(
bootp, 3, 1, do_bootp,
- "bootp\t- boot image via network using BootP/TFTP protocol\n",
- "[loadAddress] [bootfilename]\n"
+ "bootp\t- boot image via network using BOOTP/TFTP protocol\n",
+ "[loadAddress] [[hostIPaddr:]bootfilename]\n"
);
int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
rarpboot, 3, 1, do_rarpb,
"rarpboot- boot image via network using RARP/TFTP protocol\n",
- "[loadAddress] [bootfilename]\n"
+ "[loadAddress] [[hostIPaddr:]bootfilename]\n"
);
#if defined(CONFIG_CMD_DHCP)
U_BOOT_CMD(
dhcp, 3, 1, do_dhcp,
- "dhcp\t- invoke DHCP client to obtain IP/boot params\n",
- "\n"
+ "dhcp\t- boot image via network using DHCP/TFTP protocol\n",
+ "[loadAddress] [[hostIPaddr:]bootfilename]\n"
);
#endif
}
/* ------------------------------------------------------------------------- */
+
+extern int greth_initialize(bd_t *bis);
+
+#ifdef CONFIG_GRETH
+int cpu_eth_init(bd_t *bis)
+{
+ return greth_initialize(bis);
+}
+#endif
}
/* ------------------------------------------------------------------------- */
+extern int greth_initialize(bd_t *bis);
+
+#ifdef CONFIG_GRETH
+int cpu_eth_init(bd_t *bis)
+{
+ return greth_initialize(bis);
+}
+#endif
return (0);
}
#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
return 0;
};
#endif
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
+
return (0);
}
#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
return 0;
}
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
return (0);
}
#endif /* CONFIG_HW_WATCHDOG */
+
+#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcdmafec_initialize(bd_t *bis);
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSLDMAFEC)
+ mcdmafec_initialize(bis);
+#endif
+#if defined(CONFIG_MCFFEC)
+ mcffec_initialize(bis);
+#endif
+ return 0;
+}
+#endif
eth_register(dev);
- return 1;
+ return 0;
}
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
These changes are tested with DM9000{A,EP,E} together
with a 200MHz Atmel AT91SAM92161 core
-TODO: Homerun NIC and longrun NIC are not functional, only internal at the
- moment.
+TODO: external MII is not functional, only internal at the moment.
*/
#include <common.h>
/* Board/System/Debug information/definition ---------------- */
-#define DM9801_NOISE_FLOOR 0x08
-#define DM9802_NOISE_FLOOR 0x05
-
/* #define CONFIG_DM9000_DEBUG */
#ifdef CONFIG_DM9000_DEBUG
#define DM9000_DMP_PACKET(func,packet,length)
#endif
-enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
- 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
- 8, DM9000_1M_HPNA = 0x10
-};
-enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
-};
-
/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
u32 runt_length_counter; /* counter: RX length < 64byte */
u16 dbug_cnt;
u8 phy_addr;
u8 device_wait_reset; /* device state */
- u8 nic_type; /* NIC type */
unsigned char srom[128];
void (*outblk)(volatile void *data_ptr, int count);
void (*inblk)(void *data_ptr, int count);
} board_info_t;
static board_info_t dm9000_info;
-/* For module input parameter */
-static int media_mode = DM9000_AUTO;
-static u8 nfloor = 0;
-
/* function declaration ------------------------------------- */
int eth_init(bd_t * bd);
int eth_send(volatile void *, int);
}
}
-/* Set PHY operationg mode
-*/
-static void
-set_PHY_mode(void)
-{
- u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
- if (!(media_mode & DM9000_AUTO)) {
- switch (media_mode) {
- case DM9000_10MHD:
- phy_reg4 = 0x21;
- phy_reg0 = 0x0000;
- break;
- case DM9000_10MFD:
- phy_reg4 = 0x41;
- phy_reg0 = 0x1100;
- break;
- case DM9000_100MHD:
- phy_reg4 = 0x81;
- phy_reg0 = 0x2000;
- break;
- case DM9000_100MFD:
- phy_reg4 = 0x101;
- phy_reg0 = 0x3100;
- break;
- }
- phy_write(4, phy_reg4); /* Set PHY media mode */
- phy_write(0, phy_reg0); /* Tmp */
- }
- DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
- DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
-}
-
-/*
- Init HomeRun DM9801
-*/
-static void
-program_dm9801(u16 HPNA_rev)
-{
- __u16 reg16, reg17, reg24, reg25;
- if (!nfloor)
- nfloor = DM9801_NOISE_FLOOR;
- reg16 = phy_read(16);
- reg17 = phy_read(17);
- reg24 = phy_read(24);
- reg25 = phy_read(25);
- switch (HPNA_rev) {
- case 0xb900: /* DM9801 E3 */
- reg16 |= 0x1000;
- reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
- break;
- case 0xb901: /* DM9801 E4 */
- reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
- reg17 = (reg17 & 0xfff0) + nfloor + 3;
- break;
- case 0xb902: /* DM9801 E5 */
- case 0xb903: /* DM9801 E6 */
- default:
- reg16 |= 0x1000;
- reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
- reg17 = (reg17 & 0xfff0) + nfloor;
- }
- phy_write(16, reg16);
- phy_write(17, reg17);
- phy_write(25, reg25);
-}
-
-/*
- Init LongRun DM9802
-*/
-static void
-program_dm9802(void)
-{
- __u16 reg25;
- if (!nfloor)
- nfloor = DM9802_NOISE_FLOOR;
- reg25 = phy_read(25);
- reg25 = (reg25 & 0xff00) + nfloor;
- phy_write(25, reg25);
-}
-
-/* Identify NIC type
-*/
-static void
-identify_nic(void)
-{
- struct board_info *db = &dm9000_info;
- u16 phy_reg3;
- DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
- phy_reg3 = phy_read(3);
- switch (phy_reg3 & 0xfff0) {
- case 0xb900:
- if (phy_read(31) == 0x4404) {
- db->nic_type = HOMERUN_NIC;
- program_dm9801(phy_reg3);
- DM9000_DBG("found homerun NIC\n");
- } else {
- db->nic_type = LONGRUN_NIC;
- DM9000_DBG("found longrun NIC\n");
- program_dm9802();
- }
- break;
- default:
- db->nic_type = FASTETHER_NIC;
- break;
- }
- DM9000_iow(DM9000_NCR, 0);
-}
-
/* General Purpose dm9000 reset routine */
static void
dm9000_reset(void)
/* Reset DM9000,
see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
- /* DEBUG: Make all GPIO pins outputs */
- DM9000_iow(DM9000_GPCR, 0x0F);
+ /* DEBUG: Make all GPIO0 outputs, all others inputs */
+ DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
DM9000_iow(DM9000_GPR, 0);
/* Step 2: Software reset */
- DM9000_iow(DM9000_NCR, 3);
+ DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
do {
DM9000_DBG("resetting the DM9000, 1st reset\n");
} while (DM9000_ior(DM9000_NCR) & 1);
DM9000_iow(DM9000_NCR, 0);
- DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */
+ DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
do {
DM9000_DBG("resetting the DM9000, 2nd reset\n");
/* RESET device */
dm9000_reset();
- dm9000_probe();
+
+ if (dm9000_probe() < 0)
+ return -1;
/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
io_mode = DM9000_ior(DM9000_ISR) >> 6;
break;
}
- /* NIC Type: FASTETHER, HOMERUN, LONGRUN */
- identify_nic();
-
- /* GPIO0 on pre-activate PHY */
- DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
-
- /* Set PHY */
- set_PHY_mode();
-
- /* Program operating register, only intern phy supported by now */
+ /* Program operating register, only internal phy supported */
DM9000_iow(DM9000_NCR, 0x0);
/* TX Polling clear */
DM9000_iow(DM9000_TCR, 0);
/* Less 3Kb, 200us */
- DM9000_iow(DM9000_BPTR, 0x3f);
+ DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
/* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
/* SH FIXME: This looks strange! Flow Control */
/* clear TX status */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
/* Clear interrupt status */
- DM9000_iow(DM9000_ISR, 0x0f);
+ DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
/* Set Node address */
-#ifndef CONFIG_AT91SAM9261EK
+#if !defined(CONFIG_AT91SAM9261EK)
for (i = 0; i < 6; i++)
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
#endif
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
- for (i = 0, oft = 0x10; i < 6; i++, oft++)
+
+ /* fill device MAC address registers */
+ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
DM9000_iow(oft, bd->bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
#define NCR_FCOL (1<<4)
#define NCR_FDX (1<<3)
#define NCR_LBK (3<<1)
+#define NCR_LBK_INT_MAC (1<<1)
+#define NCR_LBK_INT_PHY (2<<1)
#define NCR_RST (1<<0)
#define NSR_SPEED (1<<7)
#define RSR_CE (1<<1)
#define RSR_FOE (1<<0)
+#define EPCR_EPOS_PHY (1<<3)
+#define EPCR_EPOS_EE (0<<3)
+#define EPCR_ERPRR (1<<2)
+#define EPCR_ERPRW (1<<1)
+#define EPCR_ERRE (1<<0)
+
#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
#define FCTR_LWOT(ot) ( ot & 0xf )
+#define BPTR_BPHW(x) ((x) << 4)
+#define BPTR_JPT_200US (0x07)
+#define BPTR_JPT_600US (0x0f)
+
#define IMR_PAR (1<<7)
#define IMR_ROOM (1<<3)
#define IMR_ROM (1<<2)
#define IMR_PTM (1<<1)
#define IMR_PRM (1<<0)
+#define ISR_ROOS (1<<3)
+#define ISR_ROS (1<<2)
+#define ISR_PTS (1<<1)
+#define ISR_PRS (1<<0)
+
+#define GPCR_GPIO0_OUT (1<<0)
+
+#define GPR_PHY_PWROFF (1<<0)
+
#endif
0, /* phy name */
0, /* phy name init */
#ifdef CFG_DMA_USE_INTSRAM
- DBUF_LENGTH, /* RX BD */
+ (cbd_t *)DBUF_LENGTH, /* RX BD */
#else
0, /* RX BD */
#endif
/* setup Receive and Transmit buffer descriptor */
#ifdef CFG_DMA_USE_INTSRAM
- fec_info[i].rxbd = (int)fec_info[i].rxbd + tmp;
- tmp = fec_info[i].rxbd;
+ fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
+ tmp = (u32)fec_info[i].rxbd;
fec_info[i].txbd =
- (int)fec_info[i].txbd + tmp + (PKTBUFSRX * sizeof(cbd_t));
- tmp = fec_info[i].txbd;
+ (cbd_t *)((u32)fec_info[i].txbd + tmp +
+ (PKTBUFSRX * sizeof(cbd_t)));
+ tmp = (u32)fec_info[i].txbd;
fec_info[i].txbuf =
- (int)fec_info[i].txbuf + tmp +
- (CFG_TX_ETH_BUFFER * sizeof(cbd_t));
- tmp = fec_info[i].txbuf;
+ (char *)((u32)fec_info[i].txbuf + tmp +
+ (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
+ tmp = (u32)fec_info[i].txbuf;
#else
fec_info[i].rxbd =
(cbd_t *) memalign(CFG_CACHELINE_SIZE,
/* default speed */
bis->bi_ethspeed = 10;
- return 1;
+ return 0;
}
/* set and remember MAC address */
greth_set_hwaddr(greth, addr);
- return 1;
+ return 0;
}
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
+ (struct fec_info_s *)-1,
},
#endif
#ifdef CFG_FEC1_IOBASE
0, /* duplex and speed */
0, /* phy name */
0, /* phy name init */
+#ifdef CFG_FEC_BUF_USE_SRAM
+ (cbd_t *)DBUF_LENGTH, /* RX BD */
+#else
0, /* RX BD */
+#endif
0, /* TX BD */
0, /* rx Index */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
+ (struct fec_info_s *)-1,
}
#endif
};
/* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */
- /* FEC fix for MCF5275, FEC unable to initial transmit data packet.
+#ifndef CFG_FEC_BUF_USE_SRAM
+ /*
+ * FEC unable to initial transmit data packet.
* A nop will ensure the descriptor polling active completed.
+ * CF Internal RAM has shorter cycle access than DRAM. If use
+ * DRAM as Buffer descriptor and data, a nop is a must.
+ * Affect only V2 and V3.
*/
-#ifdef CONFIG_M5275
__asm__ ("nop");
+
#endif
#ifdef CFG_UNIFY_CACHE
icache_invalid();
#endif
+
j = 0;
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) {
int length;
for (;;) {
+#ifndef CFG_FEC_BUF_USE_SRAM
+#endif
#ifdef CFG_UNIFY_CACHE
icache_invalid();
#endif
{
struct eth_device *dev;
int i;
+#ifdef CFG_FEC_BUF_USE_SRAM
+ u32 tmp = CFG_INIT_RAM_ADDR + 0x1000;
+#endif
for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
dev->recv = fec_recv;
/* setup Receive and Transmit buffer descriptor */
+#ifdef CFG_FEC_BUF_USE_SRAM
+ fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
+ tmp = (u32)fec_info[i].rxbd;
+ fec_info[i].txbd =
+ (cbd_t *)((u32)fec_info[i].txbd + tmp +
+ (PKTBUFSRX * sizeof(cbd_t)));
+ tmp = (u32)fec_info[i].txbd;
+ fec_info[i].txbuf =
+ (char *)((u32)fec_info[i].txbuf + tmp +
+ (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
+ tmp = (u32)fec_info[i].txbuf;
+#else
fec_info[i].rxbd =
(cbd_t *) memalign(CFG_CACHELINE_SIZE,
(PKTBUFSRX * sizeof(cbd_t)));
(TX_BUF_CNT * sizeof(cbd_t)));
fec_info[i].txbuf =
(char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+#endif
+
#ifdef ET_DEBUG
printf("rxbd %x txbd %x\n",
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
miiphy_register(dev->name,
mcffec_miiphy_read, mcffec_miiphy_write);
#endif
+ if (i > 0)
+ fec_info[i - 1].next = &fec_info[i];
}
+ fec_info[i - 1].next = &fec_info[0];
/* default speed */
bis->bi_ethspeed = 10;
- return 1;
+ return 0;
}
LIB := $(obj)libsk98lin.a
-COBJS-y += skge.o
-COBJS-y += skaddr.o
-COBJS-y += skgehwt.o
-COBJS-y += skgeinit.o
-COBJS-y += skgepnmi.o
-COBJS-y += skgesirq.o
-COBJS-y += ski2c.o
-COBJS-y += sklm80.o
-COBJS-y += skqueue.o
-COBJS-y += skrlmt.o
-COBJS-y += sktimer.o
-COBJS-y += skvpd.o
-COBJS-y += skxmac2.o
-COBJS-y += skcsum.o
+COBJS-$(CONFIG_SK98) += skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o \
+ skgesirq.o ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o \
+ skvpd.o skxmac2.o skcsum.o
#COBJS-y += skproc.o
-COBJS-y += uboot_skb.o
-COBJS-y += uboot_drv.o
+COBJS-$(CONFIG_SK98) += uboot_skb.o uboot_drv.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <config.h>
-#ifdef CONFIG_SK98
-
#ifndef lint
static const char SysKonnectFileId[] =
"@(#) $Id: skaddr.c,v 1.48 2003/02/12 17:09:37 tschilli Exp $ (C) SysKonnect.";
#ifdef __cplusplus
}
#endif /* __cplusplus */
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */
#ifndef lint
} /* SkCsEvent */
#endif /* SK_USE_CSUM */
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
#include "h/skversion.h"
#if 0
#include <linux/module.h>
} /* DumpLong */
#endif
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
Event queue and dispatcher
*/
pAC->Hwt.TStop = pAC->Hwt.TStart;
SkTimerDone(pAC,Ioc) ;
}
-
-#endif /* CONFIG_SK98 */
-
/* End of file */
#include <config.h>
-#ifdef CONFIG_SK98
-
#include "h/skdrv1st.h"
#include "h/skdrv2nd.h"
return(0);
} /* SkGeInitPort */
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
* PRIVATE OID handler function prototypes
*/
0,
SK_PNMI_RO, Vct, 0},
};
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
static const char SysKonnectFileId[] =
"@(#) $Id: skgepnmi.c,v 1.102 2002/12/16 14:03:24 tschilli Exp $"
" (C) SysKonnect.";
}
} /* CheckVctStatus */
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
* Special Interrupt handler
*
} /* SkPhyIsrLone */
#endif /* OTHER_PHY */
-#endif /* CONFIG_SK98 */
-
/* End of File */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
* I2C Protocol
*/
} /* SkI2cEvent*/
#endif /* !SK_DIAG */
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
LM80 functions
*/
/* Not completed */
return(0);
}
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
#include <linux/proc_fs.h>
#include "h/skdrv1st.h"
return strorg;
}
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
Event queue and dispatcher
*/
return(0) ;
}
-#endif /* CONFIG_SK98 */
-
/* End of file */
#include <config.h>
-#ifdef CONFIG_SK98
-
#ifndef lint
static const char SysKonnectFileId[] =
"@(#) $Id: skrlmt.c,v 1.68 2003/01/31 15:26:56 rschmidt Exp $ (C) SysKonnect.";
#ifdef __cplusplus
}
#endif /* __cplusplus */
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
Event queue and dispatcher
*/
}
}
-#endif /* CONFIG_SK98 */
-
/* End of file */
#include <config.h>
-#ifdef CONFIG_SK98
-
/*
Please refer skvpd.txt for infomation how to include this module
*/
(void)VpdUpdate(pAC, IoC);
}
-
-#endif /* CONFIG_SK98 */
#include <config.h>
-#ifdef CONFIG_SK98
-
#include "h/skdrv1st.h"
#include "h/skdrv2nd.h"
return(0);
} /* SkGmCableDiagStatus */
-#endif /* CONFIG_SK98 */
-
/* End of file */
#include <common.h>
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
- defined(CONFIG_SK98)
-
#include "h/skdrv1st.h"
#include "h/skdrv2nd.h"
#include "u-boot_compat.h"
eth_register(dev[i]);
}
- return numdev;
+ return ((numdev > 0) && (numdev <= SKGE_MAX_CARDS) ? 0 : -1);
}
return 0;
}
-
-
-#endif /* CONFIG_SK98 */
*/
#include <config.h>
-
-#ifdef CONFIG_SK98
-
#include <common.h>
#include "u-boot_compat.h"
{
skb->len+=len;
}
-
-#endif /* CONFIG_SK98 */
return;
}
break;
+ case BOUND:
+ /* DHCP client bound to address */
+ break;
default:
puts ("DHCP: INVALID STATE\n");
break;
extern char BootFile[128]; /* Boot file name */
extern int BootpTry;
#ifdef CONFIG_BOOTP_RANDOM_DELAY
-ulong seed1, seed2; /* seed for random BOOTP delay */
+extern ulong seed1, seed2; /* seed for random BOOTP delay */
#endif
extern int rtl8139_initialize(bd_t*);
extern int rtl8169_initialize(bd_t*);
extern int scc_initialize(bd_t*);
-extern int skge_initialize(bd_t*);
extern int tsi108_eth_initialize(bd_t*);
-extern int uli526x_initialize(bd_t *);
extern int npe_initialize(bd_t *);
extern int uec_initialize(int);
-extern int bfin_EMAC_initialize(bd_t *);
-extern int greth_initialize(bd_t *);
-extern int mcffec_initialize(bd_t*);
-extern int mcdmafec_initialize(bd_t*);
extern int at91sam9_eth_initialize(bd_t *);
#ifdef CONFIG_API
#if defined(CONFIG_MPC8220_FEC)
mpc8220_fec_initialize(bis);
#endif
-#if defined(CONFIG_SK98)
- skge_initialize(bis);
-#endif
#if defined(CONFIG_UEC_ETH1)
uec_initialize(0);
#endif
#if defined(CONFIG_TSI108_ETH)
tsi108_eth_initialize(bis);
#endif
-#if defined(CONFIG_ULI526X)
- uli526x_initialize(bis);
-#endif
#if defined(CONFIG_RTL8139)
rtl8139_initialize(bis);
#endif
#if defined(CONFIG_RTL8169)
rtl8169_initialize(bis);
#endif
-#if defined(CONFIG_BF537)
- bfin_EMAC_initialize(bis);
-#endif
-#if defined(CONFIG_GRETH)
- greth_initialize(bis);
-#endif
-#if defined(CONFIG_MCFFEC)
- mcffec_initialize(bis);
-#endif
-#if defined(CONFIG_FSLDMAFEC)
- mcdmafec_initialize(bis);
-#endif
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263)
at91sam9_eth_initialize(bis);