]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
net: add ICPlus PHY driver
authorYegor Yefremov <yegorslists@googlemail.com>
Wed, 28 Nov 2012 10:15:18 +0000 (11:15 +0100)
committerJoe Hershberger <joe.hershberger@ni.com>
Tue, 25 Jun 2013 00:07:32 +0000 (19:07 -0500)
The driver code was taken from Linux kernel source:
drivers/net/phy/icplus.c

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
drivers/net/phy/Makefile
drivers/net/phy/icplus.c [new file with mode: 0644]
drivers/net/phy/phy.c

index af5f4b848ceefb14d535b5c79084bbfaf49ec89c..695873eaa451fee9975cade6a9abf1a2f28501a0 100644 (file)
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
 COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
 COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
 COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
+COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o
 COBJS-$(CONFIG_PHY_LXT) += lxt.o
 COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
 COBJS-$(CONFIG_PHY_MICREL) += micrel.o
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
new file mode 100644 (file)
index 0000000..dd5c592
--- /dev/null
@@ -0,0 +1,94 @@
+/*
+ * ICPlus PHY drivers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ */
+#include <phy.h>
+
+/* IP101A/G - IP1001 */
+#define IP10XX_SPEC_CTRL_STATUS         16      /* Spec. Control Register */
+#define IP1001_SPEC_CTRL_STATUS_2       20      /* IP1001 Spec. Control Reg 2 */
+#define IP1001_PHASE_SEL_MASK           3       /* IP1001 RX/TXPHASE_SEL */
+#define IP1001_APS_ON                   11      /* IP1001 APS Mode  bit */
+#define IP101A_G_APS_ON                 2       /* IP101A/G APS Mode bit */
+#define IP101A_G_IRQ_CONF_STATUS        0x11    /* Conf Info IRQ & Status Reg */
+#define IP101A_G_IRQ_PIN_USED           (1<<15) /* INTR pin used */
+#define IP101A_G_IRQ_DEFAULT            IP101A_G_IRQ_PIN_USED
+
+static int ip1001_config(struct phy_device *phydev)
+{
+       int c;
+
+       /* Enable Auto Power Saving mode */
+       c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
+       if (c < 0)
+               return c;
+       c |= IP1001_APS_ON;
+       c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
+       if (c < 0)
+               return c;
+
+       /* INTR pin used: speed/link/duplex will cause an interrupt */
+       c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
+                     IP101A_G_IRQ_DEFAULT);
+       if (c < 0)
+               return c;
+
+       if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
+               /*
+                * Additional delay (2ns) used to adjust RX clock phase
+                * at RGMII interface
+                */
+               c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
+               if (c < 0)
+                       return c;
+
+               c |= IP1001_PHASE_SEL_MASK;
+               c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
+                             c);
+               if (c < 0)
+                       return c;
+       }
+
+       return 0;
+}
+
+static int ip1001_startup(struct phy_device *phydev)
+{
+       genphy_update_link(phydev);
+       genphy_parse_link(phydev);
+
+       return 0;
+}
+static struct phy_driver IP1001_driver = {
+       .name = "ICPlus IP1001",
+       .uid = 0x02430d90,
+       .mask = 0x0ffffff0,
+       .features = PHY_GBIT_FEATURES,
+       .config = &ip1001_config,
+       .startup = &ip1001_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+int phy_icplus_init(void)
+{
+       phy_register(&IP1001_driver);
+
+       return 0;
+}
index 8f4c0c6bc55fc07784c07480a0588b173c4146fc..77d19c645df2afa3edcb5d2fdb02e2eac1bb47d9 100644 (file)
@@ -433,6 +433,9 @@ int phy_init(void)
 #ifdef CONFIG_PHY_ET1011C
        phy_et1011c_init();
 #endif
+#ifdef CONFIG_PHY_ICPLUS
+       phy_icplus_init();
+#endif
 #ifdef CONFIG_PHY_LXT
        phy_lxt_init();
 #endif