]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
authorTom Rini <trini@konsulko.com>
Thu, 9 Nov 2017 13:11:30 +0000 (08:11 -0500)
committerTom Rini <trini@konsulko.com>
Thu, 9 Nov 2017 13:11:30 +0000 (08:11 -0500)
20 files changed:
arch/arm/dts/rk3368-lion.dts
arch/arm/dts/rk3399-firefly.dts
arch/arm/dts/rk3399-puma.dtsi
common/spl/Kconfig
configs/evb-rk3399_defconfig
configs/firefly-rk3399_defconfig
doc/README.rockchip
include/configs/evb_rk3229.h
include/configs/kylin_rk3036.h
include/configs/lion_rk3368.h
include/configs/puma_rk3399.h
include/configs/rk3036_common.h
include/configs/rk3188_common.h
include/configs/rk322x_common.h
include/configs/rk3288_common.h
include/configs/rk3328_common.h
include/configs/rk3399_common.h
include/configs/rock.h
include/configs/rockchip-common.h
include/configs/sheep_rk3368.h

index 850db500e4e4be623499b5b420898ec3bb1aab33..f018b8b146368984ea38b0214442cbe2e175eff6 100644 (file)
@@ -68,7 +68,7 @@
        phy-supply = <&vcc33_io>;
        phy-mode = "rgmii";
        clock_in_out = "input";
-       snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+       snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        snps,reset-delays-us = <2 10000 50000>;
        assigned-clocks = <&cru SCLK_MAC>;
index 31e3ba8a4742bb4fb862859e3808288016f42aa4..f134c006889e686163db9d67d71ceaf063d6792a 100644 (file)
                                regulator-always-on;
                                regulator-boot-on;
                                regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-max-microvolt = <3000000>;
                                regulator-state-mem {
                                        regulator-on-in-suspend;
-                                       regulator-suspend-microvolt = <3300000>;
+                                       regulator-suspend-microvolt = <3000000>;
                                };
                        };
 
index 65ab3801391b50a238e196248db1eecbf0fbbf8b..96bd4fec01d1734560b779324f4a79e492592bb2 100644 (file)
 
                module_led {
                        label = "module_led";
-                       gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+                       gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
 
                sd_card_led {
                        label = "sd_card_led";
-                       gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                       gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
                };
        };
@@ -94,8 +94,7 @@
                compatible = "regulator-fixed";
                regulator-name = "usbhub_enable";
                enable-active-low;
-               gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
-               regulator-always-on;
+               gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
                regulator-boot-on;
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                compatible = "regulator-fixed";
                u-boot,dm-pre-reloc;
                regulator-name = "bios_enable";
-               enable-active-low;
-               gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
                regulator-always-on;
                regulator-boot-on;
                regulator-min-microvolt = <1800000>;
        vcc5v0_otg: vcc5v0-otg-regulator {
                compatible = "regulator-fixed";
                enable-active-high;
-               gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+               gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&otg_vbus_drv>;
                regulator-name = "vcc5v0_otg";
        vcc5v0_host: vcc5v0-host-regulator {
                compatible = "regulator-fixed";
                enable-active-low;
-               gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+               gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&host_vbus_drv>;
                regulator-name = "vcc5v0_host";
        phy-supply = <&vcc_phy>;
        phy-mode = "rgmii";
        clock_in_out = "input";
-       snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
+       snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        snps,reset-delays-us = <2 10000 50000>;
        assigned-clocks = <&cru SCLK_RMII_SRC>;
        vdd_gpu: fan535555@60 {
                compatible = "fcs,fan53555";
                reg = <0x60>;
-               vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+               vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
                vin-supply = <&vcc5v0_sys>;
                regulator-compatible = "fan53555-reg";
                regulator-name = "vdd_gpu";
                                regulator-always-on;
                                regulator-boot-on;
                                regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-max-microvolt = <3000000>;
                                regulator-name = "vcc_sd";
                                regulator-state-mem {
                                        regulator-on-in-suspend;
-                                       regulator-suspend-microvolt = <3300000>;
+                                       regulator-suspend-microvolt = <3000000>;
                                };
                        };
 
        vdd_cpu_b: fan53555@60 {
                compatible = "fcs,fan53555";
                reg = <0x60>;
-               vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+               vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
                vin-supply = <&vcc5v0_sys>;
                regulator-compatible = "fan53555-reg";
                regulator-name = "vdd_cpu_b";
        assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
        assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
        assigned-clock-rates = <100000000>;
-       ep-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+       ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
        num-lanes = <4>;
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_clkreqn>;
 };
 
 &usb_host0_ehci {
-       status = "okay";
+       status = "disabled";
 };
 
 &usb_host0_ohci {
-       status = "okay";
+       status = "disabled";
 };
 
 &dwc3_typec0 {
-       status = "disabled";
+       status = "okay";
 };
 
 &usb_host1_ehci {
-       status = "okay";
+       status = "disabled";
 };
 
 &usb_host1_ohci {
-       status = "okay";
+       status = "disabled";
 };
 
 &dwc3_typec1 {
                puma_pin_hog: puma_pin_hog {
                        rockchip,pins =
                                /* We need pull-ups on Q7 buttons */
-                               <0  4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
-                               <0 10 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
-                               <0 11 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
-                               <0  9 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
+                               <RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
+                               <RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
+                               <RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
+                               <RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
                };
        };
 
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins =
-                               <1 22 RK_FUNC_GPIO &pcfg_pull_up>;
+                               <RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        leds_pins_puma: led_pins@0 {
                        rockchip,pins =
-                               <2 25 RK_FUNC_GPIO &pcfg_pull_none>,
-                               <2 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
+                               <RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
        };
 
        usb2 {
                otg_vbus_drv: otg-vbus-drv {
                        rockchip,pins =
-                               <2 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                host_vbus_drv: host-vbus-drv {
                        rockchip,pins =
-                               <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        i2c8 {
                i2c8_xfer_a: i2c8-xfer {
-                       rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>,
-                                       <1 20 RK_FUNC_1 &pcfg_pull_up>;
+                       rockchip,pins =
+                               <RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
+                               <RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
                };
        };
 };
 &i2c6_xfer {
        /* Enable pull-ups, the pins would float otherwise. */
        rockchip,pins =
-               <2 10 RK_FUNC_2 &pcfg_pull_up>,
-               <2 9 RK_FUNC_2 &pcfg_pull_up>;
+               <RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
+               <RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
 };
 
 &i2c7 {
index 0bd8370337bcc5bd5d7d551abee2c49880535a76..e987c07f5a7c1f0254f389bf77867fda45cfc418 100644 (file)
@@ -142,11 +142,12 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
        default 0x50 if ARCH_SUNXI
        default 0x75 if ARCH_DAVINCI
        default 0x8a if ARCH_MX6
-       default 0x100 if ARCH_ROCKCHIP || ARCH_UNIPHIER
+       default 0x100 if ARCH_UNIPHIER
        default 0x140 if ARCH_MVEBU
        default 0x200 if ARCH_SOCFPGA || ARCH_AT91
        default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
                         OMAP54XX || AM33XX || AM43XX
+       default 0x4000 if ARCH_ROCKCHIP
        help
          Address on the MMC to load U-Boot from, when the MMC is being used
          in raw mode. Units: MMC sectors (1 sector = 512 bytes).
index 42df743cbe2469e835cf8b4c18e7f86c5a29c9dd..7b5ea821f9027186c4fcd1e7e64c2c92d1323cbe 100644 (file)
@@ -12,7 +12,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
index 262048843fcf2c938207a8046f1a3aad9892f506..dc3cda4260c4b97a6550314711e9f0372471d465 100644 (file)
@@ -12,7 +12,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF_SUPPORT=y
 CONFIG_SPL_ATF_TEXT_BASE=0x00010000
 CONFIG_CMD_BOOTZ=y
index 4b7be0b715212bb122b929d4be8ddd9d34db7d89..9d5af3d53d0aebcb8b810fa60657a21a92433c34 100644 (file)
@@ -99,13 +99,13 @@ To write an image that boots from an SD card (assumed to be /dev/sdc):
    ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
        firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
    sudo dd if=out of=/dev/sdc seek=64 && \
-   sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256
+   sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=16384
 
 This puts the Rockchip header and SPL image first and then places the U-Boot
-image at block 256 (i.e. 128KB from the start of the SD card). This
+image at block 16384 (i.e. 4MB from the start of the SD card). This
 corresponds with this setting in U-Boot:
 
-   #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR     256
+   #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR     0x4000
 
 Put this SD (or micro-SD) card into your board and reset it. You should see
 something like:
index 8906c8f0b1a7cc9b4b2a129b82da8dc91ce2bc94..ae981f7610dc4159452662bc25c86a58740407a9 100644 (file)
@@ -11,8 +11,6 @@
 
 
 /* Store env in emmc */
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE                 (32 << 10)
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_SYS_MMC_ENV_PART         0
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
index 36009b8599e5c32decfd1045a89573e55cf47513..d2d630d6107f7dd5c6609d6f6615358a7f98ff8b 100644 (file)
@@ -13,8 +13,6 @@
 #ifndef CONFIG_SPL_BUILD
 
 /* Store env in emmc */
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE                        SZ_32K
 #define CONFIG_SYS_MMC_ENV_DEV         0 /* emmc */
 #define CONFIG_SYS_MMC_ENV_PART                0 /* user area */
 
index 4118ffd65b41d16742524f4aed3d31387710df6d..c40dbadc151cb18beee5b640c49dab3a27373b19 100644 (file)
@@ -13,6 +13,5 @@
 #define KERNEL_LOAD_ADDR               0x280000
 #define DTB_LOAD_ADDR                  0x5600000
 #define INITRD_LOAD_ADDR               0x5bf0000
-#define CONFIG_ENV_SIZE                        0x2000
 
 #endif
index e481a28ae953995a83bbf94bce72bd6d2befdcda..39d07862669ac773a2785e51d21a04b2d4e24b7e 100644 (file)
 #undef CONFIG_ENV_OFFSET
 #define CONFIG_ENV_OFFSET (240 * 1024)
 
+#if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV 1
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SECT_SIZE           (8 * 1024)
+#define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ  CONFIG_SF_DEFAULT_SPEED
+#endif
 
 #define SDRAM_BANK_SIZE                        (2UL << 30)
 
index 9ac0df57dedb4d51fa21359f8c3dee853d0478ff..4ed8f5a6c764f78b82b7628fd708b89d41df0053 100644 (file)
@@ -10,7 +10,6 @@
 #include "rockchip-common.h"
 
 #define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
index 5e462346be2aef20f6ef7b27e64e778396e4445d..cfa5364710234ba8dcb8eaaea34aadcd16da4761 100644 (file)
@@ -14,7 +14,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 
index fa9abc0a561dc87d0154ae28ccd8f4f67a48aed9..b22169d163a2f7a93a8547856573c3dc5021ac10 100644 (file)
@@ -10,7 +10,6 @@
 #include "rockchip-common.h"
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /*  64M */
index 34f255847a8c940c793a291c1da72e69795f9804..2b8f618f721be35aecf929123c456991933f2019 100644 (file)
@@ -12,7 +12,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 
index 9819b22ce23662f779a8faa843cd620536489ff1..af556323f89a4c1b4ef347ba5ba7edcc7dd1b6b8 100644 (file)
@@ -9,7 +9,6 @@
 
 #include "rockchip-common.h"
 
-#define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
index 1d7a87271c96791d462831bc27b9e229a6e114e1..561bfa73b664c26d56ae5b3e8d3ea53f712e6514 100644 (file)
@@ -10,7 +10,6 @@
 #include "rockchip-common.h"
 
 #define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
index 8d845d95e378262ba5e2dad2f4c1997ebef15432..468dfdbff9880f3b9d46010d8521adf95ffdf8ee 100644 (file)
 
 #define CONFIG_SYS_MMC_ENV_DEV 0
 
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-/* SPL @ 32k for 34k
- * u-boot directly after @ 68k for 400k or so
- * ENV @ 992k
- */
-#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
-#else
-/* SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
- */
-#define CONFIG_ENV_OFFSET (96 * 1024)
-#endif
-
 #endif
index 96b5fce46f24e7dbc02961b54502936cb3423216..35d948ae29f196897b6666ead7ece10682bab9da 100644 (file)
 
 #endif
 
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-/* SPL @ 32k for 34k
- * u-boot directly after @ 68k for 400k or so
- * ENV @ 992k
- */
-#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
-#else
-/* SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
+/*
+ * Rockchip SoCs use fixed ENV 32KB@(4MB-32KB)
  */
-#define CONFIG_ENV_OFFSET (96 * 1024)
-#endif
+#define CONFIG_ENV_OFFSET      (SZ_4M - SZ_32K)
+#define CONFIG_ENV_SIZE                SZ_32K
 
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
index eac9755bbad6fef9e90279d07ec9e5b06ba0e586..4eb4fb0e2fa6f590ce96ecfcf212be075aeaff02 100644 (file)
@@ -13,7 +13,6 @@
 #define KERNEL_LOAD_ADDR               0x280000
 #define DTB_LOAD_ADDR                  0x5600000
 #define INITRD_LOAD_ADDR               0x5bf0000
-#define CONFIG_ENV_SIZE                        0x2000
 
 #define CONFIG_CONSOLE_SCROLL_LINES    10