omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
+Eric Benard <eric@eukrea.com>
+
+ cpuat91 ARM920T
+ cpu9260 ARM926EJS (AT91SAM9260 SoC)
+ cpu9G20 ARM926EJS (AT91SAM9G20 SoC)
+
Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
+Simon Kagstrom <simon.kagstrom@netinsight.net>
+
+ openrd_base ARM926EJS (Kirkwood SoC)
+
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
omap1610inn \
omap5912osk \
omap730p2 \
+ openrd_base \
rd6281a \
sbc2410x \
scb9328 \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
- at91sam9g10ek \
+ at91sam9g10ek \
at91sam9g20ek \
at91sam9m10g45ek \
at91sam9rlek \
cmc_pu2 \
+ CPUAT91 \
+ CPU9260 \
+ CPU9G20 \
csb637 \
kb9202 \
meesc \
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+CPUAT91_RAM_config \
+CPUAT91_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
+ @$(MKCONFIG) -a cpuat91 arm arm920t cpuat91 eukrea at91rm9200
+
csb637_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
fi;
@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
+CPU9G20_128M_config \
+CPU9G20_config \
+CPU9260_128M_config \
+CPU9260_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
+ @$(MKCONFIG) -a cpu9260 arm arm926ejs cpu9260 eukrea at91
+
meesc_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
omap5912osk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk ti omap
+openrd_base_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
+
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
omap730p2_config \
#
TEXT_BASE = 0x00600000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000a00 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x0000002A # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000046 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E811 # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := openrd_base.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strength reduced
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+
+DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
+# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT: Enabled
+# bit15: 1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.c:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "openrd_base.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(OPENRD_OE_VAL_LOW,
+ OPENRD_OE_VAL_HIGH,
+ OPENRD_OE_LOW, OPENRD_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD, /* Alt UART1_TXD */
+ MPP14_SD_D0, /* Alt UART1_RXD */
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO, /* UART1 / SD sel */
+ MPP35_TDM_CH0_TX_QL,
+ MPP36_TDM_SPI_CS1,
+ MPP37_TDM_CH2_TX_QL,
+ MPP38_TDM_CH2_RX_QL,
+ MPP39_AUDIO_I2SBCLK,
+ MPP40_AUDIO_I2SDO,
+ MPP41_AUDIO_I2SLRC,
+ MPP42_AUDIO_I2SMCLK,
+ MPP43_AUDIO_I2SDI,
+ MPP44_AUDIO_EXTCLK,
+ MPP45_TDM_PCLK,
+ MPP46_TDM_FS,
+ MPP47_TDM_DRX,
+ MPP48_TDM_DTX,
+ MPP49_TDM_CH0_RX_QL,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config);
+
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __OPENRD_BASE_H
+#define __OPENRD_BASE_H
+
+#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
+#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
+#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __OPENRD_BASE_H */
#
TEXT_BASE = 0x00600000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000099 # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 1, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 0, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
#include <common.h>
#include <nand.h>
-#include <linux/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# (C) Copyright 2009
+# Eric Benard <eric@eukrea.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += led.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x21f00000
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void cpu9260_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+#if defined(CONFIG_CPU9G20)
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
+ AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_TDF_(3));
+#elif defined(CONFIG_CPU9260)
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_TDF_(2));
+#endif
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void cpu9260_macb_hw_init(void)
+{
+ unsigned long rstc;
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0D << 8)) |
+ AT91_RSTC_URSTEN);
+
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
+ ;
+
+ /* Restore NRST value */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (rstc) |
+ AT91_RSTC_URSTEN);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+ at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* arch number of the board */
+#if defined(CONFIG_CPU9G20)
+ gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
+#elif defined(CONFIG_CPU9260)
+ gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ cpu9260_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ cpu9260_macb_hw_init();
+#endif
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) !=
+ PHYS_SDRAM_SIZE)
+ return -1;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
+ STATUS_LED_OFF, STATUS_LED_OFF};
+
+void coloured_LED_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+ at91_set_gpio_output(CONFIG_BLUE_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 1);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+ at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+}
+
+void red_LED_off(void)
+{
+ at91_set_gpio_value(CONFIG_RED_LED, 1);
+ saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void green_LED_off(void)
+{
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
+}
+
+void yellow_LED_off(void)
+{
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
+}
+
+void blue_LED_off(void)
+{
+ at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+ saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
+}
+
+void red_LED_on(void)
+{
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void green_LED_on(void)
+{
+ at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
+}
+
+void yellow_LED_on(void)
+{
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
+}
+
+void blue_LED_on(void)
+{
+ at91_set_gpio_value(CONFIG_BLUE_LED, 0);
+ saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ if (STATUS_LED_BLUE == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
+ blue_LED_off();
+ else
+ blue_LED_on();
+ } else if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+ red_LED_off();
+ else
+ red_LED_on();
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+ green_LED_off();
+ else
+ green_LED_on();
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
+ yellow_LED_off();
+ else
+ yellow_LED_on();
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (STATUS_LED_BLUE == mask) {
+ if (STATUS_LED_ON == state)
+ blue_LED_on();
+ else
+ blue_LED_off();
+ } else if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == state)
+ red_LED_on();
+ else
+ red_LED_off();
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == state)
+ green_LED_on();
+ else
+ green_LED_off();
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == state)
+ yellow_LED_on();
+ else
+ yellow_LED_off();
+ }
+}
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de. <http://lists.denx.de/mailman/listinfo/u-boot>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := cpuat91.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x21F00000
--- /dev/null
+/*
+ * (C) Copyright 2006 Eukrea Electromatique <www.eukrea.com>
+ * Eric Benard <eric@eukrea.com>
+ * based on at91rm9200dk.c which is :
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <ks8721.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+ /* arch number of CPUAT91-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#if defined(CONFIG_DRIVER_ETHER)
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = ks8721_initphy;
+ p_phyops->IsPhyConnected = ks8721_isphyconnected;
+ p_phyops->GetLinkSpeed = ks8721_getlinkspeed;
+ p_phyops->AutoNegotiate = ks8721_autonegotiate;
+}
+
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
COBJS += dm9161.o
COBJS += ether.o
COBJS += i2c.o
+COBJS-$(CONFIG_KS8721_PHY) += ks8721.o
COBJS += lxt972.o
COBJS += reset.o
COBJS += spi.o
COBJS += timer.o
COBJS += usb.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Author : Eric Benard (Eukrea Electromatique)
+ * based on dm9161.c which is :
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <ks8721.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ * ks8721_isphyconnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * 1 - if id read successfully
+ * 0 - if error
+ */
+unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac)
+{
+ unsigned short id1, id2;
+
+ at91rm9200_EmacEnableMDIO(p_mac);
+ at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1);
+ at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2);
+ at91rm9200_EmacDisableMDIO(p_mac);
+
+ if ((id1 == (KS8721_PHYID_OUI >> 6)) &&
+ ((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) {
+ if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL)
+ printf("Micrel KS8721bL PHY detected : ");
+ else
+ printf("Unknown Micrel PHY detected : ");
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Name:
+ * ks8721_getlinkspeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * 1 - if link status set succesfully
+ * 0 - if link status not set
+ */
+unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac)
+{
+ unsigned short stat1;
+
+ if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1))
+ return 0;
+
+ if (!(stat1 & KS8721_LINK_STATUS)) {
+ /* link status up? */
+ printf("Link Down !\n");
+ return 0;
+ }
+
+ if (stat1 & KS8721_100BASE_TX_FD) {
+ /* set Emac for 100BaseTX and Full Duplex */
+ printf("100BT FD\n");
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return 1;
+ }
+
+ if (stat1 & KS8721_10BASE_T_FD) {
+ /* set MII for 10BaseT and Full Duplex */
+ printf("10BT FD\n");
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return 1;
+ }
+
+ if (stat1 & KS8721_100BASE_T4_HD) {
+ /* set MII for 100BaseTX and Half Duplex */
+ printf("100BT HD\n");
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ return 1;
+ }
+
+ if (stat1 & KS8721_10BASE_T_HD) {
+ /* set MII for 10BaseT and Half Duplex */
+ printf("10BT HD\n");
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Name:
+ * ks8721_initphy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * 1 - if link status set succesfully
+ * 0 - if link status not set
+ */
+unsigned char ks8721_initphy(AT91PS_EMAC p_mac)
+{
+ unsigned char ret = 1;
+ unsigned short intvalue;
+
+ at91rm9200_EmacEnableMDIO(p_mac);
+
+ /* Try another time */
+ if (!ks8721_getlinkspeed(p_mac))
+ ret = ks8721_getlinkspeed(p_mac);
+
+ /* Disable PHY Interrupts */
+ intvalue = 0;
+ at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue);
+ at91rm9200_EmacDisableMDIO(p_mac);
+
+ return ret;
+}
+
+/*
+ * Name:
+ * ks8721_autonegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * 1 - if link status set successfully
+ * 0 - if link status not set
+ */
+unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+ unsigned short phyanar;
+ unsigned short phyanalpar;
+
+ /* Set ks8721 control register */
+ if (!at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value))
+ return 0;
+
+ /* remove autonegotiation enable */
+ value &= ~KS8721_AUTONEG;
+ /* Electrically isolate PHY */
+ value |= KS8721_ISOLATE;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ /*
+ * Set the Auto_negotiation Advertisement Register
+ * MII advertising for Next page, 100BaseTxFD and HD,
+ * 10BaseTFD and HD, IEEE 802.3
+ */
+ phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX |
+ KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) {
+ return 0;
+ }
+ /* Read the Control Register */
+ if (!at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ /* Restart Auto_negotiation */
+ value |= KS8721_RESTART_AUTONEG;
+ value &= ~KS8721_ISOLATE;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ /* Check AutoNegotiate complete */
+ udelay(10000);
+ at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMSR, &value);
+ if (!(value & KS8721_AUTONEG_COMP))
+ return 0;
+
+ /* Get the AutoNeg Link partner base page */
+ if (!at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) {
+ return 0;
+ }
+
+ if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) {
+ /* Set MII for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return 1;
+ }
+
+ if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) {
+ /* Set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return 1;
+ }
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
+ || defined(CONFIG_AT91SAM9G20)
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
.word CONFIG_SYS_PIOC_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
+COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o
SOBJS = reset.o
--- /dev/null
+/*
+ * SoC-specific code for TMS320DM646x chips
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/arch/hardware.h>
+
+void davinci_enable_uart0(void)
+{
+ lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+ lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DAVINCI_I2C
+void davinci_enable_i2c(void)
+{
+ lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+}
+#endif
/* turn off L2 cache */
l2_cache_disable();
/* invalidate L2 cache also */
- v7_flush_dcache_all(get_device_type());
+ invalidate_dcache(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
LIB = $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
+SOBJS += cache.o
SOBJS += reset.o
COBJS += board.o
-COBJS += cache.o
COBJS += clock.o
COBJS += gpio.o
COBJS += mem.o
* Right now flushing at low MPU speed.
* Need to move after clock init
*/
- v7_flush_dcache_all(get_device_type());
+ invalidate_dcache(get_device_type());
#ifndef CONFIG_ICACHE_OFF
icache_enable();
#endif
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This file is based on and replaces the existing cache.c file
+ * The copyrights for the cache.c file are:
+ *
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap3.h>
+
+/*
+ * omap3 cache code
+ */
+
+.align 5
+.global invalidate_dcache
+.global l2_cache_enable
+.global l2_cache_disable
+
+/*
+ * invalidate_dcache()
+ *
+ * Invalidate the whole D-cache.
+ *
+ * Corrupted registers: r0-r5, r7, r9-r11
+ *
+ * - mm - mm_struct describing address space
+ */
+invalidate_dcache:
+ stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
+
+ mov r7, r0 @ take a backup of device type
+ cmp r0, #0x3 @ check if the device type is
+ @ GP
+ moveq r12, #0x1 @ set up to invalide L2
+smi: .word 0x01600070 @ Call SMI monitor (smieq)
+ cmp r7, #0x3 @ compare again in case its
+ @ lost
+ beq finished_inval @ if GP device, inval done
+ @ above
+
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ ands r3, r0, #0x7000000 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
+ beq finished_inval @ if loc is 0, then no need to
+ @ clean
+ mov r10, #0 @ start clean at cache level 0
+inval_loop1:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache
+ @ level
+ mov r1, r0, lsr r2 @ extract cache type bits from
+ @ clidr
+ and r1, r1, #7 @ mask of the bits for current
+ @ cache only
+ cmp r1, #2 @ see what cache we have at
+ @ this level
+ blt skip_inval @ skip if no cache, or just
+ @ i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level
+ @ in cssr
+ mov r2, #0 @ operand for mcr SBZ
+ mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
+ @ sych the new cssr&csidr,
+ @ with armv7 this is 'isb',
+ @ but we compile with armv5
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the
+ @ cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the
+ @ way size
+ clz r5, r4 @ find bit position of way
+ @ size increment
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the
+ @ index size
+inval_loop2:
+ mov r9, r4 @ create working copy of max
+ @ way size
+inval_loop3:
+ orr r11, r10, r9, lsl r5 @ factor way and cache number
+ @ into r11
+ orr r11, r11, r7, lsl r2 @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the way
+ bge inval_loop3
+ subs r7, r7, #1 @ decrement the index
+ bge inval_loop2
+skip_inval:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt inval_loop1
+finished_inval:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level
+ @ in cssr
+ mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
+ @ with armv7 this is 'isb',
+ @ but we compile with armv5
+
+ ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
+
+
+l2_cache_enable:
+ push {r0, r1, r2, lr}
+ @ ES2 onwards we can disable/enable L2 ourselves
+ bl get_cpu_rev
+ cmp r0, #CPU_3XX_ES20
+ blt l2_cache_disable_EARLIER_THAN_ES2
+ mrc 15, 0, r3, cr1, cr0, 1
+ orr r3, r3, #2
+ mcr 15, 0, r3, cr1, cr0, 1
+ b l2_cache_enable_END
+l2_cache_enable_EARLIER_THAN_ES2:
+ @ Save r0, r12 and restore them after usage
+ mov r3, ip
+ str r3, [sp, #4]
+ mov r3, r0
+ @
+ @ GP Device ROM code API usage here
+ @ r12 = AUXCR Write function and r0 value
+ @
+ mov ip, #3
+ mrc 15, 0, r0, cr1, cr0, 1
+ orr r0, r0, #2
+ @ SMI instruction to call ROM Code API
+ .word 0xe1600070
+ mov r0, r3
+ mov ip, r3
+ str r3, [sp, #4]
+l2_cache_enable_END:
+ pop {r1, r2, r3, pc}
+
+
+l2_cache_disable:
+ push {r0, r1, r2, lr}
+ @ ES2 onwards we can disable/enable L2 ourselves
+ bl get_cpu_rev
+ cmp r0, #CPU_3XX_ES20
+ blt l2_cache_disable_EARLIER_THAN_ES2
+ mrc 15, 0, r3, cr1, cr0, 1
+ bic r3, r3, #2
+ mcr 15, 0, r3, cr1, cr0, 1
+ b l2_cache_disable_END
+l2_cache_disable_EARLIER_THAN_ES2:
+ @ Save r0, r12 and restore them after usage
+ mov r3, ip
+ str r3, [sp, #4]
+ mov r3, r0
+ @
+ @ GP Device ROM code API usage here
+ @ r12 = AUXCR Write function and r0 value
+ @
+ mov ip, #3
+ mrc 15, 0, r0, cr1, cr0, 1
+ bic r0, r0, #2
+ @ SMI instruction to call ROM Code API
+ .word 0xe1600070
+ mov r0, r3
+ mov ip, r3
+ str r3, [sp, #4]
+l2_cache_disable_END:
+ pop {r1, r2, r3, pc}
+++ /dev/null
-/*
- * (C) Copyright 2008 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * omap3 L2 cache code
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/cache.h>
-
-void l2_cache_enable(void)
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() >= CPU_3XX_ES20) {
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- __asm__ __volatile__("orr r0, r0, #0x2");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
- }
-
-}
-
-void l2_cache_disable(void)
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() >= CPU_3XX_ES20) {
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- __asm__ __volatile__("bic r0, r0, #0x2");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
- }
-}
#endif
-/*
- * v7_flush_dcache_all()
- *
- * Flush the whole D-cache.
- *
- * Corrupted registers: r0-r5, r7, r9-r11
- *
- * - mm - mm_struct describing address space
- */
- .align 5
-.global v7_flush_dcache_all
-v7_flush_dcache_all:
- stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
-
- mov r7, r0 @ take a backup of device type
- cmp r0, #0x3 @ check if the device type is
- @ GP
- moveq r12, #0x1 @ set up to invalide L2
-smi: .word 0x01600070 @ Call SMI monitor (smieq)
- cmp r7, #0x3 @ compare again in case its
- @ lost
- beq finished_inval @ if GP device, inval done
- @ above
-
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- ands r3, r0, #0x7000000 @ extract loc from clidr
- mov r3, r3, lsr #23 @ left align loc bit field
- beq finished_inval @ if loc is 0, then no need to
- @ clean
- mov r10, #0 @ start clean at cache level 0
-inval_loop1:
- add r2, r10, r10, lsr #1 @ work out 3x current cache
- @ level
- mov r1, r0, lsr r2 @ extract cache type bits from
- @ clidr
- and r1, r1, #7 @ mask of the bits for current
- @ cache only
- cmp r1, #2 @ see what cache we have at
- @ this level
- blt skip_inval @ skip if no cache, or just
- @ i-cache
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level
- @ in cssr
- mov r2, #0 @ operand for mcr SBZ
- mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
- @ sych the new cssr&csidr,
- @ with armv7 this is 'isb',
- @ but we compile with armv5
- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
- and r2, r1, #7 @ extract the length of the
- @ cache lines
- add r2, r2, #4 @ add 4 (line length offset)
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 @ find maximum number on the
- @ way size
- clz r5, r4 @ find bit position of way
- @ size increment
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 @ extract max number of the
- @ index size
-inval_loop2:
- mov r9, r4 @ create working copy of max
- @ way size
-inval_loop3:
- orr r11, r10, r9, lsl r5 @ factor way and cache number
- @ into r11
- orr r11, r11, r7, lsl r2 @ factor index number into r11
- mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
- subs r9, r9, #1 @ decrement the way
- bge inval_loop3
- subs r7, r7, #1 @ decrement the index
- bge inval_loop2
-skip_inval:
- add r10, r10, #2 @ increment cache number
- cmp r3, r10
- bgt inval_loop1
-finished_inval:
- mov r10, #0 @ swith back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level
- @ in cssr
- mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
- @ with armv7 this is 'isb',
- @ but we compile with armv5
-
- ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
#define DAVINCI_MMC_SD0_BASE 0x01d11000
+#elif defined(CONFIG_SOC_DM646X)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
+
#endif
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
+#define DAVINCI_DM646X_LPSC_EMAC 14
+#define DAVINCI_DM646X_LPSC_UART0 26
+#define DAVINCI_DM646X_LPSC_I2C 31
+
void lpsc_on(unsigned int id);
void dsp_on(void);
* ES1 = rev 0
*
* ES2 onwards, the value maps to contents of IDCODE register [31:28].
+ *
+ * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
*/
#define CPU_3XX_ES10 0
#define CPU_3XX_ES20 1
void setup_auxcr(void);
void try_unlock_memory(void);
u32 get_boot_type(void);
-void v7_flush_dcache_all(u32);
+void invalidate_dcache(u32);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * Configuration settings for the Eukrea CPU9260 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_DISPLAY_CPUINFO 1
+
+#define AT91_MAIN_CLOCK 18432000
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1
+
+#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
+#define CONFIG_CPU9260 1
+#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
+#define CONFIG_CPU9G20 1
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_AT91SAM9G20 1
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_AT91SAM9260 1
+#else
+#error "Unknown board"
+#endif
+
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/* clocks */
+#if defined(CONFIG_CPU9G20)
+#define MASTER_PLL_DIV 0x01
+#define MASTER_PLL_MUL 0x2B
+#elif defined(CONFIG_CPU9260)
+#define MASTER_PLL_DIV 0x09
+#define MASTER_PLL_MUL 0x61
+#endif
+
+/* CKGR_MOR - enable main osc. */
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOSCEN | \
+ (255 << 8)) /* Main Oscillator Start-up Time */
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_OUT | \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_6 | \
+ AT91_PMC_PDIV_2)
+#define CONFIG_SYS_MCKR2_VAL \
+ CONFIG_SYS_MCKR1_VAL
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+#endif
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
+
+/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+ (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
+ AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1 0x287
+/* SDRAMC_CR - Configuration register*/
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_SDRC_CR_VAL_64MB \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_2 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* Write Recovery Delay */ \
+ (9 << 12) | /* Row Cycle Delay */ \
+ (3 << 16) | /* Row Precharge Delay */ \
+ (3 << 20) | /* Row to Column Delay */ \
+ (6 << 24) | /* Active to Precharge Delay */ \
+ (10 << 28)) /* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_CR_VAL_128MB \
+ (AT91_SDRAMC_NC_10 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_2 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* Write Recovery Delay */ \
+ (9 << 12) | /* Row Cycle Delay */ \
+ (3 << 16) | /* Row Precharge Delay */ \
+ (3 << 20) | /* Row to Column Delay */ \
+ (6 << 24) | /* Active to Precharge Delay */ \
+ (10 << 28)) /* Exit Self Refresh to Active Delay */
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_SDRC_CR_VAL_64MB \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_2 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (2 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (8 << 28)) /* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_CR_VAL_128MB \
+ (AT91_SDRAMC_NC_10 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_2 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (2 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (8 << 28)) /* Exit Self Refresh to Active Delay */
+#endif
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit */
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
+ AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(3))
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
+ AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(2))
+#endif
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+#define CONFIG_CMD_FAT 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
+#else
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
+#endif
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+
+/* NOR flash */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_2 0x12000000
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ { PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_RESET_PHY_R 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY 1
+
+/* LEDS */
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_RED 0
+#define STATUS_LED_GREEN 1
+#define STATUS_LED_YELLOW 2
+#define STATUS_LED_BLUE 3
+/* Red */
+#define STATUS_LED_BIT STATUS_LED_RED
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+/* Green */
+#define STATUS_LED_BIT1 STATUS_LED_GREEN
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* Yellow */
+#define STATUS_LED_BIT2 STATUS_LED_YELLOW
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
+/* Blue */
+#define STATUS_LED_BIT3 STATUS_LED_BLUE
+#define STATUS_LED_STATE3 STATUS_LED_ON
+#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT STATUS_LED_BIT
+
+#define CONFIG_RED_LED AT91_PIN_PC11
+#define CONFIG_GREEN_LED AT91_PIN_PC12
+#define CONFIG_YELLOW_LED AT91_PIN_PC7
+#define CONFIG_BLUE_LED AT91_PIN_PC9
+
+/* USB */
+#define CONFIG_USB_ATMEL 1
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x21000000
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x21e00000
+
+#undef CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SYS_USE_FLASH 1
+
+#if defined(CONFIG_SYS_USE_FLASH)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "256k(u-boot)ro," \
+ "128k(u-boot-env)ro," \
+ "1792k(kernel)," \
+ "-(rootfs);" \
+ "atmel_nand:-(nand)"
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_BASEDIR "cpu9G20"
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_BASEDIR "cpu9260"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,0\0" \
+ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
+ "run ramargs;bootm 22000000\0" \
+ "flashboot=run ramargs;bootm 0x10060000\0" \
+ "basedir=" CONFIG_SYS_BASEDIR "\0" \
+ "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
+ "off 0x10000000 0x1003ffff;erase 0x10000000 " \
+ "0x1003ffff;cp.b 0x24000000 0x10000000 " \
+ "$(filesize)\0" \
+ "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
+ " 0x10060000 0x1021ffff;erase 0x10060000 " \
+ "0x1021ffff;cp.b 0x24000000 0x10060000 " \
+ "$(filesize)\0" \
+ "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
+ "protect off 0x10220000 0x13ffffff;erase " \
+ "0x10220000 0x13ffffff;cp.b 0x24000000 " \
+ "0x10220000 $(filesize)\0" \
+ ""
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_PROMPT "CPU9G20=> "
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_PROMPT "CPU9260=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SILENT_CONSOLE 1
+#define CONFIG_NETCONSOLE 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_STACKSIZE (32 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--- /dev/null
+/*
+ * CPUAT91 by (C) Copyright 2006 Eric Benard
+ * eric@eukrea.com
+ *
+ * Configuration settings for the CPUAT91 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_CPUAT91_RAM
+#define CONFIG_SKIP_LOWLEVEL_INIT 1
+#define CONFIG_SKIP_RELOCATE_UBOOT 1
+#define CONFIG_CPUAT91 1
+#else
+#define CONFIG_BOOTDELAY 1
+#endif
+
+#define AT91C_MAIN_CLOCK 179712000
+#define AT91C_MASTER_CLOCK 59904000
+
+#define AT91_SLOW_CLOCK 32768
+
+#define CONFIG_ARM920T 1
+#define CONFIG_AT91RM9200 1
+
+#undef CONFIG_USE_IRQ
+#define USE_920T_MMU 1
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL 0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL 0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
+#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_AT91RM9200_USART 1
+#define CONFIG_DBGU 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#define CONFIG_HARD_I2C 1
+
+#if defined(CONFIG_HARD_I2C)
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#endif
+
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_MII 1
+#define CONFIG_CMD_CACHE 1
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+
+#if defined(CONFIG_HARD_I2C)
+#define CONFIG_CMD_EEPROM 1
+#define CONFIG_CMD_I2C 1
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x02000000
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
+
+#define CONFIG_DRIVER_ETHER 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_AT91C_USE_RMII 1
+#define CONFIG_PHY_ADDRESS (1 << 5)
+#define CONFIG_KS8721_PHY 1
+
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define PHYS_FLASH_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_AT91C_PQFP_UHPBU 1
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#endif
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+
+#define CONFIG_SYS_LOAD_ADDR 0x21000000
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CONFIG_SYS_PROMPT "CPUAT91=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_LONGHELP 1
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (32 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#define CONFIG_DEVICE_NULLDEV 1
+#define CONFIG_SILENT_CONSOLE 1
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+
+#define CONFIG_VERSION_VARIABLE 1
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "128k(u-boot)ro," \
+ "128k(u-boot-env)," \
+ "1408k(kernel)," \
+ "-(rootfs)"
+
+#define CONFIG_BOOTARGS \
+ "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdid=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
+ "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
+ "10000000 ${filesize}\0" \
+ "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
+ "1019ffff; erase 10040000 1019ffff; cp.b 21000000 " \
+ "10040000 ${filesize}\0" \
+ "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
+ "101a0000 10ffffff; erase 101a0000 10ffffff; cp.b " \
+ "21000000 101A0000 ${filesize}\0" \
+ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "flashboot=run ramargs;bootm 10040000\0" \
+ "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
+ "bootm 21000000\0"
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/* Spectrum Digital TMS320DM355 EVM board */
#define DAVINCI_DM355EVM
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE SZ_128M
+#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
-/* NYET -- #define CONFIG_NAND_DAVINCI */
-#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
-/* TEMPORARY -- no safe place to save env, yet */
-#define CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_CMD_SAVEENV
-
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_MUSB_HCD
#define CONFIG_CMD_USB
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP
-#define CONFIG_ENV_SIZE SZ_16K
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x3C0000
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
-/* NYET -- #define CONFIG_BOOTDELAY 5 */
+#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
#define CONFIG_BOOTARGS \
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
-#define CONFIG_STACKSIZE SZ_256K /* regular stack */
-#define CONFIG_SYS_MALLOC_LEN SZ_512K /* malloc() arena */
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/* Spectrum Digital TMS320DM365 EVM board */
#define DAVINCI_DM365EVM
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE SZ_128M
+#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SAVEENV
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE SZ_256K
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_TIMESTAMP
/* U-Boot memory configuration */
-#define CONFIG_STACKSIZE SZ_256K /* regular stack */
-#define CONFIG_SYS_MALLOC_LEN SZ_1M /* malloc() arena */
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/*
* Define this to make U-Boot skip low level initialization when loaded
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
-#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT \
"nand0=davinci_nand.0"
"mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
#else
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/*=======*/
/* Board */
#define CONFIG_NAND_DAVINCI
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/* Board */
#define SFFSDR
#define CONFIG_NAND_DAVINCI
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/*
* Define this to make U-Boot skip low level initialization when loaded
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
-#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_OPENRD_BASE_H
+#define _CONFIG_OPENRD_BASE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nOpenRD_base"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_OPENRD_BASE /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x60000
+#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define MTDIDS_DEFAULT "nand0=nand_mtd"
+#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
+ "0x400000@0x100000(uImage),"\
+ "0x1fb00000@0x500000(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
+ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
+ "mtdids="MTDIDS_DEFAULT"\0" \
+ "mtdparts="MTDPARTS_DEFAULT"\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_OPENRD_BASE_H */
--- /dev/null
+/*
+ * NOTE: MICREL ethernet Physical layer
+ *
+ * Version: KS8721.h
+ *
+ * Authors: Eric Benard (based on dm9161.h)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */
+
+#define KS8721_BMCR 0
+#define KS8721_BMSR 1
+#define KS8721_PHYID1 2
+#define KS8721_PHYID2 3
+#define KS8721_ANAR 4
+#define KS8721_ANLPAR 5
+#define KS8721_ANER 6
+#define KS8721_RECR 15
+#define KS8721_MDINTR 27
+#define KS8721_100BT 31
+
+/* --Bit definitions: KS8721_BMCR */
+#define KS8721_RESET (1 << 15)
+#define KS8721_LOOPBACK (1 << 14)
+#define KS8721_SPEED_SELECT (1 << 13)
+#define KS8721_AUTONEG (1 << 12)
+#define KS8721_POWER_DOWN (1 << 11)
+#define KS8721_ISOLATE (1 << 10)
+#define KS8721_RESTART_AUTONEG (1 << 9)
+#define KS8721_DUPLEX_MODE (1 << 8)
+#define KS8721_COLLISION_TEST (1 << 7)
+#define KS8721_DISABLE (1 << 0)
+
+/*--Bit definitions: KS8721_BMSR */
+#define KS8721_100BASE_T4 (1 << 15)
+#define KS8721_100BASE_TX_FD (1 << 14)
+#define KS8721_100BASE_T4_HD (1 << 13)
+#define KS8721_10BASE_T_FD (1 << 12)
+#define KS8721_10BASE_T_HD (1 << 11)
+#define KS8721_MF_PREAMB_SUPPR (1 << 6)
+#define KS8721_AUTONEG_COMP (1 << 5)
+#define KS8721_REMOTE_FAULT (1 << 4)
+#define KS8721_AUTONEG_ABILITY (1 << 3)
+#define KS8721_LINK_STATUS (1 << 2)
+#define KS8721_JABBER_DETECT (1 << 1)
+#define KS8721_EXTEND_CAPAB (1 << 0)
+
+/*--Bit definitions: KS8721_PHYID */
+#define KS8721_PHYID_OUI 0x0885
+#define KS8721_LSB_MASK 0x3F
+
+#define KS8721BL_MODEL 0x21
+#define KS8721_MODELMASK 0x3F0
+#define KS8721BL_REV 0x9
+#define KS8721_REVMASK 0xF
+
+/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */
+#define KS8721_NP (1 << 15)
+#define KS8721_ACK (1 << 14)
+#define KS8721_RF (1 << 13)
+#define KS8721_PAUSE (1 << 10)
+#define KS8721_T4 (1 << 9)
+#define KS8721_TX_FDX (1 << 8)
+#define KS8721_TX_HDX (1 << 7)
+#define KS8721_10_FDX (1 << 6)
+#define KS8721_10_HDX (1 << 5)
+#define KS8721_AN_IEEE_802_3 0x0001
+
+/****************** function prototypes **********************/
+unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac);
+unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac);
+unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char ks8721_initphy(AT91PS_EMAC p_mac);
projects / people / ms / u-boot.git / commitdiff
