F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
-ARM MARVELL KIRKWOOD
+ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
M: Prafulla Wadaskar <prafulla@marvell.com>
M: Luka Perkov <luka.perkov@sartura.hr>
+M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
+F: arch/arm/mach-mvebu/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
-# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU
-# SoC's, the SPL U-Boot returns to the BootROM after it completes
-# the SDRAM setup. The BootROM expects no U-Boot header in the main
-# U-Boot image. So we need to combine SPL and u-boot.bin instead of
-# u-boot.img in this case.
-ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
-u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage)
-else
u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
-endif
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
to port U-Boot to your hardware platform. To do this, follow these
steps:
-1. Add a new configuration option for your board to the toplevel
- "boards.cfg" file, using the existing entries as examples.
- Follow the instructions there to keep the boards in order.
-2. Create a new directory to hold your board specific code. Add any
+1. Create a new directory to hold your board specific code. Add any
files you need. In your board directory, you will need at least
- the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
-3. Create a new configuration file "include/configs/<board>.h" for
- your board
+ the "Makefile" and a "<board>.c".
+2. Create a new configuration file "include/configs/<board>.h" for
+ your board.
3. If you're porting U-Boot to a new CPU, then also create a new
directory to hold your CPU specific code. Add any files you need.
4. Run "make <board>_defconfig" with your new name.
}
-static int dev_stor_index(block_dev_desc_t *dd)
-{
- int i, type;
-
- type = dev_stor_type(dd);
- for (i = 0; i < specs[type].max_dev; i++)
- if (dd == get_dev(specs[type].name, i))
- return i;
-
- return (specs[type].max_dev);
-}
-
-
lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
int type;
return 0;
}
- return (dd->block_read(dev_stor_index(dd), start, len, buf));
+ return dd->block_read(dd, start, len, buf);
}
1:
#endif
- /* Setup stack- and frame-pointers */
+ /* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
- /* Allocate and zero GD, update SP */
+ /* Allocate reserved area from current top of stack */
mov %r0, %sp
- bl board_init_f_mem
-
- /* Update stack- and frame-pointers */
+ bl board_init_f_alloc_reserve
+ /* Set stack below reserved area, adjust frame pointer accordingly */
mov %sp, %r0
mov %fp, %sp
+ /* Initialize reserved area - note: r0 already contains address */
+ bl board_init_f_init_reserve
+
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
j board_init_f
select OF_CONTROL
select OF_SEPARATE
select DM
+ select DM_ETH
select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_OF_CONTROL
+ select SPL_SIMPLE_BUS
config TARGET_DEVKIT3250
bool "Support devkit3250"
source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
-source "board/Marvell/db-88f6820-gp/Kconfig"
-source "board/Marvell/db-mv784mp-gp/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
-machine-$(CONFIG_ARMADA_XP) += mvebu
+machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
*/
#include <common.h>
-#include <asm/arch/cpu.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
-#include <dm.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
&clk->u3clk + (uart_id - 3));
}
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata lpc32xx_uart[] = {
+ { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK },
+};
+
+#if defined(CONFIG_LPC32XX_HSUART)
+static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+ { HS_UART1_BASE, },
+ { HS_UART2_BASE, },
+ { HS_UART7_BASE, },
+};
+#endif
+
+U_BOOT_DEVICES(lpc32xx_uarts) = {
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
+#endif
+ { "ns16550_serial", &lpc32xx_uart[0], },
+ { "ns16550_serial", &lpc32xx_uart[1], },
+ { "ns16550_serial", &lpc32xx_uart[2], },
+ { "ns16550_serial", &lpc32xx_uart[3], },
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
+#endif
+};
+#endif
+
void lpc32xx_dma_init(void)
{
/* Enable DMA interface */
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
+ armada-388-clearfog.dtb \
armada-388-gp.dtb \
- armada-xp-gp.dtb
+ armada-xp-gp.dtb \
+ armada-xp-maxbcm.dtb \
+ armada-xp-synology-ds414.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
serial0 = &uart0;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
+ spi0 = &qspi;
};
cpus {
qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
- reg = <0x47900000 0x100>;
+ reg = <0x47900000 0x100>,
+ <0x30000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "mx66l51235l";
+ compatible = "mx66l51235l","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ u-boot,dm-pre-reloc;
rtc@10300 {
compatible = "marvell,orion-rtc";
--- /dev/null
+/*
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-388.dtsi"
+
+/ {
+ model = "SolidRun Clearfog A1";
+ compatible = "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* 256 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+ ethernet@30000 {
+ mac-address = [00 50 43 02 02 02];
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@34000 {
+ mac-address = [00 50 43 02 02 03];
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+ };
+
+ ethernet@70000 {
+ mac-address = [00 50 43 02 02 01];
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
+
+ i2c@11000 {
+ /* Is there anything on this? */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ /* The MCP3021 is 100kHz clock only */
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ /* Also something at 0x64 */
+ };
+
+ i2c@11100 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ mdio@72004 {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy_dedicated: ethernet-phy@0 {
+ /*
+ * Annoyingly, the marvell phy driver
+ * configures the LED register, rather
+ * than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <0>;
+ };
+ };
+
+ pinctrl@18000 {
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "ref";
+ };
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
+ marvell,pins = "mpp23", "mpp41";
+ marvell,function = "gpio";
+ };
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_sdhci_pins: clearfog-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ };
+
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+ };
+
+ sata@a8000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sata@e0000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ bus-width = <4>;
+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-0 = <&clearfog_sdhci_pins
+ &clearfog_sdhci_cd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <®_3p3v>;
+ wp-inverted;
+ };
+
+ serial@12000 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ serial@12100 {
+ /* mikrobus uart */
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ spi@10680 {
+ /*
+ * We don't seem to have the W25Q32 on the
+ * A1 Rev 2.0 boards, so disable SPI.
+ * CS0: W25Q32 (doesn't appear to be present)
+ * CS1:
+ * CS2: mikrobus
+ */
+ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "w25q32", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+ status = "disabled";
+ };
+ };
+
+ usb3@f8000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+ pcie@2,0 {
+ /* Port 1, Lane 0. CONN3, nearest power. */
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ pcie@3,0 {
+ /* Port 2, Lane 0. CONN2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+ moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
+ sfp,ethernet = <ð2>;
+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ dsa@0 {
+ compatible = "marvell,dsa";
+ dsa,ethernet = <ð1>;
+ dsa,mii-bus = <&mdio>;
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4 0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ };
+
+ port@6 {
+ /* 88E1512 external phy */
+ reg = <6>;
+ label = "lan6";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+};
+
+/*
++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
+MPP18: gpio ? (pca9655 int?)
+MPP19: gpio ? (clkreq?)
+MPP20: gpio ? (sd0 detect)
+MPP21: sd0:cmd x sd0
+MPP22: gpio x mikro int
+MPP23: gpio x switch irq
++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
+MPP24: ua1:rxd x mikro rx
+MPP25: ua1:txd x mikro tx
+MPP26: i2c1:sck x mikro sck
+MPP27: i2c1:sda x mikro sda
+MPP28: sd0:clk x sd0
+MPP29: gpio x mikro rst
+MPP30: ge1:txd2 ? (config)
+MPP31: ge1:txd3 ? (config)
++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
+MPP32: ge1:txctl ? (unused)
+MPP33: gpio ? (pic_com0)
+MPP34: gpio x rear button (pic_com1)
+MPP35: gpio ? (pic_com2)
+MPP36: gpio ? (unused)
+MPP37: sd0:d3 x sd0
+MPP38: sd0:d0 x sd0
+MPP39: sd0:d1 x sd0
++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
+MPP40: sd0:d2 x sd0
+MPP41: gpio x switch reset
+MPP42: gpio ? sw1-1
+MPP43: spi1:cs2 x mikro cs
+MPP44: sata3:prsnt ? (unused)
+MPP45: ref:clk_out0 ?
+MPP46: ref:clk_out1 x switch clk
+MPP47: 4 ? (unused)
++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
+MPP48: tdm:pclk
+MPP49: tdm:fsync
+MPP50: tdm:drx
+MPP51: tdm:dtx
+MPP52: tdm:int
+MPP53: tdm:rst
+MPP54: gpio ? (pwm)
+MPP55: spi1:cs1 x slic
++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
+MPP56: spi1:mosi x mikro mosi
+MPP57: spi1:sck x mikro sck
+MPP58: spi1:miso x mikro miso
+MPP59: spi1:cs0 x w25q32
+*/
stdout-path = "serial0:115200n8";
};
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi0 = &spi0;
+ };
+
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
+ u-boot,dm-pre-reloc;
};
/* GE1 CON15 */
soc {
compatible = "marvell,armada380-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
internal-regs {
compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
stdout-path = "serial0:115200n8";
};
+ aliases {
+ spi0 = &spi0;
+ };
+
memory {
device_type = "memory";
/*
internal-regs {
serial@12000 {
status = "okay";
+ u-boot,dm-pre-reloc;
};
serial@12100 {
status = "okay";
spi0: spi@10600 {
status = "okay";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
--- /dev/null
+/*
+ * Device Tree file for Marvell Armada XP maxbcm board
+ *
+ * Copyright (C) 2013-2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78460.dtsi"
+
+/ {
+ model = "Marvell Armada XP MAXBCM";
+ compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ /*
+ * 8 GB of plug-in RAM modules by default.The amount
+ * of memory available can be changed by the
+ * bootloader according the size of the module
+ * actually plugged. However, memory between
+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
+ * the address range used for I/O (internal registers,
+ * MBus windows).
+ */
+ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
+ <0x00000001 0x00000000 0x00000001 0x00000000>;
+ };
+
+ cpus {
+ pm_pic {
+ ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
+ <&gpio0 17 GPIO_ACTIVE_LOW>,
+ <&gpio0 18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor@0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+ serial@12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+ serial@12100 {
+ status = "okay";
+ };
+ serial@12200 {
+ status = "okay";
+ };
+ serial@12300 {
+ status = "okay";
+ };
+ pinctrl {
+ pinctrl-0 = <&pic_pins>;
+ pinctrl-names = "default";
+ pic_pins: pic-pins-0 {
+ marvell,pins = "mpp16", "mpp17",
+ "mpp18";
+ marvell,function = "gpio";
+ };
+ };
+ sata@a0000 {
+ nr-ports = <2>;
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+ ethernet@74000 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+ ethernet@30000 {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ ethernet@34000 {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };
+
+ /* Front-side USB slot */
+ usb@50000 {
+ status = "okay";
+ };
+
+ /* Back-side USB slot */
+ usb@51000 {
+ status = "okay";
+ };
+
+ spi0: spi@10600 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+ };
+
+ nand@d0000 {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree file for Synology DS414
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+ model = "Synology DS414";
+ compatible = "synology,ds414", "marvell,armadaxp-mv78230",
+ "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * Connected to Marvell 88SX7042 SATA-II controller
+ * handling the four disks.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * Connected to EtronTech EJ168A XHCI controller
+ * providing the two rear USB 3.0 ports.
+ */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+
+ /* RTC is provided by Seiko S-35390A below */
+ rtc@10300 {
+ status = "disabled";
+ };
+
+ spi0: spi@10600 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q064";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+
+ /*
+ * Warning!
+ *
+ * Synology u-boot uses its compiled-in environment
+ * and it seems Synology did not care to change u-boot
+ * default configuration in order to allow saving a
+ * modified environment at a sensible location. So,
+ * if you do a 'saveenv' under u-boot, your modified
+ * environment will be saved at 1MB after the start
+ * of the flash, i.e. in the middle of the uImage.
+ * For that reason, it is strongly advised not to
+ * change the default environment, unless you know
+ * what you are doing.
+ */
+ partition@00000000 { /* u-boot */
+ label = "RedBoot";
+ reg = <0x00000000 0x000d0000>; /* 832KB */
+ };
+
+ partition@000c0000 { /* uImage */
+ label = "zImage";
+ reg = <0x000d0000 0x002d0000>; /* 2880KB */
+ };
+
+ partition@003a0000 { /* uInitramfs */
+ label = "rd.gz";
+ reg = <0x003a0000 0x00430000>; /* 4250KB */
+ };
+
+ partition@007d0000 { /* MAC address and serial number */
+ label = "vendor";
+ reg = <0x007d0000 0x00010000>; /* 64KB */
+ };
+
+ partition@007e0000 {
+ label = "RedBoot config";
+ reg = <0x007e0000 0x00010000>; /* 64KB */
+ };
+
+ partition@007f0000 {
+ label = "FIS directory";
+ reg = <0x007f0000 0x00010000>; /* 64KB */
+ };
+ };
+ };
+
+ i2c@11000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ s35390a: s35390a@30 {
+ compatible = "sii,s35390a";
+ reg = <0x30>;
+ };
+ };
+
+ /* Connected to a header on device's PCB. This
+ * provides the main console for the device.
+ *
+ * Warning: the device may not boot with a 3.3V
+ * USB-serial converter connected when the power
+ * button is pressed. The converter needs to be
+ * connected a few seconds after pressing the
+ * power button. This is possibly due to UART0_TXD
+ * pin being sampled at reset (bit 0 of SAR).
+ */
+ serial@12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ /* Connected to a Microchip PIC16F883 for power control */
+ serial@12100 {
+ status = "okay";
+ };
+
+ poweroff@12100 {
+ compatible = "synology,power-off";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ };
+
+ /* Front USB 2.0 port */
+ usb@50000 {
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
+ &sata3_pwr_pin &sata4_pwr_pin>;
+ pinctrl-names = "default";
+
+ sata1_regulator: sata1-regulator {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA1 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <2000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata2_regulator: sata2-regulator {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "SATA2 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <4000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata3_regulator: sata3-regulator {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "SATA3 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <6000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata4_regulator: sata4-regulator {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "SATA4 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <8000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ sata1_pwr_pin: sata1-pwr-pin {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+
+ sata2_pwr_pin: sata2-pwr-pin {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ sata3_pwr_pin: sata3-pwr-pin {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
+ sata4_pwr_pin: sata4-pwr-pin {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ sata1_pres_pin: sata1-pres-pin {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ sata2_pres_pin: sata2-pres-pin {
+ marvell,pins = "mpp35";
+ marvell,function = "gpio";
+ };
+
+ sata3_pres_pin: sata3-pres-pin {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+
+ sata4_pres_pin: sata4-pres-pin {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit0_pin: syno-id-bit0-pin {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit1_pin: syno-id-bit1-pin {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit2_pin: syno-id-bit2-pin {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ fan1_alarm_pin: fan1-alarm-pin {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+
+ fan2_alarm_pin: fan2-alarm-pin {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
bootrom {
compatible = "marvell,bootrom";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
ethernet1 = &cpsw_emac1;
d_can0 = &dcan1;
d_can1 = &dcan2;
+ spi0 = &qspi;
};
timer {
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
- reg = <0x4b300000 0x100>;
- reg-names = "qspi_base";
+ reg = <0x4b300000 0x100>,
+ <0x5c000000 0x4000000>,
+ <0x4a002558 0x4>;
+ reg-names = "qspi_base", "qspi_mmap",
+ "qspi_ctrlmod";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
#define CONFIG_NR_DRAM_BANKS_MAX 2
/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
-#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
(CONFIG_SYS_LPC32XX_UART == 7)
+#if !defined(CONFIG_LPC32XX_HSUART)
#define CONFIG_LPC32XX_HSUART
-#else
-#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_NS16550_COM1 UART3_BASE
-#define CONFIG_SYS_NS16550_COM2 UART4_BASE
-#define CONFIG_SYS_NS16550_COM3 UART5_BASE
-#define CONFIG_SYS_NS16550_COM4 UART6_BASE
#endif
-#if defined(CONFIG_LPC32XX_HSUART)
-#if CONFIG_SYS_LPC32XX_UART == 1
-#define HS_UART_BASE HS_UART1_BASE
-#elif CONFIG_SYS_LPC32XX_UART == 2
-#define HS_UART_BASE HS_UART2_BASE
-#else /* CONFIG_SYS_LPC32XX_UART == 7 */
-#define HS_UART_BASE HS_UART7_BASE
+#if !defined(CONFIG_SYS_NS16550_CLK)
+#define CONFIG_SYS_NS16550_CLK 13000000
#endif
+
+#if !defined(CONFIG_LPC32XX_HSUART)
+#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
+#else
+#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#endif
mov r0, sp
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mov sp, r0
+ /* set up gd here, outside any C code */
+ mov r9, r0
+ bl board_init_f_init_reserve
mov r0, #0
bl board_init_f
bl spl_relocate_stack_gd
cmp r0, #0
movne sp, r0
+ movne r9, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
- bl board_init_f_mem
+ mov x0, sp
+ bl board_init_f_alloc_reserve
mov sp, x0
+ /* set up gd here, outside any C code */
+ mov x18, x0
+ bl board_init_f_init_reserve
mov x0, #0
bl board_init_f
#define CONFIG_SYS_I2C_SPEED 100000
#endif
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
+
#endif /* _KW_CONFIG_H */
if ARCH_MVEBU
+config ARMADA_38X
+ bool
+
+config ARMADA_XP
+ bool
+
+config MV78230
+ bool
+ select ARMADA_XP
+
+config MV78260
+ bool
+ select ARMADA_XP
+
+config MV78460
+ bool
+ select ARMADA_XP
+
+config DB_88F6820_GP
+ bool
+ select ARMADA_38X
+
choice
prompt "Marvell MVEBU (Armada XP/38x) board select"
optional
+config TARGET_CLEARFOG
+ bool "Support ClearFog"
+ select DB_88F6820_GP
+
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
+ select DB_88F6820_GP
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
+ select MV78460
+
+config TARGET_DS414
+ bool "Support Synology DS414"
+ select MV78230
config TARGET_MAXBCM
bool "Support maxbcm"
+ select MV78460
endchoice
-config SYS_SOC
- default "mvebu"
+config SYS_BOARD
+ default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds414" if TARGET_DS414
+ default "maxbcm" if TARGET_MAXBCM
-config MVEBU_BOOTROM_UARTBOOT
- bool "Use kwboot to boot via BootROM xmodem protocol"
- help
- This option provides support for booting via the Marvell
- xmodem protocol, used by the kwboot tool.
+config SYS_CONFIG_NAME
+ default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds414" if TARGET_DS414
+ default "maxbcm" if TARGET_MAXBCM
- Please don't forget to configure the boot device in
- the board specific kwbimage.cfg file this way:
- BOOT_FROM uart
+config SYS_VENDOR
+ default "Marvell" if TARGET_DB_MV784MP_GP
+ default "Marvell" if TARGET_DB_88F6820_GP
+ default "solidrun" if TARGET_CLEARFOG
+ default "Synology" if TARGET_DS414
+
+config SYS_SOC
+ default "mvebu"
endif
obj-y = cpu.o
obj-y += dram.o
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o
+obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
+obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
endif
obj-y += gpio.o
obj-y += mbus.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/
+obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
+obj-$(CONFIG_ARMADA_XP) += serdes/axp/
endif
/*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <netdev.h>
#include <ahci.h>
#include <linux/mbus.h>
#include <asm/io.h>
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
- if (devid == SOC_MV78460_ID)
+ switch (devid) {
+ case SOC_MV78230_ID:
+ case SOC_MV78260_ID:
+ case SOC_MV78460_ID:
return MVEBU_SOC_AXP;
-
- if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
- devid == SOC_88F6828_ID)
+ case SOC_88F6810_ID:
+ case SOC_88F6820_ID:
+ case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
-
+ }
return MVEBU_SOC_UNKNOWN;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
+
+#if defined(CONFIG_ARMADA_38X)
+/* SAR frequency values for Armada 38x */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0x0, 0x0, 666, 333, 333 },
+ { 0x2, 0x0, 800, 400, 400 },
+ { 0x4, 0x0, 1066, 533, 533 },
+ { 0x6, 0x0, 1200, 600, 600 },
+ { 0x8, 0x0, 1332, 666, 666 },
+ { 0xc, 0x0, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#else
+/* SAR frequency values for Armada XP */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0xa, 0x5, 800, 400, 400 },
+ { 0x1, 0x5, 1066, 533, 533 },
+ { 0x2, 0x5, 1200, 600, 600 },
+ { 0x2, 0x9, 1200, 600, 400 },
+ { 0x3, 0x5, 1333, 667, 667 },
+ { 0x4, 0x5, 1500, 750, 750 },
+ { 0x4, 0x9, 1500, 750, 500 },
+ { 0xb, 0x9, 1600, 800, 533 },
+ { 0xb, 0xa, 1600, 800, 640 },
+ { 0xb, 0x5, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#endif
+
+void get_sar_freq(struct sar_freq_modes *sar_freq)
+{
+ u32 val;
+ u32 freq;
+ int i;
+
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+ freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
+#if !defined(CONFIG_ARMADA_38X)
+ /*
+ * Shift CPU0 clock frequency select bit from SAR2 register
+ * into correct position
+ */
+ freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
+ >> SAR2_CPU_FREQ_OFFS) << 3;
+#endif
+ for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
+ if (sar_freq_tab[i].val == freq) {
+#if defined(CONFIG_ARMADA_38X)
+ *sar_freq = sar_freq_tab[i];
+ return;
+#else
+ int k;
+ u8 ffc;
+
+ ffc = (val & SAR_FFC_FREQ_MASK) >>
+ SAR_FFC_FREQ_OFFS;
+ for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
+ if (sar_freq_tab[k].ffc == ffc) {
+ *sar_freq = sar_freq_tab[k];
+ return;
+ }
+ }
+ i = k;
+#endif
+ }
+ }
+
+ /* SAR value not found, return 0 for frequencies */
+ *sar_freq = sar_freq_tab[i - 1];
+}
+
int print_cpuinfo(void)
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+ struct sar_freq_modes sar_freq;
puts("SoC: ");
switch (devid) {
+ case SOC_MV78230_ID:
+ puts("MV78230-");
+ break;
+ case SOC_MV78260_ID:
+ puts("MV78260-");
+ break;
case SOC_MV78460_ID:
puts("MV78460-");
break;
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
switch (revid) {
case 1:
- puts("A0\n");
+ puts("A0");
break;
case 2:
- puts("B0\n");
+ puts("B0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
switch (revid) {
case MV_88F68XX_Z1_ID:
- puts("Z1\n");
+ puts("Z1");
break;
case MV_88F68XX_A0_ID:
- puts("A0\n");
+ puts("A0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
+ get_sar_freq(&sar_freq);
+ printf(" at %d MHz\n", sar_freq.p_clk);
+
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
/* Power up PLL and PHY channel */
- clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
+ setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
/* Assert VCOCAL_START */
- clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
+ setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
mdelay(1);
*/
for (dev = 0; dev < 3; dev++) {
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
+ setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
/* Assert REG_RCAL_START in channel REG 1 */
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
+ setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
udelay(40);
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
+ clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
}
}
+/*
+ * This function is not called from the SPL U-Boot version
+ */
int arch_cpu_init(void)
{
-#if !defined(CONFIG_SPL_BUILD)
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
* still locked to cache.
*/
mmu_disable();
-#endif
/* Linux expects the internal registers to be at 0xf1000000 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-#if !defined(CONFIG_SPL_BUILD)
/*
* From this stage on, the SoC detection is working. As we have
* configured the internal register base to the value used
* in the macros / defines in the U-Boot header (soc.h).
*/
- /*
- * To fully release / unlock this area from cache, we need
- * to flush all caches and disable the L2 cache.
- */
- icache_disable();
- dcache_disable();
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-#endif
+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+ /*
+ * To fully release / unlock this area from cache, we need
+ * to flush all caches and disable the L2 cache.
+ */
+ icache_disable();
+ dcache_disable();
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
/*
* We need to call mvebu_mbus_probe() before calling
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
- u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
- MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- int i;
-
- /*
- * Only Armada XP supports all 4 ethernet interfaces. A38x has
- * slightly different base addresses for its 2-3 interfaces.
- */
- if (mvebu_soc_family() != MVEBU_SOC_AXP) {
- enet_base[1] = MVEBU_EGIGA2_BASE;
- enet_base[2] = MVEBU_EGIGA3_BASE;
- }
-
- for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
- mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_MV_SDHCI
int board_mmc_init(bd_t *bis)
{
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
- struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
- /* First disable L2 cache - may still be enable from BootROM */
- if (mvebu_soc_family() == MVEBU_SOC_A38X)
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
-#endif
+
+void v7_outer_cache_enable(void)
+{
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ u32 u;
+
+ /* The L2 cache is already disabled at this point */
+
+ /*
+ * For Aurora cache in no outer mode, enable via the CP15
+ * coprocessor broadcasting of cache commands to L2.
+ */
+ asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+ u |= BIT(8); /* Set the FW bit */
+ asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+
+ isb();
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#ifdef CONFIG_SYS_MVEBU_DDR_A38X
-#include "../../../drivers/ddr/marvell/axp/xor.h"
-#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
-#endif
-#ifdef CONFIG_SYS_MVEBU_DDR_AXP
+#if defined(CONFIG_ARCH_MVEBU)
+/* Use common XOR definitions for A3x and AXP */
#include "../../../drivers/ddr/marvell/axp/xor.h"
#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif
mvebu_sdram_bs_set(bank, size);
}
-#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP)
+#if defined(CONFIG_ARCH_MVEBU)
static u32 xor_ctrl_save;
static u32 xor_base_save;
static u32 xor_mask_save;
}
}
+#if defined(CONFIG_ARCH_MVEBU)
void board_add_ram_info(int use_default)
{
+ struct sar_freq_modes sar_freq;
+
+ get_sar_freq(&sar_freq);
+ printf(" (%d MHz, ", sar_freq.d_clk);
+
if (ecc_enabled())
- printf(" (ECC");
+ printf("ECC");
else
- printf(" (ECC not");
+ printf("ECC not");
printf(" enabled)");
}
+#endif
#include <asm/arch/soc.h>
-#if defined(CONFIG_ARMADA_XP)
+#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
+/*
+ * Set this for the common xor register definitions needed in dram.c
+ * for A38x as well here.
+ */
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif
#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#endif
+
/*
* By default kwbimage.cfg from board specific folder is used
* If for some board, different configuration file need to be used,
* SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI 1
-#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_KIRKWOOD_SPI
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS 0
#endif
#endif
#endif
+/* Needed for SPI NOR booting in SPL */
+#define CONFIG_DM_SEQ_ALIAS 1
+
/*
* Ethernet Driver configuration
*/
#define CONFIG_SYS_I2C_SPEED 100000
#endif
-/* Common SPL configuration */
-#ifndef CONFIG_SPL_LDSCRIPT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds"
-#endif
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE 25000000
#endif /* __MVEBU_CONFIG_H */
u32 irq_level;
};
+struct sar_freq_modes {
+ u8 val;
+ u8 ffc; /* Fabric Frequency Configuration */
+ u32 p_clk;
+ u32 nb_clk;
+ u32 d_clk;
+};
+
/* Needed for dynamic (board-specific) mbus configuration */
extern struct mvebu_mbus_state mbus_state;
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+void get_sar_freq(struct sar_freq_modes *sar_freq);
+
/*
* Highspeed SERDES PHY config init, ported from bin_hdr
* to mainline U-Boot
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
+#define SOC_MV78230_ID 0x7823
+#define SOC_MV78260_ID 0x7826
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
#if defined(CONFIG_SPL_BUILD)
/*
- * On A38x switching the regs base address without running from
- * SDRAM doesn't seem to work. So let the SPL still use the
- * default base address and switch to the new address in the
- * main u-boot later.
+ * The SPL U-Boot version still runs with the default
+ * address for the internal registers, configured by
+ * the BootROM. Only the main U-Boot version uses the
+ * new internal register base address, that also is
+ * required for the Linux kernel.
*/
#define SOC_REGS_PHY_BASE 0xd0000000
#else
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
-#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
-#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
-#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
-#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
-#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
#define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
-#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
-#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
+#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
+
+/* BootROM error register (also includes some status infos) */
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS 28
+#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
+#define BOOTROM_ERR_MODE_UART 0x6
+
+#if defined(CONFIG_ARMADA_38X)
+/* SAR values for Armada 38x */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
+
+#define SAR_CPU_FREQ_OFFS 10
+#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 4
+#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 4
+#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x28
+#define BOOT_FROM_SPI 0x32
+#define BOOT_FROM_MMC 0x30
+#define BOOT_FROM_MMC_ALT 0x31
+#else
+/* SAR values for Armada XP */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
+#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
+
+#define SAR_CPU_FREQ_OFFS 21
+#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_FFC_FREQ_OFFS 24
+#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
+#define SAR2_CPU_FREQ_OFFS 20
+#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 5
+#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 5
+#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x2
+#define BOOT_FROM_SPI 0x3
+#endif
+
#endif /* _MVEBU_SOC_H */
#include <config.h>
#include <linux/linkage.h>
-#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
ENDPROC(return_to_bootrom)
-#else
-ENTRY(save_boot_params)
- b save_boot_params_ret
-ENDPROC(save_boot_params)
-#endif
/*
* cache_inv - invalidate Cache line
#if defined(CONFIG_KIRKWOOD)
mbus_state.soc = &kirkwood_mbus_data;
#endif
-#if defined(CONFIG_ARMADA_XP)
+#if defined(CONFIG_ARCH_MVEBU)
mbus_state.soc = &armada_370_xp_mbus_data;
#endif
#define BOARD_ID_BASE 0x0
/* New board ID numbers */
-#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
+#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1)
#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
-#define INVALID_BAORD_ID 0xFFFFFFFF
+#define INVALID_BOARD_ID 0xFFFFFFFF
/* Sample at Reset */
#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
#endif
}
-static u8 board_sat_r_get(u8 dev_num, u8 reg)
+__weak u8 board_sat_r_get(u8 dev_num, u8 reg)
{
u8 data;
u8 *dev;
u32 board_id = board_id_get();
int ret;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
switch (board_id) {
+ case DB_78X60_AMC_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_CUSTOMER_ID:
+ case RD_78460_SERVER_ID:
+ case RD_78460_SERVER_REV2_ID:
+ case DB_78X60_PCAC_ID:
+ return (0x1 << 1) | 1;
+ case FPGA_88F78XX0_ID:
+ case RD_78460_NAS_ID:
+ return (0x0 << 1) | 1;
case DB_784MP_GP_ID:
dev = rd78460gp_twsi_dev;
dev = db88f78xx0rev2_twsi_dev;
break;
- case DB_78X60_PCAC_ID:
- case FPGA_88F78XX0_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_SERVER_REV2_ID:
default:
return 0;
}
/* Read MPP module ID */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
if (ret)
return MV_ERROR;
u16 ctrl_model_get(void)
{
- /* Right now only MV78460 supported */
+ /*
+ * SoC version can't be autodetected. So we need to rely on a define
+ * from the config system here.
+ */
+#if defined(CONFIG_MV78230)
+ return MV_78230_DEV_ID;
+#elif defined(CONFIG_MV78260)
+ return MV_78260_DEV_ID;
+#else
return MV_78460_DEV_ID;
+#endif
}
u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
}
+static int serdes_max_lines_get(void)
+{
+ switch (ctrl_model_get()) {
+ case MV_78230_DEV_ID:
+ return 7;
+ case MV_78260_DEV_ID:
+ return 12;
+ case MV_78460_DEV_ID:
+ return 16;
+ }
+
+ return 0;
+}
+
int serdes_phy_config(void)
{
int status = MV_OK;
u8 device_rev;
u32 rx_high_imp_mode;
u16 ctrl_mode;
- u32 board_id = board_id_get();
u32 pex_if;
u32 pex_if_num;
/*
- * TODO:
- * Right now we only support the MV78460 with 16 serdes lines
+ * Get max. serdes lines count
*/
- max_serdes_lines = 16;
+ max_serdes_lines = serdes_max_lines_get();
if (max_serdes_lines == 0)
return MV_OK;
- switch (board_id) {
- case DB_78X60_AMC_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_CUSTOMER_ID:
- case RD_78460_SERVER_ID:
- case RD_78460_SERVER_REV2_ID:
- case DB_78X60_PCAC_ID:
- satr11 = (0x1 << 1) | 1;
- break;
- case FPGA_88F78XX0_ID:
- case RD_78460_NAS_ID:
- satr11 = (0x0 << 1) | 1;
- break;
- case DB_88F78XX0_BP_REV2_ID:
- case DB_784MP_GP_ID:
- case DB_88F78XX0_BP_ID:
- satr11 = board_sat_r_get(1, 1);
- if ((u8) MV_ERROR == (u8) satr11)
- return MV_ERROR;
- break;
- }
+ satr11 = board_sat_r_get(1, 1);
+ if ((u8) MV_ERROR == (u8) satr11)
+ return MV_ERROR;
board_modules_scan();
memset(addr, 0, sizeof(addr));
pex_if, PEX_DEVICE_AND_VENDOR_ID));
devId &= 0xFFFF;
devId |= ((ctrl_mode << 16) & 0xffff0000);
- DEBUG_INIT_S("Update Device ID PEX");
- DEBUG_INIT_D(pex_if, 1);
- DEBUG_INIT_D(devId, 8);
- DEBUG_INIT_S("\n");
+ DEBUG_INIT_FULL_S("Update Device ID PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_D(devId, 8);
+ DEBUG_INIT_FULL_S("\n");
reg_write(PEX_CFG_DIRECT_ACCESS
(pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
if ((pex_if < 8) &&
(info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
pex_if += 3;
}
- DEBUG_INIT_S("Update PEX Device ID 0x");
- DEBUG_INIT_D(ctrl_mode, 4);
- DEBUG_INIT_S("0\n");
+ DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
+ DEBUG_INIT_FULL_D(ctrl_mode, 4);
+ DEBUG_INIT_FULL_S("0\n");
}
tmp = reg_read(PEX_DBG_STATUS_REG(0));
DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <debug_uart.h>
+#include <fdtdec.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
+static u32 get_boot_device(void)
{
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
- return BOOT_DEVICE_SPI;
-#endif
-#if defined(CONFIG_SPL_MMC_SUPPORT)
- return BOOT_DEVICE_MMC1;
+ u32 val;
+ u32 boot_device;
+
+ /*
+ * First check, if UART boot-mode is active. This can only
+ * be done, via the bootrom error register. Here the
+ * MSB marks if the UART mode is active.
+ */
+ val = readl(CONFIG_BOOTROM_ERR_REG);
+ boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
+ debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+ if (boot_device == BOOTROM_ERR_MODE_UART)
+ return BOOT_DEVICE_UART;
+
+ /*
+ * Now check the SAR register for the strapped boot-device
+ */
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
+ debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+ switch (boot_device) {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case BOOT_FROM_MMC:
+ case BOOT_FROM_MMC_ALT:
+ return BOOT_DEVICE_MMC1;
#endif
+ case BOOT_FROM_UART:
+ return BOOT_DEVICE_UART;
+ case BOOT_FROM_SPI:
+ default:
+ return BOOT_DEVICE_SPI;
+ };
+}
+
+u32 spl_boot_device(void)
+{
+ return get_boot_device();
}
#ifdef CONFIG_SPL_MMC_SUPPORT
void board_init_f(ulong dummy)
{
-#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT
- /*
- * Only call arch_cpu_init() when not returning to the
- * Marvell BootROM, which is done when booting via
- * the xmodem protocol (kwboot tool). Otherwise the
- * internal register will get remapped and the BootROM
- * can't continue to run correctly.
- */
-
- /* Linux expects the internal registers to be at 0xf1000000 */
- arch_cpu_init();
-#endif
+ int ret;
/*
* Pin muxing needs to be done before UART output, since
*/
board_early_init_f();
+ /* Example code showing how to enable the debug UART on MVEBU */
+#ifdef EARLY_UART
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+#endif
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Use special translation offset for SPL */
+ dm_set_translation_offset(0xd0000000 - 0xf1000000);
+
preloader_console_init();
timer_init();
/* Setup DDR */
ddr3_init();
-#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
/*
* Return to the BootROM to continue the Marvell xmodem
* UART boot protocol. As initiated by the kwboot tool.
* need to return to the BootROM to enable this xmodem
* UART download.
*/
- return_to_bootrom();
-#endif
+ if (get_boot_device() == BOOT_DEVICE_UART)
+ return_to_bootrom();
}
* Copyright (C) Marvell International Ltd. and its affiliates
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/arch/soc.h>
-#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG &tmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
-#if defined(CONFIG_ARMADA_XP)
-#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
-#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
-#else
-#define CTCR_ARM_TIMER_25MHZ(cntr) 0
-#endif
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static int init_done __attribute__((section(".data"))) = 0;
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct kwtmr_val tmr[4];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
DECLARE_GLOBAL_DATA_PTR;
-static struct kwtmr_registers *tmr_regs =
- (struct kwtmr_registers *)MVEBU_TIMER_BASE;
-
-static inline ulong read_timer(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
- }
- lastdec = now;
+#define TIMER_LOAD_VAL 0xffffffff
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- uint current;
- ulong delayticks;
-
- current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
- if (current < delayticks) {
- delayticks -= current;
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
- while ((TIMER_LOAD_VAL - delayticks) <
- readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
- } else {
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
- (current - delayticks)) ;
- }
-}
+static int init_done __attribute__((section(".data"))) = 0;
/*
- * init the counter
+ * Timer initialization
*/
int timer_init(void)
{
init_done = 1;
/* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10);
+ writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14);
+#if defined(CONFIG_ARCH_MVEBU)
+ /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */
+ setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11));
+#endif
/* enable timer in auto reload mode */
- clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
- CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
- CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
-
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
+ setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3);
return 0;
}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- *(.vectors)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*_i2c_*)));
- } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
endif
obj-y += rk_timer.o
-obj-y += rk_early_print.o
obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
*/
#include <common.h>
+#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3036.h>
#include <asm/arch/hardware.h>
GPIO1C2_MASK << GPIO1C2_SHIFT,
GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
- rk_uart_init((void *)DEBUG_UART_BASE);
+ debug_uart_init();
#endif
rockchip_timer_init();
sdram_init();
while (1)
;
}
+
+void hang(void)
+{
+ while (1)
+ ;
+}
+++ /dev/null
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <common.h>
-
-static struct rk_uart *uart_ptr;
-
-static void uart_wrtie_byte(char byte)
-{
- writel(byte, &uart_ptr->rbr);
- while (!(readl(&uart_ptr->lsr) & 0x40))
- ;
-}
-
-void print(char *s)
-{
- while (*s) {
- if (*s == '\n')
- uart_wrtie_byte('\r');
- uart_wrtie_byte(*s);
- s++;
- }
-}
-
-void print_hex(unsigned int n)
-{
- int i;
- int temp;
-
- uart_wrtie_byte('0');
- uart_wrtie_byte('x');
-
- for (i = 8; i > 0; i--) {
- temp = (n >> (i - 1) * 4) & 0x0f;
- if (temp < 10)
- uart_wrtie_byte((char)(temp + '0'));
- else
- uart_wrtie_byte((char)(temp - 10 + 'a'));
- }
- uart_wrtie_byte('\n');
- uart_wrtie_byte('\r');
-}
-
-/*
- * TODO: since rk3036 only 4K sram to use in SPL, for saving space,
- * we implement uart driver this way, we should convert this to use
- * ns16550 driver in future, which support DEBUG_UART in the standard way
- */
-void rk_uart_init(void *base)
-{
- uart_ptr = (struct rk_uart *)base;
- writel(0x83, &uart_ptr->lcr);
- writel(0x0d, &uart_ptr->rbr);
- writel(0x03, &uart_ptr->lcr);
-
- /* fifo enable, sfe is shadow register of FCR[0] */
- writel(0x01, &uart_ptr->sfe);
-}
config TEGRA_COMMON
bool "Tegra common options"
select DM
+ select DM_ETH
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
+ depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \
+ ARCH_UNIPHIER_PH1_SLD8
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
+config CMD_DDRMPHY_DUMP
+ bool "Enable dump command of DDR Multi PHY parameters"
+ depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B
+ help
+ The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
+ training; it is useful for the evaluation of DDR Multi PHY training.
+
endif
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
obj-y += cache_uniphier.o
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-y += pinctrl/ clk/
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_init(void)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
-#include <mach/soc_info.h>
+#include "init.h"
+#include "micro-support-card.h"
+#include "soc-info.h"
int board_early_init_f(void)
{
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_early_init_r(void)
{
#include <common.h>
#include <libfdt.h>
#include <linux/kernel.h>
-#include <mach/init.h>
+
+#include "init.h"
DECLARE_GLOBAL_DATA_PTR;
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o
+
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
#include <common.h>
#include <spl.h>
-#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
u32 spl_boot_device(void)
{
*/
#include <common.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#include <common.h>
#include <linux/io.h>
#include <asm/armv7.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_ld4_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro4_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro5_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void proxstream2_clk_init(void)
{
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "ddrmphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+static void __iomem *get_phy_base(int ch)
+{
+ return (void __iomem *)(0x5b830000 + ch * 0x00200000);
+}
+
+static int get_nr_ch(void)
+{
+ const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+ return bd->dram_ch2_width ? 3 : 2;
+}
+
+static int get_nr_datx8(int ch)
+{
+ unsigned int width;
+
+ const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+ switch (ch) {
+ case 0:
+ width = bd->dram_ch0_width;
+ break;
+ case 1:
+ width = bd->dram_ch1_width;
+ break;
+ default:
+ width = bd->dram_ch2_width;
+ break;
+ }
+
+ return width / 8;
+}
+
+static void print_bdl(void __iomem *reg, int n)
+{
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
+}
+
+static void dump_loop(void (*callback)(void __iomem *))
+{
+ int ch, dx, nr_ch, nr_dx;
+ void __iomem *dx_base;
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
+ nr_dx = get_nr_datx8(ch);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ printf("CH%dDX%d:", ch, dx);
+ (*callback)(dx_base);
+ dx_base += DMPHY_DX_STRIDE;
+ printf("\n");
+ }
+ }
+}
+
+static void zq_dump(void)
+{
+ int ch, zq, nr_ch, nr_zq, i;
+ void __iomem *zq_base;
+ u32 dr, pr;
+
+ printf("\n--- Impedance Data ---\n");
+ printf(" ZPD ZPU OPD OPU ZDV ODV\n");
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
+ nr_zq = 3;
+
+ for (zq = 0; zq < nr_zq; zq++) {
+ printf("CH%dZQ%d:", ch, zq);
+
+ dr = readl(zq_base + DMPHY_ZQ_DR);
+ for (i = 0; i < 4; i++) {
+ printf(FS PRINTF_FORMAT, dr & 0x7f);
+ dr >>= 7;
+ }
+
+ pr = readl(zq_base + DMPHY_ZQ_PR);
+ for (i = 0; i < 2; i++) {
+ printf(FS PRINTF_FORMAT, pr & 0xf);
+ pr >>= 4;
+ }
+
+ zq_base += DMPHY_ZQ_STRIDE;
+ printf("\n");
+ }
+ }
+}
+
+static void __wbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
+}
+
+static void wbdl_dump(void)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
+}
+
+static void rbdl_dump(void)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
+
+ dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+static void wld_dump(void)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+static void dqsgd_dump(void)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(void __iomem *dx_base)
+{
+ int i;
+ u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
+
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(void)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %p : %08x\n", \
+ ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
+
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
+ DMPHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %p : %08x\n", \
+ ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
+
+static void reg_dump(void)
+{
+ int ch, dx, nr_ch, nr_dx;
+ void __iomem *phy_base;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ phy_base = get_phy_base(ch);
+ nr_dx = get_nr_datx8(ch);
+
+ printf("== Ch%d ==\n", ch);
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGCR2);
+ REG_DUMP(PGCR3);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR0);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(DTPR3);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR0);
+ DX_REG_DUMP(dx, GCR1);
+ DX_REG_DUMP(dx, GCR2);
+ DX_REG_DUMP(dx, GCR3);
+ DX_REG_DUMP(dx, GTR);
+ }
+ }
+}
+
+static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd = argv[1];
+
+ if (argc == 1)
+ cmd = "all";
+
+ if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
+ zq_dump();
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump();
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump();
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump();
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump();
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump();
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddrm, 2, 1, do_ddrm,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the followings\n"
+ "ddrm zq - dump Impedance Data\n"
+ "ddrm wbdl - dump Write Bit Delay\n"
+ "ddrm rbdl - dump Read Bit Delay\n"
+ "ddrm wld - dump Write Leveling\n"
+ "ddrm dqsgd - dump DQS Gating Delay\n"
+ "ddrm mdl - dump Master Delay Line\n"
+ "ddrm reg - dump registers\n"
+);
#include <common.h>
#include <linux/io.h>
-#include <mach/sg-regs.h>
+
+#include "sg-regs.h"
int print_cpuinfo(void)
{
#include <linux/serial_reg.h>
#include <linux/linkage.h>
-#include <mach/bcu-regs.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "bcu/bcu-regs.h"
+#include "sc-regs.h"
+#include "sg-regs.h"
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
ddrphy-training.o ddrphy-ph1-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \
ddrphy-training.o ddrphy-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
+
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
#include <common.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
#if 1
--- /dev/null
+/*
+ * UniPhier DDR MultiPHY registers
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRMPHY_REGS_H
+#define ARCH_DDRMPHY_REGS_H
+
+#include <linux/bitops.h>
+
+#define DMPHY_SHIFT 2
+
+#define DMPHY_RIDR (0x000 << DMPHY_SHIFT)
+#define DMPHY_PIR (0x001 << DMPHY_SHIFT)
+#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define DMPHY_PIR_WL BIT(9) /* Write Leveling */
+#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT)
+#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
+#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT)
+#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT)
+#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
+#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
+#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT)
+#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT)
+#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
+#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT)
+#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
+#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT)
+#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT)
+#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT)
+#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT)
+#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT)
+#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT)
+#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT)
+#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT)
+#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT)
+#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT)
+#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT)
+#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT)
+#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT)
+#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT)
+#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT)
+#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT)
+#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT)
+#define DMPHY_DCR (0x022 << DMPHY_SHIFT)
+#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT)
+#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT)
+#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT)
+#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT)
+#define DMPHY_MR0 (0x027 << DMPHY_SHIFT)
+#define DMPHY_MR1 (0x028 << DMPHY_SHIFT)
+#define DMPHY_MR2 (0x029 << DMPHY_SHIFT)
+#define DMPHY_MR3 (0x02A << DMPHY_SHIFT)
+#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT)
+#define DMPHY_DTCR (0x02C << DMPHY_SHIFT)
+#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT))
+#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT)
+#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT)
+#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT)
+#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT)
+#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT)
+#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT)
+#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT)
+#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT)
+#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT)
+#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
+#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
+/* ZQ */
+#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT)
+#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT)
+#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT)
+#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT)
+#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT)
+/* DATX8 */
+#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT)
+#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT))
+#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT)
+#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT)
+#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT)
+
+#endif /* ARCH_DDRMPHY_REGS_H */
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
#include <config.h>
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "../soc-info.h"
+#include "ddrmphy-regs.h"
+
+/* UM registers */
+#define UMC_MBUS0 0x00080004
+#define UMC_MBUS1 0x00081004
+#define UMC_MBUS2 0x00082004
+#define UMC_MBUS3 0x00083004
+
+/* UD registers */
+#define UMC_BITPERPIXELMODE_D0 0x010
+#define UMC_PAIR1DOFF_D0 0x054
+
+/* DC registers */
+#define UMC_INITSET 0x014
+#define UMC_INITSTAT 0x018
+#define UMC_CMDCTLA 0x000
+#define UMC_CMDCTLB 0x004
+#define UMC_SPCCTLA 0x030
+#define UMC_SPCCTLB 0x034
+#define UMC_SPCSETB 0x03c
+#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
+#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
+#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
+#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
+#define UMC_ACSSETA 0x060
+#define UMC_FLOWCTLA 0x400
+#define UMC_FLOWCTLB 0x404
+#define UMC_FLOWCTLC 0x408
+#define UMC_FLOWCTLG 0x508
+#define UMC_FLOWCTLOB0 0x520
+#define UMC_FLOWCTLOB1 0x524
+#define UMC_RDATACTL_D0 0x600
+#define UMC_RDATACTL_RADLTY_SHIFT 4
+#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define UMC_RDATACTL_RAD2LTY_SHIFT 8
+#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
+#define UMC_WDATACTL_D0 0x604
+#define UMC_RDATACTL_D1 0x608
+#define UMC_WDATACTL_D1 0x60c
+#define UMC_DATASET 0x610
+#define UMC_RESPCTL 0x624
+#define UMC_DCCGCTL 0x720
+#define UMC_ERRMASKA 0x958
+#define UMC_ERRMASKB 0x95c
+#define UMC_BSICMAPSET 0x988
+#define UMC_DIOCTLA 0xc00
+#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
+#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
+#define UMC_DFICUPDCTLA 0xc20
+
+enum dram_freq {
+ FREQ_1866M,
+ FREQ_2133M,
+ FREQ_NR,
+};
+
+enum dram_size {
+ SIZE_0,
+ SIZE_512M,
+ SIZE_1G,
+ SIZE_NR,
+};
+
+static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
+static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
+static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
+static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357};
+static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
+static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88};
+static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0};
+static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00};
+static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89};
+static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125};
+static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8};
+
+static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722};
+/*
+ * The ch2 is a different generation UMC core.
+ * The register spec is different, unfortunately.
+ */
+static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44};
+static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
+static u32 umc_spcctla[FREQ_NR][SIZE_NR] = {
+ {0x00000000, 0x004A071D, 0x0078071D},
+ {0x00000000, 0x0055081E, 0x0089081E},
+};
+
+static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
+/* The ch2 is different for some reason only hardware guys know... */
+static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
+static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
+
+/* DDR multiPHY */
+static inline int ddrphy_get_rank(int dx)
+{
+ return dx / 2;
+}
+
+static void ddrphy_fifo_reset(void __iomem *phy_base)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR0);
+ tmp &= ~DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+
+ tmp |= DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR1);
+
+ if (enable)
+ tmp &= ~DMPHY_PGCR1_INHVT;
+ else
+ tmp |= DMPHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + DMPHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
+{
+ int dx;
+ u32 lcdlr1, rdqsd;
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqsd = clamp(rdqsd + step, 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
+ writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
+ readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
+{
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+ const int nr_dx = width / 8;
+ int dx, rank;
+ u32 gtr;
+ int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ gtr = readl(dx_base + DMPHY_DX_GTR);
+ for (rank = 0; rank < 4; rank++) {
+ dgsl = gtr & 0x7;
+ /* if dgsl is zero, this rank was not trained. skip. */
+ if (dgsl) {
+ dgsl_min = min(dgsl_min, dgsl);
+ dgsl_max = max(dgsl_max, dgsl);
+ }
+ gtr >>= 3;
+ }
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ if (dgsl_min != dgsl_max)
+ printf("DQS Gateing System Latencies are not all leveled.\n");
+
+ return dgsl_max;
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
+{
+ u32 tmp;
+ void __iomem *zq_base, *dx_base;
+ int zq, dx;
+ int nr_dx;
+
+ nr_dx = width / 8;
+
+ writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
+ /*
+ * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
+ * to avoid read error issue.
+ */
+ writel(0x07d81e37, phy_base + DMPHY_PGCR0);
+ writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
+
+ tmp = ddrphy_pgcr2[freq];
+ if (width >= 32)
+ tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
+ writel(tmp, phy_base + DMPHY_PGCR2);
+
+ writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
+ writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
+ writel(0x00083def, phy_base + DMPHY_PTR2);
+ writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
+ writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
+
+ writel(0x55555555, phy_base + DMPHY_ACIOCR1);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR2);
+ writel(0x55555555, phy_base + DMPHY_ACIOCR3);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR4);
+ writel(0x00000055, phy_base + DMPHY_ACIOCR5);
+ writel(0x00181aa4, phy_base + DMPHY_DXCCR);
+
+ writel(0x0024641e, phy_base + DMPHY_DSGCR);
+ writel(0x0000040b, phy_base + DMPHY_DCR);
+ writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
+ writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
+ writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
+ writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
+ writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
+ writel(0x00000006, phy_base + DMPHY_MR1);
+ writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
+ writel(0x00000000, phy_base + DMPHY_MR3);
+
+ tmp = 0;
+ for (dx = 0; dx < nr_dx; dx++)
+ tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
+ writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
+
+ writel(0x00000000, phy_base + DMPHY_DTAR0);
+ writel(0x00000008, phy_base + DMPHY_DTAR1);
+ writel(0x00000010, phy_base + DMPHY_DTAR2);
+ writel(0x00000018, phy_base + DMPHY_DTAR3);
+ writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
+ writel(0x7788bb44, phy_base + DMPHY_DTDR1);
+
+ /* impedance control settings */
+ writel(0x04048900, phy_base + DMPHY_ZQCR);
+
+ zq_base = phy_base + DMPHY_ZQ_BASE;
+ for (zq = 0; zq < 4; zq++) {
+ /*
+ * board-dependent
+ * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
+ */
+ writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
+ zq_base += DMPHY_ZQ_STRIDE;
+ }
+
+ /* DATX8 settings */
+ dx_base = phy_base + DMPHY_DX_BASE;
+ for (dx = 0; dx < 4; dx++) {
+ tmp = readl(dx_base + DMPHY_DX_GCR0);
+ tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
+ tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
+ DMPHY_DX_GCR0_WLRKEN_MASK;
+ writel(tmp, dx_base + DMPHY_DX_GCR0);
+
+ writel(0x00000000, dx_base + DMPHY_DX_GCR1);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR2);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR3);
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
+ cpu_relax();
+
+ ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
+ {
+ "Impedance Calibration",
+ DMPHY_PIR_ZCAL,
+ DMPHY_PGSR0_ZCDONE,
+ DMPHY_PGSR0_ZCERR,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence dram_init_sequence[] = {
+ {
+ "DRAM Initialization",
+ DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
+ DMPHY_PGSR0_DIDONE,
+ 0,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence training_sequence[] = {
+ {
+ "Write Leveling",
+ DMPHY_PIR_WL,
+ DMPHY_PGSR0_WLDONE,
+ DMPHY_PGSR0_WLERR,
+ },
+ {
+ "Read DQS Gate Training",
+ DMPHY_PIR_QSGATE,
+ DMPHY_PGSR0_QSGDONE,
+ DMPHY_PGSR0_QSGERR,
+ },
+ {
+ "Write Leveling Adjustment",
+ DMPHY_PIR_WLADJ,
+ DMPHY_PGSR0_WLADONE,
+ DMPHY_PGSR0_WLAERR,
+ },
+ {
+ "Read Bit Deskew",
+ DMPHY_PIR_RDDSKW,
+ DMPHY_PGSR0_RDDONE,
+ DMPHY_PGSR0_RDERR,
+ },
+ {
+ "Write Bit Deskew",
+ DMPHY_PIR_WRDSKW,
+ DMPHY_PGSR0_WDDONE,
+ DMPHY_PGSR0_WDERR,
+ },
+ {
+ "Read Eye Training",
+ DMPHY_PIR_RDEYE,
+ DMPHY_PGSR0_REDONE,
+ DMPHY_PGSR0_REERR,
+ },
+ {
+ "Write Eye Training",
+ DMPHY_PIR_WREYE,
+ DMPHY_PGSR0_WEDONE,
+ DMPHY_PGSR0_WEERR,
+ },
+ { /* sentinel */ }
+};
+
+static int __ddrphy_training(void __iomem *phy_base,
+ const struct ddrphy_init_sequence *seq)
+{
+ const struct ddrphy_init_sequence *s;
+ u32 pgsr0;
+ u32 init_flag = DMPHY_PIR_INIT;
+ u32 done_flag = DMPHY_PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (s = seq; s->description; s++) {
+ init_flag |= s->init_flag;
+ done_flag |= s->done_flag;
+ }
+
+ writel(init_flag, phy_base + DMPHY_PIR);
+
+ do {
+ if (--timeout < 0) {
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(phy_base + DMPHY_PGSR0);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (s = seq; s->description; s++) {
+ if (pgsr0 & s->err_flag) {
+ printf("%s: error: %s failed\n", __func__,
+ s->description);
+ return -EIO;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
+
+static int ddrphy_impedance_calibration(void __iomem *phy_base)
+{
+ int ret;
+ u32 tmp;
+
+ ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
+ if (ret)
+ return ret;
+
+ /*
+ * Because of a hardware bug, IDONE flag is set when the first ZQ block
+ * is calibrated. The flag does not guarantee the completion for all
+ * the ZQ blocks. Wait a little more just in case.
+ */
+ udelay(1);
+
+ /* reflect ZQ settings and enable average algorithm*/
+ tmp = readl(phy_base + DMPHY_ZQCR);
+ tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+ tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ tmp |= DMPHY_ZQCR_AVGEN;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+
+ return 0;
+}
+
+static int ddrphy_dram_init(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, dram_init_sequence);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, training_sequence);
+}
+
+/* UMC */
+static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency)
+{
+ u32 val;
+ int latency;
+
+ val = readl(umc_dc_base + UMC_RDATACTL_D0);
+ latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
+ latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
+ UMC_RDATACTL_RAD2LTY_SHIFT;
+ /*
+ * UMC works at the half clock rate of the PHY.
+ * The LSB of latency is ignored
+ */
+ latency += phy_latency & ~1;
+
+ val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, umc_dc_base + UMC_RDATACTL_D0);
+ writel(val, umc_dc_base + UMC_RDATACTL_D1);
+
+ readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */
+}
+
+/* enable/disable auto refresh */
+void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(umc_dc_base + UMC_SPCSETB);
+ tmp &= ~UMC_SPCSETB_AREFMD_MASK;
+
+ if (enable)
+ tmp |= UMC_SPCSETB_AREFMD_ARB;
+ else
+ tmp |= UMC_SPCSETB_AREFMD_REG;
+
+ writel(tmp, umc_dc_base + UMC_SPCSETB);
+ udelay(1);
+}
+
+static void umc_ud_init(void __iomem *umc_base, int ch)
+{
+ writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
+
+ if (ch == 2)
+ writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
+}
+
+static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
+ enum dram_size size, int ch, int width)
+{
+ int latency;
+ u32 val;
+
+ writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA);
+
+ writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
+ umc_dc_base + UMC_CMDCTLB);
+
+ writel(umc_spcctla[freq][size / (width / 16)],
+ umc_dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB);
+
+ val = 0x000e000e;
+ latency = 12;
+ /* ES2 inserted one more FF to the logic. */
+ if (uniphier_get_soc_model() >= 2)
+ latency += 2;
+
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, umc_dc_base + UMC_RDATACTL_D0);
+ if (width >= 32)
+ writel(val, umc_dc_base + UMC_RDATACTL_D1);
+
+ writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0);
+ if (width >= 32)
+ writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1);
+ writel(0x04000000, umc_dc_base + UMC_DATASET);
+ writel(0x00400020, umc_dc_base + UMC_DCCGCTL);
+ writel(0x00000084, umc_dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, umc_dc_base + UMC_ACSSETA);
+
+ writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
+ umc_dc_base + UMC_FLOWCTLA);
+
+ writel(0x00004400, umc_dc_base + UMC_FLOWCTLC);
+ writel(0x200A0A00, umc_dc_base + UMC_SPCSETB);
+ writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA);
+ writel(0x0000000D, umc_dc_base + UMC_RESPCTL);
+
+ if (ch != 2) {
+ writel(0x00202000, umc_dc_base + UMC_FLOWCTLB);
+ writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0);
+ writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1);
+ writel(0x00080700, umc_dc_base + UMC_BSICMAPSET);
+ } else {
+ writel(0x00200000, umc_dc_base + UMC_FLOWCTLB);
+ writel(0x00000000, umc_dc_base + UMC_BSICMAPSET);
+ }
+
+ writel(0x00000000, umc_dc_base + UMC_ERRMASKA);
+ writel(0x00000000, umc_dc_base + UMC_ERRMASKB);
+}
+
+static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch,
+ enum dram_size size, int width)
+{
+ void __iomem *umc_dc_base = umc_base + 0x00011000;
+ void __iomem *phy_base = umc_base + 0x00030000;
+ int ret;
+
+ writel(0x00000002, umc_dc_base + UMC_INITSET);
+ while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2))
+ cpu_relax();
+
+ /* deassert PHY reset signals */
+ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+ umc_dc_base + UMC_DIOCTLA);
+
+ ddrphy_init(phy_base, freq, width);
+
+ ret = ddrphy_impedance_calibration(phy_base);
+ if (ret)
+ return ret;
+
+ ddrphy_dram_init(phy_base);
+ if (ret)
+ return ret;
+
+ umc_dc_init(umc_dc_base, freq, size, ch, width);
+
+ umc_ud_init(umc_base, ch);
+
+ if (size) {
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+ }
+
+ udelay(1);
+
+ /* match the system latency between UMC and PHY */
+ umc_set_system_latency(umc_dc_base,
+ ddrphy_get_system_latency(phy_base, width));
+
+ udelay(1);
+
+ /* stop auto refresh before clearing FIFO in PHY */
+ umc_refresh_ctrl(umc_dc_base, 0);
+ ddrphy_fifo_reset(phy_base);
+ umc_refresh_ctrl(umc_dc_base, 1);
+
+ udelay(10);
+
+ return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x000000ff, um_base + UMC_MBUS0);
+ writel(0x000000ff, um_base + UMC_MBUS1);
+ writel(0x000000ff, um_base + UMC_MBUS2);
+ writel(0x000000ff, um_base + UMC_MBUS3);
+}
+
+int proxstream2_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5b600000;
+ void __iomem *umc_ch0_base = (void __iomem *)0x5b800000;
+ void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000;
+ void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000;
+ enum dram_freq freq;
+ int ret;
+
+ switch (bd->dram_freq) {
+ case 1866:
+ freq = FREQ_1866M;
+ break;
+ case 2133:
+ freq = FREQ_2133M;
+ break;
+ default:
+ printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M,
+ bd->dram_ch0_width);
+ if (ret) {
+ printf("failed to initialize UMC ch0\n");
+ return ret;
+ }
+
+ ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M,
+ bd->dram_ch1_width);
+ if (ret) {
+ printf("failed to initialize UMC ch1\n");
+ return ret;
+ }
+
+ ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M,
+ bd->dram_ch2_width);
+ if (ret) {
+ printf("failed to initialize UMC ch2\n");
+ return ret;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+int proxstream2_umc_init(const struct uniphier_board_data *bd);
void ph1_sld3_pin_init(void);
void ph1_ld4_pin_init(void);
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_ld4_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro4_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro5_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld3_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld8_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int proxstream2_init(const struct uniphier_board_data *bd)
{
+ int ret;
+
proxstream2_sbc_init(bd);
support_card_reset();
led_puts("L4");
+ ret = proxstream2_umc_init(bd);
+ if (ret)
+ return ret;
+
+ led_puts("L5");
+
return 0;
}
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/soc_info.h>
+
+#include "../init.h"
+#include "../soc-info.h"
void spl_board_init(void)
{
*/
#include <linux/linkage.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
ldr r1, = SSCC
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
-#include <mach/arm-mpcore.h>
-#include <mach/sbc-regs.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int proxstream2_memconf_init(const struct uniphier_board_data *bd)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int memconf_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/ctype.h>
#include <linux/io.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
#define MICRO_SUPPORT_CARD_BASE 0x43f00000
#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
-#include <mach/sbc-regs.h>
struct memory_bank {
phys_addr_t base;
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld4_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld6b_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro4_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro5_pin_init(void)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld3_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld8_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void proxstream2_pin_init(void)
{
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
+#include "../init.h"
int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
static void dpll_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/micro-support-card.h>
+#include "micro-support-card.h"
int misc_init_f(void)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/sc-regs.h>
+
+#include "sc-regs.h"
void reset_cpu(unsigned long ignored)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int proxstream2_sbc_init(const struct uniphier_board_data *bd)
{
#include <linux/io.h>
#include <linux/types.h>
-#include <mach/sg-regs.h>
-#include <mach/soc_info.h>
+
+#include "sg-regs.h"
+#include "soc-info.h"
#if UNIPHIER_MULTI_SOC
enum uniphier_soc_id uniphier_get_soc_type(void)
#include <common.h>
#include <linux/io.h>
-#include <mach/arm-mpcore.h>
+
+#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = dram.o
-obj-y += gpio.o
-obj-$(CONFIG_ARMADA_XP) += mbus.o
-obj-y += timer.o
-
-obj-y += serdes/
addi r8, r0, __end
mts rslr, r8
- /* TODO: Redo this code to call board_init_f_mem() */
+ /* TODO: Redo this code to call board_init_f_*() */
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
mts rshr, r1
ori r12, r12, 0x1a0
mts rmsr, r12
- /* TODO: Redo this code to call board_init_f_mem() */
+ /* TODO: Redo this code to call board_init_f_*() */
clear_bss:
/* clear BSS segments */
addi r5, r0, __bss_start
stw r0, 4(sp)
mov fp, sp
- /* Allocate and zero GD, update SP */
+ /* Allocate and initialize reserved area, update SP */
mov r4, sp
- movhi r2, %hi(board_init_f_mem@h)
- ori r2, r2, %lo(board_init_f_mem@h)
+ movhi r2, %hi(board_init_f_alloc_reserve@h)
+ ori r2, r2, %lo(board_init_f_alloc_reserve@h)
callr r2
-
- /* Update stack- and frame-pointers */
mov sp, r2
+ mov r4, sp
+ movhi r2, %hi(board_init_f_init_reserve@h)
+ ori r2, r2, %lo(board_init_f_init_reserve@h)
+ callr r2
+
+ /* Update frame-pointer */
mov fp, sp
/* Call board_init_f -- never returns */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mr r1, r3
+ bl board_init_f_init_reserve
li r0,0
stwu r0, -4(r1)
stwu r0, -4(r1)
bl cpu_init_f /* run low-level CPU init code (from Flash) */
#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mr r1, r3
+ bl board_init_f_init_reserve
stwu r0, -4(r1)
stwu r0, -4(r1)
#endif
printf("Failed to set promiscuous mode: %d %s\n"
"Falling back to the old \"flags\" way...\n",
errno, strerror(errno));
+ if (strlen(ifname) >= IFNAMSIZ) {
+ printf("Interface name %s is too long.\n", ifname);
+ return -EINVAL;
+ }
strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) {
printf("Failed to read flags: %d %s\n", errno,
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("ValleyView SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported);
}
#ifndef CONFIG_EFI_APP
debug("%s: Cannot find GMA node\n", __func__);
return -EINVAL;
}
- ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
- gma_node);
+ ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
+ if (ret)
+ return ret;
+ ret = gma_func0_init(dev, blob, gma_node);
if (ret)
return ret;
return res;
}
-int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
- const void *blob, int node)
+int gma_func0_init(struct udevice *dev, const void *blob, int node)
{
#ifdef CONFIG_VIDEO
ulong start;
int ret;
/* IGD needs to be Bus Master */
- reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
+ dm_pci_read_config32(dev, PCI_COMMAND, ®32);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- x86_pci_write_config32(dev, PCI_COMMAND, reg32);
+ dm_pci_write_config32(dev, PCI_COMMAND, reg32);
/* Use write-combining for the graphics memory, 256MB */
- base = pci_read_bar32(hose, dev, 2);
+ base = dm_pci_read_bar32(dev, 2);
mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
mtrr_commit(true);
- gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
+ gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
debug("GT bar %p\n", gtt_bar);
ret = gma_pm_init_pre_vbios(gtt_bar);
if (ret)
#ifdef CONFIG_VIDEO
start = get_timer(0);
- ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
+ ret = dm_pci_run_vga_bios(dev, int15_handler,
+ PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
debug("BIOS ran in %lums\n", get_timer(start));
#endif
/* Post VBIOS init */
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
+ {},
};
/*
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Quark SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Quark SDHCI", mmc_supported);
}
void cpu_irq_init(void)
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Topcliff SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Topcliff SDHCI", mmc_supported);
}
#endif
/* Set up global data */
mov %esp, %eax
- call board_init_f_mem
+ call board_init_f_alloc_reserve
mov %eax, %esp
+ call board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
call debug_uart_init
void bd82x6x_pci_init(pci_dev_t dev);
void bd82x6x_usb_ehci_init(pci_dev_t dev);
void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
- const void *blob, int node);
+int gma_func0_init(struct udevice *dev, const void *blob, int node);
int bd82x6x_init(void);
/**
vbe_set_mode(mode_info);
}
-void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
struct vbe_mode_info *mode_info)
{
+ pci_dev_t pcidev = dm_pci_get_bdf(dev);
u32 num_dev;
num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 |
unsigned short func = (unsigned short)M.x86.R_EAX;
int retval = 1;
unsigned short devid, vendorid, devfn;
+ struct udevice *dev;
/* Use short to get rid of gabage in upper half of 32-bit register */
short devindex;
unsigned char bus;
- pci_dev_t dev;
+ pci_dev_t bdf;
u32 dword;
u16 word;
u8 byte, reg;
+ int ret;
switch (func) {
case 0xb101: /* PCIBIOS Check */
devid = M.x86.R_ECX;
vendorid = M.x86.R_EDX;
devindex = M.x86.R_ESI;
- dev = pci_find_device(vendorid, devid, devindex);
- if (dev != -1) {
+ bdf = -1;
+ ret = dm_pci_find_device(vendorid, devid, devindex, &dev);
+ if (!ret) {
unsigned short busdevfn;
+
+ bdf = dm_pci_get_bdf(dev);
M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
/*
* busnum is an unsigned char;
* devfn is an int, so we mask it off.
*/
- busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 |
- PCI_FUNC(dev);
+ busdevfn = (PCI_BUS(bdf) << 8) | PCI_DEV(bdf) << 3 |
+ PCI_FUNC(bdf);
debug("0x%x: return 0x%x\n", func, busdevfn);
M.x86.R_EBX = busdevfn;
retval = 1;
devfn = M.x86.R_EBX & 0xff;
bus = M.x86.R_EBX >> 8;
reg = M.x86.R_EDI;
- dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
+ bdf = PCI_BDF(bus, devfn >> 3, devfn & 7);
+
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
+ if (ret) {
+ debug("%s: Device %x not found\n", __func__, bdf);
+ break;
+ }
switch (func) {
case 0xb108: /* Read Config Byte */
- byte = x86_pci_read_config8(dev, reg);
+ dm_pci_read_config8(dev, reg, &byte);
M.x86.R_ECX = byte;
break;
case 0xb109: /* Read Config Word */
- word = x86_pci_read_config16(dev, reg);
+ dm_pci_read_config16(dev, reg, &word);
M.x86.R_ECX = word;
break;
case 0xb10a: /* Read Config Dword */
- dword = x86_pci_read_config32(dev, reg);
+ dm_pci_read_config32(dev, reg, &dword);
M.x86.R_ECX = dword;
break;
case 0xb10b: /* Write Config Byte */
byte = M.x86.R_ECX;
- x86_pci_write_config8(dev, reg, byte);
+ dm_pci_write_config8(dev, reg, byte);
break;
case 0xb10c: /* Write Config Word */
word = M.x86.R_ECX;
- x86_pci_write_config16(dev, reg, word);
+ dm_pci_write_config16(dev, reg, word);
break;
case 0xb10d: /* Write Config Dword */
dword = M.x86.R_ECX;
- x86_pci_write_config32(dev, reg, dword);
+ dm_pci_write_config32(dev, reg, dword);
break;
}
-
#ifdef CONFIG_REALMODE_DEBUG
debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
bus, devfn, reg, M.x86.R_ECX);
/*
* The second time we enter here, adjust the size of malloc()
* pool before relocation. Given gd->malloc_base was adjusted
- * after the call to board_init_f_mem() in arch/x86/cpu/start.S,
- * we should fix up gd->malloc_limit here.
+ * after the call to board_init_f_init_reserve() in arch/x86/
+ * cpu/start.S, we should fix up gd->malloc_limit here.
*/
gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
}
+++ /dev/null
-if TARGET_DB_88F6820_GP
-
-config SYS_BOARD
- default "db-88f6820-gp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-88f6820-gp"
-
-endif
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-if TARGET_DB_MV784MP_GP
-
-config SYS_BOARD
- default "db-mv784mp-gp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-mv784mp-gp"
-
-endif
return pci_eth_init(bis);
}
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1545 PHY */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
{
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- u16 devadr = phy_addr[0];
- char *name = "neta0";
u16 reg;
- if (miiphy_set_current_dev(name))
- return;
-
/* Enable QSGMII AN */
/* Set page to 4 */
- miiphy_write(name, devadr, 0x16, 4);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
/* Enable AN */
- miiphy_write(name, devadr, 0x0, 0x1140);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
/* Set page to 0 */
- miiphy_write(name, devadr, 0x16, 0);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
/* Phy C_ANEG */
- miiphy_read(name, devadr, 0x4, ®);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
reg |= 0x1E0;
- miiphy_write(name, devadr, 0x4, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
/* Soft-Reset */
- miiphy_write(name, devadr, 22, 0x0000);
- miiphy_write(name, devadr, 0, 0x9140);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
/* Power up the phy */
- miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
- miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
- printf("88E1545 Initialized on %s\n", name);
+ printf("88E1545 Initialized\n");
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
--- /dev/null
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cmd_syno.o
--- /dev/null
+/*
+ * Commands to deal with Synology specifics.
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/io.h>
+#include "../drivers/ddr/marvell/axp/ddr3_init.h"
+
+#define ETH_ALEN 6
+#define ETHADDR_MAX 4
+#define SYNO_SN_TAG "SN="
+#define SYNO_CHKSUM_TAG "CHK="
+
+
+static int do_syno_populate(int argc, char * const argv[])
+{
+ unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+ unsigned int cs = CONFIG_SF_DEFAULT_CS;
+ unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
+ unsigned int mode = CONFIG_SF_DEFAULT_MODE;
+ struct spi_flash *flash;
+ unsigned long addr = 0x80000; /* XXX: parameterize this? */
+ loff_t offset = 0x007d0000;
+ loff_t len = 0x00010000;
+ char *buf, *bufp;
+ char var[128];
+ char val[128];
+ int ret, n;
+
+ /* XXX: arg parsing to select flash here? */
+
+ flash = spi_flash_probe(bus, cs, speed, mode);
+ if (!flash) {
+ printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
+ return 1;
+ }
+
+ buf = map_physmem(addr, len, MAP_WRBACK);
+ if (!buf) {
+ puts("Failed to map physical memory\n");
+ return 1;
+ }
+
+ ret = spi_flash_read(flash, offset, len, buf);
+ if (ret) {
+ puts("Failed to read from SPI flash\n");
+ goto out_unmap;
+ }
+
+ for (n = 0; n < ETHADDR_MAX; n++) {
+ char ethaddr[ETH_ALEN];
+ int i, sum = 0;
+ unsigned char csum = 0;
+
+ for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) {
+ sum += bufp[i];
+ csum += bufp[i];
+ ethaddr[i] = bufp[i];
+ }
+ if (!sum) /* MAC address empty */
+ continue;
+ if (csum != bufp[i]) { /* seventh byte is checksum value */
+ printf("Invalid MAC address for interface %d!\n", n);
+ continue;
+ }
+ if (n == 0)
+ sprintf(var, "ethaddr");
+ else
+ sprintf(var, "eth%daddr", n);
+ snprintf(val, sizeof(val) - 1,
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ ethaddr[0], ethaddr[1], ethaddr[2],
+ ethaddr[3], ethaddr[4], ethaddr[5]);
+ printf("parsed %s = %s\n", var, val);
+ setenv(var, val);
+ }
+ if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) {
+ char *snp, *csump;
+ int csum = 0;
+ unsigned long c;
+
+ snp = bufp = buf + 32 + strlen(SYNO_SN_TAG);
+ for (n = 0; bufp[n] && bufp[n] != ','; n++)
+ csum += bufp[n];
+ bufp[n] = '\0';
+
+ /* should come right after, but you never know */
+ bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG);
+ if (!bufp) {
+ printf("Serial number checksum tag missing!\n");
+ goto out_unmap;
+ }
+
+ csump = bufp += strlen(SYNO_CHKSUM_TAG);
+ for (n = 0; bufp[n] && bufp[n] != ','; n++)
+ ;
+ bufp[n] = '\0';
+
+ if (strict_strtoul(csump, 10, &c) || c != csum) {
+ puts("Invalid serial number found!\n");
+ ret = 1;
+ goto out_unmap;
+ }
+ printf("parsed SN = %s\n", snp);
+ setenv("SN", snp);
+ } else { /* old style format */
+ unsigned char csum = 0;
+
+ for (n = 0, bufp = buf + 32; n < 10; n++)
+ csum += bufp[n];
+
+ if (csum != bufp[n]) {
+ puts("Invalid serial number found!\n");
+ ret = 1;
+ goto out_unmap;
+ }
+ bufp[n] = '\0';
+ printf("parsed SN = %s\n", buf + 32);
+ setenv("SN", buf + 32);
+ }
+out_unmap:
+ unmap_physmem(buf, len);
+ return ret;
+}
+
+/* map bit position to function in POWER_MNG_CTRL_REG */
+static const char * const pwr_mng_bit_func[] = {
+ "audio",
+ "ge3", "ge2", "ge1", "ge0",
+ "pcie00", "pcie01", "pcie02", "pcie03",
+ "pcie10", "pcie11", "pcie12", "pcie13",
+ "bp",
+ "sata0_link", "sata0_core",
+ "lcd",
+ "sdio",
+ "usb0", "usb1", "usb2",
+ "idma", "xor0", "crypto",
+ NULL,
+ "tdm",
+ "pcie20", "pcie30",
+ "xor1",
+ "sata1_link", "sata1_core",
+ NULL,
+};
+
+static int do_syno_clk_gate(int argc, char * const argv[])
+{
+ u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+ const char *func, *state;
+ int i, val;
+
+ if (argc < 2)
+ return -1;
+
+ if (!strcmp(argv[1], "get")) {
+ puts("Clock Gating:\n");
+ for (i = 0; i < 32; i++) {
+ func = pwr_mng_bit_func[i];
+ if (!func)
+ continue;
+ state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF";
+ printf("%s:\t\t%s\n", func, state);
+ }
+ return 0;
+ }
+ if (argc < 4)
+ return -1;
+ if (!strcmp(argv[1], "set")) {
+ func = argv[2];
+ state = argv[3];
+ for (i = 0; i < 32; i++) {
+ if (!pwr_mng_bit_func[i])
+ continue;
+ if (!strcmp(func, pwr_mng_bit_func[i]))
+ break;
+ }
+ if (i == 32) {
+ printf("Error: name '%s' not known\n", func);
+ return -1;
+ }
+ val = state[0] != '0';
+ pwr_mng_ctrl_reg |= (val << i);
+ pwr_mng_ctrl_reg &= ~(!val << i);
+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+ }
+ return 0;
+}
+
+static int do_syno(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ const char *cmd;
+ int ret = 0;
+
+ if (argc < 2)
+ goto usage;
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (!strcmp(cmd, "populate_env"))
+ ret = do_syno_populate(argc, argv);
+ else if (!strcmp(cmd, "clk_gate"))
+ ret = do_syno_clk_gate(argc, argv);
+
+ if (ret != -1)
+ return ret;
+usage:
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ syno, 5, 1, do_syno,
+ "Synology specific commands",
+ "populate_env - Read vendor data from SPI flash into environment\n"
+ "clk_gate (get|set name 1|0) - Manage clock gating\n"
+);
--- /dev/null
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ds414.o
--- /dev/null
+/*
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
+
+#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30))
+#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15))
+#define DS414_GPP_OUT_VAL_HIGH (0)
+
+#define DS414_GPP_OUT_POL_LOW (0)
+#define DS414_GPP_OUT_POL_MID (0)
+#define DS414_GPP_OUT_POL_HIGH (0)
+
+#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30)))
+#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \
+ BIT(13) | BIT(14) | BIT(15)))
+#define DS414_GPP_OUT_ENA_HIGH (~0)
+
+static const u32 ds414_mpp_control[] = {
+ 0x11111111,
+ 0x22221111,
+ 0x22222222,
+ 0x00000000,
+ 0x11110000,
+ 0x00004000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+/* DDR3 static MC configuration */
+
+/* 1G_v1 (4x2Gbits) adapted by DS414 */
+MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
+ {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
+ {0x00001404, 0x30000800}, /*Dunit Control Low Register */
+ {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
+ {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
+
+ {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
+
+ {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
+ {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
+ {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
+ {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
+ {0x00001428, 0x000F8830}, /*Dunit Control High Register */
+ {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
+ {0x0000147C, 0x0000C671},
+
+ {0x000014a0, 0x00000001},
+ {0x000014a8, 0x00000100}, /*2:1 */
+ {0x00020220, 0x00000006},
+
+ {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
+ {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
+ {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
+
+ {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
+ {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
+
+ {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
+ {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
+
+ {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
+ {0x000150C, 0x00000000}, /* CS1 Size */
+ {0x0001514, 0x00000000}, /* CS2 Size */
+ {0x000151C, 0x00000000}, /* CS3 Size */
+
+ {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
+ {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
+
+ {0x000015D0, 0x00000650}, /*MR0 */
+ {0x000015D4, 0x00000044}, /*MR1 */
+ {0x000015D8, 0x00000010}, /*MR2 */
+ {0x000015DC, 0x00000000}, /*MR3 */
+
+ {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
+ {0x000015EC, 0xF800A225}, /*DDR PHY */
+
+ {0x0, 0x0}
+};
+
+MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+ {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
+ { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
+ { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
+ PEX_BUS_DISABLED },
+ 0x0040, serdes_change_m_phy
+ }
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+ return &ds414_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ return &ds414_serdes_cfg[0];
+}
+
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ return (0x1 << 1 | 1);
+}
+
+int board_early_init_f(void)
+{
+ int i;
+
+ /* Set GPP Out value */
+ reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
+ reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
+ reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
+
+ /* set GPP polarity */
+ reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
+ reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
+ reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
+
+ /* Set GPP Out Enable */
+ reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
+ reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
+ reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
+
+ for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
+ reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ u32 pwr_mng_ctrl_reg;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Gate unused clocks
+ *
+ * Note: Disabling unused PCIe lanes will hang PCI bus scan.
+ * Once this is resolved, bits 10-12, 26 and 27 can be
+ * unset here as well.
+ */
+ pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+ pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
+ pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */
+ pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */
+ pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
+ pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
+ pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */
+ pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */
+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: DS414\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include <i2c.h>
-#include <netdev.h>
void pin_mux_usb(void)
{
/* For CD GPIO PP1 */
pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
-
-#ifdef CONFIG_PCI
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-#endif
return 1;
/* read out the first block, get the config data information */
- n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
ofs = src % blk_len;
if (ofs) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1,
tmp_buf);
if (!n)
goto failure;
}
cnt = size / blk_len;
if (cnt) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no, cnt,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no, cnt,
dst);
if (n != cnt)
goto failure;
block_no += cnt;
}
if (size) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1,
tmp_buf);
if (!n)
goto failure;
return 1;
/* read out the first block, get the config data information */
- n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \
/* GPMC */ \
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
+ MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
+ MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\
MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\
MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\
MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \
MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \
MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \
/* MMC1 */ \
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /* MMC1_CMD */ \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /* MMC1_DAT0 */ \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /* MMC1_DAT1 */ \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /* MMC1_DAT2 */ \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /* MMC1_DAT3 */ \
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \
/* UART2 */ \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | DIS | M0)) /* UART2_CTS */ \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTU | DIS | M0)) /* UART2_RTS */ \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \
/* UART1 */ \
- MUX_VAL(CP(UART1_TX), (IDIS | PTU | DIS | M0)) /* UART1_TX */ \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTU | DIS | M0)) /* UART1_RTS */ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */ \
- MUX_VAL(CP(UART1_RX), (IEN | PTU | DIS | M0)) /* UART1_RX */ \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \
/* MCBSP4 */ \
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \
/* I2C2 */ \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /* I2C2_SCL */ \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /* I2C2_SDA */ \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \
/* I2C3 */ \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /* I2C3_SCL */ \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /* I2C3_SDA */ \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \
/* I2C4 */ \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \
MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \
/* SYS */ \
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \
/* JTAG */ \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | DIS | M0)) /* JTAG_EMU0 */ \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | DIS | M0)) /* JTAG_EMU1 */ \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \
/* ETK */ \
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \
MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \
MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \
MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \
- MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \
+ MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \
MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \
MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \
MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \
+++ /dev/null
-if TARGET_MAXBCM
-
-config SYS_BOARD
- default "maxbcm"
-
-config SYS_CONFIG_NAME
- default "maxbcm"
-
-endif
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
return 0;
}
-#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E6185 switch */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
{
- char *name = "neta0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* todo: fill this with the real setup / config code */
-
- printf("88E6185 Initialized on %s\n", name);
+ /*
+ * todo:
+ * Fill this with the real setup / config code.
+ * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+ * for details.
+ */
+ printf("88E6185 Initialized\n");
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
#include <asm/gpio.h>
#include "pinmux-config-cardhu.h"
#include <i2c.h>
-#include <netdev.h>
#define PMU_I2C_ADDRESS 0x2D
#define MAX_I2C_RETRY 3
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
*/
#include <common.h>
-#include <netdev.h>
#include <power/as3722.h>
#include <asm/arch/gpio.h>
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
*/
#include <common.h>
-#include <netdev.h>
#include <i2c.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
--- /dev/null
+CLEARFOG BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/soldrun/clearfog/
+F: include/configs/clearfog.h
+F: configs/clearfog_defconfig
--- /dev/null
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := clearfog.o
--- /dev/null
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+Generate the U-Boot image with these commands:
+
+$ make clearfog_defconfig
+$ make
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+Now all you need to do is copy this image on a SD card.
+For example with this command:
+
+$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
+
+Please use the correct device node for your setup instead
+of "/dev/sdX" here!
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG 0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-15t1-clearfog"
+ */
+#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
+#define BOARD_GPP_OUT_ENA_MID 0xffffffff
+
+#define BOARD_GPP_OUT_VAL_LOW 0x0
+#define BOARD_GPP_OUT_VAL_MID 0x0
+#define BOARD_GPP_POL_LOW 0x0
+#define BOARD_GPP_POL_MID 0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+ u8 chip;
+ u8 addr;
+ u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+ { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */
+ { 0x20, 6, 0xf9 },
+ { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */
+ { 0x20, 6, 0xb9 },
+ { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */
+ { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */
+};
+
+static struct serdes_map board_serdes_map[] = {
+ {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_LOW} }, /* temperature */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+ writel(0x10400011, MVEBU_MPP_BASE + 0x08);
+ writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
+ writel(0x44400002, MVEBU_MPP_BASE + 0x10);
+ writel(0x41144004, MVEBU_MPP_BASE + 0x14);
+ writel(0x40333333, MVEBU_MPP_BASE + 0x18);
+ writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int i;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Toggle GPIO41 to reset onboard switch and phy */
+ clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+ clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
+ mdelay(1);
+ setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+ mdelay(10);
+
+ /* Init I2C IO expanders */
+ for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+ i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: SolidRun ClearFog\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
--- /dev/null
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM sdio
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
#include <asm/io.h>
#include <dm.h>
#include <i2c.h>
-#include <netdev.h>
#include "pinmux-config-apalis_t30.h"
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* CONFIG_PCI_TEGRA */
help
Extract a part of a multi-image.
+config CMD_POWEROFF
+ bool
+
endmenu
menu "Environment commands"
flag = 0; /* assume no special flags for now */
if (len > 0)
- strcpy(lastcommand, console_buffer);
+ strlcpy(lastcommand, console_buffer,
+ CONFIG_SYS_CBSIZE + 1);
else if (len == 0)
flag |= CMD_FLAG_REPEAT;
#ifdef CONFIG_BOOT_RETRY_TIME
"Perform RESET of the CPU",
""
);
+
+#ifdef CONFIG_CMD_POWEROFF
+U_BOOT_CMD(
+ poweroff, 1, 0, do_poweroff,
+ "Perform POWEROFF of the device",
+ ""
+);
+#endif
", Block Size: %ld\n",
info.start, info.size, info.blksz);
- if (dev_desc->block_read(dev, info.start, 1, (ulong *) addr) != 1) {
+ if (dev_desc->block_read(dev_desc, info.start, 1, (ulong *)addr) != 1) {
printf("** Read error on %d:%d\n", dev, part);
bootstage_error(BOOTSTAGE_ID_IDE_PART_READ);
return 1;
cnt /= info.blksz;
cnt -= 1;
- if (dev_desc->block_read(dev, info.start + 1, cnt,
- (ulong *)(addr + info.blksz)) != cnt) {
+ if (dev_desc->block_read(dev_desc, info.start + 1, cnt,
+ (ulong *)(addr + info.blksz)) != cnt) {
printf("** Read error on %d:%d\n", dev, part);
bootstage_error(BOOTSTAGE_ID_IDE_READ);
return 1;
#ifdef CONFIG_ATAPI
static void atapi_inquiry(block_dev_desc_t *dev_desc);
-static ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer);
+static ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
#endif
if (strcmp(argv[1], "read") == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ block_dev_desc_t *dev_desc;
ulong n;
#ifdef CONFIG_SYS_64BIT_LBA
curr_device, blk, cnt);
#endif
- n = ide_dev_desc[curr_device].block_read(curr_device,
- blk, cnt,
- (ulong *)addr);
+ dev_desc = &ide_dev_desc[curr_device];
+ n = dev_desc->block_read(dev_desc, blk, cnt,
+ (ulong *)addr);
/* flush cache after read */
flush_cache(addr,
cnt * ide_dev_desc[curr_device].blksz);
printf("\nIDE write: device %d block # %ld, count %ld ... ",
curr_device, blk, cnt);
#endif
- n = ide_write(curr_device, blk, cnt, (ulong *) addr);
+ n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
+ (ulong *)addr);
printf("%ld blocks written: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
/* ------------------------------------------------------------------------- */
-ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char c;
unsigned char pwrsave = 0; /* power save */
/* ------------------------------------------------------------------------- */
-ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt, const void *buffer)
+ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char c;
#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char ccb[12]; /* Command descriptor block */
ulong cnt;
return CMD_RET_FAILURE;
}
/* Switch to the RPMB partition */
- original_part = mmc->part_num;
- if (mmc->part_num != MMC_PART_RPMB) {
- if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0)
- return CMD_RET_FAILURE;
- mmc->part_num = MMC_PART_RPMB;
- }
+ original_part = mmc->block_dev.part_num;
+ if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
+ return CMD_RET_FAILURE;
ret = cp->cmd(cmdtp, flag, argc, argv);
/* Return to original partition */
- if (mmc->part_num != original_part) {
- if (mmc_switch_part(curr_device, original_part) != 0)
- return CMD_RET_FAILURE;
- mmc->part_num = original_part;
- }
+ if (mmc_select_hwpart(curr_device, original_part) != 0)
+ return CMD_RET_FAILURE;
return ret;
}
#endif
printf("\nMMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
- n = mmc->block_dev.block_read(curr_device, blk, cnt, addr);
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_write(curr_device, blk, cnt, addr);
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk, cnt, addr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_erase(curr_device, blk, cnt);
+ n = mmc->block_dev.block_erase(&mmc->block_dev, blk, cnt);
printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("mmc%d is current device\n", curr_device);
else
printf("mmc%d(part %d) is current device\n",
- curr_device, mmc->part_num);
+ curr_device, mmc->block_dev.hwpart);
return CMD_RET_SUCCESS;
}
}
#ifdef CONFIG_DM_PCI
- ret = pci_bus_find_bdf(bdf, &dev);
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
if (ret) {
printf("No such device\n");
return CMD_RET_FAILURE;
return 1;
}
- if (dev_desc->block_read(dev, offset + blk, cnt, addr) < 0) {
+ if (dev_desc->block_read(dev_desc, offset + blk, cnt, addr) < 0) {
printf("Error reading blocks\n");
return 1;
}
static int sata_curr_device = -1;
block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+static unsigned long sata_bread(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
+{
+ return sata_read(block_dev->dev, start, blkcnt, dst);
+}
+
+static unsigned long sata_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ return sata_write(block_dev->dev, start, blkcnt, buffer);
+}
+
int __sata_initialize(void)
{
int rc;
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].blksz = 512;
sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
- sata_dev_desc[i].block_read = sata_read;
- sata_dev_desc[i].block_write = sata_write;
+ sata_dev_desc[i].block_read = sata_bread;
+ sata_dev_desc[i].block_write = sata_bwrite;
rc = init_sata(i);
if (!rc) {
static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
unsigned long *blksz);
-static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer);
-static ulong scsi_write(int device, lbaint_t blknr,
+static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
+static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer);
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
void scsi_init(void)
{
- int busdevfunc;
+ int busdevfunc = -1;
int i;
/*
* Find a device from the list, this driver will support a single
*/
for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
/* get PCI Device ID */
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_find_device(scsi_device_list[i].vendor,
+ scsi_device_list[i].device, 0, &dev);
+ if (!ret) {
+ busdevfunc = dm_pci_get_bdf(dev);
+ break;
+ }
+#else
busdevfunc = pci_find_device(scsi_device_list[i].vendor,
scsi_device_list[i].device,
0);
+#endif
if (busdevfunc != -1)
break;
}
ulong n;
printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
scsi_curr_dev, blk, cnt);
- n = scsi_read(scsi_curr_dev, blk, cnt, (ulong *)addr);
+ n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
+ blk, cnt, (ulong *)addr);
printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
return 0;
} else if (strcmp(argv[1], "write") == 0) {
printf("\nSCSI write: device %d block # %ld, "
"count %ld ... ",
scsi_curr_dev, blk, cnt);
- n = scsi_write(scsi_curr_dev, blk, cnt,
- (ulong *)addr);
+ n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
+ blk, cnt, (ulong *)addr);
printf("%ld blocks written: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
return 0;
#define SCSI_MAX_READ_BLK 0xFFFF
#define SCSI_LBA48_READ 0xFFFFFFF
-static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
+static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
/* Almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_WRITE_BLK 0xFFFF
-static ulong scsi_write(int device, lbaint_t blknr,
+static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
printf("\nUSB read: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
- n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt,
+ n = stor_dev->block_read(stor_dev, blk, cnt,
(ulong *)addr);
printf("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
printf("\nUSB write: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
- n = stor_dev->block_write(usb_stor_curr_dev, blk, cnt,
+ n = stor_dev->block_write(stor_dev, blk, cnt,
(ulong *)addr);
printf("%ld blocks write: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
static int ums_read_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf)
{
- block_dev_desc_t *block_dev = ums_dev->block_dev;
+ block_dev_desc_t *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
- return block_dev->block_read(dev_num, blkstart, blkcnt, buf);
+ return block_dev->block_read(block_dev, blkstart, blkcnt, buf);
}
static int ums_write_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, const void *buf)
{
- block_dev_desc_t *block_dev = ums_dev->block_dev;
+ block_dev_desc_t *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
- return block_dev->block_write(dev_num, blkstart, blkcnt, buf);
+ return block_dev->block_write(block_dev, blkstart, blkcnt, buf);
+}
+
+static struct ums *ums;
+static int ums_count;
+
+static void ums_fini(void)
+{
+ int i;
+
+ for (i = 0; i < ums_count; i++)
+ free((void *)ums[i].name);
+ free(ums);
+ ums = 0;
+ ums_count = 0;
}
-static struct ums ums_dev = {
- .read_sector = ums_read_sector,
- .write_sector = ums_write_sector,
- .name = "UMS disk",
-};
+#define UMS_NAME_LEN 16
-struct ums *ums_init(const char *devtype, const char *devnum)
+static int ums_init(const char *devtype, const char *devnums)
{
+ char *s, *t, *devnum, *name;
block_dev_desc_t *block_dev;
int ret;
+ struct ums *ums_new;
- ret = get_device(devtype, devnum, &block_dev);
- if (ret < 0)
- return NULL;
+ s = strdup(devnums);
+ if (!s)
+ return -1;
+
+ t = s;
+ ums_count = 0;
+
+ for (;;) {
+ devnum = strsep(&t, ",");
+ if (!devnum)
+ break;
+
+ ret = get_device(devtype, devnum, &block_dev);
+ if (ret < 0)
+ goto cleanup;
+
+ /* f_mass_storage.c assumes SECTOR_SIZE sectors */
+ if (block_dev->blksz != SECTOR_SIZE) {
+ ret = -1;
+ goto cleanup;
+ }
- /* f_mass_storage.c assumes SECTOR_SIZE sectors */
- if (block_dev->blksz != SECTOR_SIZE)
- return NULL;
+ ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
+ if (!ums_new) {
+ ret = -1;
+ goto cleanup;
+ }
+ ums = ums_new;
+
+ ums[ums_count].read_sector = ums_read_sector;
+ ums[ums_count].write_sector = ums_write_sector;
+ ums[ums_count].start_sector = 0;
+ ums[ums_count].num_sectors = block_dev->lba;
+ name = malloc(UMS_NAME_LEN);
+ if (!name) {
+ ret = -1;
+ goto cleanup;
+ }
+ snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
+ ums[ums_count].name = name;
+ ums[ums_count].block_dev = *block_dev;
+
+ printf("UMS: LUN %d, dev %d, hwpart %d, sector %#x, count %#x\n",
+ ums_count, ums[ums_count].block_dev.dev,
+ ums[ums_count].block_dev.hwpart,
+ ums[ums_count].start_sector,
+ ums[ums_count].num_sectors);
+
+ ums_count++;
+ }
+
+ if (!ums_count)
+ ret = -1;
+ else
+ ret = 0;
- ums_dev.block_dev = block_dev;
- ums_dev.start_sector = 0;
- ums_dev.num_sectors = block_dev->lba;
+cleanup:
+ free(s);
- printf("UMS: disk start sector: %#x, count: %#x\n",
- ums_dev.start_sector, ums_dev.num_sectors);
+ if (ret < 0)
+ ums_fini();
- return &ums_dev;
+ return ret;
}
int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
const char *usb_controller;
const char *devtype;
const char *devnum;
- struct ums *ums;
unsigned int controller_index;
int rc;
int cable_ready_timeout __maybe_unused;
devnum = argv[2];
}
- ums = ums_init(devtype, devnum);
- if (!ums)
+ rc = ums_init(devtype, devnum);
+ if (rc < 0)
return CMD_RET_FAILURE;
controller_index = (unsigned int)(simple_strtoul(
usb_controller, NULL, 0));
if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
error("Couldn't init USB controller.");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_ums_init;
}
- rc = fsg_init(ums);
+ rc = fsg_init(ums, ums_count);
if (rc) {
error("fsg_init failed");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_board;
}
rc = g_dnl_register("usb_dnl_ums");
if (rc) {
error("g_dnl_register failed");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_board;
}
/* Timeout unit: seconds */
while (!g_dnl_board_usb_cable_connected()) {
if (ctrlc()) {
puts("\rCTRL+C - Operation aborted.\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
if (!cable_ready_timeout) {
puts("\rUSB cable not detected.\n" \
"Command exit.\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
printf("\rAuto exit in: %.2d s.", cable_ready_timeout);
if (rc == -EPIPE)
printf("\rCTRL+C - Operation aborted\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
}
-exit:
+
+cleanup_register:
g_dnl_unregister();
+cleanup_board:
board_usb_cleanup(controller_index, USB_INIT_DEVICE);
- return CMD_RET_SUCCESS;
+cleanup_ums_init:
+ ums_fini();
+
+ return rc;
}
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
{
int i;
- for (i = 0; i < sizeof(env_flags_varaccess_mask); i++)
+ for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++)
if (env_flags_varaccess_mask[i] ==
(binflags & ENV_FLAGS_VARACCESS_BIN_MASK))
return (enum env_flags_varaccess)i;
return CONFIG_SYS_MMC_ENV_PART;
}
+static unsigned char env_mmc_orig_hwpart;
+
static int mmc_set_env_part(struct mmc *mmc)
{
uint part = mmc_get_env_part(mmc);
dev = 0;
#endif
- if (part != mmc->part_num) {
- ret = mmc_switch_part(dev, part);
- if (ret)
- puts("MMC partition switch failed\n");
- }
+ env_mmc_orig_hwpart = mmc->block_dev.hwpart;
+ ret = mmc_select_hwpart(dev, part);
+ if (ret)
+ puts("MMC partition switch failed\n");
return ret;
}
#ifdef CONFIG_SPL_BUILD
dev = 0;
#endif
- if (mmc_get_env_part(mmc) != mmc->part_num)
- mmc_switch_part(dev, mmc->part_num);
+ mmc_select_hwpart(dev, env_mmc_orig_hwpart);
#endif
}
blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
- n = mmc->block_dev.block_write(CONFIG_SYS_MMC_ENV_DEV, blk_start,
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
blk_cnt, (u_char *)buffer);
return (n == blk_cnt) ? 0 : -1;
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
- int dev = CONFIG_SYS_MMC_ENV_DEV;
-
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer);
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
+ (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
block_dev_desc_t *dev_desc = sparse->dev_desc;
int ret;
- ret = dev_desc->block_write(dev_desc->dev, offset, size, data);
+ ret = dev_desc->block_write(dev_desc, offset, size, data);
if (!ret)
return -EIO;
puts("Flashing Raw Image\n");
- blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt,
- buffer);
+ blks = dev_desc->block_write(dev_desc, info->start, blkcnt, buffer);
if (blks != blkcnt) {
error("failed writing to device %d\n", dev_desc->dev);
fastboot_fail(response_str, "failed writing to device");
printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
blks_start, blks_start + blks_size);
- blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size);
+ blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
if (blks != blks_size) {
error("failed erasing from device %d", dev_desc->dev);
fastboot_fail(response_str, "failed erasing from device");
void fdt_fixup_ethernet(void *fdt)
{
int node, i, j;
- char enet[16], *tmp, *end;
+ char *tmp, *end;
char mac[16];
const char *path;
unsigned char mac_addr[6];
+ int offset;
node = fdt_path_offset(fdt, "/aliases");
if (node < 0)
return;
- if (!getenv("ethaddr")) {
- if (getenv("usbethaddr")) {
- strcpy(mac, "usbethaddr");
- } else {
- debug("No ethernet MAC Address defined\n");
- return;
- }
- } else {
- strcpy(mac, "ethaddr");
- }
-
- i = 0;
- while ((tmp = getenv(mac)) != NULL) {
- sprintf(enet, "ethernet%d", i);
- path = fdt_getprop(fdt, node, enet, NULL);
- if (!path) {
- debug("No alias for %s\n", enet);
- sprintf(mac, "eth%daddr", ++i);
- continue;
- }
+ for (offset = fdt_first_property_offset(fdt, node);
+ offset > 0;
+ offset = fdt_next_property_offset(fdt, offset)) {
+ const char *name;
+ int len = strlen("ethernet");
+
+ path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
+ if (!strncmp(name, "ethernet", len)) {
+ i = trailing_strtol(name);
+ if (i != -1) {
+ if (i == 0)
+ strcpy(mac, "ethaddr");
+ else
+ sprintf(mac, "eth%daddr", i);
+ } else {
+ continue;
+ }
+ tmp = getenv(mac);
+ if (!tmp)
+ continue;
+
+ for (j = 0; j < 6; j++) {
+ mac_addr[j] = tmp ?
+ simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
- for (j = 0; j < 6; j++) {
- mac_addr[j] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
+ do_fixup_by_path(fdt, path, "mac-address",
+ &mac_addr, 6, 0);
+ do_fixup_by_path(fdt, path, "local-mac-address",
+ &mac_addr, 6, 1);
}
-
- do_fixup_by_path(fdt, path, "mac-address", &mac_addr, 6, 0);
- do_fixup_by_path(fdt, path, "local-mac-address",
- &mac_addr, 6, 1);
-
- sprintf(mac, "eth%daddr", ++i);
}
}
return 0;
}
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+ uint8_t *output, int *output_size)
+{
+ struct hash_algo *algo;
+ int ret;
+
+ ret = hash_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ if (output_size && *output_size < algo->digest_size) {
+ debug("Output buffer size %d too small (need %d bytes)",
+ *output_size, algo->digest_size);
+ return -ENOSPC;
+ }
+ if (output_size)
+ *output_size = algo->digest_size;
+ algo->hash_func_ws(data, len, output, algo->chunk_size);
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
/**
* store_result: Store the resulting sum to an address or variable
*
return 0;
}
-void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
+static void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
{
int i;
printf("%02x", output[i]);
}
-int hash_block(const char *algo_name, const void *data, unsigned int len,
- uint8_t *output, int *output_size)
-{
- struct hash_algo *algo;
- int ret;
-
- ret = hash_lookup_algo(algo_name, &algo);
- if (ret)
- return ret;
-
- if (output_size && *output_size < algo->digest_size) {
- debug("Output buffer size %d too small (need %d bytes)",
- *output_size, algo->digest_size);
- return -ENOSPC;
- }
- if (output_size)
- *output_size = algo->digest_size;
- algo->hash_func_ws(data, len, output, algo->chunk_size);
-
- return 0;
-}
-
int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
return 0;
}
#endif
+#endif
if (initrd_high == ~0)
initrd_copy_to_ram = 0;
} else {
- /* not set, no restrictions to load high */
- initrd_high = ~0;
+ initrd_high = getenv_bootm_mapsize() + getenv_bootm_low();
}
#define _USE_MEMCPY
#endif
-/* Unfortunately x86 can't compile this code as gd cannot be assigned */
-#ifndef CONFIG_X86
+/* Unfortunately x86 or ARM can't compile this code as gd cannot be assigned */
+#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
__weak void arch_setup_gd(struct global_data *gd_ptr)
{
gd = gd_ptr;
}
-#endif /* !CONFIG_X86 */
+#endif /* !CONFIG_X86 && !CONFIG_ARM */
-ulong board_init_f_mem(ulong top)
+/*
+ * Allocate reserved space for use as 'globals' from 'top' address and
+ * return 'bottom' address of allocated space
+ *
+ * Notes:
+ *
+ * Actual reservation cannot be done from within this function as
+ * it requires altering the C stack pointer, so this will be done by
+ * the caller upon return from this function.
+ *
+ * IMPORTANT:
+ *
+ * Alignment constraints may differ for each 'chunk' allocated. For now:
+ *
+ * - GD is aligned down on a 16-byte boundary
+ *
+ * - the early malloc arena is not aligned, therefore it follows the stack
+ * alignment constraint of the architecture for which we are bulding.
+ *
+ * - GD is allocated last, so that the return value of this functions is
+ * both the bottom of the reserved area and the address of GD, should
+ * the calling context need it.
+ */
+
+ulong board_init_f_alloc_reserve(ulong top)
+{
+ /* Reserve early malloc arena */
+#if defined(CONFIG_SYS_MALLOC_F)
+ top -= CONFIG_SYS_MALLOC_F_LEN;
+#endif
+ /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */
+ top = rounddown(top-sizeof(struct global_data), 16);
+
+ return top;
+}
+
+/*
+ * Initialize reserved space (which has been safely allocated on the C
+ * stack from the C runtime environment handling code).
+ *
+ * Notes:
+ *
+ * Actual reservation was done by the caller; the locations from base
+ * to base+size-1 (where 'size' is the value returned by the allocation
+ * function above) can be accessed freely without risk of corrupting the
+ * C runtime environment.
+ *
+ * IMPORTANT:
+ *
+ * Upon return from the allocation function above, on some architectures
+ * the caller will set gd to the lowest reserved location. Therefore, in
+ * this initialization function, the global data MUST be placed at base.
+ *
+ * ALSO IMPORTANT:
+ *
+ * On some architectures, gd will already be good when entering this
+ * function. On others, it will only be good once arch_setup_gd() returns.
+ * Therefore, global data accesses must be done:
+ *
+ * - through gd_ptr if before the call to arch_setup_gd();
+ *
+ * - through gd once arch_setup_gd() has been called.
+ *
+ * Do not use 'gd->' until arch_setup_gd() has been called!
+ *
+ * IMPORTANT TOO:
+ *
+ * Initialization for each "chunk" (GD, early malloc arena...) ends with
+ * an incrementation line of the form 'base += <some size>'. The last of
+ * these incrementations seems useless, as base will not be used any
+ * more after this incrementation; but if/when a new "chunk" is appended,
+ * this increment will be essential as it will give base right value for
+ * this new chunk (which will have to end with its own incrementation
+ * statement). Besides, the compiler's optimizer will silently detect
+ * and remove the last base incrementation, therefore leaving that last
+ * (seemingly useless) incrementation causes no code increase.
+ */
+
+void board_init_f_init_reserve(ulong base)
{
struct global_data *gd_ptr;
#ifndef _USE_MEMCPY
int *ptr;
#endif
- /* Leave space for the stack we are running with now */
- top -= 0x40;
+ /*
+ * clear GD entirely and set it up.
+ * Use gd_ptr, as gd may not be properly set yet.
+ */
- top -= sizeof(struct global_data);
- top = ALIGN(top, 16);
- gd_ptr = (struct global_data *)top;
+ gd_ptr = (struct global_data *)base;
+ /* zero the area */
#ifdef _USE_MEMCPY
memset(gd_ptr, '\0', sizeof(*gd));
#else
for (ptr = (int *)gd_ptr; ptr < (int *)(gd_ptr + 1); )
*ptr++ = 0;
#endif
+ /* set GD unless architecture did it already */
+#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
arch_setup_gd(gd_ptr);
+#endif
+ /* next alloc will be higher by one GD plus 16-byte alignment */
+ base += roundup(sizeof(struct global_data), 16);
+
+ /*
+ * record early malloc arena start.
+ * Use gd as it is now properly set for all architectures.
+ */
#if defined(CONFIG_SYS_MALLOC_F)
- top -= CONFIG_SYS_MALLOC_F_LEN;
- gd->malloc_base = top;
+ /* go down one 'early malloc arena' */
+ gd->malloc_base = base;
+ /* next alloc will be higher by one 'early malloc arena' size */
+ base += CONFIG_SYS_MALLOC_F_LEN;
#endif
-
- return top;
}
* more stack space for things like the MMC sub-system.
*
* This function calculates the stack position, copies the global_data into
- * place and returns the new stack position. The caller is responsible for
- * setting up the sp register.
+ * place, sets the new gd (except for ARM, for which setting GD within a C
+ * function may not always work) and returns the new stack position. The
+ * caller is responsible for setting up the sp register and, in the case
+ * of ARM, setting up gd.
+ *
+ * All of this is done using the same layout and alignments as done in
+ * board_init_f_init_reserve() / board_init_f_alloc_reserve().
*
* @return new stack location, or 0 to use the same stack
*/
{
#ifdef CONFIG_SPL_STACK_R
gd_t *new_gd;
- ulong ptr;
-
- /* Get stack position: use 8-byte alignment for ABI compliance */
- ptr = CONFIG_SPL_STACK_R_ADDR - sizeof(gd_t);
- ptr &= ~7;
- new_gd = (gd_t *)ptr;
- memcpy(new_gd, (void *)gd, sizeof(gd_t));
- gd = new_gd;
+ ulong ptr = CONFIG_SPL_STACK_R_ADDR;
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
gd->malloc_ptr = 0;
}
#endif
-
+ /* Get stack position: use 8-byte alignment for ABI compliance */
+ ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
+ new_gd = (gd_t *)ptr;
+ memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if !defined(CONFIG_ARM)
+ gd = new_gd;
+#endif
return ptr;
#else
return 0;
unsigned long count;
u32 image_size_sectors;
struct image_header *header;
- int dev_num = mmc->block_dev.dev;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
sizeof(struct image_header));
/* read image header to find the image size & load address */
- count = mmc->block_dev.block_read(dev_num, sector, 1, header);
+ count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
debug("read sector %lx, count=%lu\n", sector, count);
if (count == 0)
goto end;
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
- count = mmc->block_dev.block_read(dev_num, sector, image_size_sectors,
+ count = mmc->block_dev.block_read(&mmc->block_dev, sector,
+ image_size_sectors,
(void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
{
unsigned long count;
- count = mmc->block_dev.block_read(
- mmc->block_dev.dev,
+ count = mmc->block_dev.block_read(&mmc->block_dev,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *) CONFIG_SYS_SPL_ARGS_ADDR);
block_dev_desc_t *dev_desc);
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss);
-unsigned long usb_stor_read(int device, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer);
-unsigned long usb_stor_write(int device, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer);
+static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
+static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer);
void uhci_show_temp_int_td(void);
#ifdef CONFIG_PARTITIONS
}
#endif /* CONFIG_USB_BIN_FIXUP */
-unsigned long usb_stor_read(int device, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer)
+static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
return blkcnt;
}
-unsigned long usb_stor_write(int device, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer)
+static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_CLEARFOG=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6820_GP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DS414=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MAXBCM=y
-CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_TARGET_WORK_92105=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
for (i=0; i<limit; i++)
{
- ulong res = dev_desc->block_read(dev_desc->dev, i, 1,
- (ulong *)block_buffer);
+ ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer;
for (i = 0; i < limit; i++)
{
- ulong res = dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)block_buffer);
+ ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct bootcode_block *boot = (struct bootcode_block *)block_buffer;
while (block != 0xFFFFFFFF)
{
- ulong res = dev_desc->block_read(dev_desc->dev, block, 1,
+ ulong res = dev_desc->block_read(dev_desc, block, 1,
(ulong *)block_buffer);
if (res == 1)
{
PRINTF("Trying to load block #0x%X\n", block);
- res = dev_desc->block_read(dev_desc->dev, block, 1,
- (ulong *)block_buffer);
+ res = dev_desc->block_read(dev_desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
/* Convert char[4] in little endian format to the host format integer
*/
-static inline int le32_to_int(unsigned char *le32)
+static inline unsigned int le32_to_int(unsigned char *le32)
{
return ((le32[3] << 24) +
(le32[2] << 16) +
return p->boot_ind == 0x80;
}
-static void print_one_part(dos_partition_t *p, int ext_part_sector,
+static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
int part_num, unsigned int disksig)
{
- int lba_start = ext_part_sector + le32_to_int (p->start4);
- int lba_size = le32_to_int (p->size4);
+ lbaint_t lba_start = ext_part_sector + le32_to_int (p->start4);
+ lbaint_t lba_size = le32_to_int (p->size4);
- printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
+ printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength
+ "u\t%08x-%02x\t%02x%s%s\n",
part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
(is_bootable(p) ? " Boot" : ""));
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1)
+ if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)buffer) != 1)
return -1;
if (test_block_type(buffer) != DOS_MBR)
/* Print a partition that is relative to its Extended partition table
*/
static void print_partition_extended(block_dev_desc_t *dev_desc,
- int ext_part_sector, int relative,
+ lbaint_t ext_part_sector,
+ lbaint_t relative,
int part_num, unsigned int disksig)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
int i;
- if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
+ (ulong *)buffer) != 1) {
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return;
}
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
print_partition_extended(dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
/* Print a partition that is relative to its Extended partition table
*/
-static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector,
- int relative, int part_num,
+static int get_partition_info_extended (block_dev_desc_t *dev_desc,
+ lbaint_t ext_part_sector,
+ lbaint_t relative, int part_num,
int which_part, disk_partition_t *info,
unsigned int disksig)
{
int i;
int dos_type;
- if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
+ (ulong *)buffer) != 1) {
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return -1;
}
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
return get_partition_info_extended (dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
/* Read legacy MBR from block 0 and validate it */
- if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)legacymbr) != 1)
+ if ((dev_desc->block_read(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
return -1;
}
p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
/* Write MBR sector to the MMC device */
- if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) {
+ if (dev_desc->block_write(dev_desc, 0, 1, p_mbr) != 1) {
printf("** Can't write to device %d **\n",
dev_desc->dev);
return -1;
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
/* Write the First GPT to the block right after the Legacy MBR */
- if (dev_desc->block_write(dev_desc->dev, 1, 1, gpt_h) != 1)
+ if (dev_desc->block_write(dev_desc, 1, 1, gpt_h) != 1)
goto err;
- if (dev_desc->block_write(dev_desc->dev, 2, pte_blk_cnt, gpt_e)
+ if (dev_desc->block_write(dev_desc, 2, pte_blk_cnt, gpt_e)
!= pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
- if (dev_desc->block_write(dev_desc->dev,
+ if (dev_desc->block_write(dev_desc,
(lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ 1,
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
- if (dev_desc->block_write(dev_desc->dev,
+ if (dev_desc->block_write(dev_desc,
(lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
gpt_h) != 1)
goto err;
/* write MBR */
lba = 0; /* MBR is always at 0 */
cnt = 1; /* MBR (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, buf) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "MBR", cnt, lba);
return 1;
/* write Primary GPT */
lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
cnt = 1; /* GPT Header (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Primary GPT Header", cnt, lba);
return 1;
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Primary GPT Entries", cnt, lba);
return 1;
/* write Backup GPT */
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Backup GPT Entries", cnt, lba);
return 1;
lba = le64_to_cpu(gpt_h->my_lba);
cnt = 1; /* GPT Header (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Backup GPT Header", cnt, lba);
return 1;
}
/* Read GPT Header from device */
- if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head)
- != 1) {
+ if (dev_desc->block_read(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
printf("*** ERROR: Can't read GPT header ***\n");
return 0;
}
gpt_header * pgpt_head)
{
size_t count = 0, blk_cnt;
+ lbaint_t blk;
gpt_entry *pte = NULL;
if (!dev_desc || !pgpt_head) {
}
/* Read GPT Entries from device */
+ blk = le64_to_cpu(pgpt_head->partition_entry_lba);
blk_cnt = BLOCK_CNT(count, dev_desc);
- if (dev_desc->block_read (dev_desc->dev,
- (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba),
- (lbaint_t) (blk_cnt), pte)
- != blk_cnt) {
-
+ if (dev_desc->block_read(dev_desc, blk, (lbaint_t)blk_cnt, pte)
+ != blk_cnt) {
printf("*** ERROR: Can't read GPT Entries ***\n");
free(pte);
return NULL;
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
- if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1)
- return (-1);
+ if (dev_desc->block_read(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+ return -1;
if(ppr->desctype!=0x01) {
if(verb)
printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
PRINTF(" Lastsect:%08lx\n",lastsect);
for(i=blkaddr;i<lastsect;i++) {
PRINTF("Reading block %d\n", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1)
- return (-1);
+ if (dev_desc->block_read(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+ return -1;
if(ppr->desctype==0x00)
break; /* boot entry found */
if(ppr->desctype==0xff) {
}
bootaddr=le32_to_int(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1) {
+ if (dev_desc->block_read(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
bootaddr,dev_desc->dev, part_num);
n = 1; /* assuming at least one partition */
for (i=1; i<=n; ++i) {
- if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)mpart) != 1) ||
+ if ((dev_desc->block_read(dev_desc, i, 1,
+ (ulong *)mpart) != 1) ||
(mpart->signature != MAC_PARTITION_MAGIC) ) {
return (-1);
}
char c;
printf ("%4ld: ", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)mpart) != 1) {
+ if (dev_desc->block_read(dev_desc, i, 1, (ulong *)mpart) != 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
dev_desc->dev, i);
return;
*/
static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p)
{
- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)ddb_p) != 1) {
+ if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
printf ("** Can't read Driver Desriptor Block **\n");
return (-1);
}
* partition 1 first since this is the only way to
* know how many partitions we have.
*/
- if (dev_desc->block_read (dev_desc->dev, n, 1, (ulong *)pdb_p) != 1) {
+ if (dev_desc->block_read(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
printf ("** Can't read Partition Map on %d:%d **\n",
dev_desc->dev, n);
return (-1);
SW8 OFF(1)/ON(0) Description
------------------------------------------
- bit 1 ----> CS1_SPLIT
+ bit 1 <---- CS1_SPLIT
bit 2 <---- CASE9_ON
bit 3 <---- CASE10_ON
bit 4 Don't Care Reserve
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ddr/marvell/a38x/
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ddr/marvell/axp/
+obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
+obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
obj-$(CONFIG_SATA_DWC) += sata_dwc.o
+obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_IDE_SIL680) += sil680.o
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev = probe_ent->dev;
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+# else
pci_dev_t pdev = probe_ent->dev;
- u16 tmp16;
unsigned short vendor;
+# endif
+ u16 tmp16;
#endif
void __iomem *mmio = probe_ent->mmio_base;
u32 tmp, cap_save, cmd;
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
+ u16 tmp16;
+
+ dm_pci_read_config16(dev, 0x92, &tmp16);
+ dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
+ }
+# else
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
+# endif
#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
+ tmp |= PCI_COMMAND_MASTER;
+ dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
+# else
pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
+# endif
#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev = probe_ent->dev;
+# else
pci_dev_t pdev = probe_ent->dev;
+# endif
u16 cc;
#endif
void __iomem *mmio = probe_ent->mmio_base;
#ifdef CONFIG_SCSI_AHCI_PLAT
scc_s = "SATA";
#else
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(dev, 0x0a, &cc);
+# else
pci_read_config_word(pdev, 0x0a, &cc);
+# endif
if (cc == 0x0101)
scc_s = "IDE";
else if (cc == 0x0106)
}
#ifndef CONFIG_SCSI_AHCI_PLAT
-static int ahci_init_one(pci_dev_t pdev)
+# ifdef CONFIG_DM_PCI
+static int ahci_init_one(struct udevice *dev)
+# else
+static int ahci_init_one(pci_dev_t dev)
+# endif
{
u16 vendor;
int rc;
}
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
- probe_ent->dev = pdev;
+ probe_ent->dev = dev;
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
+#ifdef CONFIG_DM_PCI
+ probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
+ PCI_REGION_MEM);
+
+ /* Take from kernel:
+ * JMicron-specific fixup:
+ * make sure we're in AHCI mode
+ */
+ dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+ if (vendor == 0x197b)
+ dm_pci_write_config8(dev, 0x41, 0xa1);
+#else
+ probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
- debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* Take from kernel:
* JMicron-specific fixup:
* make sure we're in AHCI mode
*/
- pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
if (vendor == 0x197b)
- pci_write_config_byte(pdev, 0x41, 0xa1);
+ pci_write_config_byte(dev, 0x41, 0xa1);
+#endif
+ debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* initialize adapter */
rc = ahci_host_init(probe_ent);
if (rc)
u32 linkmap;
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
+ if (ret)
+ return;
+ ahci_init_one(dev);
+# else
ahci_init_one(busdevfunc);
+# endif
#endif
linkmap = probe_ent->link_port_map;
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/soc.h>
-#elif defined(CONFIG_ARMADA_XP)
+#elif defined(CONFIG_ARCH_MVEBU)
#include <linux/mbus.h>
#endif
* Initialize SATA memory windows for Armada XP
*/
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_ARCH_MVEBU
static void mvsata_ide_conf_mbus_windows(void)
{
const struct mbus_dram_target_info *dram;
int ret = MVSATA_STATUS_TIMEOUT;
int status;
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_ARCH_MVEBU
mvsata_ide_conf_mbus_windows();
#endif
return NULL;
}
-static unsigned long host_block_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer)
+static unsigned long host_block_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
{
+ int dev = block_dev->dev;
struct host_block_dev *host_dev = find_host_device(dev);
if (!host_dev)
return -1;
}
-static unsigned long host_block_write(int dev, unsigned long start,
- lbaint_t blkcnt, const void *buffer)
+static unsigned long host_block_write(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ const void *buffer)
{
+ int dev = block_dev->dev;
struct host_block_dev *host_dev = find_host_device(dev);
if (os_lseek(host_dev->fd,
start * host_dev->blk_dev.blksz,
--- /dev/null
+/*
+ * Copyright (C) Excito Elektronik i Skåne AB, 2010.
+ * Author: Tor Krill <tor@excito.com>
+ *
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This driver supports the SATA controller of some Mavell SoC's.
+ * Here a (most likely incomplete) list of the supported SoC's:
+ * - Kirkwood
+ * - Armada 370
+ * - Armada XP
+ *
+ * This driver implementation is an alternative to the already available
+ * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
+ * But this driver only supports PIO mode and as this new driver also
+ * supports transfer via DMA, its much faster.
+ *
+ * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
+ * by this driver. As they have an AHCI compatible SATA controller
+ * integrated.
+ */
+
+/*
+ * TODO:
+ * Better error recovery
+ * No support for using PRDs (Thus max 64KB transfers)
+ * No NCQ support
+ * No port multiplier support
+ */
+
+#include <common.h>
+#include <fis.h>
+#include <libata.h>
+#include <malloc.h>
+#include <sata.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <linux/mbus.h>
+
+#if defined(CONFIG_KIRKWOOD)
+#include <asm/arch/kirkwood.h>
+#define SATAHC_BASE KW_SATA_BASE
+#else
+#include <asm/arch/soc.h>
+#define SATAHC_BASE MVEBU_AXP_SATA_BASE
+#endif
+
+#define SATA0_BASE (SATAHC_BASE + 0x2000)
+#define SATA1_BASE (SATAHC_BASE + 0x4000)
+
+/* EDMA registers */
+#define EDMA_CFG 0x000
+#define EDMA_CFG_NCQ (1 << 5)
+#define EDMA_CFG_EQUE (1 << 9)
+#define EDMA_TIMER 0x004
+#define EDMA_IECR 0x008
+#define EDMA_IEMR 0x00c
+#define EDMA_RQBA_HI 0x010
+#define EDMA_RQIPR 0x014
+#define EDMA_RQIPR_IPMASK (0x1f << 5)
+#define EDMA_RQIPR_IPSHIFT 5
+#define EDMA_RQOPR 0x018
+#define EDMA_RQOPR_OPMASK (0x1f << 5)
+#define EDMA_RQOPR_OPSHIFT 5
+#define EDMA_RSBA_HI 0x01c
+#define EDMA_RSIPR 0x020
+#define EDMA_RSIPR_IPMASK (0x1f << 3)
+#define EDMA_RSIPR_IPSHIFT 3
+#define EDMA_RSOPR 0x024
+#define EDMA_RSOPR_OPMASK (0x1f << 3)
+#define EDMA_RSOPR_OPSHIFT 3
+#define EDMA_CMD 0x028
+#define EDMA_CMD_ENEDMA (0x01 << 0)
+#define EDMA_CMD_DISEDMA (0x01 << 1)
+#define EDMA_CMD_ATARST (0x01 << 2)
+#define EDMA_CMD_FREEZE (0x01 << 4)
+#define EDMA_TEST_CTL 0x02c
+#define EDMA_STATUS 0x030
+#define EDMA_IORTO 0x034
+#define EDMA_CDTR 0x040
+#define EDMA_HLTCND 0x060
+#define EDMA_NTSR 0x094
+
+/* Basic DMA registers */
+#define BDMA_CMD 0x224
+#define BDMA_STATUS 0x228
+#define BDMA_DTLB 0x22c
+#define BDMA_DTHB 0x230
+#define BDMA_DRL 0x234
+#define BDMA_DRH 0x238
+
+/* SATA Interface registers */
+#define SIR_ICFG 0x050
+#define SIR_CFG_GEN2EN (0x1 << 7)
+#define SIR_PLL_CFG 0x054
+#define SIR_SSTATUS 0x300
+#define SSTATUS_DET_MASK (0x0f << 0)
+#define SIR_SERROR 0x304
+#define SIR_SCONTROL 0x308
+#define SIR_SCONTROL_DETEN (0x01 << 0)
+#define SIR_LTMODE 0x30c
+#define SIR_LTMODE_NELBE (0x01 << 7)
+#define SIR_PHYMODE3 0x310
+#define SIR_PHYMODE4 0x314
+#define SIR_PHYMODE1 0x32c
+#define SIR_PHYMODE2 0x330
+#define SIR_BIST_CTRL 0x334
+#define SIR_BIST_DW1 0x338
+#define SIR_BIST_DW2 0x33c
+#define SIR_SERR_IRQ_MASK 0x340
+#define SIR_SATA_IFCTRL 0x344
+#define SIR_SATA_TESTCTRL 0x348
+#define SIR_SATA_IFSTATUS 0x34c
+#define SIR_VEND_UNIQ 0x35c
+#define SIR_FIS_CFG 0x360
+#define SIR_FIS_IRQ_CAUSE 0x364
+#define SIR_FIS_IRQ_MASK 0x368
+#define SIR_FIS_DWORD0 0x370
+#define SIR_FIS_DWORD1 0x374
+#define SIR_FIS_DWORD2 0x378
+#define SIR_FIS_DWORD3 0x37c
+#define SIR_FIS_DWORD4 0x380
+#define SIR_FIS_DWORD5 0x384
+#define SIR_FIS_DWORD6 0x388
+#define SIR_PHYM9_GEN2 0x398
+#define SIR_PHYM9_GEN1 0x39c
+#define SIR_PHY_CFG 0x3a0
+#define SIR_PHYCTL 0x3a4
+#define SIR_PHYM10 0x3a8
+#define SIR_PHYM12 0x3b0
+
+/* Shadow registers */
+#define PIO_DATA 0x100
+#define PIO_ERR_FEATURES 0x104
+#define PIO_SECTOR_COUNT 0x108
+#define PIO_LBA_LOW 0x10c
+#define PIO_LBA_MID 0x110
+#define PIO_LBA_HI 0x114
+#define PIO_DEVICE 0x118
+#define PIO_CMD_STATUS 0x11c
+#define PIO_STATUS_ERR (0x01 << 0)
+#define PIO_STATUS_DRQ (0x01 << 3)
+#define PIO_STATUS_DF (0x01 << 5)
+#define PIO_STATUS_DRDY (0x01 << 6)
+#define PIO_STATUS_BSY (0x01 << 7)
+#define PIO_CTRL_ALTSTAT 0x120
+
+/* SATAHC arbiter registers */
+#define SATAHC_CFG 0x000
+#define SATAHC_RQOP 0x004
+#define SATAHC_RQIP 0x008
+#define SATAHC_ICT 0x00c
+#define SATAHC_ITT 0x010
+#define SATAHC_ICR 0x014
+#define SATAHC_ICR_PORT0 (0x01 << 0)
+#define SATAHC_ICR_PORT1 (0x01 << 1)
+#define SATAHC_MIC 0x020
+#define SATAHC_MIM 0x024
+#define SATAHC_LED_CFG 0x02c
+
+#define REQUEST_QUEUE_SIZE 32
+#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
+
+struct crqb {
+ u32 dtb_low; /* DW0 */
+ u32 dtb_high; /* DW1 */
+ u32 control_flags; /* DW2 */
+ u32 drb_count; /* DW3 */
+ u32 ata_cmd_feat; /* DW4 */
+ u32 ata_addr; /* DW5 */
+ u32 ata_addr_exp; /* DW6 */
+ u32 ata_sect_count; /* DW7 */
+};
+
+#define CRQB_ALIGN 0x400
+
+#define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
+#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
+#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
+#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
+#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
+#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
+#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
+#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
+
+#define CRQB_CMDFEAT_CMDMASK (0xff << 16)
+#define CRQB_CMDFEAT_CMDSHIFT 16
+#define CRQB_CMDFEAT_FEATMASK (0xff << 16)
+#define CRQB_CMDFEAT_FEATSHIFT 24
+
+#define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
+#define CRQB_ADDR_LBA_LOWSHIFT 0
+#define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
+#define CRQB_ADDR_LBA_MIDSHIFT 8
+#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
+#define CRQB_ADDR_LBA_HIGHSHIFT 16
+#define CRQB_ADDR_DEVICE_MASK (0xff << 24)
+#define CRQB_ADDR_DEVICE_SHIFT 24
+
+#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
+#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
+#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
+#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
+#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
+#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
+#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
+#define CRQB_ADDR_FEATURE_EXP_SHIFT 24
+
+#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
+#define CRQB_SECTCOUNT_COUNT_SHIFT 0
+#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
+#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
+
+#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
+
+struct eprd {
+ u32 phyaddr_low;
+ u32 bytecount_eot;
+ u32 phyaddr_hi;
+ u32 reserved;
+};
+
+#define EPRD_PHYADDR_MASK 0xfffffffe
+#define EPRD_BYTECOUNT_MASK 0x0000ffff
+#define EPRD_EOT (0x01 << 31)
+
+struct crpb {
+ u32 id;
+ u32 flags;
+ u32 timestamp;
+};
+
+#define CRPB_ALIGN 0x100
+
+#define READ_CMD 0
+#define WRITE_CMD 1
+
+/*
+ * Since we don't use PRDs yet max transfer size
+ * is 64KB
+ */
+#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
+
+/* Keep track if hw is initialized or not */
+static u32 hw_init;
+
+struct mv_priv {
+ char name[12];
+ u32 link;
+ u32 regbase;
+ u32 queue_depth;
+ u16 pio;
+ u16 mwdma;
+ u16 udma;
+
+ void *crqb_alloc;
+ struct crqb *request;
+
+ void *crpb_alloc;
+ struct crpb *response;
+};
+
+static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
+{
+ ulong start;
+
+ start = get_timer(0);
+ do {
+ if ((in_le32(addr) & mask) == val)
+ return 0;
+ } while (get_timer(start) < timeout_msec);
+
+ return -ETIMEDOUT;
+}
+
+/* Cut from sata_mv in linux kernel */
+static int mv_stop_edma_engine(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int i;
+
+ /* Disable eDMA. The disable bit auto clears. */
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
+
+ /* Wait for the chip to confirm eDMA is off. */
+ for (i = 10000; i > 0; i--) {
+ u32 reg = in_le32(priv->regbase + EDMA_CMD);
+ if (!(reg & EDMA_CMD_ENEDMA)) {
+ debug("EDMA stop on port %d succesful\n", port);
+ return 0;
+ }
+ udelay(10);
+ }
+ debug("EDMA stop on port %d failed\n", port);
+ return -1;
+}
+
+static int mv_start_edma_engine(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ /* Check preconditions */
+ tmp = in_le32(priv->regbase + SIR_SSTATUS);
+ if ((tmp & SSTATUS_DET_MASK) != 0x03) {
+ printf("Device error on port: %d\n", port);
+ return -1;
+ }
+
+ tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
+ if (tmp & (ATA_BUSY | ATA_DRQ)) {
+ printf("Device not ready on port: %d\n", port);
+ return -1;
+ }
+
+ /* Clear interrupt cause */
+ out_le32(priv->regbase + EDMA_IECR, 0x0);
+
+ tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
+ tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
+ out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
+
+ /* Configure edma operation */
+ tmp = in_le32(priv->regbase + EDMA_CFG);
+ tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
+ tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
+ out_le32(priv->regbase + EDMA_CFG, tmp);
+
+ out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
+
+ /* Configure fis, set all to no-wait for now */
+ out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
+
+ /* Setup request queue */
+ out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RQIPR, priv->request);
+ out_le32(priv->regbase + EDMA_RQOPR, 0x0);
+
+ /* Setup response queue */
+ out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RSOPR, priv->response);
+ out_le32(priv->regbase + EDMA_RSIPR, 0x0);
+
+ /* Start edma */
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
+
+ return 0;
+}
+
+static int mv_reset_channel(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ /* Make sure edma is stopped */
+ mv_stop_edma_engine(port);
+
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
+ udelay(25); /* allow reset propagation */
+ out_le32(priv->regbase + EDMA_CMD, 0);
+ mdelay(10);
+
+ return 0;
+}
+
+static void mv_reset_port(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ mv_reset_channel(port);
+
+ out_le32(priv->regbase + EDMA_CMD, 0x0);
+ out_le32(priv->regbase + EDMA_CFG, 0x101f);
+ out_le32(priv->regbase + EDMA_IECR, 0x0);
+ out_le32(priv->regbase + EDMA_IEMR, 0x0);
+ out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RQIPR, 0x0);
+ out_le32(priv->regbase + EDMA_RQOPR, 0x0);
+ out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RSIPR, 0x0);
+ out_le32(priv->regbase + EDMA_RSOPR, 0x0);
+ out_le32(priv->regbase + EDMA_IORTO, 0xfa);
+}
+
+static void mv_reset_one_hc(void)
+{
+ out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
+ out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
+ out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
+}
+
+static int probe_port(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int tries, tries2, set15 = 0;
+ u32 tmp;
+
+ debug("Probe port: %d\n", port);
+
+ for (tries = 0; tries < 2; tries++) {
+ /* Clear SError */
+ out_le32(priv->regbase + SIR_SERROR, 0x0);
+
+ /* trigger com-init */
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
+ out_le32(priv->regbase + SIR_SCONTROL, tmp);
+
+ mdelay(1);
+
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ tries2 = 5;
+ do {
+ tmp = (tmp & 0x0f0) | 0x300;
+ out_le32(priv->regbase + SIR_SCONTROL, tmp);
+ mdelay(10);
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ } while ((tmp & 0xf0f) != 0x300 && tries2--);
+
+ mdelay(10);
+
+ for (tries2 = 0; tries2 < 200; tries2++) {
+ tmp = in_le32(priv->regbase + SIR_SSTATUS);
+ if ((tmp & SSTATUS_DET_MASK) == 0x03) {
+ debug("Found device on port\n");
+ return 0;
+ }
+ mdelay(1);
+ }
+
+ if ((tmp & SSTATUS_DET_MASK) == 0) {
+ debug("No device attached on port %d\n", port);
+ return -ENODEV;
+ }
+
+ if (!set15) {
+ /* Try on 1.5Gb/S */
+ debug("Try 1.5Gb link\n");
+ set15 = 1;
+ out_le32(priv->regbase + SIR_SCONTROL, 0x304);
+
+ tmp = in_le32(priv->regbase + SIR_ICFG);
+ tmp &= ~SIR_CFG_GEN2EN;
+ out_le32(priv->regbase + SIR_ICFG, tmp);
+
+ mv_reset_channel(port);
+ }
+ }
+
+ debug("Failed to probe port\n");
+ return -1;
+}
+
+/* Get request queue in pointer */
+static int get_reqip(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
+ tmp = tmp >> EDMA_RQIPR_IPSHIFT;
+
+ return tmp;
+}
+
+static void set_reqip(int port, int reqin)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
+ tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
+ out_le32(priv->regbase + EDMA_RQIPR, tmp);
+}
+
+/* Get next available slot, ignoring possible overwrite */
+static int get_next_reqip(int port)
+{
+ int slot = get_reqip(port);
+ slot = (slot + 1) % REQUEST_QUEUE_SIZE;
+ return slot;
+}
+
+/* Get response queue in pointer */
+static int get_rspip(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
+ tmp = tmp >> EDMA_RSIPR_IPSHIFT;
+
+ return tmp;
+}
+
+/* Get response queue out pointer */
+static int get_rspop(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
+ tmp = tmp >> EDMA_RSOPR_OPSHIFT;
+ return tmp;
+}
+
+/* Get next response queue pointer */
+static int get_next_rspop(int port)
+{
+ return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE;
+}
+
+/* Set response queue pointer */
+static void set_rspop(int port, int reqin)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
+ tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
+
+ out_le32(priv->regbase + EDMA_RSOPR, tmp);
+}
+
+static int wait_dma_completion(int port, int index, u32 timeout_msec)
+{
+ u32 tmp, res;
+
+ tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
+ res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
+ tmp, timeout_msec);
+ if (res)
+ printf("Failed to wait for completion on port %d\n", port);
+
+ return res;
+}
+
+static void process_responses(int port)
+{
+#ifdef DEBUG
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+#endif
+ u32 tmp;
+ u32 outind = get_rspop(port);
+
+ /* Ack interrupts */
+ tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
+ if (port == 0)
+ tmp &= ~(BIT(0) | BIT(8));
+ else
+ tmp &= ~(BIT(1) | BIT(9));
+ tmp &= ~(BIT(4));
+ out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
+
+ while (get_rspip(port) != outind) {
+#ifdef DEBUG
+ debug("Response index %d flags %08x on port %d\n", outind,
+ priv->response[outind].flags, port);
+#endif
+ outind = get_next_rspop(port);
+ set_rspop(port, outind);
+ }
+}
+
+static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
+ u8 *buffer, u32 len, u32 iswrite)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ struct crqb *req;
+ int slot;
+
+ if (len >= 64 * 1024) {
+ printf("We only support <64K transfers for now\n");
+ return -1;
+ }
+
+ /* Initialize request */
+ slot = get_reqip(port);
+ memset(&priv->request[slot], 0, sizeof(struct crqb));
+ req = &priv->request[slot];
+
+ req->dtb_low = (u32)buffer;
+
+ /* Dont use PRDs */
+ req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
+ req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
+ req->control_flags |=
+ ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
+ & CRQB_CNTRLFLAGS_PMPORTMASK);
+
+ req->drb_count = len;
+
+ req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
+ CRQB_CMDFEAT_CMDMASK;
+ req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
+ CRQB_CMDFEAT_FEATMASK;
+
+ req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
+ CRQB_ADDR_LBA_LOWMASK;
+ req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
+ CRQB_ADDR_LBA_MIDMASK;
+ req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
+ CRQB_ADDR_LBA_HIGHMASK;
+ req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
+ CRQB_ADDR_DEVICE_MASK;
+
+ req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
+ CRQB_ADDR_LBA_LOW_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
+ CRQB_ADDR_LBA_MID_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
+ CRQB_ADDR_LBA_HIGH_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
+ CRQB_ADDR_FEATURE_EXP_MASK;
+
+ req->ata_sect_count =
+ (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
+ CRQB_SECTCOUNT_COUNT_MASK;
+ req->ata_sect_count |=
+ (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
+ CRQB_SECTCOUNT_COUNT_EXP_MASK;
+
+ /* Flush data */
+ flush_dcache_range((u32)req, (u32)req + sizeof(*req));
+
+ /* Trigger operation */
+ slot = get_next_reqip(port);
+ set_reqip(port, slot);
+
+ /* Wait for completion */
+ if (wait_dma_completion(port, slot, 10000)) {
+ printf("ATA operation timed out\n");
+ return -1;
+ }
+
+ process_responses(port);
+
+ /* Invalidate data on read */
+ if (buffer && len)
+ invalidate_dcache_range((u32)buffer, (u32)buffer + len);
+
+ return len;
+}
+
+static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
+ u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d cfis;
+ u32 res;
+ u64 block;
+
+ block = (u64)start;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
+
+ cfis.lba_high_exp = (block >> 40) & 0xff;
+ cfis.lba_mid_exp = (block >> 32) & 0xff;
+ cfis.lba_low_exp = (block >> 24) & 0xff;
+ cfis.lba_high = (block >> 16) & 0xff;
+ cfis.lba_mid = (block >> 8) & 0xff;
+ cfis.lba_low = block & 0xff;
+ cfis.device = ATA_LBA;
+ cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
+ cfis.sector_count = blkcnt & 0xff;
+
+ res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
+ is_write);
+
+ return res >= 0 ? blkcnt : res;
+}
+
+static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
+ int is_write)
+{
+ struct sata_fis_h2d cfis;
+ lbaint_t block;
+ u32 res;
+
+ block = start;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+ cfis.device = ATA_LBA;
+
+ cfis.device |= (block >> 24) & 0xf;
+ cfis.lba_high = (block >> 16) & 0xff;
+ cfis.lba_mid = (block >> 8) & 0xff;
+ cfis.lba_low = block & 0xff;
+ cfis.sector_count = (u8)(blkcnt & 0xff);
+
+ res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
+ is_write);
+
+ return res >= 0 ? blkcnt : res;
+}
+
+static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer, int is_write)
+{
+ lbaint_t start, blks;
+ u8 *addr;
+ int max_blks;
+
+ debug("%s: %ld %ld\n", __func__, blknr, blkcnt);
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = MV_ATA_MAX_SECTORS;
+ do {
+ if (blks > max_blks) {
+ if (sata_dev_desc[dev].lba48) {
+ mv_sata_rw_cmd_ext(dev, start, max_blks, addr,
+ is_write);
+ } else {
+ mv_sata_rw_cmd(dev, start, max_blks, addr,
+ is_write);
+ }
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ if (sata_dev_desc[dev].lba48) {
+ mv_sata_rw_cmd_ext(dev, start, blks, addr,
+ is_write);
+ } else {
+ mv_sata_rw_cmd(dev, start, blks, addr,
+ is_write);
+ }
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blkcnt;
+}
+
+static int mv_ata_exec_ata_cmd_nondma(int port,
+ struct sata_fis_h2d *cfis, u8 *buffer,
+ u32 len, u32 iswrite)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int i;
+ u16 *tp;
+
+ debug("%s\n", __func__);
+
+ out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
+ out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
+ out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
+ out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
+ out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
+ out_le32(priv->regbase + PIO_DEVICE, cfis->device);
+ out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
+
+ if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
+ ATA_BUSY, 0x0, 10000)) {
+ debug("Failed to wait for completion\n");
+ return -1;
+ }
+
+ if (len > 0) {
+ tp = (u16 *)buffer;
+ for (i = 0; i < len / 2; i++) {
+ if (iswrite)
+ out_le16(priv->regbase + PIO_DATA, *tp++);
+ else
+ *tp++ = in_le16(priv->regbase + PIO_DATA);
+ }
+ }
+
+ return len;
+}
+
+static int mv_sata_identify(int port, u16 *id)
+{
+ struct sata_fis_h2d h2d;
+
+ memset(&h2d, 0, sizeof(struct sata_fis_h2d));
+
+ h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ h2d.command = ATA_CMD_ID_ATA;
+
+ /* Give device time to get operational */
+ mdelay(10);
+
+ return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id,
+ ATA_ID_WORDS * 2, READ_CMD);
+}
+
+static void mv_sata_xfer_mode(int port, u16 *id)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ priv->pio = id[ATA_ID_PIO_MODES];
+ priv->mwdma = id[ATA_ID_MWDMA_MODES];
+ priv->udma = id[ATA_ID_UDMA_MODES];
+ debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
+ priv->udma);
+}
+
+static void mv_sata_set_features(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ struct sata_fis_h2d cfis;
+ u8 udma_cap;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_SET_FEATURES;
+ cfis.features = SETFEATURES_XFER;
+
+ /* First check the device capablity */
+ udma_cap = (u8) (priv->udma & 0xff);
+
+ if (udma_cap == ATA_UDMA6)
+ cfis.sector_count = XFER_UDMA_6;
+ if (udma_cap == ATA_UDMA5)
+ cfis.sector_count = XFER_UDMA_5;
+ if (udma_cap == ATA_UDMA4)
+ cfis.sector_count = XFER_UDMA_4;
+ if (udma_cap == ATA_UDMA3)
+ cfis.sector_count = XFER_UDMA_3;
+
+ mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD);
+}
+
+int mv_sata_spin_down(int dev)
+{
+ struct sata_fis_h2d cfis;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
+
+ if (priv->link == 0) {
+ debug("No device on port: %d\n", dev);
+ return 1;
+ }
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_STANDBY;
+
+ return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
+}
+
+int mv_sata_spin_up(int dev)
+{
+ struct sata_fis_h2d cfis;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
+
+ if (priv->link == 0) {
+ debug("No device on port: %d\n", dev);
+ return 1;
+ }
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_IDLE;
+
+ return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
+}
+
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+ return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD);
+}
+
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
+{
+ return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD);
+}
+
+/*
+ * Initialize SATA memory windows
+ */
+static void mvsata_ide_conf_mbus_windows(void)
+{
+ const struct mbus_dram_target_info *dram;
+ int i;
+
+ dram = mvebu_mbus_dram_info();
+
+ /* Disable windows, Set Size/Base to 0 */
+ for (i = 0; i < 4; i++) {
+ writel(0, MVSATA_WIN_CONTROL(i));
+ writel(0, MVSATA_WIN_BASE(i));
+ }
+
+ for (i = 0; i < dram->num_cs; i++) {
+ const struct mbus_dram_window *cs = dram->cs + i;
+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ MVSATA_WIN_CONTROL(i));
+ writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
+ }
+}
+
+int init_sata(int dev)
+{
+ struct mv_priv *priv;
+
+ debug("Initialize sata dev: %d\n", dev);
+
+ if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
+ printf("Invalid sata device %d\n", dev);
+ return -1;
+ }
+
+ priv = (struct mv_priv *)malloc(sizeof(struct mv_priv));
+ if (!priv) {
+ printf("Failed to allocate memory for private sata data\n");
+ return -ENOMEM;
+ }
+
+ memset((void *)priv, 0, sizeof(struct mv_priv));
+
+ /* Allocate and align request buffer */
+ priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
+ CRQB_ALIGN);
+ if (!priv->crqb_alloc) {
+ printf("Unable to allocate memory for request queue\n");
+ return -ENOMEM;
+ }
+ memset(priv->crqb_alloc, 0,
+ sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
+ priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
+ ~(CRQB_ALIGN - 1));
+
+ /* Allocate and align response buffer */
+ priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
+ CRPB_ALIGN);
+ if (!priv->crpb_alloc) {
+ printf("Unable to allocate memory for response queue\n");
+ return -ENOMEM;
+ }
+ memset(priv->crpb_alloc, 0,
+ sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
+ priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
+ ~(CRPB_ALIGN - 1));
+
+ sata_dev_desc[dev].priv = (void *)priv;
+
+ sprintf(priv->name, "SATA%d", dev);
+
+ priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE;
+
+ if (!hw_init) {
+ debug("Initialize sata hw\n");
+ hw_init = 1;
+ mv_reset_one_hc();
+ mvsata_ide_conf_mbus_windows();
+ }
+
+ mv_reset_port(dev);
+
+ if (probe_port(dev)) {
+ priv->link = 0;
+ return -ENODEV;
+ }
+ priv->link = 1;
+
+ return 0;
+}
+
+int reset_sata(int dev)
+{
+ return 0;
+}
+
+int scan_sata(int port)
+{
+ unsigned char serial[ATA_ID_SERNO_LEN + 1];
+ unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
+ unsigned char product[ATA_ID_PROD_LEN + 1];
+ u64 n_sectors;
+ u16 *id;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ if (!priv->link)
+ return -ENODEV;
+
+ id = (u16 *)malloc(ATA_ID_WORDS * 2);
+ if (!id) {
+ printf("Failed to malloc id data\n");
+ return -ENOMEM;
+ }
+
+ mv_sata_identify(port, id);
+ ata_swap_buf_le16(id, ATA_ID_WORDS);
+#ifdef DEBUG
+ ata_dump_id(id);
+#endif
+
+ /* Serial number */
+ ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
+ memcpy(sata_dev_desc[port].product, serial, sizeof(serial));
+
+ /* Firmware version */
+ ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
+ memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware));
+
+ /* Product model */
+ ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
+ memcpy(sata_dev_desc[port].vendor, product, sizeof(product));
+
+ /* Total sectors */
+ n_sectors = ata_id_n_sectors(id);
+ sata_dev_desc[port].lba = n_sectors;
+
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ sata_dev_desc[port].lba48 = 1;
+ debug("Device support LBA48\n");
+ }
+
+ /* Get the NCQ queue depth from device */
+ priv->queue_depth = ata_id_queue_depth(id);
+
+ /* Get the xfer mode from device */
+ mv_sata_xfer_mode(port, id);
+
+ /* Set the xfer mode to highest speed */
+ mv_sata_set_features(port);
+
+ /* Start up */
+ mv_start_edma_engine(port);
+
+ return 0;
+}
return in16(base + off);
}
-static unsigned long systemace_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer);
+static unsigned long systemace_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer);
static block_dev_desc_t systemace_dev = { 0 };
* the dev_desc) to read blocks of data. The return value is the
* number of blocks read. A zero return indicates an error.
*/
-static unsigned long systemace_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer)
+static unsigned long systemace_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
{
int retry;
unsigned blk_countdown;
bool "Support numbered aliases in device tree"
depends on DM
default y
+ help
+ Most boards will have a '/aliases' node containing the path to
+ numbered devices (e.g. serial0 = &serial0). This feature can be
+ disabled if it is not required.
+
+config SPL_DM_SEQ_ALIAS
+ bool "Support numbered aliases in device tree in SPL"
+ depends on DM
+ default n
help
Most boards will have a '/aliases' node containing the path to
numbered devices (e.g. serial0 = &serial0). This feature can be
dev->seq = -1;
dev->req_seq = -1;
- if (CONFIG_IS_ENABLED(OF_CONTROL) && IS_ENABLED(CONFIG_DM_SEQ_ALIAS)) {
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) {
/*
* Some devices, such as a SPI bus, I2C bus and serial ports
* are numbered using aliases.
return dev->uclass->uc_drv->name;
}
-fdt_addr_t dev_get_addr(struct udevice *dev)
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
fdt_addr_t addr;
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
const fdt32_t *reg;
+ int len = 0;
+ int na, ns;
+
+ na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (na < 1) {
+ debug("bad #address-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (ns < 0) {
+ debug("bad #size-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
- if (!reg)
+ reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+ if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
+ debug("Req index out of range\n");
return FDT_ADDR_T_NONE;
+ }
+
+ reg += index * (na + ns);
/*
* Use the full-fledged translate function for complex
* bus setups.
*/
- return fdt_translate_address((void *)gd->fdt_blob,
+ addr = fdt_translate_address((void *)gd->fdt_blob,
dev->of_offset, reg);
+ } else {
+ /*
+ * Use the "simple" translate function for less complex
+ * bus setups.
+ */
+ addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ dev->parent->of_offset,
+ dev->of_offset, "reg",
+ index, NULL);
+ if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
+ if (device_get_uclass_id(dev->parent) ==
+ UCLASS_SIMPLE_BUS)
+ addr = simple_bus_translate(dev->parent, addr);
+ }
}
/*
- * Use the "simple" translate function for less complex
- * bus setups.
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling dm_set_translation_offset() that
+ * will get added to all addresses returned by dev_get_addr().
*/
- addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev->parent->of_offset,
- dev->of_offset, "reg",
- 0, NULL);
- if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
- if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
- addr = simple_bus_translate(dev->parent, addr);
- }
+ addr += dm_get_translation_offset();
return addr;
#else
#endif
}
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+ return dev_get_addr_index(dev, 0);
+}
+
bool device_has_children(struct udevice *dev)
{
return !list_empty(&dev->child_head);
DECLARE_GLOBAL_DATA_PTR;
+struct root_priv {
+ fdt_addr_t translation_offset; /* optional translation offset */
+};
+
static const struct driver_info root_info = {
.name = "root_driver",
};
return gd->dm_root;
}
+fdt_addr_t dm_get_translation_offset(void)
+{
+ struct udevice *root = dm_root();
+ struct root_priv *priv = dev_get_priv(root);
+
+ return priv->translation_offset;
+}
+
+void dm_set_translation_offset(fdt_addr_t offs)
+{
+ struct udevice *root = dm_root();
+ struct root_priv *priv = dev_get_priv(root);
+
+ priv->translation_offset = offs;
+}
+
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fix_drivers(void)
{
U_BOOT_DRIVER(root_driver) = {
.name = "root_driver",
.id = UCLASS_ROOT,
+ .priv_auto_alloc_size = sizeof(struct root_priv),
};
/* This is the root uclass */
return MV_OK;
}
-/*
- * Read training result table
- */
-int hws_ddr3_tip_read_training_result(
- u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
-{
- dev_num = dev_num;
-
- if (result == NULL)
- return MV_BAD_PARAM;
- memcpy(result, training_result, sizeof(result));
-
- return MV_OK;
-}
-
/*
* Get training result info pointer
*/
struct hws_topology_map *topology);
int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
-int hws_ddr3_tip_read_training_result(u32 dev_num,
- enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
#define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define ECC_SUPPORT
+#endif
#define NEW_FABRIC_TWSI_ADDR 0x4E
#ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
* DDR3_TRAINING_DEBUG - Debug prints of internal code
*/
#define DDR_TARGET_FABRIC 5
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define DRAM_ECC 1
+#else
+#define DRAM_ECC 0
+#endif
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
#define BUS_WIDTH 32
#else
#define BUS_WIDTH 64
#define __AXP_MC_STATIC_H
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
-#else /* MV_DDR_64BIT */
+#else /* CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B040}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
/*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
#endif
DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n")
#ifdef MV_DEBUG_WL
+#define DEBUG_WL_S(s) puts(s)
+#define DEBUG_WL_D(d, l) printf("%x", d)
#define DEBUG_RL_S(s) \
debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s)
#define DEBUG_RL_D(d, l) \
DEBUG_WL_FULL_D((u32) phase, 1);
DEBUG_WL_FULL_S(", Delay = ");
DEBUG_WL_FULL_D((u32) delay, 1);
- DEBUG_WL_FULL_S(", Counter = ");
- DEBUG_WL_FULL_D((u32) i, 1);
DEBUG_WL_FULL_S("\n");
/* Drive DQS high for one cycle - All data PUPs */
static long dfu_file_buf_len;
static long dfu_file_buf_filled;
-static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
-{
- int ret;
-
- if (part == mmc->part_num)
- return 0;
-
- ret = mmc_switch_part(dfu->data.mmc.dev_num, part);
- if (ret) {
- error("Cannot switch to partition %d\n", part);
- return ret;
- }
- mmc->part_num = part;
-
- return 0;
-}
-
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
{
}
if (dfu->data.mmc.hw_partition >= 0) {
- part_num_bkp = mmc->part_num;
- ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition);
+ part_num_bkp = mmc->block_dev.hwpart;
+ ret = mmc_select_hwpart(dfu->data.mmc.dev_num,
+ dfu->data.mmc.hw_partition);
if (ret)
return ret;
}
dfu->data.mmc.dev_num, blk_start, blk_count, buf);
switch (op) {
case DFU_OP_READ:
- n = mmc->block_dev.block_read(dfu->data.mmc.dev_num, blk_start,
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk_start,
blk_count, buf);
break;
case DFU_OP_WRITE:
- n = mmc->block_dev.block_write(dfu->data.mmc.dev_num, blk_start,
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
blk_count, buf);
break;
default:
if (n != blk_count) {
error("MMC operation failed");
if (dfu->data.mmc.hw_partition >= 0)
- mmc_access_part(dfu, mmc, part_num_bkp);
+ mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
return -EIO;
}
if (dfu->data.mmc.hw_partition >= 0) {
- ret = mmc_access_part(dfu, mmc, part_num_bkp);
+ ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
if (ret)
return ret;
}
#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
-#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
+#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
#include <asm/arch/soc.h>
#elif defined(CONFIG_SUNXI)
#include <asm/arch/i2c.h>
blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst);
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
+ vdst);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
hang();
/*
* Read source addr from sd card
*/
- err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
+ err = mmc->block_dev.block_read(&mmc->block_dev,
+ CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
if (err != 1) {
puts("spl: mmc read failed!!\n");
free(tmp_buf);
#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
- err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
return blkcnt;
}
-static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
+static ulong mmc_bread(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
{
+ int dev_num = block_dev->dev;
+ int err;
lbaint_t cur, blocks_todo = blkcnt;
if (blkcnt == 0)
if (!mmc)
return 0;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return 0;
+
if ((start + blkcnt) > mmc->block_dev.lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
if (!mmc)
return -ENODEV;
- if (mmc->part_num == hwpart)
+ if (mmc->block_dev.hwpart == hwpart)
return 0;
if (mmc->part_config == MMCPART_NOAVAILABLE) {
if (ret)
return ret;
- mmc->part_num = hwpart;
-
return 0;
}
* Set the capacity if the switch succeeded or was intended
* to return to representing the raw device.
*/
- if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
+ if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
ret = mmc_set_capacity(mmc, part_num);
+ mmc->block_dev.hwpart = part_num;
+ }
return ret;
}
mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
}
- err = mmc_set_capacity(mmc, mmc->part_num);
+ err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
if (err)
return err;
/* fill in device description */
mmc->block_dev.lun = 0;
+ mmc->block_dev.hwpart = 0;
mmc->block_dev.type = 0;
mmc->block_dev.blksz = mmc->read_bl_len;
mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
return err;
/* The internal partition reset to user partition(0) at every CMD0*/
- mmc->part_num = 0;
+ mmc->block_dev.hwpart = 0;
/* Test for SD version 2 */
err = mmc_send_if_cond(mmc);
#ifndef CONFIG_SPL_BUILD
-extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt);
+unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt);
-extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
- const void *src);
+unsigned long mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src);
#else /* CONFIG_SPL_BUILD */
/* SPL will never write or erase, declare dummies to reduce code size. */
-static inline unsigned long mmc_berase(int dev_num, lbaint_t start,
- lbaint_t blkcnt)
+static inline unsigned long mmc_berase(block_dev_desc_t *block_dev,
+ lbaint_t start, lbaint_t blkcnt)
{
return 0;
}
-static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
- const void *src)
+static inline ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src)
{
return 0;
}
return err;
}
-unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt)
+unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt)
{
+ int dev_num = block_dev->dev;
int err = 0;
u32 start_rem, blkcnt_rem;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return -1;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return -1;
+
/*
* We want to see if the requested start or total block count are
* unaligned. We discard the whole numbers and only care about the
return blkcnt;
}
-ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src)
+ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt,
+ const void *src)
{
+ int dev_num = block_dev->dev;
lbaint_t cur, blocks_todo = blkcnt;
+ int err;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return 0;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return 0;
+
if (mmc_set_blocklen(mmc, mmc->write_bl_len))
return 0;
#include <sdhci.h>
#include <asm/pci.h>
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids)
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
{
struct sdhci_host *mmc_host;
- pci_dev_t devbusfn;
u32 iobase;
int ret;
int i;
- for (i = 0; i < num_ids; i++) {
- devbusfn = pci_find_devices(mmc_supported, i);
- if (devbusfn == -1)
- return -ENODEV;
+ for (i = 0; ; i++) {
+ struct udevice *dev;
+ ret = pci_find_device_id(mmc_supported, i, &dev);
+ if (ret)
+ return ret;
mmc_host = malloc(sizeof(struct sdhci_host));
if (!mmc_host)
return -ENOMEM;
mmc_host->name = (char *)name;
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
mmc_host->ioaddr = (void *)iobase;
mmc_host->quirks = 0;
ret = add_sdhci(mmc_host, 0, 0);
panic("Failed to allocate memory\n");
if (mmc_getcd(mmc) && mmc_init(mmc) == 0 &&
- mmc->block_dev.block_read(mmc->block_dev.dev, 16, 1, buf) == 1 &&
+ mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 &&
strncmp(&buf[4], "eGON.BT0", 8) == 0)
valid_signature = 1;
void spi_flash_free(struct spi_flash *flash)
{
- spi_flash_remove(flash->spi->dev);
+ device_remove(flash->spi->dev);
}
int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
return 0;
}
-int spi_flash_remove(struct udevice *dev)
-{
- return device_remove(dev);
-}
-
static int spi_flash_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
enum spi_dual_flash {
SF_SINGLE_FLASH = 0,
- SF_DUAL_STACKED_FLASH = 1 << 0,
- SF_DUAL_PARALLEL_FLASH = 1 << 1,
+ SF_DUAL_STACKED_FLASH = BIT(0),
+ SF_DUAL_PARALLEL_FLASH = BIT(1),
};
/* Enum list - Full read commands */
enum spi_read_cmds {
- ARRAY_SLOW = 1 << 0,
- ARRAY_FAST = 1 << 1,
- DUAL_OUTPUT_FAST = 1 << 2,
- DUAL_IO_FAST = 1 << 3,
- QUAD_OUTPUT_FAST = 1 << 4,
- QUAD_IO_FAST = 1 << 5,
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ QUAD_OUTPUT_FAST = BIT(3),
+ DUAL_IO_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
};
/* Normal - Extended - Full command set */
/* sf param flags */
enum {
-#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
- SECT_4K = 1 << 0,
+#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
+ SECT_4K = 0,
#else
- SECT_4K = 0 << 0,
+ SECT_4K = BIT(0),
#endif
- SECT_32K = 1 << 1,
- E_FSR = 1 << 2,
- SST_WR = 1 << 3,
- WR_QPP = 1 << 4,
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_WR = BIT(3),
+ WR_QPP = BIT(4),
};
enum spi_nor_option_flags {
- SNOR_F_SST_WR = (1 << 0),
- SNOR_F_USE_FSR = (1 << 1),
+ SNOR_F_SST_WR = BIT(0),
+ SNOR_F_USE_FSR = BIT(1),
};
#define SPI_FLASH_3B_ADDR_LEN 3
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS1 0x35
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
#endif
/* Common status */
-#define STATUS_WIP (1 << 0)
-#define STATUS_QEB_WINSPAN (1 << 1)
-#define STATUS_QEB_MXIC (1 << 6)
-#define STATUS_PEC (1 << 7)
+#define STATUS_WIP BIT(0)
+#define STATUS_QEB_WINSPAN BIT(1)
+#define STATUS_QEB_MXIC BIT(6)
+#define STATUS_PEC BIT(7)
+#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (flash->spi->mode & SPI_TX_BYTE)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
cmd[3] = addr >> 0;
}
-/* Read commands array */
-static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_QUAD_IO_FAST,
-};
-
static int read_sr(struct spi_flash *flash, u8 *rs)
{
int ret;
}
#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int read_evcr(struct spi_flash *flash, u8 *evcr)
+{
+ int ret;
+ const u8 cmd = CMD_READ_EVCR;
+
+ ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
+ if (ret < 0) {
+ debug("SF: error reading EVCR\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int write_evcr(struct spi_flash *flash, u8 evcr)
+{
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_WRITE_EVCR;
+ ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
+ if (ret < 0) {
+ debug("SF: error while writing EVCR register\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
{
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bank_end;
+ goto bar_end;
switch (idcode0) {
case SPI_FLASH_CFI_MFR_SPANSION:
return ret;
}
-bank_end:
+bar_end:
flash->bank_curr = curr_bank;
return 0;
}
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
+ struct spi_slave *spi = flash->spi;
+
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- flash->spi->flags |= SPI_XFER_U_PAGE;
+ spi->flags |= SPI_XFER_U_PAGE;
} else {
- flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ spi->flags &= ~SPI_XFER_U_PAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
if (buf == NULL)
timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
byte_addr = offset % page_size;
chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
- if (flash->spi->max_write_size)
+ if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
+ (size_t)spi->max_write_size);
spi_flash_addr(write_addr, cmd);
struct spi_slave *spi = flash->spi;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ struct spi_slave *spi = flash->spi;
u8 *cmd, cmdsz;
u32 remain_len, read_len, read_addr;
int bank_sel = 0;
/* Handle memory-mapped SPI */
if (flash->memory_map) {
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
}
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
spi_flash_copy_mmap(data, flash->memory_map + offset, len);
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
- spi_release_bus(flash->spi);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+ spi_release_bus(spi);
return 0;
}
#ifdef CONFIG_SPI_FLASH_SST
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
int ret;
u8 cmd[4] = {
CMD_SST_BP,
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
return ret;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
if (ret)
return ret;
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual, cmd_len;
int ret;
u8 cmd[4];
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
cmd[0], offset);
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len,
buf + actual, 2);
if (ret) {
debug("SF: sst word program failed\n");
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
-static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+static int macronix_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_MXIC) {
- debug("SF: mxic: QEB is already set\n");
- } else {
- ret = write_sr(flash, STATUS_QEB_MXIC);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_MXIC)
+ return 0;
+
+ ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+
+ /* read SR and check it */
+ ret = read_sr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
+ printf("SF: Macronix SR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_WINSPAN) {
- debug("SF: winspan: QEB is already set\n");
- } else {
- ret = write_cr(flash, STATUS_QEB_WINSPAN);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_WINSPAN)
+ return 0;
+
+ ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+
+ /* read CR and check it */
+ ret = read_cr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
+ printf("SF: Spansion CR Quad bit not clear\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int micron_quad_enable(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = read_evcr(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (!(qeb_status & STATUS_QEB_MICRON))
+ return 0;
+
+ ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
+ if (ret < 0)
+ return ret;
+
+ /* read EVCR and check it */
+ ret = read_evcr(flash, &qeb_status);
+ if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
+ printf("SF: Micron EVCR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
}
#endif
-static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
- return spi_flash_set_qeb_mxic(flash);
+ return macronix_quad_enable(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
- return spi_flash_set_qeb_winspan(flash);
+ return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- debug("SF: QEB is volatile for %02x flash\n", idcode0);
- return 0;
+ return micron_quad_enable(flash);
#endif
default:
printf("SF: Need set QEB func for %02x flash\n", idcode0);
struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params;
u16 jedec, ext_jedec;
- u8 idcode[5];
- u8 cmd;
+ u8 cmd, idcode[5];
int ret;
+ static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_ARRAY_FAST,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_IO_FAST };
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
/* Assign spi data */
flash->name = params->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = flash->spi->option;
+ flash->dual_flash = spi->option;
/* Assign spi flash flags */
if (params->flags & SST_WR)
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (spi->mode & SPI_TX_BYTE)
flash->write = sst_write_bp;
else
flash->write = sst_write_wp;
flash->sector_size = flash->erase_size;
/* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ cmd = fls(params->e_rd_cmd & spi->mode_rx);
if (cmd) {
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
}
/* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = spi_flash_set_qeb(flash, idcode[0]);
+ ret = set_quad_mode(flash, idcode[0]);
if (ret) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
return -EINVAL;
* or via a PCI bridge, fill in platdata before we probe the hardware.
*/
if (device_is_on_pci_bus(dev)) {
- pci_dev_t bdf = pci_get_bdf(dev);
+ pci_dev_t bdf = dm_pci_get_bdf(dev);
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
eeprom->use_eerd = true;
eeprom->use_eewr = false;
break;
-
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- case e1000_ich8lan:
- {
- int32_t i = 0;
-
- eeprom->type = e1000_eeprom_ich8;
- eeprom->use_eerd = false;
- eeprom->use_eewr = false;
- eeprom->word_size = E1000_SHADOW_RAM_WORDS;
- uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
- ICH_FLASH_GFPREG);
- /* Zero the shadow RAM structure. But don't load it from NVM
- * so as to save time for driver init */
- if (hw->eeprom_shadow_ram != NULL) {
- for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = false;
- hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
- }
- }
-
- hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
- ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size = ((flash_size >> 16)
- & ICH_GFPREG_BASE_MASK) + 1;
- hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
-
- hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size /= 2 * sizeof(uint16_t);
- break;
- }
-#endif
default:
break;
}
if (eeprom->use_eerd == true)
return e1000_read_eeprom_eerd(hw, offset, words, data);
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- /* ICH EEPROM access is done via the ICH flash controller */
- if (eeprom->type == e1000_eeprom_ich8)
- return e1000_read_eeprom_ich8(hw, offset, words, data);
-#endif
/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
* acquired the EEPROM at this point, so any returns should relase it */
if (eeprom->type == e1000_eeprom_spi) {
* occuring when accessing our register space */
E1000_WRITE_FLUSH(hw);
}
-#if 0
- /* Set the PCI priority bit correctly in the CTRL register. This
- * determines if the adapter gives priority to receives, or if it
- * gives equal priority to transmits and receives. Valid only on
- * 82542 and 82543 silicon.
- */
- if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
- ctrl = E1000_READ_REG(hw, CTRL);
- E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
- }
-#endif
+
switch (hw->mac_type) {
case e1000_82545_rev_3:
case e1000_82546_rev_3:
break;
}
-#if 0
- /* Clear all of the statistics registers (clear on read). It is
- * important that we do this after we have tried to establish link
- * because the symbol error count will increment wildly if there
- * is no link.
- */
- e1000_clear_hw_cntrs(hw);
-
- /* ICH8 No-snoop bits are opposite polarity.
- * Set to snoop by default after reset. */
- if (hw->mac_type == e1000_ich8lan)
- e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
-#endif
-
if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
- /* put the card in its initial state */
-#if 0
- E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
-#endif
mdelay(10);
}
#ifndef CONFIG_E1000_NO_NVM
/* Validate the EEPROM and get chipset information */
-#if !defined(CONFIG_MVBC_1G)
if (e1000_init_eeprom_params(hw)) {
E1000_ERR(hw, "EEPROM is invalid!\n");
return -EINVAL;
if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
e1000_validate_eeprom_checksum(hw))
return -ENXIO;
-#endif
e1000_read_mac_addr(hw, enetaddr);
#endif
e1000_get_bus_type(hw);
int ret;
hw->name = dev->name;
- ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev),
- plat->enetaddr);
+ ret = e1000_init_one(hw, trailing_strtol(dev->name),
+ dm_pci_get_bdf(dev), plat->enetaddr);
if (ret < 0) {
printf(pr_fmt("failed to initialize card: %d\n"), ret);
return ret;
e1000_media_type media_type;
e1000_fc_type fc;
e1000_bus_type bus_type;
-#if 0
- e1000_bus_speed bus_speed;
- e1000_bus_width bus_width;
- uint32_t io_base;
-#endif
uint32_t asf_firmware_present;
#ifndef CONFIG_E1000_NO_NVM
uint32_t eeprom_semaphore_present;
uint32_t original_fc;
uint32_t txcw;
uint32_t autoneg_failed;
-#if 0
- uint32_t max_frame_size;
- uint32_t min_frame_size;
- uint32_t mc_filter_type;
- uint32_t num_mc_addrs;
- uint32_t collision_delta;
- uint32_t tx_packet_delta;
- uint32_t ledctl_default;
- uint32_t ledctl_mode1;
- uint32_t ledctl_mode2;
-#endif
uint16_t autoneg_advertised;
uint16_t pci_cmd_word;
uint16_t fc_high_water;
uint16_t fc_low_water;
uint16_t fc_pause_time;
-#if 0
- uint16_t current_ifs_val;
- uint16_t ifs_min_val;
- uint16_t ifs_max_val;
- uint16_t ifs_step_size;
- uint16_t ifs_ratio;
-#endif
uint16_t device_id;
uint16_t vendor_id;
uint16_t subsystem_id;
uint8_t forced_speed_duplex;
uint8_t wait_autoneg_complete;
uint8_t dma_fairness;
-#if 0
- uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
-#endif
bool disable_polarity_correction;
bool speed_downgraded;
bool get_link_status;
bool report_tx_early;
bool phy_reset_disable;
bool initialize_hw_bits_disable;
-#if 0
- bool adaptive_ifs;
- bool ifs_params_forced;
- bool in_ifs_mode;
-#endif
e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state;
};
* These have been tested to perform correctly, but they are not used by any
* of the EEPROM commands at this time.
*/
-#if 0
-static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr)
+static __maybe_unused int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw,
+ bool intr)
{
u8 op[] = { SPI_EEPROM_DISABLE_WR };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
-static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
- u8 status, bool intr)
+static __maybe_unused int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
+ u8 status, bool intr)
{
u8 op[] = { SPI_EEPROM_WRITE_STATUS, status };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
-#endif
static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr)
{
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
return -EFAULT;
}
+ /* write the phy and reg addressse into the MII address reg */
+ writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
+ ®s->madr);
+
+ /* write data to the MII write register */
+ writel(data, ®s->mwtd);
+
/* wait till the MII is not busy */
timeout = MII_TIMEOUT;
do {
return -EFAULT;
}
- /* write the phy and reg addressse into the MII address reg */
- writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
- ®s->madr);
-
- /* write data to the MII write register */
- writel(data, ®s->mwtd);
-
/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
reg_ofs, data);*/
* Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
*
* U-Boot version:
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
*
* Based on the Linux version which is:
* Copyright (C) 2012 Marvell
*/
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
#include <linux/compat.h>
#include <linux/mbus.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if !defined(CONFIG_PHYLIB)
# error Marvell mvneta requires PHYLIB
#endif
mvneta_port_enable(pp);
}
-static void mvneta_adjust_link(struct eth_device *dev)
+static void mvneta_adjust_link(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct phy_device *phydev = pp->phydev;
int status_change = 0;
}
}
-static int mvneta_open(struct eth_device *dev)
+static int mvneta_open(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
int ret;
ret = mvneta_setup_rxqs(pp);
}
/* Initialize hw */
-static int mvneta_init(struct mvneta_port *pp)
+static int mvneta_init2(struct mvneta_port *pp)
{
int queue;
}
/* Device initialization routine */
-static int mvneta_probe(struct eth_device *dev)
+static int mvneta_init(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvneta_port *pp = dev_get_priv(dev);
int err;
pp->tx_ring_size = MVNETA_MAX_TXD;
pp->rx_ring_size = MVNETA_MAX_RXD;
- err = mvneta_init(pp);
+ err = mvneta_init2(pp);
if (err < 0) {
dev_err(&pdev->dev, "can't init eth hal\n");
return err;
}
- mvneta_conf_mbus_windows(pp);
-
- mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def);
+ mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
err = mvneta_port_power_up(pp, pp->phy_interface);
if (err < 0) {
}
/*
- * smi_reg_read - miiphy_read callback function.
+ * mvneta_mdio_read - miiphy_read callback function.
*
* Returns 16bit phy register value, or 0xffff on error
*/
-static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data)
+static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = bus->priv;
u32 smi_reg;
u32 timeout;
/* check parameters */
- if (phy_adr > MVNETA_PHY_ADDR_MASK) {
- printf("Error: Invalid PHY address %d\n", phy_adr);
+ if (addr > MVNETA_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
return -EFAULT;
}
- if (reg_ofs > MVNETA_PHY_REG_MASK) {
- printf("Err: Invalid register offset %d\n", reg_ofs);
+ if (reg > MVNETA_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
return -EFAULT;
}
return -EFAULT;
/* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS)
+ smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
+ | (reg << MVNETA_SMI_REG_ADDR_OFFS)
| MVNETA_SMI_OPCODE_READ;
/* write the smi register */
mvreg_write(pp, MVNETA_SMI, smi_reg);
- /*wait till read value is ready */
+ /* wait till read value is ready */
timeout = MVNETA_SMI_TIMEOUT;
do {
for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
;
- *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK);
-
- return 0;
+ return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
}
/*
- * smi_reg_write - imiiphy_write callback function.
+ * mvneta_mdio_write - miiphy_write callback function.
*
* Returns 0 if write succeed, -EINVAL on bad parameters
* -ETIME on timeout
*/
-static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = bus->priv;
u32 smi_reg;
/* check parameters */
- if (phy_adr > MVNETA_PHY_ADDR_MASK) {
- printf("Error: Invalid PHY address %d\n", phy_adr);
+ if (addr > MVNETA_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
return -EFAULT;
}
- if (reg_ofs > MVNETA_PHY_REG_MASK) {
- printf("Err: Invalid register offset %d\n", reg_ofs);
+ if (reg > MVNETA_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
return -EFAULT;
}
return -EFAULT;
/* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << MVNETA_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS);
+ smi_reg = value << MVNETA_SMI_DATA_OFFS;
+ smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
+ | (reg << MVNETA_SMI_REG_ADDR_OFFS);
smi_reg &= ~MVNETA_SMI_OPCODE_READ;
/* write the smi register */
return 0;
}
-static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis)
+static int mvneta_start(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct phy_device *phydev;
mvneta_port_power_up(pp, pp->phy_interface);
}
/* Full init on first call */
- mvneta_probe(dev);
+ mvneta_init(dev);
pp->init = 1;
} else {
/* Upon all following calls, this is enough */
return 0;
}
-static int mvneta_send(struct eth_device *dev, void *ptr, int len)
+static int mvneta_send(struct udevice *dev, void *packet, int length)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct mvneta_tx_queue *txq = &pp->txqs[0];
struct mvneta_tx_desc *tx_desc;
int sent_desc;
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
- tx_desc->buf_phys_addr = (u32)ptr;
- tx_desc->data_size = len;
- flush_dcache_range((u32)ptr, (u32)ptr + len);
+ tx_desc->buf_phys_addr = (u32)packet;
+ tx_desc->data_size = length;
+ flush_dcache_range((u32)packet, (u32)packet + length);
/* First and Last descriptor */
tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
/* txDone has increased - hw sent packet */
mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
- return 0;
return 0;
}
-static int mvneta_recv(struct eth_device *dev)
+static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
int rx_done;
- int packets_done;
struct mvneta_rx_queue *rxq;
+ int rx_bytes = 0;
/* get rx queue */
rxq = mvneta_rxq_handle_get(pp, rxq_def);
rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
- packets_done = rx_done;
- while (packets_done--) {
+ if (rx_done) {
struct mvneta_rx_desc *rx_desc;
unsigned char *data;
u32 rx_status;
- int rx_bytes;
/*
* No cache invalidation needed here, since the desc's are
(rx_status & MVNETA_RXD_ERR_SUMMARY)) {
mvneta_rx_error(pp, rx_desc);
/* leave the descriptor untouched */
- continue;
+ return -EIO;
}
/* 2 bytes for marvell header. 4 bytes for crc */
* No cache invalidation needed here, since the rx_buffer's are
* located in a uncached memory region
*/
- net_process_received_packet(data, rx_bytes);
- }
+ *packetp = data;
- /* Update rxq management counters */
- if (rx_done)
mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+ }
- return 0;
-}
-
-static void mvneta_halt(struct eth_device *dev)
-{
- struct mvneta_port *pp = dev->priv;
-
- mvneta_port_down(pp);
- mvneta_port_disable(pp);
+ return rx_bytes;
}
-int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr)
+static int mvneta_probe(struct udevice *dev)
{
- struct eth_device *dev;
- struct mvneta_port *pp;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvneta_port *pp = dev_get_priv(dev);
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ struct mii_dev *bus;
+ unsigned long addr;
void *bd_space;
- dev = calloc(1, sizeof(*dev));
- if (dev == NULL)
- return -ENOMEM;
-
- pp = calloc(1, sizeof(*pp));
- if (pp == NULL)
- return -ENOMEM;
-
- dev->priv = pp;
-
/*
* Allocate buffer area for descs and rx_buffers. This is only
* done once for all interfaces. As only one interface can
MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
}
- sprintf(dev->name, "neta%d", devnum);
+ pp->base = (void __iomem *)pdata->iobase;
- pp->base = (void __iomem *)base_addr;
- dev->iobase = base_addr;
- dev->init = mvneta_init_u_boot;
- dev->halt = mvneta_halt;
- dev->send = mvneta_send;
- dev->recv = mvneta_recv;
- dev->write_hwaddr = NULL;
+ /* Configure MBUS address windows */
+ mvneta_conf_mbus_windows(pp);
- /*
- * The PHY interface type is configured via the
- * board specific CONFIG_SYS_NETA_INTERFACE_TYPE
- * define.
- */
- pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE;
+ /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
+ pp->phy_interface = pdata->phy_interface;
+
+ /* Now read phyaddr from DT */
+ addr = fdtdec_get_int(blob, node, "phy", 0);
+ addr = fdt_node_offset_by_phandle(blob, addr);
+ pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mvneta_mdio_read;
+ bus->write = mvneta_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)pp;
+ pp->bus = bus;
- eth_register(dev);
+ return mdio_register(bus);
+}
- pp->phyaddr = phy_addr;
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
- pp->bus = miiphy_get_dev_by_name(dev->name);
+static void mvneta_stop(struct udevice *dev)
+{
+ struct mvneta_port *pp = dev_get_priv(dev);
- return 1;
+ mvneta_port_down(pp);
+ mvneta_port_disable(pp);
}
+
+static const struct eth_ops mvneta_ops = {
+ .start = mvneta_start,
+ .send = mvneta_send,
+ .recv = mvneta_recv,
+ .stop = mvneta_stop,
+};
+
+static int mvneta_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const char *phy_mode;
+
+ pdata->iobase = dev_get_addr(dev);
+
+ /* Get phy-mode / phy_interface from DT */
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mvneta_ids[] = {
+ { .compatible = "marvell,armada-370-neta" },
+ { .compatible = "marvell,armada-xp-neta" },
+ { }
+};
+
+U_BOOT_DRIVER(mvneta) = {
+ .name = "mvneta",
+ .id = UCLASS_ETH,
+ .of_match = mvneta_ids,
+ .ofdata_to_platdata = mvneta_ofdata_to_platdata,
+ .probe = mvneta_probe,
+ .ops = &mvneta_ops,
+ .priv_auto_alloc_size = sizeof(struct mvneta_port),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
pci_dev_t devno;
u32 iobase;
- devno = pci_get_bdf(dev);
+ devno = dm_pci_get_bdf(dev);
/*
* The priv structure contains the descriptors and frame buffers which
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
-static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
+#ifdef CONFIG_DM_ETH
+static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
+ uchar **packetp)
+#else
+static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
uchar **packetp)
+#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
+#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
- pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)
+ dm_pci_mem_to_phys(dev,
+ (pci_addr_t)(unsigned long)
+ tpc->RxBufferRing[cur_rx]));
+#else
+ tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
+ pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
+#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
#ifdef CONFIG_DM_ETH
*packetp = rxdata;
{
struct rtl8169_private *priv = dev_get_priv(dev);
- return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp);
+ return rtl_recv_common(dev, priv->iobase, packetp);
}
#else
static int rtl_recv(struct eth_device *dev)
/**************************************************************************
SEND - Transmit a frame
***************************************************************************/
-static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
+#ifdef CONFIG_DM_ETH
+static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
void *packet, int length)
+#else
+static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
+ void *packet, int length)
+#endif
{
/* send the packet to destination */
ptxb[len++] = '\0';
tpc->TxDescArray[entry].buf_Haddr = 0;
+#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
- pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
+ dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
+#else
+ tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
+ pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
+#endif
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
{
struct rtl8169_private *priv = dev_get_priv(dev);
- return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length);
+ return rtl_send_common(dev, priv->iobase, packet, length);
}
#else
RTL_W32(MAR0 + 4, mc_filter[1]);
}
-static void rtl8169_hw_start(pci_dev_t bdf)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_hw_start(struct udevice *dev)
+#else
+static void rtl8169_hw_start(pci_dev_t dev)
+#endif
{
u32 i;
tpc->cur_rx = 0;
- RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf,
+#ifdef CONFIG_DM_ETH
+ RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
+#else
+ RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
+ (pci_addr_t)(unsigned long)tpc->TxDescArray));
+#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
+#ifdef CONFIG_DM_ETH
+ RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
+ dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+#else
RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
- bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+ dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
#endif
}
-static void rtl8169_init_ring(pci_dev_t bdf)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_init_ring(struct udevice *dev)
+#else
+static void rtl8169_init_ring(pci_dev_t dev)
+#endif
{
int i;
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
+#ifdef CONFIG_DM_ETH
+ tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
+ dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+#else
tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
- bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+ dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+#endif
rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
#endif
}
-static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr)
+#else
+static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
+#endif
{
int i;
printf ("%s\n", __FUNCTION__);
#endif
- rtl8169_init_ring(bdf);
- rtl8169_hw_start(bdf);
+ rtl8169_init_ring(dev);
+ rtl8169_hw_start(dev);
/* Construct a perfect filter frame with the mac address as first match
* and broadcast for all others */
for (i = 0; i < 192; i++)
{
struct eth_pdata *plat = dev_get_platdata(dev);
- rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr);
+ rtl8169_common_start(dev, plat->enetaddr);
return 0;
}
region = 1;
break;
}
- pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4,
- &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
iobase &= ~0xf;
- priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase);
+ priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
if (ret < 0) {
#
ifneq ($(CONFIG_DM_PCI),)
-obj-$(CONFIG_PCI) += pci-uclass.o
+obj-y += pci_rom.o
+obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o
else
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
endif
-obj-$(CONFIG_PCI) += pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o
+obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
#include <fdtdec.h>
#include <inttypes.h>
#include <pci.h>
+#include <asm/io.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
#endif
+#include "pci_internal.h"
DECLARE_GLOBAL_DATA_PTR;
return dev;
}
-pci_dev_t pci_get_bdf(struct udevice *dev)
+pci_dev_t dm_pci_get_bdf(struct udevice *dev)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct udevice *bus = dev->parent;
return -ENODEV;
}
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
{
struct udevice *bus;
int ret;
return -ENODEV;
}
+static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
+ unsigned int device, int *indexp,
+ struct udevice **devp)
+{
+ struct pci_child_platdata *pplat;
+ struct udevice *dev;
+
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ pplat = dev_get_parent_platdata(dev);
+ if (pplat->vendor == vendor && pplat->device == device) {
+ if (!(*indexp)--) {
+ *devp = dev;
+ return 0;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+ struct udevice **devp)
+{
+ struct udevice *bus;
+
+ /* Scan all known buses */
+ for (uclass_first_device(UCLASS_PCI, &bus);
+ bus;
+ uclass_next_device(&bus)) {
+ if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
+ return device_probe(*devp);
+ }
+ *devp = NULL;
+
+ return -ENODEV;
+}
+
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ /* Scan all known buses */
+ for (pci_find_first_device(&dev);
+ dev;
+ pci_find_next_device(&dev)) {
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+
+ if (pplat->class == find_class && !index--) {
+ *devp = dev;
+ return device_probe(*devp);
+ }
+ }
+ *devp = NULL;
+
+ return -ENODEV;
+}
+
int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long value, enum pci_size_t size)
{
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
+ return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
+ size);
}
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
+ return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
size);
}
int ret;
debug("%s: device %s\n", __func__, dev->name);
- ret = pciauto_config_device(hose, pci_get_bdf(dev));
+ ret = dm_pciauto_config_device(dev);
if (ret < 0)
return ret;
max_bus = ret;
return sub_bus;
}
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
+int dm_pci_hose_probe_bus(struct udevice *bus)
{
- struct udevice *parent, *bus;
int sub_bus;
int ret;
debug("%s\n", __func__);
- parent = hose->bus;
-
- /* Find the bus within the parent */
- ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
- if (ret) {
- debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
- bdf, parent->name, ret);
- return ret;
- }
sub_bus = pci_get_bus_max() + 1;
debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
- pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
+ dm_pciauto_prescan_setup_bridge(bus, sub_bus);
ret = device_probe(bus);
if (ret) {
return -EPIPE;
}
sub_bus = pci_get_bus_max();
- pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
+ dm_pciauto_postscan_setup_bridge(bus, sub_bus);
return sub_bus;
}
/* Find this device in the device tree */
ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
- /* Search for a driver */
-
- /* If nothing in the device tree, bind a generic device */
+ /* If nothing in the device tree, bind a device */
if (ret == -ENODEV) {
struct pci_device_id find_id;
ulong val;
return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
}
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
+{
+ u32 addr;
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ dm_pci_read_config32(dev, bar, &addr);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ return addr & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
+
+static int _dm_pci_bus_to_phys(struct udevice *ctlr,
+ pci_addr_t bus_addr, unsigned long flags,
+ unsigned long skip_mask, phys_addr_t *pa)
+{
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ struct pci_region *res;
+ int i;
+
+ for (i = 0; i < hose->region_count; i++) {
+ res = &hose->regions[i];
+
+ if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+ continue;
+
+ if (res->flags & skip_mask)
+ continue;
+
+ if (bus_addr >= res->bus_start &&
+ (bus_addr - res->bus_start) < res->size) {
+ *pa = (bus_addr - res->bus_start + res->phys_start);
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
+ unsigned long flags)
+{
+ phys_addr_t phys_addr = 0;
+ struct udevice *ctlr;
+ int ret;
+
+ /* The root controller has the region information */
+ ctlr = pci_get_controller(dev);
+
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
+ if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+ ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
+ flags, PCI_REGION_SYS_MEMORY,
+ &phys_addr);
+ if (!ret)
+ return phys_addr;
+ }
+
+ ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
+
+ if (ret)
+ puts("pci_hose_bus_to_phys: invalid physical address\n");
+
+ return phys_addr;
+}
+
+int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags, unsigned long skip_mask,
+ pci_addr_t *ba)
+{
+ struct pci_region *res;
+ struct udevice *ctlr;
+ pci_addr_t bus_addr;
+ int i;
+ struct pci_controller *hose;
+
+ /* The root controller has the region information */
+ ctlr = pci_get_controller(dev);
+ hose = dev_get_uclass_priv(ctlr);
+
+ for (i = 0; i < hose->region_count; i++) {
+ res = &hose->regions[i];
+
+ if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+ continue;
+
+ if (res->flags & skip_mask)
+ continue;
+
+ bus_addr = phys_addr - res->phys_start + res->bus_start;
+
+ if (bus_addr >= res->bus_start &&
+ (bus_addr - res->bus_start) < res->size) {
+ *ba = bus_addr;
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags)
+{
+ pci_addr_t bus_addr = 0;
+ int ret;
+
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
+ if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+ ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
+ PCI_REGION_SYS_MEMORY, &bus_addr);
+ if (!ret)
+ return bus_addr;
+ }
+
+ ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
+
+ if (ret)
+ puts("pci_hose_phys_to_bus: invalid physical address\n");
+
+ return bus_addr;
+}
+
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
+{
+ pci_addr_t pci_bus_addr;
+ u32 bar_response;
+
+ /* read BAR address */
+ dm_pci_read_config32(dev, bar, &bar_response);
+ pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+
+ /*
+ * Pass "0" as the length argument to pci_bus_to_virt. The arg
+ * isn't actualy used on any platform because u-boot assumes a static
+ * linear mapping. In the future, this could read the BAR size
+ * and pass that as the size if needed.
+ */
+ return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
*/
/*
- * PCI routines
+ * Old PCI routines
+ *
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci-uclass.c.
*/
#include <common.h>
--- /dev/null
+/*
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+#endif
+
+void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+ struct pci_region *mem,
+ struct pci_region *prefetch, struct pci_region *io,
+ bool enum_only)
+{
+ u32 bar_response;
+ pci_size_t bar_size;
+ u16 cmdstat = 0;
+ int bar, bar_nr = 0;
+ u8 header_type;
+ int rom_addr;
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
+ int found_mem64 = 0;
+ u16 class;
+
+ dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+ cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
+ PCI_COMMAND_MASTER;
+
+ for (bar = PCI_BASE_ADDRESS_0;
+ bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+ /* Tickle the BAR and get the response */
+ if (!enum_only)
+ dm_pci_write_config32(dev, bar, 0xffffffff);
+ dm_pci_read_config32(dev, bar, &bar_response);
+
+ /* If BAR is not implemented go to the next BAR */
+ if (!bar_response)
+ continue;
+
+ found_mem64 = 0;
+
+ /* Check the BAR type and set our address mask */
+ if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+ bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
+ if (!enum_only)
+ bar_res = io;
+
+ debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+ bar_nr, (unsigned long long)bar_size);
+ } else {
+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+
+ if (!enum_only) {
+ dm_pci_write_config32(dev, bar + 4,
+ 0xffffffff);
+ }
+ dm_pci_read_config32(dev, bar + 4,
+ &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) |
+ bar_response;
+
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
+ + 1;
+ if (!enum_only)
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response &
+ PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
+ if (!enum_only) {
+ if (prefetch && (bar_response &
+ PCI_BASE_ADDRESS_MEM_PREFETCH)) {
+ bar_res = prefetch;
+ } else {
+ bar_res = mem;
+ }
+ }
+
+ debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+ bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+ (unsigned long long)bar_size);
+ }
+
+ if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
+ &bar_value) == 0) {
+ /* Write it out and update our limit */
+ dm_pci_write_config32(dev, bar, (u32)bar_value);
+
+ if (found_mem64) {
+ bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, bar,
+ (u32)(bar_value >> 32));
+#else
+ /*
+ * If we are a 64-bit decoder then increment to
+ * the upper 32 bits of the bar and force it to
+ * locate in the lower 4GB of memory.
+ */
+ dm_pci_write_config32(dev, bar, 0x00000000);
+#endif
+ }
+ }
+
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
+
+ debug("\n");
+
+ bar_nr++;
+ }
+
+ if (!enum_only) {
+ /* Configure the expansion ROM address */
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+ if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+ rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+ PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+ dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
+ dm_pci_read_config32(dev, rom_addr, &bar_response);
+ if (bar_response) {
+ bar_size = -(bar_response & ~1);
+ debug("PCI Autoconfig: ROM, size=%#x, ",
+ (unsigned int)bar_size);
+ if (pciauto_region_allocate(mem, bar_size,
+ &bar_value) == 0) {
+ dm_pci_write_config32(dev, rom_addr,
+ bar_value);
+ }
+ cmdstat |= PCI_COMMAND_MEMORY;
+ debug("\n");
+ }
+ }
+ }
+
+ /* PCI_COMMAND_IO must be set for VGA device */
+ dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+ if (class == PCI_CLASS_DISPLAY_VGA)
+ cmdstat |= PCI_COMMAND_IO;
+
+ dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
+ dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
+ CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
+}
+
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ u16 cmdstat, prefechable_64;
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+ dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Configure bus number registers */
+ dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
+ PCI_BUS(dm_pci_get_bdf(dev)));
+ dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus);
+ dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ dm_pci_write_config16(dev, PCI_MEMORY_BASE,
+ (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ }
+
+ if (pci_prefetch) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
+ (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
+#endif
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ } else {
+ /* We don't support prefetchable memory for now, so disable */
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+ dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
+ dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ dm_pci_write_config8(dev, PCI_IO_BASE,
+ (pci_io->bus_lower & 0x0000f000) >> 8);
+ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+ (pci_io->bus_lower & 0xffff0000) >> 16);
+
+ cmdstat |= PCI_COMMAND_IO;
+ }
+
+ /* Enable memory and I/O accesses, enable bus master */
+ dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+}
+
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ /* Configure bus number registers */
+ dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
+ (pci_mem->bus_lower - 1) >> 16);
+ }
+
+ if (pci_prefetch) {
+ u16 prefechable_64;
+
+ dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
+ (pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+#endif
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ dm_pci_write_config8(dev, PCI_IO_LIMIT,
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+ }
+}
+
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
+ */
+int dm_pciauto_config_device(struct udevice *dev)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
+ unsigned short class;
+ bool enum_only = false;
+ int n;
+
+#ifdef CONFIG_PCI_ENUM_ONLY
+ enum_only = true;
+#endif
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+
+ switch (class) {
+ case PCI_CLASS_BRIDGE_PCI:
+ debug("PCI Autoconfig: Found P2P bridge, device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+
+ dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+
+ n = dm_pci_hose_probe_bus(dev);
+ if (n < 0)
+ return n;
+ sub_bus = (unsigned int)n;
+ break;
+
+ case PCI_CLASS_BRIDGE_CARDBUS:
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+
+ debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+
+ break;
+
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+ case PCI_CLASS_BRIDGE_OTHER:
+ debug("PCI Autoconfig: Skipping bridge device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+ break;
+#endif
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+ case PCI_CLASS_BRIDGE_OTHER:
+ /*
+ * The host/PCI bridge 1 seems broken in 8349 - it presents
+ * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+ * device claiming resources io/mem/irq.. we only allow for
+ * the PIMMR window to be allocated (BAR0 - 1MB size)
+ */
+ debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
+ dm_pciauto_setup_device(dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io,
+ enum_only);
+ break;
+#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ debug("PCI AutoConfig: Found PowerPC device\n");
+
+ default:
+ dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+ break;
+ }
+
+ return sub_bus;
+}
/*
- * arch/powerpc/kernel/pci_auto.c
- *
- * PCI autoconfiguration library
+ * PCI autoconfiguration library (legacy version, do not change)
*
* Author: Matt Porter <mporter@mvista.com>
*
#include <errno.h>
#include <pci.h>
+/*
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci_auto.c.
+ */
+
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
bar_res = prefetch;
else
bar_res = mem;
-#endif
debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
bar_nr, bar_res == prefetch ? "Prf" : "Mem",
(unsigned long long)bar_size);
+#endif
}
#ifndef CONFIG_PCI_ENUM_ONLY
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
-#else
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
PCI_BUS(dev) - hose->first_busno);
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
sub_bus - hose->first_busno);
-#endif
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
-#else
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
sub_bus - hose->first_busno);
-#endif
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
unsigned short class;
int n;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
pciauto_setup_device(hose, dev, 2, pci_mem,
pci_prefetch, pci_io);
-#ifdef CONFIG_DM_PCI
- n = dm_pci_hose_probe_bus(hose, dev);
- if (n < 0)
- return n;
- sub_bus = (unsigned int)n;
-#else
/* Passing in current_busno allows for sibling P2P bridges */
hose->current_busno++;
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
-#endif
break;
case PCI_CLASS_BRIDGE_CARDBUS:
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dev));
-#ifndef CONFIG_DM_PCI
hose->current_busno++;
-#endif
break;
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
};
}
-pci_dev_t pci_find_class(uint find_class, int index)
-{
- int bus;
- int devnum;
- pci_dev_t bdf;
- uint32_t class;
-
- for (bus = 0; bus <= pci_last_busno(); bus++) {
- for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
- pci_read_config_dword(PCI_BDF(bus, devnum, 0),
- PCI_CLASS_REVISION, &class);
- if (class >> 16 == 0xffff)
- continue;
-
- for (bdf = PCI_BDF(bus, devnum, 0);
- bdf <= PCI_BDF(bus, devnum,
- PCI_MAX_PCI_FUNCTIONS - 1);
- bdf += PCI_BDF(0, 0, 1)) {
- pci_read_config_dword(bdf, PCI_CLASS_REVISION,
- &class);
- class >>= 8;
-
- if (class != find_class)
- continue;
- /*
- * Decrement the index. We want to return the
- * correct device, so index is 0 for the first
- * matching device, 1 for the second, etc.
- */
- if (index) {
- index--;
- continue;
- }
- /* Return index'th controller. */
- return bdf;
- }
- }
- }
-
- return -ENODEV;
-}
-
__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
return 0;
}
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
/* Get a virtual address associated with a BAR region */
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
return -1;
}
+
+pci_dev_t pci_find_class(uint find_class, int index)
+{
+ int bus;
+ int devnum;
+ pci_dev_t bdf;
+ uint32_t class;
+
+ for (bus = 0; bus <= pci_last_busno(); bus++) {
+ for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
+ pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+ PCI_CLASS_REVISION, &class);
+ if (class >> 16 == 0xffff)
+ continue;
+
+ for (bdf = PCI_BDF(bus, devnum, 0);
+ bdf <= PCI_BDF(bus, devnum,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ bdf += PCI_BDF(0, 0, 1)) {
+ pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+ &class);
+ class >>= 8;
+
+ if (class != find_class)
+ continue;
+ /*
+ * Decrement the index. We want to return the
+ * correct device, so index is 0 for the first
+ * matching device, 1 for the second, etc.
+ */
+ if (index) {
+ index--;
+ continue;
+ }
+ /* Return index'th controller. */
+ return bdf;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
if (pci_find_device_id(ids, index, &dev))
return -1;
- return pci_get_bdf(dev);
+ return dm_pci_get_bdf(dev);
}
--- /dev/null
+/*
+ * Internal PCI functions, not exported outside drivers/pci
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __pci_internal_h
+#define __pci_internal_h
+
+/**
+ * dm_pciauto_prescan_setup_bridge() - Set up a bridge for scanning
+ *
+ * This gets a bridge ready so that its downstream devices can be scanned.
+ * It sets up the bus number and memory range registers. Once the scan is
+ * completed, dm_pciauto_postscan_setup_bridge() should be called.
+ *
+ * @dev: Bridge device to be scanned
+ * @sub_bus: Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_postscan_setup_bridge() - Finish set up of a bridge after scanning
+ *
+ * This should be called after a bus scan is complete. It adjusts the memory
+ * ranges to fit with the devices actually found on the other side (downstream)
+ * of the bridge.
+ *
+ * @dev: Bridge device that was scanned
+ * @sub_bus: Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_config_device() - Configure a PCI device ready for use
+ *
+ * If the device is a bridge, downstream devices will be probed.
+ *
+ * @dev: Device to configure
+ * @return the maximum PCI bus number found by this device. If there are no
+ * bridges, this just returns the device's bus number. If the device is a
+ * bridge then it will return a larger number, depending on the devices on
+ * that bridge. On error, returns a -ve error number.
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+#endif
}
#endif
+static int mvebu_pex_unit_is_x4(int pex_idx)
+{
+ int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
+ u32 mask = (0x0f << (pex_unit * 8));
+
+ return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
+}
+
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
{
u32 val;
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
bus = hose->last_busno + 1;
+
+ /* need to skip more for X4 links, otherwise scan will hang */
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ if (mvebu_pex_unit_is_x4(i))
+ i += 3;
+ }
}
}
#include <common.h>
#include <bios_emul.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <pci.h>
#include <video_fb.h>
#include <linux/screen_info.h>
-__weak bool board_should_run_oprom(pci_dev_t dev)
+__weak bool board_should_run_oprom(struct udevice *dev)
{
return true;
}
-static bool should_load_oprom(pci_dev_t dev)
+static bool should_load_oprom(struct udevice *dev)
{
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
return 1;
return vendev;
}
-static int pci_rom_probe(pci_dev_t dev, uint class,
- struct pci_rom_header **hdrp)
+static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
{
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct pci_rom_header *rom_header;
struct pci_rom_data *rom_data;
- u16 vendor, device;
u16 rom_vendor, rom_device;
u32 rom_class;
u32 vendev;
u32 mapped_vendev;
u32 rom_address;
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(dev, PCI_DEVICE_ID, &device);
- vendev = vendor << 16 | device;
+ vendev = pplat->vendor << 16 | pplat->device;
mapped_vendev = board_map_oprom_vendev(vendev);
if (vendev != mapped_vendev)
debug("Device ID mapped to %#08x\n", mapped_vendev);
rom_address = CONFIG_VGA_BIOS_ADDR;
#else
- pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+ dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
debug("%s: rom_address=%x\n", __func__, rom_address);
return -ENOENT;
}
/* Enable expansion ROM address decoding. */
- pci_write_config_dword(dev, PCI_ROM_ADDRESS,
- rom_address | PCI_ROM_ADDRESS_ENABLE);
+ dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
+ rom_address | PCI_ROM_ADDRESS_ENABLE);
#endif
debug("Option ROM address %x\n", rom_address);
rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
le16_to_cpu(rom_header->signature));
#ifndef CONFIG_VGA_BIOS_ADDR
/* Disable expansion ROM address decoding */
- pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address);
+ dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
#endif
return -EINVAL;
}
rom_vendor, rom_device);
/* If the device id is mapped, a mismatch is expected */
- if ((vendor != rom_vendor || device != rom_device) &&
+ if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
(vendev == mapped_vendev)) {
printf("ID mismatch: vendor ID %04x, device ID %04x\n",
rom_vendor, rom_device);
debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
rom_class, rom_data->type);
- if (class != rom_class) {
+ if (pplat->class != rom_class) {
debug("Class Code mismatch ROM %06x, dev %06x\n",
- rom_class, class);
+ rom_class, pplat->class);
}
*hdrp = rom_header;
screen_info->rsvd_pos = vesa->reserved_mask_pos;
}
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+ int exec_method)
{
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct pci_rom_header *rom, *ram;
int vesa_mode = -1;
- uint class;
bool emulate;
int ret;
/* Only execute VGA ROMs */
- pci_read_config_dword(dev, PCI_REVISION_ID, &class);
- if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
- debug("%s: Class %#x, should be %#x\n", __func__, class,
+ if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
PCI_CLASS_DISPLAY_VGA);
return -ENODEV;
}
- class >>= 8;
if (!should_load_oprom(dev))
return -ENXIO;
- ret = pci_rom_probe(dev, class, &rom);
+ ret = pci_rom_probe(dev, &rom);
if (ret)
return ret;
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
- ret = biosemu_setup(dev, &info);
+ ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
if (ret)
return ret;
biosemu_set_interrupt_handler(0x15, int15_handler);
- ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
- vesa_mode, &mode_info);
+ ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
+ info, true, vesa_mode, &mode_info);
if (ret)
return ret;
#endif
during serial port initialization (default y). Set this to n on
boards which have no debug serial port whatsoever.
+config SERIAL_PRESENT
+ bool "Provide a serial driver"
+ depends on DM_SERIAL
+ default y
+ help
+ In very space-constrained devices even the full UART driver is too
+ large. In this case the debug UART can still be used in some cases.
+ This option enables the full UART in U-Boot, so if is it disabled,
+ the full UART driver will be omitted, thus saving space.
+
+config SPL_SERIAL_PRESENT
+ bool "Provide a serial driver in SPL"
+ depends on DM_SERIAL
+ default y
+ help
+ In very space-constrained devices even the full UART driver is too
+ large. In this case the debug UART can still be used in some cases.
+ This option enables the full UART in SPL, so if is it disabled,
+ the full UART driver will be omitted, thus saving space.
+
config DM_SERIAL
bool "Enable Driver Model for serial drivers"
depends on DM
/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
+#include <dm.h>
#include <serial.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
+#include <asm/arch/uart.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
+struct lpc32xx_hsuart_priv {
+ struct hsuart_regs *hsuart;
+};
-static void lpc32xx_serial_setbrg(void)
+static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
{
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
u32 div;
/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
- div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
+ div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
if (div > 255)
div = 255;
writel(div, &hsuart->rate);
+
+ return 0;
}
-static int lpc32xx_serial_getc(void)
+static int lpc32xx_serial_getc(struct udevice *dev)
{
- while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
- /* NOP */;
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
+ return -EAGAIN;
return readl(&hsuart->rx) & HSUART_RX_DATA;
}
-static void lpc32xx_serial_putc(const char c)
+static int lpc32xx_serial_putc(struct udevice *dev, const char c)
{
- if (c == '\n')
- serial_putc('\r');
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ /* Wait for empty FIFO */
+ if (readl(&hsuart->level) & HSUART_LEVEL_TX)
+ return -EAGAIN;
writel(c, &hsuart->tx);
- /* Wait for character to be sent */
- while (readl(&hsuart->level) & HSUART_LEVEL_TX)
- /* NOP */;
+ return 0;
}
-static int lpc32xx_serial_tstc(void)
+static int lpc32xx_serial_pending(struct udevice *dev, bool input)
{
- if (readl(&hsuart->level) & HSUART_LEVEL_RX)
- return 1;
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ if (input) {
+ if (readl(&hsuart->level) & HSUART_LEVEL_RX)
+ return 1;
+ } else {
+ if (readl(&hsuart->level) & HSUART_LEVEL_TX)
+ return 1;
+ }
return 0;
}
-static int lpc32xx_serial_init(void)
+static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
{
- lpc32xx_serial_setbrg();
-
/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
&hsuart->ctrl);
+
return 0;
}
-static struct serial_device lpc32xx_serial_drv = {
- .name = "lpc32xx_serial",
- .start = lpc32xx_serial_init,
- .stop = NULL,
+static int lpc32xx_hsuart_probe(struct udevice *dev)
+{
+ struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+
+ priv->hsuart = (struct hsuart_regs *)platdata->base;
+
+ lpc32xx_serial_init(priv->hsuart);
+
+ return 0;
+}
+
+static const struct dm_serial_ops lpc32xx_hsuart_ops = {
.setbrg = lpc32xx_serial_setbrg,
- .putc = lpc32xx_serial_putc,
- .puts = default_serial_puts,
.getc = lpc32xx_serial_getc,
- .tstc = lpc32xx_serial_tstc,
+ .putc = lpc32xx_serial_putc,
+ .pending = lpc32xx_serial_pending,
};
-void lpc32xx_serial_initialize(void)
-{
- serial_register(&lpc32xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &lpc32xx_serial_drv;
-}
+U_BOOT_DRIVER(lpc32xx_hsuart) = {
+ .name = "lpc32xx_hsuart",
+ .id = UCLASS_SERIAL,
+ .probe = lpc32xx_hsuart_probe,
+ .ops = &lpc32xx_hsuart_ops,
+ .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
/* try Processor Local Bus device first */
addr = dev_get_addr(dev);
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
return ret;
}
- ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset,
- &pci_addr, &bar);
+ ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
};
#endif
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
U_BOOT_DRIVER(ns16550_serial) = {
.name = "ns16550_serial",
.id = UCLASS_SERIAL,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+#endif
#endif /* CONFIG_DM_SERIAL */
{
}
-#ifdef CONFIG_DM_STDIO
+#if defined(CONFIG_DM_STDIO) && CONFIG_IS_ENABLED(SERIAL_PRESENT)
static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
_serial_putc(sdev->priv, ch);
}
U_BOOT_ENV_CALLBACK(baudrate, on_baudrate);
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_post_probe(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
.pre_remove = serial_pre_remove,
.per_device_auto_alloc_size = sizeof(struct serial_dev_priv),
};
+#endif
* and byte program command for SST flash
*/
if (plat->ich_version == 7) {
- slave->op_mode_rx = SPI_OPM_RX_AS;
- slave->op_mode_tx = SPI_OPM_TX_BP;
+ slave->mode_rx = SPI_RX_SLOW;
+ slave->mode = SPI_TX_BYTE;
}
return 0;
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#endif
#include <asm/arch-mvebu/spi.h>
+static void _spi_cs_activate(struct kwspi_registers *reg)
+{
+ setbits_le32(®->ctrl, KWSPI_CSN_ACT);
+}
+
+static void _spi_cs_deactivate(struct kwspi_registers *reg)
+{
+ clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
+}
+
+static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ unsigned int tmpdout, tmpdin;
+ int tm, isread = 0;
+
+ debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
+
+ if (flags & SPI_XFER_BEGIN)
+ _spi_cs_activate(reg);
+
+ /*
+ * handle data in 8-bit chunks
+ * TBD: 2byte xfer mode to be enabled
+ */
+ clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
+
+ while (bitlen > 4) {
+ debug("loopstart bitlen %d\n", bitlen);
+ tmpdout = 0;
+
+ /* Shift data so it's msb-justified */
+ if (dout)
+ tmpdout = *(u32 *)dout & 0xff;
+
+ clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
+ writel(tmpdout, ®->dout); /* Write the data out */
+ debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+ tmpdout, bitlen);
+
+ /*
+ * Wait for SPI transmit to get out
+ * or time out (1 second = 1000 ms)
+ * The NE event must be read and cleared first
+ */
+ for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
+ if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
+ isread = 1;
+ tmpdin = readl(®->din);
+ debug("spi_xfer: din %p..%08x read\n",
+ din, tmpdin);
+
+ if (din) {
+ *((u8 *)din) = (u8)tmpdin;
+ din += 1;
+ }
+ if (dout)
+ dout += 1;
+ bitlen -= 8;
+ }
+ if (isread)
+ break;
+ }
+ if (tm >= KWSPI_TIMEOUT)
+ printf("*** spi_xfer: Time out during SPI transfer\n");
+
+ debug("loopend bitlen %d\n", bitlen);
+ }
+
+ if (flags & SPI_XFER_END)
+ _spi_cs_deactivate(reg);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+
static struct kwspi_registers *spireg =
(struct kwspi_registers *)MVEBU_SPI_BASE;
void spi_cs_activate(struct spi_slave *slave)
{
- setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
+ _spi_cs_activate(spireg);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
+ _spi_cs_deactivate(spireg);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- unsigned int tmpdout, tmpdin;
- int tm, isread = 0;
+ return _spi_xfer(spireg, bitlen, dout, din, flags);
+}
- debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
- slave->bus, slave->cs, dout, din, bitlen);
+#else
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+/* Here now the DM part */
- /*
- * handle data in 8-bit chunks
- * TBD: 2byte xfer mode to be enabled
- */
- clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
+struct mvebu_spi_platdata {
+ struct kwspi_registers *spireg;
+};
- while (bitlen > 4) {
- debug("loopstart bitlen %d\n", bitlen);
- tmpdout = 0;
+struct mvebu_spi_priv {
+ struct kwspi_registers *spireg;
+};
- /* Shift data so it's msb-justified */
- if (dout)
- tmpdout = *(u32 *)dout & 0xff;
+static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data;
- clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ);
- writel(tmpdout, &spireg->dout); /* Write the data out */
- debug("*** spi_xfer: ... %08x written, bitlen %d\n",
- tmpdout, bitlen);
+ /* calculate spi clock prescaller using max_hz */
+ data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
+ data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
+ data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
- /*
- * Wait for SPI transmit to get out
- * or time out (1 second = 1000 ms)
- * The NE event must be read and cleared first
- */
- for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
- if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
- isread = 1;
- tmpdin = readl(&spireg->din);
- debug("spi_xfer: din %p..%08x read\n",
- din, tmpdin);
+ /* program spi clock prescaler using max_hz */
+ writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
+ debug("data = 0x%08x\n", data);
- if (din) {
- *((u8 *)din) = (u8)tmpdin;
- din += 1;
- }
- if (dout)
- dout += 1;
- bitlen -= 8;
- }
- if (isread)
- break;
- }
- if (tm >= KWSPI_TIMEOUT)
- printf("*** spi_xfer: Time out during SPI transfer\n");
+ return 0;
+}
- debug("loopend bitlen %d\n", bitlen);
- }
+static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
+}
+
+static int mvebu_spi_probe(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+
+ writel(KWSPI_SMEMRDY, ®->ctrl);
+ writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
+ writel(KWSPI_IRQMASK, ®->irq_mask);
+
+ return 0;
+}
+
+static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
return 0;
}
+
+static const struct dm_spi_ops mvebu_spi_ops = {
+ .xfer = mvebu_spi_xfer,
+ .set_speed = mvebu_spi_set_speed,
+ .set_mode = mvebu_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mvebu_spi_ids[] = {
+ { .compatible = "marvell,armada-380-spi" },
+ { .compatible = "marvell,armada-xp-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mvebu_spi) = {
+ .name = "mvebu_spi",
+ .id = UCLASS_SPI,
+ .of_match = mvebu_spi_ids,
+ .ops = &mvebu_spi_ops,
+ .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
+ .probe = mvebu_spi_probe,
+};
+#endif
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
+ slave->mode_rx = plat->mode_rx;
return 0;
}
int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat)
{
- int mode = 0;
+ int mode = 0, mode_rx = 0;
+ int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
mode |= SPI_3WIRE;
if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
+
+ /* Device DUAL/QUAD mode */
+ value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_TX_QUAD;
+ break;
+ default:
+ error("spi-tx-bus-width %d not supported\n", value);
+ break;
+ }
+
plat->mode = mode;
+ value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode_rx |= SPI_RX_DUAL;
+ break;
+ case 4:
+ mode_rx |= SPI_RX_QUAD;
+ break;
+ default:
+ error("spi-rx-bus-width %d not supported\n", value);
+ break;
+ }
+
+ plat->mode_rx = mode_rx;
+
return 0;
}
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE QSPI_WC
#define MM_SWITCH 0x01
-#define MEM_CS 0x100
+#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff0ff
#define MMAP_START_ADDR_DRA 0x5c000000
#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
+#define QSPI_CMD_READ_DUAL (0x6b << 0)
#define QSPI_CMD_READ_QUAD (0x6b << 0)
#define QSPI_CMD_READ_FAST (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
+#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
#define QSPI_CMD_WRITE (0x2 << 16)
#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
u32 data3;
};
-/* ti qspi slave */
-struct ti_qspi_slave {
+/* ti qspi priv */
+struct ti_qspi_priv {
+#ifndef CONFIG_DM_SPI
struct spi_slave slave;
+#else
+ void *memory_map;
+ uint max_hz;
+ u32 num_cs;
+#endif
struct ti_qspi_regs *base;
+ void *ctrl_mod_mmap;
unsigned int mode;
u32 cmd;
u32 dc;
};
-static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct ti_qspi_slave, slave);
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
- struct spi_slave *slave = &qslave->slave;
- u32 memval = 0;
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- slave->memory_map = (void *)MMAP_START_ADDR_DRA;
-#else
- slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
-#endif
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
- memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_8_BITS |
- QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS);
- slave->op_mode_rx = SPI_OPM_RX_QOF;
-#else
- memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
- QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS;
-#endif
-
- writel(memval, &qslave->base->setup0);
-}
-
-static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint clk_div;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
clk_div = (QSPI_FCLK / hz) - 1;
/* disable SCLK */
- writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
- &qslave->base->clk_ctrl);
+ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
+ &priv->base->clk_ctrl);
/* assign clk_div values */
if (clk_div < 0)
clk_div = QSPI_CLK_DIV_MAX;
/* enable SCLK */
- writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
+ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}
-void spi_cs_activate(struct spi_slave *slave)
+static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
- /* CS handled in xfer */
- return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
-
- writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+ writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
/* dummy readl to ensure bus sync */
- readl(&qslave->base->cmd);
+ readl(&priv->base->cmd);
}
-void spi_init(void)
+static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
- /* nothing to do */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ti_qspi_slave *qslave;
-
-#ifdef CONFIG_AM43XX
- gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
- gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
- qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
- if (!qslave) {
- printf("SPI_error: Fail to allocate ti_qspi_slave\n");
- return NULL;
- }
-
- qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
- qslave->mode = mode;
-
- ti_spi_set_speed(&qslave->slave, max_hz);
+ priv->dc = 0;
+ if (mode & SPI_CPHA)
+ priv->dc |= QSPI_CKPHA(0);
+ if (mode & SPI_CPOL)
+ priv->dc |= QSPI_CKPOL(0);
+ if (mode & SPI_CS_HIGH)
+ priv->dc |= QSPI_CSPOL(0);
-#ifdef CONFIG_TI_SPI_MMAP
- ti_spi_setup_spi_register(qslave);
-#endif
-
- return &qslave->slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
- free(qslave);
-}
+ writel(priv->dc, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
-
- qslave->dc = 0;
- if (qslave->mode & SPI_CPHA)
- qslave->dc |= QSPI_CKPHA(slave->cs);
- if (qslave->mode & SPI_CPOL)
- qslave->dc |= QSPI_CKPOL(slave->cs);
- if (qslave->mode & SPI_CS_HIGH)
- qslave->dc |= QSPI_CSPOL(slave->cs);
-
- writel(qslave->dc, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ priv->dc <<= cs * 8;
+ writel(priv->dc, &priv->base->dc);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ writel(0, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
+}
- debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
+static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
+{
+ u32 val;
- writel(0, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ val = readl(ctrl_mod_mmap);
+ if (enable)
+ val |= MEM_CS(cs);
+ else
+ val &= MEM_CS_UNSELECT;
+ writel(val, ctrl_mod_mmap);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags,
+ u32 cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout;
uchar *rxp = din;
uint status;
int timeout;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- int val;
-#endif
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
- slave->bus, slave->cs, bitlen, words, flags);
-
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val |= MEM_CS;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val &= MEM_CS_UNSELECT;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(~MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
return 0;
}
}
/* Setup command reg */
- qslave->cmd = 0;
- qslave->cmd |= QSPI_WLEN(8);
- qslave->cmd |= QSPI_EN_CS(slave->cs);
- if (qslave->mode & SPI_3WIRE)
- qslave->cmd |= QSPI_3_PIN;
- qslave->cmd |= 0xfff;
+ priv->cmd = 0;
+ priv->cmd |= QSPI_WLEN(8);
+ priv->cmd |= QSPI_EN_CS(cs);
+ if (priv->mode & SPI_3WIRE)
+ priv->cmd |= QSPI_3_PIN;
+ priv->cmd |= 0xfff;
/* FIXME: This delay is required for successfull
* completion of read/write/erase. Once its root
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
- qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
- writel(*txp++, &qslave->base->data);
- writel(qslave->cmd | QSPI_WR_SNGL,
- &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
+ writel(*txp++, &priv->base->data);
+ writel(priv->cmd | QSPI_WR_SNGL,
+ &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: TX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
debug("tx done, status %08x\n", status);
}
if (rxp) {
- qslave->cmd |= QSPI_RD_SNGL;
+ priv->cmd |= QSPI_RD_SNGL;
debug("rx cmd %08x dc %08x\n",
- qslave->cmd, qslave->dc);
+ priv->cmd, priv->dc);
#ifdef CONFIG_DRA7XX
udelay(500);
#endif
- writel(qslave->cmd, &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ writel(priv->cmd, &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: RX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
- *rxp++ = readl(&qslave->base->data);
+ *rxp++ = readl(&priv->base->data);
debug("rx done, status %08x, read %02x\n",
status, *(rxp-1));
}
/* Terminate frame */
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ ti_qspi_cs_deactivate(priv);
return 0;
}
*((unsigned int *)offset) += len;
}
#endif
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_priv, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ ti_qspi_cs_deactivate(priv);
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
+{
+ u32 memval = 0;
+
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+ struct spi_slave *slave = &priv->slave;
+ memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+ QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS);
+ slave->mode_rx = SPI_RX_QUAD;
+#else
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+ QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS;
+#endif
+
+ writel(memval, &priv->base->setup0);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct ti_qspi_priv *priv;
+
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
+ priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
+ if (!priv) {
+ printf("SPI_error: Fail to allocate ti_qspi_priv\n");
+ return NULL;
+ }
+
+ priv->base = (struct ti_qspi_regs *)QSPI_BASE;
+ priv->mode = mode;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
+
+ ti_spi_set_speed(priv, max_hz);
+
+#ifdef CONFIG_TI_SPI_MMAP
+ ti_spi_setup_spi_register(priv);
+#endif
+
+ return &priv->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_set_mode(priv, priv->mode);
+ return __ti_qspi_claim_bus(priv, priv->slave.cs);
+}
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_release_bus(priv);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
+ priv->slave.bus, priv->slave.cs, bitlen, flags);
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+}
+
+#else /* CONFIG_DM_SPI */
+
+static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
+ struct spi_slave *slave,
+ bool enable)
+{
+ u32 memval;
+ u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
+
+ if (!enable) {
+ writel(0, &priv->base->setup0);
+ return;
+ }
+
+ memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+
+ switch (mode) {
+ case SPI_RX_QUAD:
+ memval |= QSPI_CMD_READ_QUAD;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_QUAD;
+ slave->mode_rx = SPI_RX_QUAD;
+ break;
+ case SPI_RX_DUAL:
+ memval |= QSPI_CMD_READ_DUAL;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_DUAL;
+ break;
+ default:
+ memval |= QSPI_CMD_READ;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
+ memval |= QSPI_SETUP0_READ_NORMAL;
+ break;
+ }
+
+ writel(memval, &priv->base->setup0);
+}
+
+
+static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ ti_spi_set_speed(priv, max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ return __ti_qspi_set_mode(priv, mode);
+}
+
+static int ti_qspi_claim_bus(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave_plat->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ __ti_qspi_setup_memorymap(priv, slave, true);
+
+ return __ti_qspi_claim_bus(priv, slave_plat->cs);
+}
+
+static int ti_qspi_release_bus(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ __ti_qspi_setup_memorymap(priv, slave, false);
+ __ti_qspi_release_bus(priv);
+
+ return 0;
+}
+
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+}
+
+static int ti_qspi_probe(struct udevice *bus)
+{
+ /* Nothing to do in probe */
+ return 0;
+}
+
+static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+ fdt_addr_t addr;
+
+ priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
+ priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+ addr = dev_get_addr_index(bus, 2);
+ priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+
+ priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
+ if (priv->max_hz < 0) {
+ debug("Error: Max frequency missing\n");
+ return -ENODEV;
+ }
+ priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
+ debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
+ (int)priv->base, priv->max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_child_pre_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ slave->memory_map = priv->memory_map;
+ return 0;
+}
+
+static const struct dm_spi_ops ti_qspi_ops = {
+ .claim_bus = ti_qspi_claim_bus,
+ .release_bus = ti_qspi_release_bus,
+ .xfer = ti_qspi_xfer,
+ .set_speed = ti_qspi_set_speed,
+ .set_mode = ti_qspi_set_mode,
+};
+
+static const struct udevice_id ti_qspi_ids[] = {
+ { .compatible = "ti,dra7xxx-qspi" },
+ { .compatible = "ti,am4372-qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(ti_qspi) = {
+ .name = "ti_qspi",
+ .id = UCLASS_SPI,
+ .of_match = ti_qspi_ids,
+ .ops = &ti_qspi_ops,
+ .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
+ .probe = ti_qspi_probe,
+ .child_pre_probe = ti_qspi_child_pre_probe,
+};
+#endif /* CONFIG_DM_SPI */
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <linux/mii.h>
#include <malloc.h>
* @mchash: shadow for the network adapter's multicast hash registers
*/
struct mcs7830_private {
+#ifdef CONFIG_DM_ETH
+ uint8_t rx_buf[MCS7830_RX_URB_SIZE];
+ struct ueth_data ueth;
+#endif
uint8_t config;
uint8_t mchash[8];
};
/*
* mcs7830_read_reg() - read a register of the network adapter
- * @dev: network device to read from
+ * @udev: network device to read from
* @idx: index of the register to start reading from
* @size: number of bytes to read
* @data: buffer to read into
* Return: zero upon success, negative upon error
*/
-static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx,
+static int mcs7830_read_reg(struct usb_device *udev, uint8_t idx,
uint16_t size, void *data)
{
int len;
debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
- len = usb_control_msg(dev->pusb_dev,
- usb_rcvctrlpipe(dev->pusb_dev, 0),
+ len = usb_control_msg(udev,
+ usb_rcvctrlpipe(udev, 0),
MCS7830_RD_BREQ,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, idx, buf, size,
/*
* mcs7830_write_reg() - write a register of the network adapter
- * @dev: network device to write to
+ * @udev: network device to write to
* @idx: index of the register to start writing to
* @size: number of bytes to write
* @data: buffer holding the data to write
* Return: zero upon success, negative upon error
*/
-static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx,
+static int mcs7830_write_reg(struct usb_device *udev, uint8_t idx,
uint16_t size, void *data)
{
int len;
debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
memcpy(buf, data, size);
- len = usb_control_msg(dev->pusb_dev,
- usb_sndctrlpipe(dev->pusb_dev, 0),
+ len = usb_control_msg(udev,
+ usb_sndctrlpipe(udev, 0),
MCS7830_WR_BREQ,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, idx, buf, size,
/*
* mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution
- * @dev: network device to talk to
+ * @udev: network device to talk to
* @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode
* @index: number of the PHY register to read or write
* Return: zero upon success, negative upon error
*/
-static int mcs7830_phy_emit_wait(struct ueth_data *dev,
+static int mcs7830_phy_emit_wait(struct usb_device *udev,
uint8_t rwflag, uint8_t index)
{
int rc;
/* send the PHY read/write request */
cmd[0] = rwflag | PHY_CMD1_PHYADDR;
cmd[1] = PHY_CMD2_PEND | (index & 0x1f);
- rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ rc = mcs7830_write_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd);
if (rc < 0)
return rc;
/* wait for the response to become available (usually < 1ms) */
retry = 10;
do {
- rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ rc = mcs7830_read_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd);
if (rc < 0)
return rc;
if (cmd[1] & PHY_CMD2_READY)
/*
* mcs7830_read_phy() - read a PHY register of the network adapter
- * @dev: network device to read from
+ * @udev: network device to read from
* @index: index of the PHY register to read from
* Return: non-negative 16bit register content, negative upon error
*/
-static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index)
+static int mcs7830_read_phy(struct usb_device *udev, uint8_t index)
{
int rc;
uint16_t val;
/* issue the PHY read request and wait for its execution */
- rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index);
+ rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_READ, index);
if (rc < 0)
return rc;
/* fetch the PHY data which was read */
- rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ rc = mcs7830_read_reg(udev, REG_PHY_DATA, sizeof(val), &val);
if (rc < 0)
return rc;
rc = le16_to_cpu(val);
- debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc);
+ debug("%s(%d) => 0x%04X\n", __func__, index, rc);
return rc;
}
/*
* mcs7830_write_phy() - write a PHY register of the network adapter
- * @dev: network device to write to
+ * @udev: network device to write to
* @index: index of the PHY register to write to
* @val: value to write to the PHY register
* Return: zero upon success, negative upon error
*/
-static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val)
+static int mcs7830_write_phy(struct usb_device *udev, uint8_t index,
+ uint16_t val)
{
int rc;
- debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val);
+ debug("%s(%d, 0x%04X)\n", __func__, index, val);
/* setup the PHY data which is to get written */
val = cpu_to_le16(val);
- rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ rc = mcs7830_write_reg(udev, REG_PHY_DATA, sizeof(val), &val);
if (rc < 0)
return rc;
/* issue the PHY write request and wait for its execution */
- rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index);
+ rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_WRITE, index);
if (rc < 0)
return rc;
/*
* mcs7830_write_config() - write to the network adapter's config register
- * @eth: network device to write to
+ * @udev: network device to write to
+ * @priv: private data
* Return: zero upon success, negative upon error
*
* the data which gets written is taken from the shadow config register
* within the device driver's private data
*/
-static int mcs7830_write_config(struct ueth_data *dev)
+static int mcs7830_write_config(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
- rc = mcs7830_write_reg(dev, REG_CONFIG,
+ rc = mcs7830_write_reg(udev, REG_CONFIG,
sizeof(priv->config), &priv->config);
if (rc < 0) {
debug("writing config to adapter failed\n");
/*
* mcs7830_write_mchash() - write the network adapter's multicast filter
- * @eth: network device to write to
+ * @udev: network device to write to
+ * @priv: private data
* Return: zero upon success, negative upon error
*
* the data which gets written is taken from the shadow multicast hashes
* within the device driver's private data
*/
-static int mcs7830_write_mchash(struct ueth_data *dev)
+static int mcs7830_write_mchash(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
- rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH,
+ rc = mcs7830_write_reg(udev, REG_MULTICAST_HASH,
sizeof(priv->mchash), &priv->mchash);
if (rc < 0) {
debug("writing multicast hash to adapter failed\n");
/*
* mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation
- * @eth: network device to run link negotiation on
+ * @udev: network device to run link negotiation on
* Return: zero upon success, negative upon error
*
* the routine advertises available media and starts autonegotiation
*/
-static int mcs7830_set_autoneg(struct ueth_data *dev)
+static int mcs7830_set_autoneg(struct usb_device *udev)
{
int adv, flg;
int rc;
*/
adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA;
- rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv);
+ rc = mcs7830_write_phy(udev, MII_ADVERTISE, adv);
flg = 0;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
flg |= BMCR_ANENABLE;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
flg |= BMCR_ANRESTART;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
return rc;
}
/*
* mcs7830_get_rev() - identify a network adapter's chip revision
- * @eth: network device to identify
+ * @udev: network device to identify
* Return: non-negative number, reflecting the revision number
*
* currently, only "rev C and higher" and "below rev C" are needed, so
* the return value is #1 for "below rev C", and #2 for "rev C and above"
*/
-static int mcs7830_get_rev(struct ueth_data *dev)
+static int mcs7830_get_rev(struct usb_device *udev)
{
uint8_t buf[2];
int rc;
int rev;
/* register 22 is readable in rev C and higher */
- rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
+ rc = mcs7830_read_reg(udev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
if (rc < 0)
rev = 1;
else
/*
* mcs7830_apply_fixup() - identify an adapter and potentially apply fixups
- * @eth: network device to identify and apply fixups to
+ * @udev: network device to identify and apply fixups to
* Return: zero upon success (no errors emitted from here)
*
* this routine identifies the network adapter's chip revision, and applies
* fixups for known issues
*/
-static int mcs7830_apply_fixup(struct ueth_data *dev)
+static int mcs7830_apply_fixup(struct usb_device *udev)
{
int rev;
int i;
uint8_t thr;
- rev = mcs7830_get_rev(dev);
+ rev = mcs7830_get_rev(udev);
debug("%s() rev=%d\n", __func__, rev);
/*
* exactly", the introductory comment says "rev C and above")
*/
if (rev == 2) {
- debug("%s: applying rev C fixup\n", dev->eth_dev.name);
+ debug("%s: applying rev C fixup\n", __func__);
thr = PAUSE_THRESHOLD_DEFAULT;
for (i = 0; i < 2; i++) {
- (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD,
+ (void)mcs7830_write_reg(udev, REG_PAUSE_THRESHOLD,
sizeof(thr), &thr);
mdelay(1);
}
* of the interface callbacks can exchange ethernet frames; link negotiation is
* triggered from here already and continues in background
*/
-static int mcs7830_basic_reset(struct ueth_data *dev)
+static int mcs7830_basic_reset(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
/*
* comment from the respective Linux driver, which
priv->config = CONF_TXENABLE;
priv->config |= CONF_ALLMULTICAST;
- rc = mcs7830_set_autoneg(dev);
+ rc = mcs7830_set_autoneg(udev);
if (rc < 0) {
error("setting autoneg failed\n");
return rc;
}
- rc = mcs7830_write_mchash(dev);
+ rc = mcs7830_write_mchash(udev, priv);
if (rc < 0) {
error("failed to set multicast hash\n");
return rc;
}
- rc = mcs7830_write_config(dev);
+ rc = mcs7830_write_config(udev, priv);
if (rc < 0) {
error("failed to set configuration\n");
return rc;
}
- rc = mcs7830_apply_fixup(dev);
+ rc = mcs7830_apply_fixup(udev);
if (rc < 0) {
error("fixup application failed\n");
return rc;
/*
* mcs7830_read_mac() - read an ethernet adapter's MAC address
- * @eth: network device to read from
+ * @udev: network device to read from
+ * @enetaddr: place to put ethernet MAC address
* Return: zero upon success, negative upon error
*
* this routine fetches the MAC address stored within the ethernet adapter,
* and stores it in the ethernet interface's data structure
*/
-static int mcs7830_read_mac(struct eth_device *eth)
+static int mcs7830_read_mac(struct usb_device *udev, unsigned char enetaddr[])
{
- struct ueth_data *dev;
int rc;
uint8_t buf[ETH_ALEN];
debug("%s()\n", __func__);
- dev = eth->priv;
- rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf);
+ rc = mcs7830_read_reg(udev, REG_ETHER_ADDR, ETH_ALEN, buf);
if (rc < 0) {
debug("reading MAC from adapter failed\n");
return rc;
}
- memcpy(ð->enetaddr[0], buf, ETH_ALEN);
+ memcpy(enetaddr, buf, ETH_ALEN);
return 0;
}
-/*
- * mcs7830_write_mac() - write an ethernet adapter's MAC address
- * @eth: network device to write to
- * Return: zero upon success, negative upon error
- *
- * this routine takes the MAC address from the ethernet interface's data
- * structure, and writes it into the ethernet adapter such that subsequent
- * exchange of ethernet frames uses this address
- */
-static int mcs7830_write_mac(struct eth_device *eth)
+static int mcs7830_write_mac_common(struct usb_device *udev,
+ unsigned char enetaddr[])
{
- struct ueth_data *dev;
int rc;
debug("%s()\n", __func__);
- dev = eth->priv;
- if (sizeof(eth->enetaddr) != ETH_ALEN)
- return -EINVAL;
- rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr);
+ rc = mcs7830_write_reg(udev, REG_ETHER_ADDR, ETH_ALEN, enetaddr);
if (rc < 0) {
debug("writing MAC to adapter failed\n");
return rc;
return 0;
}
-/*
- * mcs7830_init() - network interface's init callback
- * @eth: network device to initialize
- * @bd: board information
- * Return: zero upon success, negative upon error
- *
- * after initial setup during probe() and get_info(), this init() callback
- * ensures that the link is up and subsequent send() and recv() calls can
- * exchange ethernet frames
- */
-static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+static int mcs7830_init_common(struct usb_device *udev)
{
- struct ueth_data *dev;
int timeout;
int have_link;
debug("%s()\n", __func__);
- dev = eth->priv;
timeout = 0;
do {
- have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS;
+ have_link = mcs7830_read_phy(udev, MII_BMSR) & BMSR_LSTATUS;
if (have_link)
break;
udelay(LINKSTATUS_TIMEOUT_RES * 1000);
return 0;
}
-/*
- * mcs7830_send() - network interface's send callback
- * @eth: network device to send the frame from
- * @packet: ethernet frame content
- * @length: ethernet frame length
- * Return: zero upon success, negative upon error
- *
- * this routine send an ethernet frame out of the network interface
- */
-static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+static int mcs7830_send_common(struct ueth_data *ueth, void *packet,
+ int length)
{
- struct ueth_data *dev;
+ struct usb_device *udev = ueth->pusb_dev;
int rc;
int gotlen;
/* there is a status byte after the ethernet frame */
ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t));
- dev = eth->priv;
-
memcpy(buf, packet, length);
- rc = usb_bulk_msg(dev->pusb_dev,
- usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ rc = usb_bulk_msg(udev,
+ usb_sndbulkpipe(udev, ueth->ep_out),
&buf[0], length, &gotlen,
USBCALL_TIMEOUT);
debug("%s() TX want len %d, got len %d, rc %d\n",
return rc;
}
-/*
- * mcs7830_recv() - network interface's recv callback
- * @eth: network device to receive frames from
- * Return: zero upon success, negative upon error
- *
- * this routine checks for available ethernet frames that the network
- * interface might have received, and notifies the network stack
- */
-static int mcs7830_recv(struct eth_device *eth)
+static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf)
{
- struct ueth_data *dev;
- ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
int rc, wantlen, gotlen;
uint8_t sts;
debug("%s()\n", __func__);
- dev = eth->priv;
/* fetch input data from the adapter */
wantlen = MCS7830_RX_URB_SIZE;
- rc = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ rc = usb_bulk_msg(ueth->pusb_dev,
+ usb_rcvbulkpipe(ueth->pusb_dev, ueth->ep_in),
&buf[0], wantlen, &gotlen,
USBCALL_TIMEOUT);
debug("%s() RX want len %d, got len %d, rc %d\n",
if (sts == STAT_RX_FRAME_CORRECT) {
debug("%s() got a frame, len=%d\n", __func__, gotlen);
- net_process_received_packet(buf, gotlen);
- return 0;
+ return gotlen;
}
debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n",
return -EIO;
}
+#ifndef CONFIG_DM_ETH
+/*
+ * mcs7830_init() - network interface's init callback
+ * @udev: network device to initialize
+ * @bd: board information
+ * Return: zero upon success, negative upon error
+ *
+ * after initial setup during probe() and get_info(), this init() callback
+ * ensures that the link is up and subsequent send() and recv() calls can
+ * exchange ethernet frames
+ */
+static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev = eth->priv;
+
+ return mcs7830_init_common(dev->pusb_dev);
+}
+
+/*
+ * mcs7830_send() - network interface's send callback
+ * @eth: network device to send the frame from
+ * @packet: ethernet frame content
+ * @length: ethernet frame length
+ * Return: zero upon success, negative upon error
+ *
+ * this routine send an ethernet frame out of the network interface
+ */
+static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev = eth->priv;
+
+ return mcs7830_send_common(dev, packet, length);
+}
+
+/*
+ * mcs7830_recv() - network interface's recv callback
+ * @eth: network device to receive frames from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine checks for available ethernet frames that the network
+ * interface might have received, and notifies the network stack
+ */
+static int mcs7830_recv(struct eth_device *eth)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
+ struct ueth_data *ueth = eth->priv;
+ int len;
+
+ len = mcs7830_recv_common(ueth, buf);
+ if (len <= 0)
+ net_process_received_packet(buf, len);
+
+ return 0;
+}
+
/*
* mcs7830_halt() - network interface's halt callback
* @eth: network device to cease operation of
debug("%s()\n", __func__);
}
+/*
+ * mcs7830_write_mac() - write an ethernet adapter's MAC address
+ * @eth: network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * this routine takes the MAC address from the ethernet interface's data
+ * structure, and writes it into the ethernet adapter such that subsequent
+ * exchange of ethernet frames uses this address
+ */
+static int mcs7830_write_mac(struct eth_device *eth)
+{
+ struct ueth_data *ueth = eth->priv;
+
+ return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr);
+}
+
/*
* mcs7830_iface_idx - index of detected network interfaces
*
eth->write_hwaddr = mcs7830_write_mac;
eth->priv = ss;
- if (mcs7830_basic_reset(ss))
+ if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv))
return 0;
- if (mcs7830_read_mac(eth))
+ if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr))
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
+#endif
+
+
+#ifdef CONFIG_DM_ETH
+static int mcs7830_eth_start(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+
+ return mcs7830_init_common(udev);
+}
+
+void mcs7830_eth_stop(struct udevice *dev)
+{
+ debug("** %s()\n", __func__);
+}
+
+int mcs7830_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct ueth_data *ueth = &priv->ueth;
+
+ return mcs7830_send_common(ueth, packet, length);
+}
+
+int mcs7830_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct ueth_data *ueth = &priv->ueth;
+ int len;
+
+ len = mcs7830_recv_common(ueth, priv->rx_buf);
+ *packetp = priv->rx_buf;
+
+ return len;
+}
+
+static int mcs7830_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+
+ packet_len = ALIGN(packet_len, 4);
+ usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
+
+ return 0;
+}
+
+int mcs7830_write_hwaddr(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return mcs7830_write_mac_common(udev, pdata->enetaddr);
+}
+
+static int mcs7830_eth_probe(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ueth_data *ueth = &priv->ueth;
+
+ if (mcs7830_basic_reset(udev, priv))
+ return 0;
+
+ if (mcs7830_read_mac(udev, pdata->enetaddr))
+ return 0;
+
+ return usb_ether_register(dev, ueth, MCS7830_RX_URB_SIZE);
+}
+
+static const struct eth_ops mcs7830_eth_ops = {
+ .start = mcs7830_eth_start,
+ .send = mcs7830_eth_send,
+ .recv = mcs7830_eth_recv,
+ .free_pkt = mcs7830_free_pkt,
+ .stop = mcs7830_eth_stop,
+ .write_hwaddr = mcs7830_write_hwaddr,
+};
+
+U_BOOT_DRIVER(mcs7830_eth) = {
+ .name = "mcs7830_eth",
+ .id = UCLASS_ETH,
+ .probe = mcs7830_eth_probe,
+ .ops = &mcs7830_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct mcs7830_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static const struct usb_device_id mcs7830_eth_id_table[] = {
+ { USB_DEVICE(0x9710, 0x7832) }, /* Moschip 7832 */
+ { USB_DEVICE(0x9710, 0x7830), }, /* Moschip 7830 */
+ { USB_DEVICE(0x9710, 0x7730), }, /* Moschip 7730 */
+ { USB_DEVICE(0x0df6, 0x0021), }, /* Sitecom LN 30 */
+ { } /* Terminating entry */
+};
+
+U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table);
+#endif
/*-------------------------------------------------------------------------*/
-struct ums *ums;
-struct fsg_common *the_fsg_common;
+static struct ums *ums;
+static int ums_count;
+static struct fsg_common *the_fsg_common;
static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
{
}
/* Perform the read */
- rc = ums->read_sector(ums,
+ rc = ums[common->lun].read_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
amount = bh->outreq->actual;
/* Perform the write */
- rc = ums->write_sector(ums,
+ rc = ums[common->lun].write_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
}
/* Perform the read */
- rc = ums->read_sector(ums,
+ rc = ums[common->lun].read_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
buf[4] = 31; /* Additional length */
/* No special options */
sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id ,
- ums->name, (u16) 0xffff);
+ ums[common->lun].name, (u16) 0xffff);
return 36;
}
int nluns, i, rc;
/* Find out how many LUNs there should be */
- nluns = 1;
+ nluns = ums_count;
if (nluns < 1 || nluns > FSG_MAX_LUNS) {
printf("invalid number of LUNs: %u\n", nluns);
return ERR_PTR(-EINVAL);
for (i = 0; i < nluns; i++) {
common->luns[i].removable = 1;
- rc = fsg_lun_open(&common->luns[i], "");
+ rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, "");
if (rc)
goto error_luns;
}
return fsg_bind_config(c->cdev, c, fsg_common);
}
-int fsg_init(struct ums *ums_dev)
+int fsg_init(struct ums *ums_devs, int count)
{
- ums = ums_dev;
+ ums = ums_devs;
+ ums_count = count;
return 0;
}
* the caller must own fsg->filesem for writing.
*/
-static int fsg_lun_open(struct fsg_lun *curlun, const char *filename)
+static int fsg_lun_open(struct fsg_lun *curlun, unsigned int num_sectors,
+ const char *filename)
{
int ro;
ro = curlun->initially_ro;
curlun->ro = ro;
- curlun->file_length = ums->num_sectors << 9;
- curlun->num_sectors = ums->num_sectors;
+ curlun->file_length = num_sectors << 9;
+ curlun->num_sectors = num_sectors;
debug("open backing file: %s\n", filename);
return 0;
struct ehci_ctrl ehci;
};
-static void ehci_pci_common_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,
- struct ehci_hcor **ret_hcor)
+#ifdef CONFIG_DM_USB
+
+static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
{
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- uint32_t cmd;
+ u32 cmd;
- hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ hccr = (struct ehci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;
*ret_hcor = hcor;
/* enable busmaster */
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
- pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+ dm_pci_write_config32(dev, PCI_COMMAND, cmd);
}
-#ifndef CONFIG_DM_USB
+#else
#ifdef CONFIG_PCI_EHCI_DEVICE
static struct pci_device_id ehci_pci_ids[] = {
};
#endif
+static void ehci_pci_legacy_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
+{
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ u32 cmd;
+
+ hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ hcor = (struct ehci_hcor *)((uintptr_t) hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
+
+ /* enable busmaster */
+ pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER;
+ pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+}
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
printf("EHCI host controller not found\n");
return -1;
}
- ehci_pci_common_init(pdev, ret_hccr, ret_hcor);
+ ehci_pci_legacy_init(pdev, ret_hccr, ret_hcor);
return 0;
}
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- ehci_pci_common_init(pci_get_bdf(dev), &hccr, &hcor);
+ ehci_pci_init(dev, &hccr, &hcor);
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
void *video_hw_init(void)
{
GraphicDevice *gdev = &ctfb;
+ struct udevice *dev;
int bits_per_pixel;
- pci_dev_t dev;
int ret;
printf("Video: ");
return NULL;
}
if (vbe_get_video_info(gdev)) {
- dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
- if (dev < 0) {
+ ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev);
+ if (ret) {
printf("no card detected\n");
return NULL;
}
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
- ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
+ ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
if (byte_offset != 0) {
int readlen;
/* read first part which isn't aligned with start of sector */
- if (ext4fs_block_dev_desc->
- block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf(" ** ext2fs_devread() read error **\n");
return 0;
}
ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_block_dev_desc->blksz);
block_len = ext4fs_block_dev_desc->blksz;
- ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
+ ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
part_info->start + sector,
- 1, (unsigned long *)p);
+ 1, (void *)p);
memcpy(buf, p, byte_len);
return 1;
}
- if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector,
- block_len >> log2blksz,
- (unsigned long *) buf) !=
- block_len >> log2blksz) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ block_len >> log2blksz,
+ (void *)buf) !=
+ block_len >> log2blksz) {
printf(" ** %s read error - block\n", __func__);
return 0;
}
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
- if (ext4fs_block_dev_desc->
- block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf("* %s read error - last part\n", __func__);
return 0;
}
if (remainder) {
if (fs->dev_desc->block_read) {
- fs->dev_desc->block_read(fs->dev_desc->dev,
+ fs->dev_desc->block_read(fs->dev_desc,
startblock, 1, sec_buf);
temp_ptr = sec_buf;
memcpy((temp_ptr + remainder),
(unsigned char *)buf, size);
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock, 1, sec_buf);
}
} else {
if (size >> log2blksz != 0) {
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock,
size >> log2blksz,
(unsigned long *)buf);
} else {
- fs->dev_desc->block_read(fs->dev_desc->dev,
+ fs->dev_desc->block_read(fs->dev_desc,
startblock, 1, sec_buf);
temp_ptr = sec_buf;
memcpy(temp_ptr, buf, size);
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock, 1,
(unsigned long *)sec_buf);
}
ti_gp_blockno = ext4fs_get_new_blk_no();
if (ti_gp_blockno == -1) {
printf("no block left to assign\n");
- goto fail;
+ return;
}
ti_gp_buff = zalloc(fs->blksz);
if (!ti_gp_buff)
- goto fail;
+ return;
ti_gp_buff_start_addr = ti_gp_buff;
(*no_blks_reqd)++;
ti_child_blockno = ext4fs_get_new_blk_no();
if (ti_child_blockno == -1) {
printf("no block left assign\n");
- goto fail;
+ goto fail1;
}
ti_child_buff = zalloc(fs->blksz);
if (!ti_child_buff)
- goto fail;
+ goto fail1;
ti_cbuff_start_addr = ti_child_buff;
*ti_parent_buff = ti_child_blockno;
ext4fs_get_new_blk_no();
if (actual_block_no == -1) {
printf("no block left\n");
- goto fail;
+ free(ti_cbuff_start_addr);
+ goto fail1;
}
*ti_child_buff = actual_block_no;
debug("TIAB %ld: %u\n", actual_block_no,
put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
ti_gp_buff_start_addr, fs->blksz);
file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
+ free(ti_gp_buff_start_addr);
+ return;
}
+fail1:
+ free(ti_pbuff_start_addr);
fail:
free(ti_gp_buff_start_addr);
}
if (!cur_dev || !cur_dev->block_read)
return -1;
- ret = cur_dev->block_read(cur_dev->dev,
- cur_part_info.start + block, nr_blocks, buf);
+ ret = cur_dev->block_read(cur_dev, cur_part_info.start + block,
+ nr_blocks, buf);
if (nr_blocks && ret == 0)
return -1;
return -1;
}
- ret = cur_dev->block_write(cur_dev->dev,
- cur_part_info.start + block,
+ ret = cur_dev->block_write(cur_dev, cur_part_info.start + block,
nr_blocks, buf);
if (nr_blocks && ret == 0)
return -1;
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start +
+ sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf (" ** reiserfs_devread() read error\n");
return 0;
}
/* read sector aligned part */
block_len = byte_len & ~(SECTOR_SIZE-1);
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, block_len/SECTOR_SIZE,
- (unsigned long *)buf) != block_len/SECTOR_SIZE) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start + sector,
+ block_len / SECTOR_SIZE,
+ (void *)buf)
+ != block_len/SECTOR_SIZE) {
printf (" ** reiserfs_devread() read error - block\n");
return 0;
}
if ( byte_len != 0 ) {
/* read rest of data which are not in whole sector */
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start +
+ sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf (" ** reiserfs_devread() read error - last part\n");
return 0;
}
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
- if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector, 1,
+ (void *)sec_buf)
+ != 1) {
printf(" ** zfs_devread() read error **\n");
return 1;
}
u8 p[SECTOR_SIZE];
block_len = SECTOR_SIZE;
- zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector,
- 1, (unsigned long *)p);
+ zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)p);
memcpy(buf, p, byte_len);
return 0;
}
- if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, block_len / SECTOR_SIZE,
- (unsigned long *) buf) != block_len / SECTOR_SIZE) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ block_len / SECTOR_SIZE,
+ (void *)buf)
+ != block_len / SECTOR_SIZE) {
printf(" ** zfs_devread() read error - block\n");
return 1;
}
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
- if (zfs_block_dev_desc->
- block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf) != 1) {
printf(" ** zfs_devread() read error - last part\n");
return 1;
}
};
struct ahci_probe_ent {
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+#else
pci_dev_t dev;
+#endif
struct ahci_ioports port[AHCI_MAX_PORTS];
u32 n_ports;
u32 hard_port_no;
int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
/* Run a BIOS ROM natively (only supported on x86 machines) */
-void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
struct vbe_mode_info *mode_info);
/**
char *const argv[]);
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*
* Error codes that commands return to cmd_process(). We use the standard 0
void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
/**
- * board_init_f_mem() - Allocate global data and set stack position
+ * ulong board_init_f_alloc_reserve - allocate reserved area
*
* This function is called by each architecture very early in the start-up
- * code to set up the environment for board_init_f(). It allocates space for
- * global_data (see include/asm-generic/global_data.h) and places the stack
- * below this.
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
*
- * This function requires a stack[1] Normally this is at @top. The function
- * starts allocating space from 64 bytes below @top. First it creates space
- * for global_data. Then it calls arch_setup_gd() which sets gd to point to
- * the global_data space and can reserve additional bytes of space if
- * required). Finally it allocates early malloc() memory
- * (CONFIG_SYS_MALLOC_F_LEN). The new top of the stack is just below this,
- * and it returned by this function.
+ * @top: top of the reserve area, growing down.
+ * @return: bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
*
- * [1] Strictly speaking it would be possible to implement this function
- * in C on many archs such that it does not require a stack. However this
- * does not seem hugely important as only 64 byte are wasted. The 64 bytes
- * are used to handle the calling standard which generally requires pushing
- * addresses or registers onto the stack. We should be able to get away with
- * less if this becomes important.
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
*
- * @top: Top of available memory, also normally the top of the stack
- * @return: New stack location
+ * @base: top from which reservation was done
*/
-ulong board_init_f_mem(ulong top);
+void board_init_f_init_reserve(ulong base);
/**
* arch_setup_gd() - Set up the global_data pointer
#endif
#undef CONFIG_DM_WARN
-#undef CONFIG_DM_SEQ_ALIAS
#undef CONFIG_DM_STDIO
#endif /* CONFIG_SPL_BUILD */
#include <configs/ti_am335x_common.h>
-/* Don't override the distro default bootdelay */
-#undef CONFIG_BOOTDELAY
-#include <config_distro_defaults.h>
-
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_FIT
# define CONFIG_FIT
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
#endif
#ifndef CONFIG_SPL_BUILD
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_CLEARFOG_H
+#define _CONFIG_CLEARFOG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MV_SDHCI
+#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
+
+/* Partition support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_ENV_MIN_ENTRIES 128
+
+/* Environment in MMC */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SECT_SIZE 0x200
+#define CONFIG_ENV_SIZE 0x10000
+/*
+ * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
+ * boot image starts @ LBA-0.
+ * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
+ * image and environment
+ */
+#define CONFIG_ENV_OFFSET 0xf0000
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH 1
+#define SPL_BOOT_SDIO_MMC_CARD 2
+#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\
+ + 1)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
+#endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_CLEARFOG_H */
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
-#define CONFIG_ARMADA_38X
-#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
-#define CONFIG_SYS_L2_PL310
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 1, 0 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+#endif
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
#endif
#endif
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_A38X
-#define CONFIG_DDR3
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* SATA support */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE
-
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
-
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
-
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA_MV
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_EFI_PARTITION
#define CONFIG_DOS_PARTITION
-#endif /* CONFIG_CMD_IDE */
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+#endif
/* NAND */
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e
+#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
-#define CONFIG_SYS_TEXT_BASE 0x83FA0000
+#define CONFIG_SYS_TEXT_BASE 0x83F00000
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
#define CONFIG_BAUDRATE 115200
+/*
+ * DMA
+ */
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DMA_LPC32XX
+#endif
+
/*
* I2C
*/
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_LPC32XX
+#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
/*
* U-Boot General Configurations
*/
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
#define CONFIG_QSPI_QUAD_SUPPORT
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x010000 : QSPI.SPL (64KiB)
--- /dev/null
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_SYNOLOGY_DS414_H
+#define _CONFIG_SYNOLOGY_DS414_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define CONFIG_PHY_ADDR { 0x1, 0x0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* USB/EHCI/XHCI configuration */
+
+#define CONFIG_DM_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* FIXME: broken XHCI support
+ * Below defines should enable support for the two rear USB3 ports. Sadly, this
+ * does not work because:
+ * - xhci-pci seems to not support DM_USB, so with that enabled it is not
+ * found.
+ * - USB init fails, controller does not respond in time */
+#if 0
+#undef CONFIG_DM_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_PCI
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if !defined(CONFIG_USB_XHCI)
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_SYS_MVFS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+
+/* DS414 bus width is 32bits */
+#define CONFIG_DDR_32BIT
+
+/* Use random ethernet address if not configured */
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
+/* Default Environment */
+#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+#define CONFIG_LOADADDR 0x80000
+#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
+#define CONFIG_PREBOOT "usb start; sf probe"
+
+#endif /* _CONFIG_SYNOLOGY_DS414_H */
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
+#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_SPL_SERIAL_SUPPORT
+
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
*/
#define CONFIG_PARTITION_UUIDS
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_CMD_PART
-/*
- * Filesystems
- */
-
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-
/*
* SPL
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x82000000\0" \
+ "loadaddr=0x82000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "fdtaddr=0x88000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80000000\0" \
+ "bootm_size=0x10000000\0" \
"boot_mmc_dev=0\0" \
"kernel_mmc_part=3\0" \
"recovery_mmc_part=4\0" \
+ "fdtfile=omap3-sniper.dtb\0" \
+ "bootfile=/boot/extlinux/extlinux.conf\0" \
"bootargs=console=ttyO2 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
/*
- * ATAGs / Device Tree
+ * ATAGs
*/
-#define CONFIG_OF_LIBFDT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
*/
#define CONFIG_SYS_LOAD_ADDR 0x82000000
-#define CONFIG_BOOTDELAY 1
#define CONFIG_ANDROID_BOOT_IMAGE
*/
#include <config_defaults.h>
+#include <config_distro_defaults.h>
#endif
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_DM_SEQ_ALIAS 1
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif
#include <config_distro_defaults.h>
+#define CONFIG_CMD_EXT4_WRITE
#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
/*
* Environment setup
*/
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance"; "\
+ "setenv bootpart " #instance":2 ; "\
+ "run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(LEGACY_MMC, legacy_mmc, 1) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadbootenv; then " \
- "run importbootenv; " \
- "fi;" \
- "if test -n ${uenvcmd}; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcboot; " \
- "fi; " \
- "if run loaduimage; then " \
- "run uimageboot;" \
- "fi; " \
- "fi"
+ BOOTENV
/*
* Defines for SPL
*/
fdt_addr_t dev_get_addr(struct udevice *dev);
+/**
+ * dev_get_addr_index() - Get the indexed reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
+
/**
* device_has_children() - check if a device has any children
*
#endif /* ! CONFIG_DEVRES */
+/**
+ * dm_set_translation_offset() - Set translation offset
+ * @offs: Translation offset
+ *
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling this function. It will be
+ * added to all addresses returned in dev_get_addr().
+ */
+void dm_set_translation_offset(fdt_addr_t offs);
+
+/**
+ * dm_get_translation_offset() - Get translation offset
+ *
+ * This function returns the translation offset that can
+ * be configured by calling dm_set_translation_offset().
+ *
+ * @return translation offset for the device address (0 as default).
+ */
+fdt_addr_t dm_get_translation_offset(void);
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LPC32XX_HSUART_PLAT_H
+#define _LPC32XX_HSUART_PLAT_H
+
+/**
+ * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ *
+ * @base: Base register address
+ */
+struct lpc32xx_hsuart_platdata {
+ unsigned long base;
+};
+
+#endif
int fdtdec_get_pci_vendev(const void *blob, int node,
u16 *vendor, u16 *device);
-/**
- * Look at the pci address of a device node that represents a PCI device
- * and parse the bus, device and function number from it. For some cases
- * like the bus number encoded in reg property is not correct after pci
- * enumeration, this function looks through the node's compatible strings
- * to get these numbers extracted instead.
- *
- * @param blob FDT blob
- * @param node node to examine
- * @param addr pci address in the form of fdt_pci_addr
- * @param bdf returns bus, device, function triplet
- * @return 0 if ok, negative on error
- */
-int fdtdec_get_pci_bdf(const void *blob, int node,
- struct fdt_pci_addr *addr, pci_dev_t *bdf);
-
/**
* Look at the pci address of a device node that represents a PCI device
* and return base address of the pci device's registers.
*
- * @param blob FDT blob
- * @param node node to examine
+ * @param dev device to examine
* @param addr pci address in the form of fdt_pci_addr
* @param bar returns base address of the pci device's registers
* @return 0 if ok, negative on error
*/
-int fdtdec_get_pci_bar32(const void *blob, int node,
- struct fdt_pci_addr *addr, u32 *bar);
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+ u32 *bar);
/**
* Look up a 32-bit integer property in a node and return it. The property
int hash_block(const char *algo_name, const void *data, unsigned int len,
uint8_t *output, int *output_size);
-/**
- * hash_show() - Print out a hash algorithm and value
- *
- * You will get a message like this (without a newline at the end):
- *
- * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257"
- *
- * @algo: Algorithm used for hash
- * @addr: Address of data that was hashed
- * @len: Length of data that was hashed
- * @output: Hash value to display
- */
-void hash_show(struct hash_algo *algo, ulong addr, ulong len,
- uint8_t *output);
-
#endif /* !USE_HOSTCC */
/**
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
-#define LBAF "%llx"
-#define LBAFU "%llu"
+#define LBAFlength "ll"
#else
typedef ulong lbaint_t;
-#define LBAF "%lx"
-#define LBAFU "%lu"
+#define LBAFlength "l"
#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
/*
* Function Prototypes
*/
void ide_init(void);
-ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer);
-ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt,
+typedef struct block_dev_desc block_dev_desc_t;
+ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer);
+ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer);
#ifdef CONFIG_IDE_PREINIT
u8 part_attr;
u8 wr_rel_set;
char part_config;
- char part_num;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
* This finds all the matching PCI IDs and sets them up as MMC devices.
*
* @name: Name to use for devices
- * @mmc_supported: PCI IDs to search for
- * @num_ids: Number of elements in @mmc_supported
+ * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
*/
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids);
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
extern struct eth_device *eth_current;
-static inline __attribute__((always_inline))
-struct eth_device *eth_get_dev(void)
+static __always_inline struct eth_device *eth_get_dev(void)
{
return eth_current;
}
/* Used only when NetConsole is enabled */
int eth_is_active(struct eth_device *dev); /* Test device for active state */
/* Set active state */
-static inline __attribute__((always_inline)) int eth_init_state_only(void)
+static __always_inline int eth_init_state_only(void)
{
eth_get_dev()->state = ETH_STATE_ACTIVE;
return 0;
}
/* Set passive state */
-static inline __attribute__((always_inline)) void eth_halt_state_only(void)
+static __always_inline void eth_halt_state_only(void)
{
eth_get_dev()->state = ETH_STATE_PASSIVE;
}
unsigned src_port, unsigned len);
#endif
-static inline __attribute__((always_inline)) int eth_is_on_demand_init(void)
+static __always_inline int eth_is_on_demand_init(void)
{
#ifdef CONFIG_NETCONSOLE
extern enum proto_t net_loop_last_protocol;
#include <ide.h>
#include <common.h>
-typedef struct block_dev_desc {
+typedef struct block_dev_desc block_dev_desc_t;
+
+struct block_dev_desc {
int if_type; /* type of the interface */
int dev; /* device number */
unsigned char part_type; /* partition type */
unsigned char target; /* target SCSI ID */
unsigned char lun; /* target LUN */
+ unsigned char hwpart; /* HW partition, e.g. for eMMC */
unsigned char type; /* device type */
unsigned char removable; /* removable device */
#ifdef CONFIG_LBA48
char vendor [40+1]; /* IDE model, SCSI Vendor */
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
- unsigned long (*block_read)(int dev,
+ unsigned long (*block_read)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt,
void *buffer);
- unsigned long (*block_write)(int dev,
+ unsigned long (*block_write)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt,
const void *buffer);
- unsigned long (*block_erase)(int dev,
+ unsigned long (*block_erase)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt);
void *priv; /* driver private struct pointer */
-}block_dev_desc_t;
+};
#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
#endif
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
/* For driver model these are defined in macros in pci_compat.c */
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
/**
- * pci_get_bdf() - Get the BDF value for a device
+ * dm_pci_get_bdf() - Get the BDF value for a device
*
* @dev: Device to check
* @return bus/device/function value (see PCI_BDF())
*/
-pci_dev_t pci_get_bdf(struct udevice *dev);
+pci_dev_t dm_pci_get_bdf(struct udevice *dev);
/**
* pci_bind_bus_devices() - scan a PCI bus and bind devices
int pci_auto_config_devices(struct udevice *bus);
/**
- * pci_bus_find_bdf() - Find a device given its PCI bus address
+ * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
*
* @bdf: PCI device address: bus, device and function -see PCI_BDF()
* @devp: Returns the device for this address, if found
* @return 0 if OK, -ENODEV if not found
*/
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
/**
* pci_bus_find_devfn() - Find a device on a bus
* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
* @return 0 if OK, -ve on error
*/
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf);
+int dm_pci_hose_probe_bus(struct udevice *bus);
/**
* pci_bus_read_config() - Read a configuration value from a device
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
+/**
+ * dm_pci_read_bar32() - read a base address register from a device
+ *
+ * @dev: Device to check
+ * @barnum: Bar number to read (numbered from 0)
+ * @return: value of BAR
+ */
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
+
+/**
+ * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
+ *
+ * @dev: Device containing the PCI address
+ * @addr: PCI address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return physical address corresponding to that PCI bus address
+ */
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
+ *
+ * @dev: Device containing the bus address
+ * @addr: Physical address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return PCI bus address corresponding to that physical address
+ */
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_map_bar() - get a virtual address associated with a BAR region
+ *
+ * Looks up a base address register and finds the physical memory address
+ * that corresponds to it
+ *
+ * @dev: Device to check
+ * @bar: Bar number to read (numbered from 0)
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return: pointer to the virtual address to use
+ */
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
+
+#define dm_pci_virt_to_bus(dev, addr, flags) \
+ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
+#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+ map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
+ (len), (map_flags))
+
+#define dm_pci_phys_to_mem(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_phys_to_io(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define dm_pci_virt_to_mem(dev, addr) \
+ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
+ dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define dm_pci_virt_to_io(dev, addr) \
+ dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
+ dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
+/**
+ * dm_pci_find_device() - find a device by vendor/device ID
+ *
+ * @vendor: Vendor ID
+ * @device: Device ID
+ * @index: 0 to find the first match, 1 for second, etc.
+ * @devp: Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+ struct udevice **devp);
+
+/**
+ * dm_pci_find_class() - find a device by class
+ *
+ * @find_class: 3-byte (24-bit) class value to find
+ * @index: 0 to find the first match, 1 for second, etc.
+ * @devp: Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
+
/**
* struct dm_pci_emul_ops - PCI device emulator operations
*/
};
/**
- * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ * dm_pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
*
* @dev: Video device containing the BIOS
* @int15_handler: Function to call to handle int 0x15
* @exec_method: flags from enum pci_rom_emul
*/
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void),
- int exec_method);
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+ int exec_method);
/**
* board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
#define __CORE_PMIC_H_
#include <i2c.h>
-#include <spi.h>
#include <linux/list.h>
#include <power/power_chrg.h>
#define _SPI_H_
/* SPI mode flags */
-#define SPI_CPHA 0x01 /* clock phase */
-#define SPI_CPOL 0x02 /* clock polarity */
-#define SPI_MODE_0 (0|0) /* (original MicroWire) */
-#define SPI_MODE_1 (0|SPI_CPHA)
-#define SPI_MODE_2 (SPI_CPOL|0)
-#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
-#define SPI_CS_HIGH 0x04 /* CS active high */
-#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
-#define SPI_3WIRE 0x10 /* SI/SO signals shared */
-#define SPI_LOOP 0x20 /* loopback mode */
-#define SPI_SLAVE 0x40 /* slave mode */
-#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
-
-/* SPI transfer flags */
-#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
-#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
-#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
-#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
-#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE (1 << 5)
-
-/* SPI TX operation modes */
-#define SPI_OPM_TX_QPP (1 << 0)
-#define SPI_OPM_TX_BP (1 << 1)
-
-/* SPI RX operation modes */
-#define SPI_OPM_RX_AS (1 << 0)
-#define SPI_OPM_RX_AF (1 << 1)
-#define SPI_OPM_RX_DOUT (1 << 2)
-#define SPI_OPM_RX_DIO (1 << 3)
-#define SPI_OPM_RX_QOF (1 << 4)
-#define SPI_OPM_RX_QIOF (1 << 5)
-#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
- SPI_OPM_RX_QIOF)
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_MODE_0 (0|0) /* (original MicroWire) */
+#define SPI_MODE_1 (0|SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL|0)
+#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
+#define SPI_CS_HIGH BIT(2) /* CS active high */
+#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
+#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
+#define SPI_LOOP BIT(5) /* loopback mode */
+#define SPI_SLAVE BIT(6) /* slave mode */
+#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */
+#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
+#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
+#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
+
+/* SPI mode_rx flags */
+#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */
+#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
+#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
/* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 << 0)
* @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
*/
struct dm_spi_slave_platdata {
unsigned int cs;
uint max_hz;
uint mode;
+ u8 mode_rx;
};
#endif /* CONFIG_DM_SPI */
*
* @dev: SPI slave device
* @max_hz: Maximum speed for this slave
- * @mode: SPI mode to use for this slave (see SPI mode flags)
* @speed: Current bus speed. This is 0 until the bus is first
* claimed.
* @bus: ID of the bus that the slave is attached to. For
* driver model this is the sequence number of the SPI
* bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave.
- * @op_mode_rx: SPI RX operation mode.
- * @op_mode_tx: SPI TX operation mode.
+ * @mode: SPI mode to use for this slave (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
struct udevice *dev; /* struct spi_slave is dev->parentdata */
uint max_hz;
uint speed;
- uint mode;
#else
unsigned int bus;
unsigned int cs;
#endif
- u8 op_mode_rx;
- u8 op_mode_tx;
+ uint mode;
+ u8 mode_rx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
u8 option;
+
u8 flags;
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */
+#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */
+#define SPI_XFER_U_PAGE BIT(4)
};
/**
/* Compatibility function - this is the old U-Boot API */
void spi_flash_free(struct spi_flash *flash);
-int spi_flash_remove(struct udevice *flash);
-
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{
unsigned int start_sector;
unsigned int num_sectors;
const char *name;
- block_dev_desc_t *block_dev;
+ block_dev_desc_t block_dev;
};
-extern struct ums *ums;
-
-int fsg_init(struct ums *);
+int fsg_init(struct ums *ums_devs, int count);
void fsg_cleanup(void);
int fsg_main_thread(void *);
int fsg_add(struct usb_configuration *c);
#ifndef USE_HOSTCC
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <serial.h>
#include <libfdt.h>
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
const char *prop_name, struct fdt_pci_addr *addr)
{
return -ENOENT;
}
-int fdtdec_get_pci_bdf(const void *blob, int node,
- struct fdt_pci_addr *addr, pci_dev_t *bdf)
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+ u32 *bar)
{
- u16 dt_vendor, dt_device, vendor, device;
- int ret;
-
- /* get vendor id & device id from the compatible string */
- ret = fdtdec_get_pci_vendev(blob, node, &dt_vendor, &dt_device);
- if (ret)
- return ret;
-
- /* extract the bdf from fdt_pci_addr */
- *bdf = addr->phys_hi & 0xffff00;
-
- /* read vendor id & device id based on bdf */
- pci_read_config_word(*bdf, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(*bdf, PCI_DEVICE_ID, &device);
-
- /*
- * Note there are two places in the device tree to fully describe
- * a pci device: one is via compatible string with a format of
- * "pciVVVV,DDDD" and the other one is the bdf numbers encoded in
- * the device node's reg address property. We read the vendor id
- * and device id based on bdf and compare the values with the
- * "VVVV,DDDD". If they are the same, then we are good to use bdf
- * to read device's bar. But if they are different, we have to rely
- * on the vendor id and device id extracted from the compatible
- * string and locate the real bdf by pci_find_device(). This is
- * because normally we may only know device's device number and
- * function number when writing device tree. The bus number is
- * dynamically assigned during the pci enumeration process.
- */
- if ((dt_vendor != vendor) || (dt_device != device)) {
- *bdf = pci_find_device(dt_vendor, dt_device, 0);
- if (*bdf == -1)
- return -ENODEV;
- }
-
- return 0;
-}
-
-int fdtdec_get_pci_bar32(const void *blob, int node,
- struct fdt_pci_addr *addr, u32 *bar)
-{
- pci_dev_t bdf;
int barnum;
- int ret;
-
- /* get pci devices's bdf */
- ret = fdtdec_get_pci_bdf(blob, node, addr, &bdf);
- if (ret)
- return ret;
/* extract the bar number from fdt_pci_addr */
barnum = addr->phys_hi & 0xff;
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
- *bar = pci_read_bar32(pci_bus_to_hose(PCI_BUS(bdf)), bdf, barnum);
+ *bar = dm_pci_read_bar32(dev, barnum);
return 0;
}
gzwrite_progress(iteration++,
totalfilled,
szexpected);
- blocks_written = dev->block_write(dev->dev,
- outblock,
+ blocks_written = dev->block_write(dev, outblock,
writeblocks,
writebuf);
outblock += blocks_written;
/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
{
- pci_dev_t pci_dev = PCI_BDF(0, 0x1f, 0);
- struct pci_controller *hose;
- struct udevice *bus, *swap;
+ struct udevice *emul, *swap;
ulong io_addr, mem_addr;
char *ptr;
/* Check that asking for the device automatically fires up PCI */
- ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &swap));
-
- ut_assertok(uclass_get_device(UCLASS_PCI, 0, &bus));
- hose = dev_get_uclass_priv(bus);
+ ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
+ ut_assert(device_active(swap));
/* First test I/O */
- io_addr = pci_read_bar32(hose, pci_dev, 0);
+ io_addr = dm_pci_read_bar32(swap, 0);
outb(2, io_addr);
ut_asserteq(2, inb(io_addr));
* Now test memory mapping - note we must unmap and remap to cause
* the swapcase emulation to see our data and response.
*/
- mem_addr = pci_read_bar32(hose, pci_dev, 1);
+ mem_addr = dm_pci_read_bar32(swap, 1);
ptr = map_sysmem(mem_addr, 20);
strcpy(ptr, "This is a TesT");
unmap_sysmem(ptr);
/* Read a few blocks and look for the string we expect */
ut_asserteq(512, dev_desc->blksz);
memset(cmp, '\0', sizeof(cmp));
- ut_asserteq(2, dev_desc->block_read(dev_desc->dev, 0, 2, cmp));
+ ut_asserteq(2, dev_desc->block_read(dev_desc, 0, 2, cmp));
ut_assertok(strcmp(cmp, "this is a test"));
return 0;
# We save time by not deleting and recreating the file system images
function prepare_env() {
rm -f ${MD5_FILE}.* ${OUT}.*
- mkdir ${OUT_DIR}
+ mkdir -p ${OUT_DIR}
}
# 1st parameter is the name of the image file to be created
fi
if [ ! -f "$1" ]; then
fallocate -l 3G "$1" &> /dev/null
+ if [ $? -ne 0 ]; then
+ echo fallocate failed - using dd instead
+ dd if=/dev/zero of=$1 bs=1024 count=$((3 * 1024 * 1024))
+ if [ $? -ne 0 ]; then
+ echo Could not create empty disk image
+ exit $?
+ fi
+ fi
mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null
if [ $? -ne 0 -a "$2" = "fat" ]; then
# If we fail and we did fat, try vfat.
mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null
fi
+ if [ $? -ne 0 ]; then
+ echo Could not create filesystem
+ exit $?
+ fi
fi
}
HOSTCFLAGS_ubsha1.o := -pedantic
hostprogs-$(CONFIG_KIRKWOOD) += kwboot
-hostprogs-$(CONFIG_ARMADA_XP) += kwboot
+hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot
hostprogs-y += proftool
hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
* 2008. Chapter 24.2 "BootROM Firmware".
*/
+#include "kwbimage.h"
+#include "mkimage.h"
+
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
+#include <image.h>
#include <libgen.h>
#include <fcntl.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/stat.h>
-#include "kwbimage.h"
-
#ifdef __GNUC__
#define PACKED __attribute((packed))
#else
hdr->blockid = IBR_HDR_UART_ID;
+ /*
+ * Subtract mkimage header size from destination address
+ * as this header is not expected by the Marvell BootROM.
+ * This way, the execution address is identical to the
+ * one the image is compiled for (TEXT_BASE).
+ */
+ hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
+
if (image_ver == 0) {
struct main_hdr_v0 *hdr_v0 = img;
projects / people / ms / u-boot.git / commitdiff
