marvell,function = "i2c0";
};
+ nand_pins: nand-pins {
+ marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+ "mpp38", "mpp28", "mpp40", "mpp42",
+ "mpp35", "mpp36", "mpp25", "mpp30",
+ "mpp32";
+ marvell,function = "dev";
+ };
+
+ nand_rb: nand-rb {
+ marvell,pins = "mpp41";
+ marvell,function = "nand";
+ };
+
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
};
flash@d0000 {
- compatible = "marvell,armada370-nand";
+ compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
+#if defined(CONFIG_ARMADA_38X)
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS 0
+#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
+#else
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
+#endif
#if defined(CONFIG_ARMADA_375)
/* SAR values for Armada 375 */
#define BOOT_DEV_SEL_OFFS 4
#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
+#define BOOT_FROM_NAND 0x0A
#define BOOT_FROM_UART 0x28
#define BOOT_FROM_UART_ALT 0x3f
#define BOOT_FROM_SPI 0x32
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+#if defined(CONFIG_ARMADA_38X)
+ /*
+ * If the bootrom error register contains any else than zeros
+ * in the first 8 bits it's an error condition. And in that case
+ * try to boot from UART.
+ */
+ if (boot_device)
+#else
if (boot_device == BOOTROM_ERR_MODE_UART)
+#endif
return BOOT_DEVICE_UART;
/*
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
+#if defined(CONFIG_ARMADA_38X)
+ case BOOT_FROM_NAND:
+ return BOOT_DEVICE_NAND;
+#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
* SPL has no chance to receive this information. So we
* need to return to the BootROM to enable this xmodem
* UART download.
+ *
+ * If booting from NAND lets let the BootROM load the
+ * rest of the bootloader.
*/
- if (get_boot_device() == BOOT_DEVICE_UART)
- return_to_bootrom();
+ switch (get_boot_device()) {
+ case BOOT_DEVICE_UART:
+#if defined(CONFIG_ARMADA_38X)
+ case BOOT_DEVICE_NAND:
+#endif
+ return_to_bootrom();
+ }
}
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_16, /* memory_width */
MEM_8G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_8, /* memory_width */
MEM_2G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_8, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_533, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
{ 0xba20, 16, 16, &timing[3] },
};
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
.maxblocks = 8, /* Last 8 blocks in each chip */
.pattern = bbt_mirror_pattern
};
+#endif
static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
.eccbytes = 32,
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-/* Environment in SPI NOR flash */
-#ifdef CONFIG_MVEBU_SPI_BOOT
-/* Environment in NAND flash */
-#endif
-
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */