]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
Merge git://git.denx.de/u-boot-marvell
authorTom Rini <trini@konsulko.com>
Thu, 30 Nov 2017 15:38:40 +0000 (10:38 -0500)
committerTom Rini <trini@konsulko.com>
Thu, 30 Nov 2017 15:38:40 +0000 (10:38 -0500)
arch/arm/dts/armada-38x.dtsi
arch/arm/mach-mvebu/include/mach/soc.h
arch/arm/mach-mvebu/spl.c
board/CZ.NIC/turris_omnia/turris_omnia.c
board/Marvell/db-88f6820-amc/db-88f6820-amc.c
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
board/gdsys/a38x/controlcenterdc.c
board/solidrun/clearfog/clearfog.c
drivers/mtd/nand/pxa3xx_nand.c
include/configs/mvebu_armada-8k.h

index dc8a1a66c1fb627d710176fa0cfdb391d6f8d180..5e5a15855189b4d546441391dffc0e53418567ed 100644 (file)
                                        marvell,function = "i2c0";
                                };
 
+                               nand_pins: nand-pins {
+                                       marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+                                                      "mpp38", "mpp28", "mpp40", "mpp42",
+                                                      "mpp35", "mpp36", "mpp25", "mpp30",
+                                                      "mpp32";
+                                       marvell,function = "dev";
+                               };
+
+                               nand_rb: nand-rb {
+                                       marvell,pins = "mpp41";
+                                       marvell,function = "nand";
+                               };
+
                                mdio_pins: mdio-pins {
                                        marvell,pins = "mpp4", "mpp5";
                                        marvell,function = "ge";
                        };
 
                        flash@d0000 {
-                               compatible = "marvell,armada370-nand";
+                               compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
                                reg = <0xd0000 0x54>;
                                #address-cells = <1>;
                                #size-cells = <1>;
index 1d302761f090f67ba71d498c619e6ba4471fdf75..1a06a1e8760249560baa51ebf022058ea7324bb0 100644 (file)
 #define COMPHY_REFCLK_ALIGNMENT        (MVEBU_REGISTER(0x182f8))
 
 /* BootROM error register (also includes some status infos) */
+#if defined(CONFIG_ARMADA_38X)
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS  0
+#define BOOTROM_ERR_MODE_MASK  (0xf << BOOTROM_ERR_MODE_OFFS)
+#else
 #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
 #define BOOTROM_ERR_MODE_OFFS  28
 #define BOOTROM_ERR_MODE_MASK  (0xf << BOOTROM_ERR_MODE_OFFS)
 #define BOOTROM_ERR_MODE_UART  0x6
+#endif
 
 #if defined(CONFIG_ARMADA_375)
 /* SAR values for Armada 375 */
 #define BOOT_DEV_SEL_OFFS      4
 #define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
 
+#define BOOT_FROM_NAND         0x0A
 #define BOOT_FROM_UART         0x28
 #define BOOT_FROM_UART_ALT     0x3f
 #define BOOT_FROM_SPI          0x32
index a72a769f7c740eeb8c4fabf46964c0ba913f2e3d..d16a62d2dd32f8d8d51369c664d1716b770f2c08 100644 (file)
@@ -26,7 +26,16 @@ static u32 get_boot_device(void)
        val = readl(CONFIG_BOOTROM_ERR_REG);
        boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
        debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+#if defined(CONFIG_ARMADA_38X)
+       /*
+        * If the bootrom error register contains any else than zeros
+        * in the first 8 bits it's an error condition. And in that case
+        * try to boot from UART.
+        */
+       if (boot_device)
+#else
        if (boot_device == BOOTROM_ERR_MODE_UART)
+#endif
                return BOOT_DEVICE_UART;
 
        /*
@@ -36,6 +45,10 @@ static u32 get_boot_device(void)
        boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
        debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
        switch (boot_device) {
+#if defined(CONFIG_ARMADA_38X)
+       case BOOT_FROM_NAND:
+               return BOOT_DEVICE_NAND;
+#endif
 #ifdef CONFIG_SPL_MMC_SUPPORT
        case BOOT_FROM_MMC:
        case BOOT_FROM_MMC_ALT:
@@ -119,7 +132,15 @@ void board_init_f(ulong dummy)
         * SPL has no chance to receive this information. So we
         * need to return to the BootROM to enable this xmodem
         * UART download.
+        *
+        * If booting from NAND lets let the BootROM load the
+        * rest of the bootloader.
         */
-       if (get_boot_device() == BOOT_DEVICE_UART)
-               return_to_bootrom();
+       switch (get_boot_device()) {
+               case BOOT_DEVICE_UART:
+#if defined(CONFIG_ARMADA_38X)
+               case BOOT_DEVICE_NAND:
+#endif
+                       return_to_bootrom();
+       }
 }
index af66837909defadcd00210b61fdde698cdc59802..b03c0a3714b19833a0a486a94c3929443a647978 100644 (file)
@@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_NORMAL,            /* temperature */
            HWS_TIM_2T} },              /* timing (force 2t) */
        5,                              /* Num Of Bus Per Interface*/
@@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_8G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_NORMAL,            /* temperature */
            HWS_TIM_2T} },              /* timing (force 2t) */
        5,                              /* Num Of Bus Per Interface*/
index ac58f9085266b7cad399e76b52a1cce15f0dbc40..7db0095f75ef05befaa3643428ed402da255ffa4 100644 (file)
@@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = {
            BUS_WIDTH_8,                /* memory_width */
            MEM_2G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index a1974cb4bd21138eaad9b9ce9dbe08cc3acfaa13..b95cd1d4aab5b99cb18c993fd6f54ff0761067d4 100644 (file)
@@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = {
            BUS_WIDTH_8,                /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index 32168d35768a1a6375c2497276b5ed7294239c81..3d74a6dfb89726cc80ee43cfe41c9e476cf47ecf 100644 (file)
@@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_533,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index 8906636f7646d931ee6051b28a58f0a13567d50e..1472e9793e5f3619e3802b1d5264e250baa5add2 100644 (file)
@@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index 6ab3c8a25add16857e225440f42ee381395046e4..cedbb239b686eb6733c0c28b506d198545429a1e 100644 (file)
@@ -233,6 +233,7 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = {
        { 0xba20, 16, 16, &timing[3] },
 };
 
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
 
@@ -255,6 +256,7 @@ static struct nand_bbt_descr bbt_mirror_descr = {
        .maxblocks = 8,         /* Last 8 blocks in each chip */
        .pattern = bbt_mirror_pattern
 };
+#endif
 
 static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
        .eccbytes = 32,
index fd60a9bfd483bec74b18a11246463a53b95b5216..d85527434a0aa5ab36dc191318be1e922449bb64 100644 (file)
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
 
-/* Environment in SPI NOR flash */
-#ifdef CONFIG_MVEBU_SPI_BOOT
-/* Environment in NAND flash */
-#endif
-
 #define CONFIG_ENV_OFFSET              0x180000 /* as Marvell U-Boot version */
 #define CONFIG_ENV_SIZE                        (64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64KiB sectors */