tests: (lscpu) update RISC-V tests to add ISA line

Signed-off-by: Karel Zak <kzak@redhat.com>

diff --git a/tests/expected/lscpu/lscpu-rv64-linux b/tests/expected/lscpu/lscpu-rv64-linux
index d741cae22fd2776095ea95598d93b784672d9177..fbfea0b4f8523ecfadba0963d4ff7caa92fd635d 100644 (file)
--- a/tests/expected/lscpu/lscpu-rv64-linux
+++ b/tests/expected/lscpu/lscpu-rv64-linux
@@ -4,6 +4,7 @@ Model name:          sifive,u74-mc
 Thread(s) per core:  2
 Core(s) per socket:  1
 Socket(s):           1
+ISA:                 rv64imafdc
 L1d cache:           64 KiB (2 instances)
 L1i cache:           64 KiB (2 instances)
 L2 cache:            2 MiB (1 instance)

diff --git a/tests/expected/lscpu/lscpu-rv64-milkvpioneer b/tests/expected/lscpu/lscpu-rv64-milkvpioneer
index 8345664d8d221cfa8c41d26c91c757c2d6458a79..69a574b971dc6d85f855e77460f7e4dc59266f7c 100644 (file)
--- a/tests/expected/lscpu/lscpu-rv64-milkvpioneer
+++ b/tests/expected/lscpu/lscpu-rv64-milkvpioneer
@@ -7,6 +7,7 @@ Model:               0x0
 Thread(s) per core:  1
 Core(s) per socket:  64
 Socket(s):           1
+ISA:                 rv64imafdcv
 NUMA node(s):        4
 NUMA node0 CPU(s):   0-7,16-23
 NUMA node1 CPU(s):   8-15,24-31

diff --git a/tests/expected/lscpu/lscpu-rv64-visionfive2 b/tests/expected/lscpu/lscpu-rv64-visionfive2
index 0b2390d88e4cf6d0f691200fb01cbb332cf4f02d..cd87ba57bd3b85930e354d1905df6f6155ec6cde 100644 (file)
--- a/tests/expected/lscpu/lscpu-rv64-visionfive2
+++ b/tests/expected/lscpu/lscpu-rv64-visionfive2
@@ -8,6 +8,7 @@ Model:               0x4210427
 Thread(s) per core:  1
 Core(s) per socket:  4
 Socket(s):           1
+ISA:                 rv64imafdc zba zbb zicntr zicsr zifencei zihpm
 L1d cache:           128 KiB (4 instances)
 L1i cache:           128 KiB (4 instances)
 L2 cache:            2 MiB (1 instance)