*.orig
*.a
*.o
+*~
#
# Top-level generic files
+commit e7670f6c1e52ae6d2a43ff75a8bcfa7a5c86e47b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Feb 14 22:43:22 2008 +0100
+
+ PPC: Use r2 instead of r29 as global data pointer
+
+ R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
+ will refuse to use load/store multiple insns; instead, it issues a
+ list of simple load/store instructions upon function entry and exit,
+ resulting in bigger code size, which in turn makes the build for a
+ few boards fail.
+
+ Use r2 instead.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3c234efa693bc59906c2be55c7918ecbb55392ea
+Author: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
+Date: Wed Jan 30 09:08:49 2008 +0100
+
+ ARM: make the machid configurable via the environment
+
+ If the variable "machid" exists, let do_bootm_linux use that instead
+ of bd->bi_arch_number.
+
+ Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
+
+commit dd24058407c5add45cc60aec6c757ddc1a17e1b0
+Author: Vlad Lungu <vlad@comsys.ro>
+Date: Wed Jan 23 16:34:46 2008 +0200
+
+ Use #ifdef CONFIG_FSLDMAFEC
+
+ MCD_tasks.c lacks [subject] so compilation of mips targets (and more, probably)
+ fails
+
+ Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+
+commit 26c7bab81e08dc7bd696c48f753428a829629bd8
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Jan 19 10:25:59 2008 +0900
+
+ common/miiphyutil.c: Cleanup MII_DEBUG and debug()
+
+ Current MII_DEBUG is confusing in two ways. One is useless define-then-
+ undef at the top of the file. The other is there is only one debug() in
+ this file, and that doesn't seem worthwhile to bother having MII_DEBUG.
+ While there are many useful printf()/puts() debug codes, but they are for
+ DEBUG, not for MII_DEBUG.
+
+ This patch tries to put them all together into MII_DEBUG and debug().
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 751b9b5189f3274b03c809172631316d6b002c82
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Thu Jan 17 16:43:25 2008 +0900
+
+ OneNAND Initial Program Loader (IPL) support
+
+ This patch enables the OneNAND boot within U-Boot.
+ Before this work, we used another OneNAND IPL called X-Loader based
+ on open source. With this work, we can build the oneboot.bin image
+ without other program.
+
+ The build sequence is simple.
+ First, it compiles the u-boot.bin
+ Second, it compiles OneNAND IPL
+ Finally, it becomes the oneboot.bin from OneNAND IPL and u-boot.bin
+ The mechanism is similar with NAND boot except it boots from itself.
+
+ Another thing is that you can only use the OneNAND IPL only to work
+ other bootloader such as RedBoot and so on.
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 21f6f9636f0e978397548751347425fbf8d42bb3
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Jan 16 13:06:59 2008 -0600
+
+ Fix CONFIG_MMC usage in fat code
+
+ A #if statement in fat.c depended on CONFIG_MMC, instead of
+ defined(CONFIG_MMC). This meant CONFIG_MMC needed to be defined
+ as "1" rather than just defined. Now it's better.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit f57d7d364ce189e39b0a64338d2f8012c074a2bd
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Tue Jan 15 12:52:31 2008 +0100
+
+ ppc: Refactor cache routines, so there is only one common set.
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit fe891ecf4d187e9d11dde869ed4623af52b54451
+Author: Hiroshi Ito <ito@mlb.co.jp>
+Date: Thu Jan 31 18:35:04 2008 +0900
+
+ NFS Timeout with large files.
+
+ Retry to send NFS packet before reaching timeout.
+
+ Signed-off-by: Hiroshi Ito <ito@mlb.co.jp>
+
+commit 88f72527f5b89c0905ad5c36cc2ef8d29dd6bbf0
+Author: Johannes Stezenbach <js@sig21.net>
+Date: Tue Jan 29 00:11:25 2008 +0100
+
+ Add dependencies to avoid race conditions with parallel make.
+
+ Signed-off-by: Johannes Stezenbach <js@sig21.net>
+
+commit 6d1b6f9f89c815eaca44acff8e73ece7181f61b6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Jan 28 05:46:01 2008 -0500
+
+ Mark board_init_[fr] as noreturn
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 161b2af4d7b48fd602ce333c355a4df0337892bb
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Jan 28 05:28:50 2008 -0500
+
+ Only use TEXT_BASE if defined by the board
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1b769881750030f10743808b9d6013e11f559350
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Jan 25 07:54:47 2008 +0100
+
+ Fix remaining CONFIG_COMMANDS
+
+ update comments
+ Fix coding style
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0c9d42e6b0b83d507335a291e3ea99240038f4b9
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date: Mon Jan 21 16:46:00 2008 +0100
+
+ Add *~ to .gitignore
+
+ One should never add a backup file ending in with ~ to the git repository.
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 3cfb0c51b2bb5ede54eca85ace5b1ba12be314b0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Jan 17 00:02:10 2008 -0600
+
+ Remove duplicate defines for ARRAY_SIZE
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c77ce474b1c57b13e9d36d9830f147966c143694
+Author: Stelian Pop <stelian@popies.net>
+Date: Mon Jan 14 22:08:14 2008 +0100
+
+ Fix incorrect address test in AT91F_DataflashSelect().
+
+ Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit d9ad115bbf7bb0842de7dbd2502b7e430f83cc3d
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Feb 13 15:09:58 2008 -0600
+
+ Fix building of fdt_support.c if DEBUG set
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c62776be8dca4097ca03d4f9415f08d4887b45d0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Feb 12 00:45:06 2008 +0100
+
+ Get rid of "#undef DEBUG" from board config files.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 73bf1e2de7862bcdbd5a9f993b3e84b67c8ea9c8
+Author: Timur Tabi <timur@freescale.com>
+Date: Tue Jan 15 17:09:41 2008 -0600
+
+ Remove #undef DEBUG from MPC83xx board header files
+
+ Remove the "#undef DEBUG" line from all Freescale 83xx board header files.
+ The inclusion of this line makes it impossible to enable debug code in
+ other source files, because "#define DEBUG" typically needs to be defined
+ before any header files are included.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 69018ce2e086e9caf35b914d675b82bc4888f077
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Jan 17 08:25:45 2008 -0600
+
+ QE: Move FDT support into a common file
+
+ Move the flat device tree setup for QE related devices into
+ a common file shared between 83xx & 85xx platforms that have QE's.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 37e3c62fa07a823e7569c872e3a9395d227ed8e3
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Mon Jan 28 10:15:02 2008 +0100
+
+ ADS5121e: DDR2 init/timing update.
+
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit ac9152830d7fdebace8a260b7737ef2870c21ca0
+Author: John Rigby <jrigby@freescale.com>
+Date: Wed Jan 30 13:36:57 2008 -0700
+
+ Device tree updates
+
+ Changes to match 5121 device tree going mainline in 2.6.25.
+
+ Change OF_SOC from "soc5121" to plain "soc".
+ Remove unneeded "ref-frequency" fixups.
+ Remove "address" enetaddr fixup.
+
+ Add bus-frequency fixup for old OF_SOC so old
+ kernels with old device trees will work with new
+ u-boot with 66MHz IPS clock
+
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit de55d18df3ff2ea614624e74793de7c43520e0e7
+Author: John Rigby <jrigby@freescale.com>
+Date: Wed Jan 30 13:36:56 2008 -0700
+
+ Change IPS freq to 66MHz
+
+ Recommended frequency is 66MHz
+ Change divider from 4 to 3.
+
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit cd9cb62f9d8b78d6c3af5d1e9b5a3d68a3d73974
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Mon Jan 14 22:38:55 2008 +0100
+
+ xsengine: rename board_post_init to board_late_init
+
+ missing migration from "Cleanup of some init functions"
+ in c837dcb1a316745092567bfe4fb266d0941884ff
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8dafa87476b0d7170e219c2f5e3842c833a91807
+Author: Larry Johnson <lrj@acm.org>
+Date: Sat Jan 12 23:35:33 2008 -0500
+
+ Add attribute POST_PREREL to ECC memory POST
+
+ Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit a93907c43f847f076dd0e34ee3b69b5e8e6d0d29
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Jan 18 01:14:03 2008 +0100
+
+ TFTP: add host ip addr support
+
+ allow to use a different server as set in serverip
+ add CONFIG_TFTP_FILE_NAME_MAX_LEN to configure the file name length
+ if not defined the max length will be at 128
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7ec8bb15ee368ea54d48d64867767a704d9ab4c2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Dec 27 10:56:54 2007 +0100
+
+ OMAP5912: fix FIFO handling in UART driver
+
+ According to the OMAP5912 Serial Interfaces Reference Guide (see
+ http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the
+ FIFO_EN enable bit in the FIFO Control Register (FCR) can only be
+ changed when the baud clock is not running, i. e. when both DLL and
+ DLH are set to 0.
+
+ Thus make sure that DLL and DLH are 0 when writing the FCR.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 16158778b5f52f201e95ded2d2d9084b0ed5670d
+Author: Harald Welte <laforge@openmoko.org>
+Date: Wed Dec 19 15:10:52 2007 +0100
+
+ ARM: S3C24x0 SoC NAND controller support
+
+ This patch adds NAND support to the S3C24x0 SoC code in u-boot
+
+ Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit a7c185ed3d9f8ebd85cfc286e1ffee72e4803163
+Author: Harald Welte <laforge@openmoko.org>
+Date: Wed Dec 19 14:24:40 2007 +0100
+
+ ARM: s3c24xx: Multiple serial port support
+
+ This patch adds support for CONFIG_SERIAL_MULTI on s3c24x0 CPU's
+
+ Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit a25f72f1f73a11de68251fb88c89991e202e68fa
+Author: Harald Welte <laforge@openmoko.org>
+Date: Wed Dec 19 14:16:57 2007 +0100
+
+ ARM: arm920t: Allow use of 'gd' pointer from IRQ
+
+ This patch allows us to use the 'gd' pointer (and thus environment
+ and everything else associated with it) from interrupt context on
+ arm920t.
+
+ Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit be19bd5cd0f454b63298844a0b5377e029b2caad
+Author: Harald Welte <laforge@openmoko.org>
+Date: Wed Dec 19 14:19:38 2007 +0100
+
+ ARM: arm920/s3c24xx: IRQ demulitplexer callback
+
+ This patch adds a IRQ demultiplexer callback to the arm920 cpu core code,
+ plus a stub implementation of it for the S3C2410.
+
+ The purpose is to allow arm920t implementations such as the s3c24x0 to
+ implement interrupt handlers in u-boot without having to touch core
+ arm920t code.
+
+ Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit a41dbbd98d201d8aea31b5d21df4742c20cd7eda
+Author: Hebbar <gururajakr@sanyo.co.in>
+Date: Tue Dec 18 16:03:07 2007 -0800
+
+ ARM: Display Ethernet info in do_bdinfo only if CONFIG_CMD_NET is defined
+
+ Add ifdef to bdinfo command to display ethernet information
+ only if CONFIG_CMD_NET is defined for arm modules.
+
+ Signed-off-by: K R Gururaja Hebbar <gururajakr@sanyo.co.in>
+
+commit f7ad79b6f9f0f45437b62e19b45356cc2aaf4884
+Author: Hebbar <gururajakr@sanyo.co.in>
+Date: Tue Dec 18 16:00:54 2007 -0800
+
+ ARM: add I2C init function call in lib_arm/board.c
+
+ Adds I2C init func call to init sequence for ARM boards. This is
+ present in ppc,blackfin and other processor init sequence.
+
+ Signed-off-by: K R Gururaja Hebbar <gururajakr@sanyo.co.in>
+
+commit 4fedfddf97461b88668b9aec774dfb7a0c6dc368
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date: Fri Dec 7 00:42:32 2007 +0100
+
+ ARM: Board voiceblue update
+
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+commit 2c5260f711168d5ee91c70ddbb7d897013eefc46
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date: Thu Dec 6 23:24:57 2007 +0100
+
+ ARM: AT91RM9200 based boards config cleanup
+
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+ Remove nowhere used struct bd_info_ext, remove trailing whitespaces, fix
+ indentation.
+
+commit 481f28b1db5cd21deb55f69399ba240e107af4c7
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date: Thu Dec 6 22:59:16 2007 +0100
+
+ ARM: Fix at91rm9200dk base address
+
+ Somewhere during development of U-Boot-1.1.3 CONFIG_BOOTBINFUNC was
+ renamed into CONFIG_INIT_CRITICAL which was 04 Apr 2005 replaced
+ with CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT.
+ However CONFIG_SKIP_LOWLEVEL_INIT has oposite meaning to
+ CONFIG_BOOTBINFUNC, so fix configuration to reflect this fact.
+ I'm sending this patch 4th (!) time in hope it produces at least some
+ reaction.
+
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+ Fix at91rm9200dk base and environment address.
+
+commit c95219fae2a7add7daa2f91aedca65b1698465c7
+Author: stefano babic <sbabic@denx.de>
+Date: Tue Nov 20 10:40:24 2007 +0100
+
+ MMC for PXA 27X (resubmit)
+
+ MMC support for X_Scale PXA is broken and does not work.
+ Mainly, the mmc_init() function cannot recognize current SD/MMC cards.
+ There were already some patches around the world but none of them was
+ merged into the official u-boot tree.
+
+ This patch makes order fixing this issue. Resubmit after code cleanup.
+
+ Applied and tested on PXA 270 (TrizepsIV module).
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 96bbfa1e6625ce23a150936863b3ecf4c853eb33
+Author: stefano babic <sbabic@denx.de>
+Date: Tue Nov 20 10:37:04 2007 +0100
+
+ Fix gcc issues in pxa-regs.h
+
+ Fix gcc4 issue. With some toolchain, a previous patch that fixes gcc4
+ issues generates wrong code.
+ (Problem was reported with gcc-4.0.2-glibc-2.3.6/arm-softfloat-linux-gnu).
+ This patch fixes the problem and solves the gcc-4 issues as the linux
+ kernel does.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+ Signed-off-by: Dmitry Ivanov <ivadmitry@gmail.com>
+
+commit 7047b388876e7b905b2ec4edb8010543e3641b85
+Author: Jens Gehrlein <sew_s@tqs.de>
+Date: Tue Jan 29 08:45:03 2008 +0100
+
+ TQM834x: enable DHCP
+
+ Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit a877004d44ca7dbc1e618add3eeb1da7c84e4bec
+Author: Jens Gehrlein <sew_s@tqs.de>
+Date: Tue Jan 29 08:45:02 2008 +0100
+
+ TQM834x: support for Spansion N-type Flashes (sector size = 256 KiB at 2x16 Bit).
+
+ Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 8931ab176025b03cfc320b3fd1eca432a88ed560
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Sat Jan 26 23:41:19 2008 -0500
+
+ Fix conditional compilation of mpx8xxx_spi driver
+
+ This driver should only compile if CONFIG_MPC8XXX_SPI is set
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 63f732d3d3880feb531f48af247c025bf01462b0
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Tue Jan 29 17:00:34 2008 +0100
+
+ API: Provide dummy halt() in the glue layer.
+
+ This fixes a demo app link failure on platforms configured with CONFIG_PANIC_HANG.
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 0dc1fc22af86d16993388d9ed9630dbaa2d51826
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Tue Jan 29 16:57:38 2008 +0100
+
+ API: Convert conditional building to the new scheme.
+
+ This fixes a build breakage with CONFIG_API enabled, which appeared after
+ the recent changes in the U-Boot build system.
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 98b742489c09780be6a832eeaa4e5eff824792bb
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Jan 25 09:56:17 2008 +0100
+
+ inka4x0: remove dead code
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 33dac03b1b5d61e4fed7bad445ba40b4c97feba0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 23 14:41:37 2008 +0100
+
+ Coding Style Cleanup; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 865f0f9754b95183cad395de7e8cb85df0c6ea1f
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jan 23 14:31:17 2008 +0100
${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
| tee ${LOG_DIR}/$target.ERR
- ${CROSS_COMPILE:-ppc_8xx-}size ${BUILD_DIR}/u-boot \
+ ${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
| tee -a ${LOG_DIR}/$target.MAKELOG
}
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
LIBS += common/libcommon.a
LIBS += libfdt/libfdt.a
-ifeq ($(CONFIG_API),y)
LIBS += api/libapi.a
-endif
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS)
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
SUBDIRS = tools \
- examples
-
-ifeq ($(CONFIG_API),y)
-SUBDIRS += api_examples
-endif
+ examples \
+ api_examples
.PHONY : $(SUBDIRS)
U_BOOT_NAND = $(obj)u-boot-nand.bin
endif
+ifeq ($(CONFIG_ONENAND_U_BOOT),y)
+ONENAND_IPL = onenand_ipl
+U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
+endif
+
__OBJS := $(subst $(obj),,$(OBJS))
__LIBS := $(subst $(obj),,$(LIBS))
#########################################################################
#########################################################################
-ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
+ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
ifeq ($(ARCH),blackfin)
ALL += $(obj)u-boot.ldr
endif
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
-$(OBJS): $(obj)include/autoconf.mk
+$(OBJS): depend $(obj)include/autoconf.mk
$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
-$(LIBS): $(obj)include/autoconf.mk
+$(LIBS): depend $(obj)include/autoconf.mk
$(MAKE) -C $(dir $(subst $(obj),,$@))
-$(SUBDIRS): $(obj)include/autoconf.mk
+$(SUBDIRS): depend $(obj)include/autoconf.mk
$(MAKE) -C $@ all
$(NAND_SPL): $(VERSION_FILE) $(obj)include/autoconf.mk
$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+$(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk
+ $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
+
+$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
+ cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
+
$(VERSION_FILE):
@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
echo -n "$(U_BOOT_VERSION)" ; \
echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
$(TOPDIR)) ; \
- echo "\"" ) > $(VERSION_FILE)
+ echo "\"" ) > $@.tmp
+ @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
gdbtools:
$(MAKE) -C tools/gdb all || exit 1
versatilepb_config : unconfig
@board/versatile/split_by_variant.sh $@
-voiceblue_smallflash_config \
voiceblue_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/voiceblue
- @if [ "$(findstring _smallflash_,$@)" ] ; then \
- $(XECHO) "... boot from lower flash bank" ; \
- echo "#define VOICEBLUE_SMALL_FLASH" >>$(obj)include/config.h ; \
- echo "VOICEBLUE_SMALL_FLASH=y" >$(obj)board/voiceblue/config.tmp ; \
- else \
- $(XECHO) "... boot from upper flash bank" ; \
- >$(obj)include/config.h ; \
- echo "VOICEBLUE_SMALL_FLASH=n" >$(obj)board/voiceblue/config.tmp ; \
- fi
- @$(MKCONFIG) -a voiceblue arm arm925t voiceblue
+ @$(MKCONFIG) $(@:_config=) arm arm925t voiceblue
cm4008_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cm4008 NULL ks8695
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
apollon_config : unconfig
+ @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+ @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
#========================================================================
# i386
@rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
+ @rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
+ $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
@rm -f $(obj)api_examples/demo $(VERSION_FILE)
clobber: clean
@rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
+ @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f
@[ ! -d $(obj)api_examples ] || find $(obj)api_examples -lname "*" -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
For PowerPC, the following registers have specific use:
R1: stack pointer
- R2: TOC pointer
+ R2: reserved for system use
R3-R4: parameter passing and return values
R5-R10: parameter passing
R13: small data area pointer
(U-Boot also uses R14 as internal GOT pointer.)
- ==> U-Boot will use R29 to hold a pointer to the global data
+ ==> U-Boot will use R2 to hold a pointer to the global data
Note: on PPC, we could use a static initializer (since the
address of the global data structure is known at compile time),
LIB = $(obj)libapi.a
-COBJS = api.o api_net.o api_storage.o api_platform-$(ARCH).o
+COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-all: $(LIB)
-
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
void dev_stor_init(void)
{
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
specs[ENUM_IDE].enum_started = 0;
specs[ENUM_IDE].enum_ended = 0;
specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
specs[ENUM_IDE].name = "ide";
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_USB)
+#if defined(CONFIG_CMD_USB)
specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
specs[ENUM_USB].enum_started = 0;
specs[ENUM_USB].enum_ended = 0;
specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB;
specs[ENUM_USB].name = "usb";
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
+#if defined(CONFIG_CMD_SCSI)
specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
include $(TOPDIR)/config.mk
-ELF += demo
-BIN += demo.bin
+ELF-$(CONFIG_API) += demo
+BIN-$(CONFIG_API) += demo.bin
+ELF := $(ELF-y)
+BIN := $(BIN-y)
#CFLAGS += -v
-COBJS := $(ELF:=.o)
-SOBJS := crt0.o
+COBJS-$(CONFIG_API) += $(ELF:=.o)
+SOBJS-$(CONFIG_API) += crt0.o
ifeq ($(ARCH),ppc)
-SOBJS += ppcstring.o
+SOBJS-$(CONFIG_API) += ppcstring.o
endif
+COBJS := $(COBJS-y)
+SOBJS := $(SOBJS-y)
LIB = $(obj)libglue.a
-LIBCOBJS= glue.o crc32.o ctype.o string.o vsprintf.o libgenwrap.o
+LIBCOBJS-$(CONFIG_API) += glue.o crc32.o ctype.o string.o vsprintf.o \
+ libgenwrap.o
+LIBCOBJS := $(LIBCOBJS-y)
LIBOBJS = $(addprefix $(obj),$(SOBJS) $(LIBCOBJS))
CPPFLAGS += -I..
-all: $(obj).depend $(OBJS) $(LIB) $(BIN) $(ELF)
+all: $(obj).depend $(OBJS) $(LIB) $(ELF) $(BIN)
#########################################################################
$(LIB): $(obj).depend $(LIBOBJS)
ub_reset();
}
-void *malloc(size_t len)
+void *malloc (size_t len)
{
return NULL;
}
+
+void hang (void)
+{
+ while (1) ;
+}
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
- im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
- im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
- im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
- im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
+ im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
+ im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
+ im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
+ im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
- im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
- im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
- im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
- im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
+ im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
+ im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
+ im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
+ im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
/* Initialize MDDRC */
for (i = 0; i < 10; i++)
im->mddrc.ddr_command = CFG_MICRON_NOP;
+ im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+ im->mddrc.ddr_command = CFG_MICRON_NOP;
+ im->mddrc.ddr_command = CFG_MICRON_RFSH;
+ im->mddrc.ddr_command = CFG_MICRON_NOP;
+ im->mddrc.ddr_command = CFG_MICRON_RFSH;
+ im->mddrc.ddr_command = CFG_MICRON_NOP;
+ im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
+ im->mddrc.ddr_command = CFG_MICRON_NOP;
+ im->mddrc.ddr_command = CFG_MICRON_EM2;
+ im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_EM2;
im->mddrc.ddr_command = CFG_MICRON_EM3;
im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
- im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
+ im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
- im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
-
- for (i = 0; i < 10; i++)
- im->mddrc.ddr_command = CFG_MICRON_NOP;
+ im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+ im->mddrc.ddr_command = CFG_MICRON_NOP;
/* Start MDDRC */
im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
void muxSetupGPMC(void)
{
/* gpmc_io_dir, MCR */
- writel(0x4800008C, 0x19000000);
+ volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
+ *MCR = 0x19000000;
/* NOR FLASH CS0 */
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
distclean: clean
- rm -f $(LIB) core config.tmp *.bak .depend
+ rm -f $(LIB) core *.bak .depend
#########################################################################
-#
-# Linux-Kernel is expected to be at 1000'8000,
-# entry 1000'8000 (mem base + reserved)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifeq ($(VOICEBLUE_SMALL_FLASH),y)
-# We load ourself to internal SRAM at 2001'2000
-# Check map file when changing TEXT_BASE.
-# Everything has fit into 192kB internal SRAM!
-TEXT_BASE = 0x20012000
-else
-# Running in SDRAM...
TEXT_BASE = 0x13FD0000
-endif
.word 0x00000000 @ FUNC_MUX_CTRL_3
.word 0x00000000 @ FUNC_MUX_CTRL_4
.word 0x12082480 @ FUNC_MUX_CTRL_5
- .word 0x00000004 @ FUNC_MUX_CTRL_6
+ .word 0x0000001c @ FUNC_MUX_CTRL_6
.word 0x00000003 @ FUNC_MUX_CTRL_7
.word 0x10001200 @ FUNC_MUX_CTRL_8
.word 0x01201012 @ FUNC_MUX_CTRL_9
return 0;
}
-int board_post_init (void)
+int board_late_init (void)
{
setenv ("stdout", "serial");
setenv ("stderr", "serial");
print_num("-> size", bd->bi_dram[i].size);
}
+#if defined(CONFIG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
puts ( "\n"
"ip_addr = ");
print_IPaddr (bd->bi_ip_addr);
+#endif
printf ("\n"
"baudrate = %d bps\n", bd->bi_baudrate);
vu_long *addr, *start, *end;
ulong val;
ulong readback;
+ int rcode = 0;
#if defined(CFG_ALT_MEMTEST)
vu_long addr_mask;
#else
ulong incr;
ulong pattern;
- int rcode = 0;
#endif
if (argc > 1) {
}
incr = -incr;
}
- return rcode;
#endif
+ return rcode;
}
U_BOOT_CMD(
tftpboot, 3, 1, do_tftpb,
"tftpboot- boot image via network using TFTP protocol\n",
- "[loadAddress] [bootfilename]\n"
+ "[loadAddress] [[hostIPaddr:]bootfilename]\n"
);
int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#include <fdt_support.h>
#include <exports.h>
-#ifdef CONFIG_QE
-#include "../drivers/qe/qe.h"
-#endif
/*
* Global data (for the gd->bd)
*/
{
#if defined(DEBUG)
int i;
- debug("Updating property '%s/%s' = ", node, prop);
+ debug("Updating property '%s/%s' = ", path, prop);
for (i = 0; i < len; i++)
debug(" %.2x", *(u8*)(val+i));
debug("\n");
int off;
#if defined(DEBUG)
int i;
- debug("Updating property '%s/%s' = ", node, prop);
+ debug("Updating property '%s' = ", prop);
for (i = 0; i < len; i++)
debug(" %.2x", *(u8*)(val+i));
debug("\n");
int off = -1;
#if defined(DEBUG)
int i;
- debug("Updating property '%s/%s' = ", node, prop);
+ debug("Updating property '%s' = ", prop);
for (i = 0; i < len; i++)
debug(" %.2x", *(u8*)(val+i));
debug("\n");
#endif
}
}
-
-#ifdef CONFIG_QE
-/*
- * If a QE firmware has been uploaded, then add the 'firmware' node under
- * the 'qe' node.
- */
-void fdt_fixup_qe_firmware(void *fdt)
-{
- struct qe_firmware_info *qe_fw_info;
- int node, ret;
-
- qe_fw_info = qe_get_firmware_info();
- if (!qe_fw_info)
- return;
-
- node = fdt_path_offset(fdt, "/qe");
- if (node < 0)
- return;
-
- /* We assume the node doesn't exist yet */
- node = fdt_add_subnode(fdt, node, "firmware");
- if (node < 0)
- return;
-
- ret = fdt_setprop(fdt, node, "extended-modes",
- &qe_fw_info->extended_modes, sizeof(u64));
- if (ret < 0)
- goto error;
-
- ret = fdt_setprop_string(fdt, node, "id", qe_fw_info->id);
- if (ret < 0)
- goto error;
-
- ret = fdt_setprop(fdt, node, "virtual-traps", qe_fw_info->vtraps,
- sizeof(qe_fw_info->vtraps));
- if (ret < 0)
- goto error;
-
- return;
-
-error:
- fdt_del_node(fdt, node);
-}
-#endif
-
#endif
#include <net.h>
/* local debug macro */
-#define MII_DEBUG
#undef MII_DEBUG
#undef debug
unsigned short tmp;
if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
-#ifdef DEBUG
- puts ("PHY ID register 2 read failed\n");
-#endif
+ debug ("PHY ID register 2 read failed\n");
return (-1);
}
reg = tmp;
-#ifdef DEBUG
- printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
-#endif
+ debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
+
if (reg == 0xFFFF) {
/* No physical device present at this address */
return (-1);
}
if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
-#ifdef DEBUG
- puts ("PHY ID register 1 read failed\n");
-#endif
+ debug ("PHY ID register 1 read failed\n");
return (-1);
}
reg |= tmp << 16;
-#ifdef DEBUG
- printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
-#endif
+ debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
+
*oui = (reg >> 10);
*model = (unsigned char)((reg >> 4) & 0x0000003F);
*rev = (unsigned char)(reg & 0x0000000F);
int loop_cnt;
if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
-#ifdef DEBUG
- printf ("PHY status read failed\n");
-#endif
+ debug ("PHY status read failed\n");
return (-1);
}
if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
-#ifdef DEBUG
- puts ("PHY reset failed\n");
-#endif
+ debug ("PHY reset failed\n");
return (-1);
}
#ifdef CONFIG_PHY_RESET_DELAY
reg = 0x8000;
while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
-# ifdef DEBUG
- puts ("PHY status read failed\n");
-# endif
+ debug ("PHY status read failed\n");
return (-1);
}
}
#else
return &serial0_device;
#endif
+#elif defined(CONFIG_S3C2410)
+#if defined(CONFIG_SERIAL1)
+ return &s3c24xx_serial0_device;
+#elif defined(CONFIG_SERIAL2)
+ return &s3c24xx_serial1_device;
+#elif defined(CONFIG_SERIAL3)
+ return &s3c24xx_serial2_device;
+#else
+#error "CONFIG_SERIAL? missing."
+#endif
#else
#error No default console
#endif
#endif
#if defined (CONFIG_STUART)
serial_register(&serial_stuart_device);
+#endif
+#if defined(CONFIG_S3C2410)
+ serial_register(&s3c24xx_serial0_device);
+ serial_register(&s3c24xx_serial1_device);
+ serial_register(&s3c24xx_serial2_device);
#endif
serial_assign (default_serial_console ()->name);
}
gccincdir := $(shell $(CC) -print-file-name=include)
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
- -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
+ -D__KERNEL__
+ifneq ($(TEXT_BASE),)
+CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+endif
ifneq ($(OBJTREE),$(SRCTREE))
CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
-LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS)
+ifneq ($(TEXT_BASE),)
+LDFLAGS += -Ttext $(TEXT_BASE)
+endif
# Location of a usable BFD library, where we define "usable" as
# "built for ${HOST}, supports ${TARGET}". Sensible values are
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
-PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring
+PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring
#endif
.globl _start
_start: b reset
+#ifdef CONFIG_ONENAND_IPL
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+
+_hang:
+ .word do_hang
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678 /* now 16*4=64 */
+#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
+#endif /* CONFIG_ONENAND_IPL */
.global _end_vect
_end_vect:
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
+#ifndef CONFIG_ONENAND_IPL
beq stack_setup
+#endif /* CONFIG_ONENAND_IPL */
ldr r2, _armboot_start
ldr r3, _bss_start
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+#ifdef CONFIG_ONENAND_IPL
+ sub sp, r0, #128 /* leave 32 words for abort-stack */
+#else
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
+#endif /* CONFIG_ONENAND_IPL */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
+#ifndef CONFIG_ONENAND_IPL
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
bne clbss_l
+#endif
ldr pc, _start_armboot
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
_start_armboot: .word start_armboot
+#endif
/*
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
+
+#ifndef CONFIG_ONENAND_IPL
/*
*************************************************************************
*
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
+#endif /* CONFIG_ONENAND_IPL */
/*
* exception handlers
*/
+#ifdef CONFIG_ONENAND_IPL
+ .align 5
+do_hang:
+ ldr sp, _TEXT_BASE /* use 32 words about stack */
+ bl hang /* hang and never return */
+#else /* !CONFIG_ONENAND IPL */
.align 5
undefined_instruction:
get_bad_stack
.word PM_RSTCTRL_WKUP
#endif
+#endif /* CONFIG_ONENAND_IPL */
void do_irq (struct pt_regs *pt_regs)
{
-#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR)
+#if defined (CONFIG_USE_IRQ)
+#if defined (ARM920_IRQ_CALLBACK)
+ ARM920_IRQ_CALLBACK();
+ return;
+#elif defined (CONFIG_ARCH_INTEGRATOR)
/* ASSUMED to be a timer interrupt */
/* Just clear it - count handled in */
/* integratorap.c */
*(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
+#endif /* ARCH_INTEGRATOR */
#else
printf ("interrupt request\n");
show_regs (pt_regs);
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
- usb.o usb_ohci.o
+ usb.o usb_ohci.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
/*NOTREACHED*/
}
+#ifdef CONFIG_USE_IRQ
+void s3c2410_irq(void)
+{
+ S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
+ u_int32_t intpnd = irq->INTPND;
+
+}
+#endif /* USE_IRQ */
+
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
--- /dev/null
+/*
+ * (C) Copyright 2006 OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if 0
+#define DEBUGN printf
+#else
+#define DEBUGN(x, args ...) {}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+#if !defined(CFG_NAND_LEGACY)
+
+#include <nand.h>
+#include <s3c2410.h>
+
+#define __REGb(x) (*(volatile unsigned char *)(x))
+#define __REGi(x) (*(volatile unsigned int *)(x))
+
+#define NF_BASE 0x4e000000
+#define NFCONF __REGi(NF_BASE + 0x0)
+#define NFCMD __REGb(NF_BASE + 0x4)
+#define NFADDR __REGb(NF_BASE + 0x8)
+#define NFDATA __REGb(NF_BASE + 0xc)
+#define NFSTAT __REGb(NF_BASE + 0x10)
+#define NFECC0 __REGb(NF_BASE + 0x14)
+#define NFECC1 __REGb(NF_BASE + 0x15)
+#define NFECC2 __REGb(NF_BASE + 0x16)
+
+#define S3C2410_NFCONF_EN (1<<15)
+#define S3C2410_NFCONF_512BYTE (1<<14)
+#define S3C2410_NFCONF_4STEP (1<<13)
+#define S3C2410_NFCONF_INITECC (1<<12)
+#define S3C2410_NFCONF_nFCE (1<<11)
+#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
+
+static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ DEBUGN("hwcontrol(): 0x%02x: ", cmd);
+
+ switch (cmd) {
+ case NAND_CTL_SETNCE:
+ NFCONF &= ~S3C2410_NFCONF_nFCE;
+ DEBUGN("NFCONF=0x%08x\n", NFCONF);
+ break;
+ case NAND_CTL_CLRNCE:
+ NFCONF |= S3C2410_NFCONF_nFCE;
+ DEBUGN("NFCONF=0x%08x\n", NFCONF);
+ break;
+ case NAND_CTL_SETALE:
+ chip->IO_ADDR_W = NF_BASE + 0x8;
+ DEBUGN("SETALE\n");
+ break;
+ case NAND_CTL_SETCLE:
+ chip->IO_ADDR_W = NF_BASE + 0x4;
+ DEBUGN("SETCLE\n");
+ break;
+ default:
+ chip->IO_ADDR_W = NF_BASE + 0xc;
+ break;
+ }
+ return;
+}
+
+static int s3c2410_dev_ready(struct mtd_info *mtd)
+{
+ DEBUGN("dev_ready\n");
+ return (NFSTAT & 0x01);
+}
+
+#ifdef CONFIG_S3C2410_NAND_HWECC
+void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd ,mode);
+ NFCONF |= S3C2410_NFCONF_INITECC;
+}
+
+static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+ u_char *ecc_code)
+{
+ ecc_code[0] = NFECC0;
+ ecc_code[1] = NFECC1;
+ ecc_code[2] = NFECC2;
+ DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
+ mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
+
+ return 0;
+}
+
+static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ if (read_ecc[0] == calc_ecc[0] &&
+ read_ecc[1] == calc_ecc[1] &&
+ read_ecc[2] == calc_ecc[2])
+ return 0;
+
+ printf("s3c2410_nand_correct_data: not implemented\n");
+ return -1;
+}
+#endif
+
+int board_nand_init(struct nand_chip *nand)
+{
+ u_int32_t cfg;
+ u_int8_t tacls, twrph0, twrph1;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+
+ DEBUGN("board_nand_init()\n");
+
+ clk_power->CLKCON |= (1 << 4);
+
+ /* initialize hardware */
+ twrph0 = 3; twrph1 = 0; tacls = 0;
+
+ cfg = S3C2410_NFCONF_EN;
+ cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
+ cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
+ cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
+
+ NFCONF = cfg;
+
+ /* initialize nand_chip data structure */
+ nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c;
+
+ /* read_buf and write_buf are default */
+ /* read_byte and write_byte are default */
+
+ /* hwcontrol always must be implemented */
+ nand->hwcontrol = s3c2410_hwcontrol;
+
+ nand->dev_ready = s3c2410_dev_ready;
+
+#ifdef CONFIG_S3C2410_NAND_HWECC
+ nand->enable_hwecc = s3c2410_nand_enable_hwecc;
+ nand->calculate_ecc = s3c2410_nand_calculate_ecc;
+ nand->correct_data = s3c2410_nand_correct_data;
+ nand->eccmode = NAND_ECC_HW3_512;
+#else
+ nand->eccmode = NAND_ECC_SOFT;
+#endif
+
+#ifdef CONFIG_S3C2410_NAND_BBT
+ nand->options = NAND_USE_FLASH_BBT;
+#else
+ nand->options = 0;
+#endif
+
+ DEBUGN("end of nand_init\n");
+
+ return 0;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for S3C2410"
+#endif
+#endif
#error "Bad: you didn't configure serial ..."
#endif
-void serial_setbrg (void)
+#if defined(CONFIG_SERIAL_MULTI)
+#include <serial.h>
+
+/* Multi serial device functions */
+#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \
+ int s3serial##port##_init (void) {\
+ return serial_init_dev(port);}\
+ void s3serial##port##_setbrg (void) {\
+ serial_setbrg_dev(port);}\
+ int s3serial##port##_getc (void) {\
+ return serial_getc_dev(port);}\
+ int s3serial##port##_tstc (void) {\
+ return serial_tstc_dev(port);}\
+ void s3serial##port##_putc (const char c) {\
+ serial_putc_dev(port, c);}\
+ void s3serial##port##_puts (const char *s) {\
+ serial_puts_dev(port, s);}
+
+#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\
+ name,\
+ bus,\
+ s3serial##port##_init,\
+ s3serial##port##_setbrg,\
+ s3serial##port##_getc,\
+ s3serial##port##_tstc,\
+ s3serial##port##_putc,\
+ s3serial##port##_puts, }
+
+#endif /* CONFIG_SERIAL_MULTI */
+
+void _serial_setbrg(const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
- int i;
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
unsigned int reg = 0;
+ int i;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
+ uart->UBRDIV = reg;
+ for (i = 0; i < 100; i++);
+}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_setbrg_dev(unsigned int dev_index)
+{
+ _serial_setbrg(dev_index);
+}
+#else
+void serial_setbrg(void)
+{
+ _serial_setbrg(UART_NR);
+}
+#endif
+
+
+/* Initialise the serial port. The settings are always 8 data bits, no parity,
+ * 1 stop bit, no start bits.
+ */
+static int serial_init_dev(const int dev_index)
+{
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
+ int i;
+
/* FIFO enable, Tx/Rx FIFO clear */
uart->UFCON = 0x07;
uart->UMCON = 0x0;
+
/* Normal,No parity,1 stop,8 bit */
uart->ULCON = 0x3;
/*
* normal,interrupt or polling
*/
uart->UCON = 0x245;
- uart->UBRDIV = reg;
#ifdef CONFIG_HWFLOW
uart->UMCON = 0x1; /* RTS up */
#endif
- for (i = 0; i < 100; i++);
+
+ /* FIXME: This is sooooooooooooooooooo ugly */
+#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
+ /* we need auto hw flow control on the gsm and gps port */
+ if (dev_index == 0 || dev_index == 1)
+ uart->UMCON = 0x10;
+#endif
+ _serial_setbrg(dev_index);
+
+ return (0);
}
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
+#if !defined(CONFIG_SERIAL_MULTI)
+/* Initialise the serial port. The settings are always 8 data bits, no parity,
+ * 1 stop bit, no start bits.
*/
int serial_init (void)
{
- serial_setbrg ();
-
- return (0);
+ return serial_init_dev(UART_NR);
}
+#endif
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+int _serial_getc (const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
/* wait for character to arrive */
while (!(uart->UTRSTAT & 0x1));
return uart->URXH & 0xff;
}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int serial_getc_dev(unsigned int dev_index)
+{
+ return _serial_getc(dev_index);
+}
+#else
+int serial_getc (void)
+{
+ return _serial_getc(UART_NR);
+}
+#endif
#ifdef CONFIG_HWFLOW
static int hwflow = 0; /* turned off by default */
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+void _serial_putc (const char c, const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
if (c == '\n')
serial_putc ('\r');
}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void serial_putc_dev(unsigned int dev_index, const char c)
+{
+ _serial_putc(c, dev_index);
+}
+#else
+void serial_putc(const char c)
+{
+ _serial_putc(c, UART_NR);
+}
+#endif
+
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc (void)
+int _serial_tstc(const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
return uart->UTRSTAT & 0x1;
}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_tstc_dev(unsigned int dev_index)
+{
+ return _serial_tstc(dev_index);
+}
+#else
+int serial_tstc(void)
+{
+ return _serial_tstc(UART_NR);
+}
+#endif
-void
-serial_puts (const char *s)
+void _serial_puts(const char *s, const int dev_index)
{
while (*s) {
- serial_putc (*s++);
+ _serial_putc (*s++, dev_index);
}
}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_puts_dev(int dev_index, const char *s)
+{
+ _serial_puts(s, dev_index);
+}
+#else
+void
+serial_puts (const char *s)
+{
+ _serial_puts(s, UART_NR);
+}
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+DECLARE_S3C_SERIAL_FUNCTIONS(0);
+struct serial_device s3c24xx_serial0_device =
+ INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1");
+DECLARE_S3C_SERIAL_FUNCTIONS(1);
+struct serial_device s3c24xx_serial1_device =
+ INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2");
+DECLARE_S3C_SERIAL_FUNCTIONS(2);
+struct serial_device s3c24xx_serial2_device =
+ INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3");
+
+#endif /* CONFIG_SERIAL_MULTI */
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
+ add r7, sp, #S_PC
+ stmdb r7, {sp, lr}^ @ Calling SP, LR
+ str lr, [r7, #0] @ Save calling PC
mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
+ str r6, [r7, #4] @ Save CPSR
+ str r0, [r7, #8] @ Save OLD_R0
mov r0, sp
.endm
#define omap_readw(x) *(volatile unsigned short *)(x)
#define omap_readl(x) *(volatile unsigned long *)(x)
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
#define OMAP_DIE_ID_0 0xfffe1800
#define OMAP_DIE_ID_1 0xfffe1804
#define OMAP_PRODUCTION_ID_0 0xfffe2000
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
- -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e
+ -ffixed-r2 -msoft-float -mcpu=603e
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_path_u32(blob, cpu_path, "ref-frequency", CFG_MPC512X_CLKIN, 1);
do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1);
- do_fixup_by_path_u32(blob, "/" OF_SOC, "ref-frequency", CFG_MPC512X_CLKIN, 1);
- do_fixup_by_path(blob, eth_path, "address", bd->bi_enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
+
+ /* this is so old kernels with old device trees will boot */
+ do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);
}
#endif
mfspr r3, PVR
blr
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbf */
-/* Description: Data Cache block flush */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbf
-ppcDcbf:
- dcbf r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbi */
-/* Description: Data Cache block Invalidate */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbi
-ppcDcbi:
- dcbi r0,r3
- blr
-
-/*--------------------------------------------------------------------------
- * Function: ppcDcbz
- * Description: Data Cache block zero.
- * Input: r3 = effective address
- * Output: none.
- *-------------------------------------------------------------------------- */
-
- .globl ppcDcbz
-ppcDcbz:
- dcbz r0,r3
- blr
-
- .globl ppcDWstore
-ppcDWstore:
- lfd 1, 0(r4)
- stfd 1, 0(r3)
- blr
-
- .globl ppcDWload
-ppcDWload:
- lfd 1, 0(r3)
- stfd 1, 0(r4)
- blr
-
/*-------------------------------------------------------------------*/
/*
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
-PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \
+PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
- -ffixed-r2 -ffixed-r29 -msoft-float
+ -ffixed-r2 -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds
#include <libfdt.h>
#include <fdt_support.h>
+extern void ft_qe_setup(void *blob);
+
DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
#ifdef CONFIG_QE
- do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
- "bus-frequency", gd->qe_clk, 1);
- do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
- "brg-frequency", gd->brg_clk, 1);
- do_fixup_by_compat_u32(blob, "fsl,qe",
- "clock-frequency", gd->qe_clk, 1);
- do_fixup_by_compat_u32(blob, "fsl,qe",
- "bus-frequency", gd->qe_clk, 1);
- do_fixup_by_compat_u32(blob, "fsl,qe",
- "brg-frequency", gd->brg_clk, 1);
+ ft_qe_setup(blob);
#endif
#ifdef CFG_NS16550
mfspr r3, PVR
blr
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbf */
-/* Description: Data Cache block flush */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbf
-ppcDcbf:
- dcbf r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbi */
-/* Description: Data Cache block Invalidate */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbi
-ppcDcbi:
- dcbi r0,r3
- blr
-
-/*--------------------------------------------------------------------------
- * Function: ppcDcbz
- * Description: Data Cache block zero.
- * Input: r3 = effective address
- * Output: none.
- *-------------------------------------------------------------------------- */
-
- .globl ppcDcbz
-ppcDcbz:
- dcbz r0,r3
- blr
-
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float -mno-string
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \
+ -Wa,-me500 -msoft-float -mno-string
#include <libfdt.h>
#include <fdt_support.h>
+extern void ft_qe_setup(void *blob);
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
#ifdef CONFIG_QE
- do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
- "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
- "brg-frequency", bd->bi_busfreq / 2, 1);
- fdt_fixup_qe_firmware(blob);
+ ft_qe_setup(blob);
#endif
#ifdef CFG_NS16550
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
+ gd->i2c1_clk = sys_info.freqSystemBus;
+ gd->i2c2_clk = sys_info.freqSystemBus;
+
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
lwbrx r3,r0,r3
blr
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbf */
-/* Description: Data Cache block flush */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbf
-ppcDcbf:
- dcbf r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbi */
-/* Description: Data Cache block Invalidate */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbi
-ppcDcbi:
- dcbi r0,r3
- blr
-
-/*--------------------------------------------------------------------------
- * Function: ppcDcbz
- * Description: Data Cache block zero.
- * Input: r3 = effective address
- * Output: none.
- *-------------------------------------------------------------------------- */
-
- .globl ppcDcbz
-ppcDcbz:
- dcbz r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcSync */
-/* Description: Processor Synchronize */
-/* Input: none. */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcSync
-ppcSync:
- sync
- blr
-
/*------------------------------------------------------------------------------*/
/*
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -mstring
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
+ gd->i2c1_clk = sys_info.freqSystemBus;
+ gd->i2c2_clk = sys_info.freqSystemBus;
if (gd->cpu_clk != 0)
return 0;
lwbrx r3,r0,r3
blr
-/*
- * Function: ppcDcbf
- * Description: Data Cache block flush
- * Input: r3 = effective address
- * Output: none.
- */
- .globl ppcDcbf
-ppcDcbf:
- dcbf r0,r3
- blr
-
-/*
- * Function: ppcDcbi
- * Description: Data Cache block Invalidate
- * Input: r3 = effective address
- * Output: none.
- */
- .globl ppcDcbi
-ppcDcbi:
- dcbi r0,r3
- blr
-
-/*
- * Function: ppcDcbz
- * Description: Data Cache block zero.
- * Input: r3 = effective address
- * Output: none.
- */
- .globl ppcDcbz
-ppcDcbz:
- dcbz r0,r3
- blr
-
-/*
- * Function: ppcSync
- * Description: Processor Synchronize
- * Input: none.
- * Output: none.
- */
- .globl ppcSync
-ppcSync:
- sync
- blr
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
- mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
+ mr r2, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
-PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
-PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
lwbrx r3,r0,r3
blr
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbf */
-/* Description: Data Cache block flush */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbf
-ppcDcbf:
- dcbf r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbi */
-/* Description: Data Cache block Invalidate */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbi
-ppcDcbi:
- dcbi r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcSync */
-/* Description: Processor Synchronize */
-/* Input: none. */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcSync
-ppcSync:
- sync
- blr
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
2. The pointer to the jump table is passed to the application in a
machine-dependent way. PowerPC, ARM, MIPS and Blackfin architectures
use a dedicated register to hold the pointer to the 'global_data'
- structure: r29 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin.
- The x86 architecture does not use such a register; instead, the pointer
- to the 'global_data' structure is passed as 'argv[-1]' pointer.
+ structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin.
+ The x86 architecture does not use such a register; instead, the
+ pointer to the 'global_data' structure is passed as 'argv[-1]'
+ pointer.
The application can access the 'global_data' structure in the same
way as U-Boot does:
/* Contains task code and structures for Multi-channel DMA */
+#include <common.h>
+
+#ifdef CONFIG_FSLDMAFEC
+
#include <MCD_dma.h>
u32 MCD_varTab0[];
#ifdef MCD_INCLUDE_EU
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#endif
+
+#endif /* CONFIG_FSLDMAFEC */
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++)
if ( dataflash_info[i].id
- && ((((int) addr) & 0xFF000000) ==
+ && ((((int) *addr) & 0xFF000000) ==
dataflash_info[i].logical_address)) {
addr_valid = 1;
break;
#endif
};
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-
static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
{
int i,j;
addr[0], addr[1],
addr[2], addr[3],
addr[4], addr[5]) ;
- debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr);
+ debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr);
setenv ("ethaddr", ethaddr);
}
return 0;
}
-#endif /* COMMANDS & CFG_NET */
+#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_CS8900 */
* AUI/TP selection ( mine has 10Base2/10BaseT select )
*
* Arguments:
- * io = for the base address
+ * io = for the base address
* irq = for the IRQ
*
* author:
- * Erik Stahlman ( erik@vt.edu )
- * Daris A Nevil ( dnevil@snmc.com )
+ * Erik Stahlman ( erik@vt.edu )
+ * Daris A Nevil ( dnevil@snmc.com )
*
*
* Hardware multicast code from Peter Cammaert ( pc@denkart.be )
* o lan91c96.c (Intel Diagnostic Manager driver)
*
* History:
- * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version)
+ * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version)
* for lan91c96
*---------------------------------------------------------------------------
*/
/*
* Function: smc_reset( void )
* Purpose:
- * This sets the SMC91111 chip to its normal state, hopefully from whatever
- * mess that any other DOS driver has put it in.
+ * This sets the SMC91111 chip to its normal state, hopefully from whatever
+ * mess that any other DOS driver has put it in.
*
* Maybe I should reset more registers to defaults in here? SOFTRST should
* do that for me.
* This sends the actual packet to the SMC9xxx chip.
*
* Algorithm:
- * First, see if a saved_skb is available.
+ * First, see if a saved_skb is available.
* ( this should NOT be called if there is no 'saved_skb'
* Now, find the packet number that the chip allocated
* Point the data pointers at it in memory
* Dump the packet to chip memory
* Check if a last byte is needed ( odd length packet )
* if so, set the control flag right
- * Tell the card to send it
+ * Tell the card to send it
* Enable the transmit interrupt, so I know if it failed
- * Free the kernel data if I actually sent it.
+ * Free the kernel data if I actually sent it.
*/
static int smc_send_packet (volatile void *packet, int packet_length)
{
}
#endif /* 0 */
-#endif /* COMMANDS & CFG_NET */
+#endif /* CONFIG_CMD_NET */
/* smc_get_ethaddr (bd_t * bd)
#include "netarm_eth.h"
#include <asm/arch/netarm_registers.h>
-
#if defined(CONFIG_CMD_NET)
static int na_mii_poll_busy (void);
setenv ("ethaddr", ethaddr);
}
-
static void na_mii_write (int reg, int value)
{
int mii_addr;
return 1;
}
-#endif /* COMMANDS & CFG_NET */
+#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_NETARMETH */
#if defined(CONFIG_CMD_NET)
-
/* packet page register access functions */
-
static unsigned char get_reg (unsigned int regno)
{
return (*(unsigned char *) regno);
}
-
static void put_reg (unsigned int regno, unsigned char val)
{
*(volatile unsigned char *) regno = val;
put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
}
-
void eth_halt (void)
{
put_reg (RTL8019_COMMAND, 0x01);
return 0;
}
-
static unsigned char nic_to_pc (void)
{
unsigned char rec_head_status;
return 0;
}
-#endif /* COMMANDS & CFG_NET */
+#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_RTL8019 */
return value;
}
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
static int rtl8169_init_board(struct eth_device *dev)
{
int i;
LIB := $(obj)qe.a
-COBJS := qe.o uccf.o uec.o uec_phy.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS := qe.o uccf.o uec.o uec_phy.o $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "qe.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * If a QE firmware has been uploaded, then add the 'firmware' node under
+ * the 'qe' node.
+ */
+void fdt_fixup_qe_firmware(void *blob)
+{
+ struct qe_firmware_info *qe_fw_info;
+ int node, ret;
+
+ qe_fw_info = qe_get_firmware_info();
+ if (!qe_fw_info)
+ return;
+
+ node = fdt_path_offset(blob, "/qe");
+ if (node < 0)
+ return;
+
+ /* We assume the node doesn't exist yet */
+ node = fdt_add_subnode(blob, node, "firmware");
+ if (node < 0)
+ return;
+
+ ret = fdt_setprop(blob, node, "extended-modes",
+ &qe_fw_info->extended_modes, sizeof(u64));
+ if (ret < 0)
+ goto error;
+
+ ret = fdt_setprop_string(blob, node, "id", qe_fw_info->id);
+ if (ret < 0)
+ goto error;
+
+ ret = fdt_setprop(blob, node, "virtual-traps", qe_fw_info->vtraps,
+ sizeof(qe_fw_info->vtraps));
+ if (ret < 0)
+ goto error;
+
+ return;
+
+error:
+ fdt_del_node(blob, node);
+}
+
+void ft_qe_setup(void *blob)
+{
+#ifdef CONFIG_QE
+ do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
+ "bus-frequency", gd->qe_clk, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
+ "brg-frequency", gd->brg_clk, 1);
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "clock-frequency", gd->qe_clk, 1);
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "bus-frequency", gd->qe_clk, 1);
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "brg-frequency", gd->brg_clk, 1);
+ fdt_fixup_qe_firmware(blob);
+#endif
+}
int qe_set_mii_clk_src(int ucc_num);
int qe_upload_firmware(const struct qe_firmware *firmware);
struct qe_firmware_info *qe_get_firmware_info(void);
+void ft_qe_setup(void *blob);
#endif /* __QE_H__ */
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
}
-
/*
* Set the RTC
*/
rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
}
-
/*
* Reset the RTC. We setting the date back to 1970-01-01.
*/
return;
}
-
/*
* Helper functions
*/
return (((n / 10) << 4) | (n % 10));
}
-#endif /* CONFIG_RTC_RX8025 && (CFG_COMMANDS & CFG_CMD_DATE) */
+#endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */
com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
#endif
com_port->lcr = LCR_BKSE | LCRVAL;
- com_port->dll = baud_divisor & 0xff;
- com_port->dlm = (baud_divisor >> 8) & 0xff;
+ com_port->dll = 0;
+ com_port->dlm = 0;
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
+ com_port->lcr = LCR_BKSE | LCRVAL;
+ com_port->dll = baud_divisor & 0xff;
+ com_port->dlm = (baud_divisor >> 8) & 0xff;
+ com_port->lcr = LCRVAL;
#if defined(CONFIG_OMAP)
#if defined(CONFIG_APTIX)
com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE | LCRVAL;
+ com_port->dll = 0;
+ com_port->dlm = 0;
+ com_port->lcr = LCRVAL;
+ com_port->mcr = MCRVAL;
+ com_port->fcr = FCRVAL;
com_port->lcr = LCR_BKSE;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
- com_port->mcr = MCRVAL;
- com_port->fcr = FCRVAL;
}
void NS16550_putc (NS16550_t com_port, char c)
*/
#include <common.h>
+#if defined(CONFIG_MPC8XXX_SPI) && defined(CONFIG_HARD_SPI)
+
#include <spi.h>
#include <asm/mpc8xxx_spi.h>
-#ifdef CONFIG_HARD_SPI
-
#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
: : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx");
#elif defined(CONFIG_PPC)
/*
- * r29 holds the pointer to the global_data, r11 is a call-clobbered
+ * r2 holds the pointer to the global_data, r11 is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
-" lwz %%r11, %0(%%r29)\n" \
+" lwz %%r11, %0(%%r2)\n" \
" lwz %%r11, %1(%%r11)\n" \
" mtctr %%r11\n" \
" bctr\n" \
* we can load the instruction and data TLB registers with the
* same values.
*/
- lwz r9,20(r29) /* gd->ram_size */
+ lwz r9,20(r2) /* gd->ram_size */
addis r9,r9,-0x80
mr r8, r9 /* Higher 8 Meg in SDRAM */
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
-" lwz %%r11, %0(%%r29)\n" \
+" lwz %%r11, %0(%%r2)\n" \
" lwz %%r11, %1(%%r11)\n" \
" mtctr %%r11\n" \
" bctr\n" \
- : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r29");
+ : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r2");
#elif defined(__arm__)
#define EXPORT_FUNC(x) \
asm volatile ( \
#if defined(__i386__)
xxx_t *pq;
#elif defined(__powerpc__)
- register volatile xxx_t *pq asm("r29");
+ register volatile xxx_t *pq asm("r2");
#elif defined(__arm__)
register volatile xxx_t *pq asm("r8");
#elif defined(__mips__)
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
- (CONFIG_MMC)
+ defined(CONFIG_MMC)
printf("Interface: ");
switch(cur_dev->if_type) {
case IF_TYPE_IDE : printf("IDE"); break;
u32 sdhc_clk;
#endif
u32 core_clk;
- u32 i2c1_clk;
- u32 i2c2_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ u32 i2c1_clk;
+ u32 i2c2_clk;
+#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#if 1
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r29")
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
#else /* We could use plain global data, but the resulting code is bigger */
#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
#define HIZCRA 0xA4050158
#define HIZCRB 0xA405015A
#define HIZCRC 0xA405015C
-#define MSELCR 0xA405015C
-#define PULCR 0xA405015E
-#define DRVCR 0xA4050180
-#define SBSCR 0xA4050182
-#define AUDTHCR 0xA4050184
-#define PSELF 0xA4050186
+#define HIZCRC 0xA405015C
+#define MSELCRA 0xA4050180
+#define MSELCRB 0xA4050182
+#define PULCR 0xA4050184
+#define SBSCR 0xA4050186
+#define DRVCR 0xA405018A
/* I/O Port */
#define PADR 0xA4050120
void reset_cmd_timeout(void);
/* lib_$(ARCH)/board.c */
-void board_init_f (ulong);
-void board_init_r (gd_t *, ulong);
+void board_init_f (ulong) __attribute__ ((noreturn));
+void board_init_r (gd_t *, ulong) __attribute__ ((noreturn));
int checkboard (void);
int checkflash (void);
int checkdram (void);
ulong get_PCI_freq (void);
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X)
+void s3c2410_irq(void);
+#define ARM920_IRQ_CALLBACK s3c2410_irq
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
#endif /* __COMMON_H_ */
* (easy to change)
*/
-#undef DEBUG
-
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
/*
#define CONFIG_EB_MCF_EV123
-#undef DEBUG
#undef CFG_HALT_BEFOR_RAM_JUMP
-#undef ET_DEBUG
/*
* High Level Configuration Options (easy to change)
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG /* General debug */
-
/*-----------------------------------------------------------------------
* High Level Configuration Options
* (easy to change)
#define CONFIG_M52277 /* define processor type */
#define CONFIG_M52277EVB /* M52277EVB board */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_MCF523x /* define processor family */
#define CONFIG_M5235 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#ifndef _M5271EVB_H
#define _M5271EVB_H
-#undef DEBUG
-
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5329 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5373 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#define CFG_I2C2_OFFSET 0x3100
/* SPI */
+#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI /* SPI with hardware support */
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#define INTEL_LXT971_PHY 1
#endif
-#undef DEBUG
-
/* Environment */
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define ERR_LED(code)
#endif
-#undef DEBUG
-
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_MVBLUE 1
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
-#undef DEBUG
-
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
/*
* Serial Port
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Environment Configuration
*/
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
-#endif
-
-#define CONFIG_IPADDR 192.168.205.1
-
-#define CONFIG_HOSTNAME tqm8349
-#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
-#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "hostname=tqm83xx\0" \
+ "hostname=tqm834x\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
- "bootfile=/tftpboot/tqm83xx/uImage\0" \
+ "bootfile=/tftpboot/tqm834x/uImage\0" \
"kernel_addr=80060000\0" \
"ramdisk_addr=80160000\0" \
- "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
+ "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \
"update=protect off 80000000 8003ffff; " \
"era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
"upd=run load;run update\0" \
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
/* default mtd partition table */
-#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
+#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
"1m(kernel),2m(initrd),"\
"-(user);"\
#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
-#undef DEBUG
-
/*
* Memory map for the ADS5121 board:
*
* [04:00] DRAM tRPA
*/
-#define CFG_MDDRC_SYS_CFG 0xF8604200
-#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
-#define CFG_MDDRC_SYS_CFG_EN 0x30000000
-#define CFG_MDDRC_TIME_CFG0 0x0000281E
-#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E
+#define CFG_MDDRC_SYS_CFG 0xF8604A00
+#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
+#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
+#define CFG_MDDRC_TIME_CFG0 0x00003D2E
+#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
#define CFG_MDDRC_TIME_CFG1 0x54EC1168
#define CFG_MDDRC_TIME_CFG2 0x35210864
#define CFG_MICRON_NOP 0x01380000
#define CFG_MICRON_PCHG_ALL 0x01100400
-#define CFG_MICRON_MR 0x01000022
#define CFG_MICRON_EM2 0x01020000
#define CFG_MICRON_EM3 0x01030000
#define CFG_MICRON_EN_DLL 0x01010000
-#define CFG_MICRON_RST_DLL 0x01000932
#define CFG_MICRON_RFSH 0x01080000
-#define CFG_MICRON_INIT_DEV_OP 0x01000832
+#define CFG_MICRON_INIT_DEV_OP 0x01000432
#define CFG_MICRON_OCD_DEFAULT 0x01010780
-#define CFG_MICRON_OCD_EXIT 0x01010400
/* DDR Priority Manager Configuration */
#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5121@0"
-#define OF_SOC "soc5121@80000000"
+#define OF_SOC "soc@80000000"
+#define OF_SOC_OLD "soc5121@80000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc5121@80000000/serial@11300"
+#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
-#undef DEBUG
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
/* 256MB SDRAM / 64MB FLASH */
-#undef DEBUG
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
* We don't actually init RAM in this case since we're using U-Boot as
#define __CONFIG_H
/* Enable debug prints */
-#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-#undef DEBUG
-
/*
* Select serial console configuration
*
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/* Board Configuration Definitions */
/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
#ifndef __MS7720SE_H
#define __MS7720SE_H
-#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH3 1
#define CONFIG_CPU_SH7720 1
#ifndef __MS7722SE_H
#define __MS7722SE_H
-#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7722 1
#ifndef __MS7750SE_H
#define __MS7750SE_H
-#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7750 1
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
* do_bdinfo - Required to build with debug
*/
-#undef DEBUG
#ifdef DEBUG
#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
#define CONFIG_QEMU_MIPS 1
#define CONFIG_MISC_INIT_R
-#undef DEBUG
-
/*IP address is default used by Qemu*/
#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
#undef CONFIG_LOGBUFFER /* External logbuffer support */
#define __CONFIG_H
/* Enable debug prints */
-#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/*****************************************************************************
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
/* #define CONFIG_INITRD_TAG 1 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#include <configs/omap1510.h>
-/*
- * High Level Configuration Options
- * (easy to change)
- */
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1510 1 /* which is in a 5910 */
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE SZ_64M
+#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x0c000000
#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
#define CFG_FLASH_CFI /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
#define CFG_MAX_FLASH_BANKS 1
-#ifdef VOICEBLUE_SMALL_FLASH
-#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 }
-#else
-#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-#endif
+#define CFG_FLASH_BASE PHYS_FLASH_1
/* FIXME: Does not work on AMD flash */
/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */
#define CFG_MONITOR_BASE PHYS_FLASH_1
-#define CFG_MONITOR_LEN SZ_128K
+#define CFG_MONITOR_LEN (256 * 1024)
/*
* Environment settings
*/
-#ifdef VOICEBLUE_SMALL_FLASH
-#define CFG_ENV_IS_NOWHERE
-#define CFG_ENV_SIZE SZ_1K
-#else
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
-#define CFG_ENV_SIZE SZ_8K
-#define CFG_ENV_SECT_SIZE SZ_64K
+#define CFG_ENV_SIZE (8 * 1024)
+#define CFG_ENV_SECT_SIZE (64 * 1024)
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE
-#endif
-
/*
* Size of malloc() pool and stack
*/
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#ifdef VOICEBLUE_SMALL_FLASH
-#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE SZ_8K
-#define PHYS_SDRAM_1_RESERVED 0
-#else
-#define CFG_MALLOC_LEN SZ_4M
-#define CONFIG_STACKSIZE SZ_1M
+#define CFG_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_STACKSIZE (1 * 1024 * 1024)
#define PHYS_SDRAM_1_RESERVED (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
-#endif
/*
* Hardware drivers
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE 0x08000300
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 1
+#define CONFIG_DRIVER_OMAP1510_I2C
+
+#define CONFIG_RTC_DS1307
+#define CFG_I2C_RTC_ADDR 0x68
+
/*
* NS16550 Configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BDI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
-#if !defined(VOICEBLUE_SMALL_FLASH)
- #define CONFIG_CMD_ENV
- #define CONFIG_CMD_JFFS2
-#endif
-
/*
* BOOTP options
#define CONFIG_LOOPW
-#ifdef VOICEBLUE_SMALL_FLASH
-#define CONFIG_BOOTDELAY 0
-#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/
-#define CFG_AUTOLOAD "n" /* no autoload */
-#define CONFIG_PREBOOT "run setup"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "setup=setenv bootargs console=ttyS0,${baudrate} " \
- "root=/dev/nfs ip=dhcp\0" \
- "update=erase c000000 c03ffff; " \
- "cp.b 10400000 c000000 ${filesize}\0"
-#else
#define CONFIG_BOOTDELAY 3
-#undef CONFIG_BOOTARGS /* boot command will set bootargs */
-#define CFG_AUTOLOAD "n" /* no autoload */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CFG_AUTOLOAD "n" /* No autoload */
#define CONFIG_BOOTCOMMAND "run nboot"
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
"silent=1\0" \
"ospart=0\0" \
- "swapos=no\0" \
+ "bootfile=/boot/uImage\0" \
"setpart=" \
- "if test $swapos = yes; then " \
- "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
- "setenv swapos no; saveenv; " \
- "else " \
- "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
+ "if test -n $swapos; then " \
+ "setenv swapos; saveenv; " \
+ "if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\
"fi\0" \
"setup=setenv bootargs console=ttyS0,$baudrate " \
"mtdparts=$mtdparts\0" \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
"nfsroot=$rootpath root=/dev/nfs\0" \
"flashargs=run setpart; setenv bootargs $bootargs " \
- "root=/dev/mtdblock$partition ro " \
+ "root=mtd:data$ospart ro " \
"rootfstype=jffs2\0" \
"initrdargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
- "fboot=run flashargs; fsload /boot/uImage; bootm\0" \
- "iboot=bootp; run initrdargs; tftp; bootm\0" \
+ "fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \
+ "mboot=bootp; run initrdargs; tftp; bootm\0" \
"nboot=bootp; run nfsargs; tftp; bootm\0"
-#endif
-#ifndef VOICEBLUE_SMALL_FLASH
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#if 1 /* feel free to disable for development */
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=omapflash.0"
-#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:128k(uboot),64k(env),64k(r_env),16256k(data1),-(data2)"
-
-#endif /* VOICEBLUE_SMALL_FLASH */
+#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
/*
* Miscellaneous configurable options
*/
-#ifndef VOICEBLUE_SMALL_FLASH
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_AUTO_COMPLETE
-#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "# " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_XSENGINE 1
#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
-#define BOARD_POST_INIT 1
+#define OARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
/* SCFR1 System Clock Frequency Register 1
*/
-#define SCFR1_IPS_DIV 0x4
+#define SCFR1_IPS_DIV 0x3
#define SCFR1_IPS_DIV_MASK 0x03800000
#define SCFR1_IPS_DIV_SHIFT 23
#endif
+#if defined(CONFIG_S3C2410)
+extern struct serial_device s3c24xx_serial0_device;
+extern struct serial_device s3c24xx_serial1_device;
+extern struct serial_device s3c24xx_serial2_device;
+#endif
extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
void (*theKernel)(int zero, int arch, uint params);
image_header_t *hdr = &header;
bd_t *bd = gd->bd;
+ int machid = bd->bi_arch_number;
+ char *s;
#ifdef CONFIG_CMDLINE_TAG
char *commandline = getenv ("bootargs");
theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep);
+ s = getenv ("machid");
+ if (s) {
+ machid = simple_strtoul (s, NULL, 16);
+ printf ("Using machid 0x%x from environment\n", machid);
+ }
+
/*
* Check if there is an initrd image
*/
cleanup_before_linux ();
- theKernel (0, bd->bi_arch_number, bd->bi_boot_params);
+ theKernel (0, machid, bd->bi_boot_params);
}
extern void rtl8019_get_enetaddr (uchar * addr);
#endif
+#if defined(CONFIG_HARD_I2C) || \
+ defined(CONFIG_SOFT_I2C)
+#include <i2c.h>
+#endif
+
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
}
#endif /* CFG_NO_FLASH */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+static int init_func_i2c (void)
+{
+ puts ("I2C: ");
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ puts ("ready\n");
+ return (0);
+}
+#endif
+
/*
* Breathe some life into the board...
*
#endif
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ init_func_i2c,
#endif
dram_init, /* configure available RAM banks */
display_dram_config,
LIB = $(obj)lib$(ARCH).a
-SOBJS = ppcstring.o ticks.o
+SOBJS = ppccache.o ppcstring.o ticks.o
COBJS = board.o \
bat_rw.o cache.o extable.o kgdb.o time.o interrupts.o
--- /dev/null
+/*
+ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <ppc_asm.tmpl>
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcDcbf */
+/* Description: Data Cache block flush */
+/* Input: r3 = effective address */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcDcbf
+ppcDcbf:
+ dcbf r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcDcbi */
+/* Description: Data Cache block Invalidate */
+/* Input: r3 = effective address */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcDcbi
+ppcDcbi:
+ dcbi r0,r3
+ blr
+
+/*--------------------------------------------------------------------------
+ * Function: ppcDcbz
+ * Description: Data Cache block zero.
+ * Input: r3 = effective address
+ * Output: none.
+ *-------------------------------------------------------------------------- */
+
+ .globl ppcDcbz
+ppcDcbz:
+ dcbz r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcSync */
+/* Description: Processor Synchronize */
+/* Input: none. */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcSync
+ppcSync:
+ sync
+ blr
#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_NFS)
#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
-#define NFS_TIMEOUT 60UL
+#define NFS_RETRY_COUNT 30
+#define NFS_TIMEOUT 2UL
static int fs_mounted = 0;
static unsigned long rpc_id = 0;
static void
NfsTimeout (void)
{
+ if ( NfsTimeoutCount++ < NFS_RETRY_COUNT ) {
+ NfsSend ();
+ return;
+ }
puts ("Timeout\n");
NetState = NETLOOP_FAIL;
return;
#define TFTP_ERROR 5
#define TFTP_OACK 6
-
+static IPaddr_t TftpServerIP;
static int TftpServerPort; /* The UDP port at their end */
static int TftpOurPort; /* The UDP port at our end */
static int TftpTimeoutCount;
#define DEFAULT_NAME_LEN (8 + 4 + 1)
static char default_filename[DEFAULT_NAME_LEN];
-static char *tftp_filename;
+
+#ifndef CONFIG_TFTP_FILE_NAME_MAX_LEN
+#define MAX_LEN 128
+#else
+#define MAX_LEN CONFIG_TFTP_FILE_NAME_MAX_LEN
+#endif
+
+static char tftp_filename[MAX_LEN];
#ifdef CFG_DIRECT_FLASH_TFTP
extern flash_info_t flash_info[];
break;
}
- NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len);
+ NetSendUDPPacket(NetServerEther, TftpServerIP, TftpServerPort, TftpOurPort, len);
}
#ifdef CONFIG_MCAST_TFTP
/* if I am the MasterClient, actively calculate what my next
* needed block is; else I'm passive; not ACKING
- */
+ */
if (Multicast) {
if (len < TftpBlkSize) {
TftpEndingBlock = TftpBlock;
char *ep; /* Environment pointer */
#endif
+ TftpServerIP = NetServerIP;
if (BootFile[0] == '\0') {
sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
NetOurIP & 0xFF,
(NetOurIP >> 8) & 0xFF,
(NetOurIP >> 16) & 0xFF,
(NetOurIP >> 24) & 0xFF );
- tftp_filename = default_filename;
+
+ strncpy(tftp_filename, default_filename, MAX_LEN);
+ tftp_filename[MAX_LEN-1] = 0;
printf ("*** Warning: no boot file name; using '%s'\n",
tftp_filename);
} else {
- tftp_filename = BootFile;
+ char *p = strchr (BootFile, ':');
+
+ if (p == NULL) {
+ strncpy(tftp_filename, BootFile, MAX_LEN);
+ tftp_filename[MAX_LEN-1] = 0;
+ } else {
+ *p++ = '\0';
+ TftpServerIP = string_to_ip (BootFile);
+ strncpy(tftp_filename, p, MAX_LEN);
+ tftp_filename[MAX_LEN-1] = 0;
+ }
}
#if defined(CONFIG_NET_MULTI)
printf ("Using %s device\n", eth_get_name());
#endif
- puts ("TFTP from server "); print_IPaddr (NetServerIP);
+ puts ("TFTP from server "); print_IPaddr (TftpServerIP);
puts ("; our IP address is "); print_IPaddr (NetOurIP);
/* Check if we need to send across this subnet */
if (NetOurGatewayIP && NetOurSubnetMask) {
- IPaddr_t OurNet = NetOurIP & NetOurSubnetMask;
- IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask;
+ IPaddr_t OurNet = NetOurIP & NetOurSubnetMask;
+ IPaddr_t ServerNet = TftpServerIP & NetOurSubnetMask;
if (OurNet != ServerNet) {
puts ("; sending through gateway ");
/* Revert TftpBlkSize to dflt */
TftpBlkSize = TFTP_BLOCK_SIZE;
#ifdef CONFIG_MCAST_TFTP
- mcast_cleanup();
+ mcast_cleanup();
#endif
TftpSend ();
--- /dev/null
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/include/config.mk
+include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_ONENAND_IPL
+CFLAGS += -DCONFIG_ONENAND_IPL
+OBJCLFAGS += --gap-fill=0x00
+
+SOBJS = start.o low_levelinit.o # _memcpy32.o
+COBJS = apollon.o onenand_read.o onenand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
+
+onenandobj := $(OBJTREE)/onenand_ipl/
+
+ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
+
+all: $(obj).depend $(ALL)
+
+$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
+
+$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(onenandobj)onenand-ipl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(onenandobj)onenand-ipl.map \
+ -o $(onenandobj)onenand-ipl
+
+# create symbolic links from common files
+
+# from cpu directory
+$(obj)start.S:
+ rm -f $(obj)start.S
+ ln -s $(SRCTREE)/cpu/$(CPU)/start.S $(obj)start.S
+
+# from onenand_ipl directory
+$(obj)onenand_ipl.h:
+ rm -f $(obj)onenand_ipl.h
+ ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $(obj)onenand_ipl.h
+
+$(obj)onenand_boot.c: $(obj)onenand_ipl.h
+ rm -f $(obj)onenand_boot.c
+ ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $(obj)onenand_boot.c
+
+$(obj)onenand_read.c: $(obj)onenand_ipl.h
+ rm -f $(obj)onenand_read.c
+ ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $(obj)onenand_read.c
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)$.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mux.h>
+
+#define write_config_reg(reg, value) \
+do { \
+ writeb(value, reg); \
+} while (0)
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+ return 0;
+}
+
+#ifdef CFG_PRINTF
+/* Pin Muxing registers used for UART1 */
+/****************************************
+ * Routine: muxSetupUART1 (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+static void muxSetupUART1(void)
+{
+ /* UART1_CTS pin configuration, PIN = D21 */
+ write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
+ /* UART1_RTS pin configuration, PIN = H21 */
+ write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
+ /* UART1_TX pin configuration, PIN = L20 */
+ write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
+ /* UART1_RX pin configuration, PIN = T21 */
+ write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
+}
+#endif
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+int s_init(int skip)
+{
+#ifdef CFG_PRINTF
+ muxSetupUART1();
+#endif
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2005-2008 Samsung Electronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# Samsung Apollon board with OMAP2420 (ARM1136) cpu
+#
+# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+# 8800'0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+TEXT_BASE = 0x00000000
--- /dev/null
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from board/omap2420h4/platform.S
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+#define APOLLON_CS0_BASE 0x00000000
+
+#ifdef PRCM_CONFIG_I
+#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
+#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
+#define SDRC_RFR_CTRL_0_VAL 0x00044C01
+
+/* GPMC */
+#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
+#define APOLLON_GPMC_CONFIG2_0 0x000c1000
+#define APOLLON_GPMC_CONFIG3_0 0x00030400
+#define APOLLON_GPMC_CONFIG4_0 0x0B841006
+#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
+#define APOLLON_GPMC_CONFIG6_0 0x00000000
+#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
+
+#elif defined(PRCM_CONFIG_II)
+#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
+#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
+#define SDRC_RFR_CTRL_0_VAL 0x00030001
+
+/* GPMC */
+#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
+#define APOLLON_GPMC_CONFIG2_0 0x00080E81
+#define APOLLON_GPMC_CONFIG3_0 0x00030400
+#define APOLLON_GPMC_CONFIG4_0 0x08041586
+#define APOLLON_GPMC_CONFIG5_0 0x020C090E
+#define APOLLON_GPMC_CONFIG6_0 0x00000000
+#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
+
+#else
+#error "Please configure PRCM schecm"
+#endif
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r3, r0 /* save skip information */
+
+ /* Disable watchdog */
+ ldr r0, =WD2_BASE
+ ldr r1, =WD_UNLOCK1
+ str r1, [r0, #WSPR]
+
+ ldr r1, =WD_UNLOCK2
+ str r1, [r0, #WSPR]
+
+#ifdef DEBUG_LED
+ /* LED0 OFF */
+ ldr r0, =0x480000E5 /* ball AA10, mode 3 */
+ mov r1, #0x0b
+ strb r1, [r0]
+#endif
+
+ /* Pin muxing for SDRC */
+ mov r1, #0x00
+ ldr r0, =0x480000A1 /* ball C12, mode 0 */
+ strb r1, [r0]
+
+ ldr r0, =0x48000032 /* ball D11, mode 0 */
+ strb r1, [r0]
+
+ ldr r0, =0x480000A3 /* ball B13, mode 0 */
+ strb r1, [r0]
+
+ /* SDRC setting */
+ ldr r0, =OMAP2420_SDRC_BASE
+ ldr r1, =0x00000010
+ str r1, [r0, #0x10]
+
+ ldr r1, =0x00000100
+ str r1, [r0, #0x44]
+
+ /* SDRC CS0 configuration */
+#ifdef CONFIG_APOLLON_PLUS
+ ldr r1, =0x01702011
+#else
+ ldr r1, =0x00d04011
+#endif
+ str r1, [r0, #0x80]
+
+ ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
+ str r1, [r0, #0x9C]
+
+ ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
+ str r1, [r0, #0xA0]
+
+ ldr r1, =SDRC_RFR_CTRL_0_VAL
+ str r1, [r0, #0xA4]
+
+ ldr r1, =0x00000041
+ str r1, [r0, #0x70]
+
+ /* Manual command sequence */
+ ldr r1, =0x00000007
+ str r1, [r0, #0xA8]
+
+ ldr r1, =0x00000000
+ str r1, [r0, #0xA8]
+
+ ldr r1, =0x00000001
+ str r1, [r0, #0xA8]
+
+ ldr r1, =0x00000002
+ str r1, [r0, #0xA8]
+ str r1, [r0, #0xA8]
+
+ /*
+ * CS0 SDRC Mode register
+ * Burst length = 4 - DDR memory
+ * Serial mode
+ * CAS latency = 3
+ */
+ ldr r1, =0x00000032
+ str r1, [r0, #0x84]
+
+ /* Note: You MUST set EMR values */
+ /* EMR1 & EMR2 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x88]
+ str r1, [r0, #0x8C]
+
+#ifdef OLD_SDRC_DLLA_CTRL
+ /* SDRC_DLLA_CTRL */
+ ldr r1, =0x00007306
+ str r1, [r0, #0x60]
+
+ ldr r1, =0x00007303
+ str r1, [r0, #0x60]
+#else
+ /* SDRC_DLLA_CTRL */
+ ldr r1, =0x00000506
+ str r1, [r0, #0x60]
+
+ ldr r1, =0x00000503
+ str r1, [r0, #0x60]
+#endif
+
+#ifdef __BROKEN_FEATURE__
+ /* SDRC_DLLB_CTRL */
+ ldr r1, =0x00000506
+ str r1, [r0, #0x68]
+
+ ldr r1, =0x00000503
+ str r1, [r0, #0x68]
+#endif
+
+ /* little delay after init */
+ mov r2, #0x1800
+1:
+ subs r2, r2, #0x1
+ bne 1b
+
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ mov r0, r3 /* pass skip info to s_init */
+
+ bl s_init /* go setup pll,mux,memory */
+
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
--- /dev/null
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from X-loader
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from x-loader
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <version.h>
+
+#include "onenand_ipl.h"
+
+#ifdef CFG_PRINTF
+int print_info(void)
+{
+ printf(XLOADER_VERSION);
+
+ return 0;
+}
+#endif
+
+typedef int (init_fnc_t)(void);
+
+init_fnc_t *init_sequence[] = {
+ board_init, /* basic board dependent setup */
+#ifdef CFG_PRINTF
+ serial_init, /* serial communications setup */
+ print_info,
+#endif
+ NULL,
+};
+
+void start_oneboot(void)
+{
+ init_fnc_t **init_fnc_ptr;
+ uchar *buf;
+
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
+ hang();
+ }
+
+ buf = (uchar *) CFG_LOAD_ADDR;
+
+ if (!onenand_read_block(buf, ONENAND_START_BLOCK))
+ buf += ONENAND_BLOCK_SIZE;
+
+ if (buf == (uchar *)CFG_LOAD_ADDR)
+ hang();
+
+ /* go run U-Boot and never return */
+ printf("Starting OS Bootloader...\n");
+ ((init_fnc_t *)CFG_LOAD_ADDR)();
+
+ /* should never come here */
+}
+
+void hang(void)
+{
+ /* if board_hang() returns, hange here */
+ printf("X-Loader hangs\n");
+ for (;;);
+}
--- /dev/null
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ONENAND_IPL_H
+#define _ONENAND_IPL_H
+
+#include <linux/mtd/onenand_regs.h>
+
+#define ONENAND_START_BLOCK 0
+#define ONENAND_BLOCK_SIZE 2048
+
+#ifndef CFG_PRINTF
+#define printf(format, args...)
+#endif
+
+#define onenand_readw(a) readw(a)
+#define onenand_writew(v, a) writew(v, a)
+
+#define THIS_ONENAND(a) (CFG_ONENAND_BASE + (a))
+
+#define READ_INTERRUPT() \
+ onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT))
+
+#define ONENAND_PAGE_SIZE 2048
+
+extern int onenand_read_block(unsigned char *buf, ulong block);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2005-2008 Samsung Electronis
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/string.h>
+
+#include "onenand_ipl.h"
+
+#define onenand_block_address(block) (block)
+#define onenand_sector_address(page) (page << 2)
+#define onenand_buffer_address() ((1 << 3) << 8)
+#define onenand_bufferram_address(block) (0)
+
+/* read a page with ECC */
+static inline int onenand_read_page(ulong block, ulong page, u_char *buf)
+{
+ unsigned long *base;
+
+#ifndef __HAVE_ARCH_MEMCPY32
+ unsigned int offset, value;
+ unsigned long *p;
+#endif
+
+ onenand_writew(onenand_block_address(block),
+ THIS_ONENAND(ONENAND_REG_START_ADDRESS1));
+
+ onenand_writew(onenand_sector_address(page),
+ THIS_ONENAND(ONENAND_REG_START_ADDRESS8));
+
+ onenand_writew(onenand_buffer_address(),
+ THIS_ONENAND(ONENAND_REG_START_BUFFER));
+
+ onenand_writew(onenand_bufferram_address(block),
+ THIS_ONENAND(ONENAND_REG_START_ADDRESS2));
+
+ onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT));
+
+ onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND));
+
+#ifndef __HAVE_ARCH_MEMCPY32
+ p = (unsigned long *) buf;
+#endif
+ base = (unsigned long *) (CFG_ONENAND_BASE + ONENAND_DATARAM);
+
+ while (!(READ_INTERRUPT() & ONENAND_INT_READ))
+ continue;
+
+#ifdef __HAVE_ARCH_MEMCPY32
+ /* 32 bytes boundary memory copy */
+ memcpy32(buf, base, ONENAND_PAGE_SIZE);
+#else
+ for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) {
+ value = *(base + offset);
+ *p++ = value;
+ }
+#endif
+
+ return 0;
+}
+
+#define ONENAND_START_PAGE 1
+#define ONENAND_PAGES_PER_BLOCK 64
+
+/**
+ * onenand_read_block - Read a block data to buf
+ * @return 0 on success
+ */
+int onenand_read_block(unsigned char *buf, ulong block)
+{
+ int page, offset = 0;
+
+ /* NOTE: you must read page from page 1 of block 0 */
+ /* read the block page by page*/
+ for (page = ONENAND_START_PAGE;
+ page < ONENAND_PAGES_PER_BLOCK; page++) {
+
+ onenand_read_page(block, page, buf + offset);
+
+ offset += ONENAND_PAGE_SIZE;
+ }
+
+ return 0;
+}
{
"ECC test",
"ecc",
- "This test checks ECC facility of memory.",
- POST_ROM | POST_ALWAYS,
+ "This test checks the ECC facility of memory.",
+ POST_ROM | POST_ALWAYS | POST_PREREL,
&ecc_post_test,
NULL,
NULL,
projects / people / ms / u-boot.git / commitdiff
