gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
+ io64 PPC405EX
iocon PPC405EP
neo PPC405EP
pcm030 MPC5200
+Ira W. Snyder <iws@ovro.caltech.edu>
+
+ P2020COME P2020
+
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
be used if available. These functions may be faster under some
conditions but may increase the binary size.
+Freescale QE/FMAN Firmware Support:
+-----------------------------------
+
+The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
+loading of "firmware", which is encoded in the QE firmware binary format.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_SYS_QE_FMAN_FW_ADDR
+ The address in the storage device where the firmware is located. The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_QE_FMAN_FW_LENGTH
+ The maximum possible size of the firmware. The firmware binary format
+ has a field that specifies the actual size of the firmware, but it
+ might not be possible to read any part of the firmware unless some
+ local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NOR
+ Specifies that QE/FMAN firmware is located in NOR flash, mapped as
+ normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the
+ virtual address in NOR flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NAND
+ Specifies that QE/FMAN firmware is located in NAND flash.
+ CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ Specifies that QE/FMAN firmware is located on the primary SD/MMC
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+ Specifies that QE/FMAN firmware is located on the primary SPI
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+
Building the Software:
======================
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
+ puts("Work-around for Erratum CPU-A003999 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
+ puts("Work-around for Erratum DDR-A003473 enabled\n");
+#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Default board reset function
+ */
+static void
+__board_reset(void)
+{
+ /* Do nothing */
+}
+void board_reset(void) __attribute__((weak, alias("__board_reset")));
+
int checkcpu (void)
{
sys_info_t sysinfo;
mtspr(DBCR0,val);
#else
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
+
+ /* Attempt board-specific reset */
+ board_reset();
+
+ /* Next try asserting HRESET_REQ */
+ out_be32(&gur->rstcr, 0x2);
udelay(100);
#endif
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
+#include <linux/compiler.h>
#include "mp.h"
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
#endif
+#include "../../../../drivers/block/fsl_sata.h"
+
DECLARE_GLOBAL_DATA_PTR;
extern void srio_init(void);
*/
int cpu_init_r(void)
{
+ __maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
- uint svr, ver;
+ uint ver;
u32 l2siz_field;
- svr = get_svr();
ver = SVR_SOC_VER(svr);
asm("msync;isync");
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
- if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
- (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+ if ((SVR_SOC_VER(svr) == SVR_P2040) ||
+ (SVR_SOC_VER(svr) == SVR_P2040_E)) {
puts("N/A\n");
goto skip_l2;
}
fman_enet_init();
#endif
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+ /*
+ * For P1022/1013 Rev1.0 silicon, after power on SATA host
+ * controller is configured in legacy mode instead of the
+ * expected enterprise mode. Software needs to clear bit[28]
+ * of HControl register to change to enterprise mode from
+ * legacy mode. We assume that the controller is offline.
+ */
+ if (IS_SVR_REV(svr, 1, 0) &&
+ ((SVR_SOC_VER(svr) == SVR_P1022) ||
+ (SVR_SOC_VER(svr) == SVR_P1022_E) ||
+ (SVR_SOC_VER(svr) == SVR_P1013) ||
+ (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+ fsl_sata_reg_t *reg;
+
+ /* first SATA controller */
+ reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+ clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
+
+ /* second SATA controller */
+ reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+ clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
+ }
+#endif
+
+
return 0;
}
{
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
int ret;
- size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
/* load QE firmware from NAND flash to DDR first */
- ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
- &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
+ &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
if (ret && ret == -EUCLEAN) {
printf ("NAND read for QE firmware at offset %x failed %d\n",
- CONFIG_SYS_QE_FW_IN_NAND, ret);
+ CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
}
#endif
qe_init(qe_base);
for (i = 0; i < 32; i++)
out_be32(&ddr->debug[i], regs->debug[i]);
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+ out_be32(&ddr->debug[12], 0x00000015);
+ out_be32(&ddr->debug[21], 0x24000000);
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
return;
}
- if (length > CONFIG_SYS_FMAN_FW_LENGTH) {
+ if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
printf("Fman firmware at %p is too large (size=%u)\n",
fmanfw, length);
return;
do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
"timer-frequency", gd->bus_clk/2, 1);
+ /*
+ * clock-freq should change to clock-frequency and
+ * flexcan-v1.0 should change to p1010-flexcan respectively
+ * in the future.
+ */
do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
- "clock_freq", gd->bus_clk, 1);
+ "clock_freq", gd->bus_clk/2, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
+ "clock-frequency", gd->bus_clk/2, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
+ "clock-frequency", gd->bus_clk/2, 1);
fdt_fixup_usb(blob);
}
#define CCSR_VIRT_TO_PHYS(x) \
(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
+{
+ printf("Warning: U-Boot configured %s at address %llx,\n"
+ "but the device tree has it at %llx\n", name, uaddr, daddr);
+}
+
/*
* Verify the device tree
*
*/
int ft_verify_fdt(void *fdt)
{
- uint64_t ccsr = 0;
+ uint64_t addr = 0;
int aliases;
int off;
/* First check the CCSR base address */
off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
if (off > 0)
- ccsr = fdt_get_base_address(fdt, off);
+ addr = fdt_get_base_address(fdt, off);
- if (!ccsr) {
+ if (!addr) {
printf("Warning: could not determine base CCSR address in "
"device tree\n");
/* No point in checking anything else */
return 0;
}
- if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
- printf("Warning: U-Boot configured CCSR at address %llx,\n"
- "but the device tree has it at %llx\n",
- (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
+ msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
/* No point in checking anything else */
return 0;
}
/*
- * Get the 'aliases' node. If there isn't one, then there's nothing
- * left to do.
+ * Check some nodes via aliases. We assume that U-Boot and the device
+ * tree enumerate the devices equally. E.g. the first serial port in
+ * U-Boot is the same as "serial0" in the device tree.
*/
aliases = fdt_path_offset(fdt, "/aliases");
if (aliases > 0) {
#endif
}
+ /*
+ * The localbus node is typically a root node, even though the lbc
+ * controller is part of CCSR. If we were to put the lbc node under
+ * the SOC node, then the 'ranges' property in the lbc node would
+ * translate through the 'ranges' property of the parent SOC node, and
+ * we don't want that. Since it's a separate node, it's possible for
+ * the 'reg' property to be wrong, so check it here. For now, we
+ * only check for "fsl,elbc" nodes.
+ */
+#ifdef CONFIG_SYS_LBC_ADDR
+ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
+ if (off > 0) {
+ const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
+ if (reg) {
+ uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
+
+ addr = fdt_translate_address(fdt, off, reg);
+ if (uaddr != addr) {
+ msg("the localbus", uaddr, addr);
+ return 0;
+ }
+ }
+ }
+#endif
+
return 1;
}
mtspr SPRN_HID1,r3
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+ mfspr r3,977
+ oris r3,r3,0x0100
+ mtspr 977,r3
+#endif
+
/* Enable branch prediction */
lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
mtspr HID1,r0
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+ mfspr r3,977
+ oris r3,r3,0x0100
+ mtspr 977,r3
+#endif
+
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
lis r0,BUCSR_ENABLE@h
{
sys_info_t sysinfo;
uint pvr, svr;
- uint ver;
uint major, minor;
char buf1[32], buf2[32];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
uint msscr0 = mfspr(MSSCR0);
svr = get_svr();
- ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
puts("Core: ");
pvr = get_pvr();
- ver = PVR_E600_VER(pvr);
major = PVR_E600_MAJ(pvr);
minor = PVR_E600_MIN(pvr);
switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
case DDR3_SPD_MODULETYPE_RDIMM:
case DDR3_SPD_MODULETYPE_MINI_RDIMM:
+ case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
/* Registered/buffered DIMMs */
pdimm->registered_dimm = 1;
for (i = 0; i < 16; i += 2) {
case DDR3_SPD_MODULETYPE_SO_DIMM:
case DDR3_SPD_MODULETYPE_MICRO_DIMM:
case DDR3_SPD_MODULETYPE_MINI_UDIMM:
+ case DDR3_SPD_MODULETYPE_MINI_CDIMM:
+ case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
+ case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
+ case DDR3_SPD_MODULETYPE_LRDIMM:
+ case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
+ case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
/* Unbuffered DIMMs */
if (spd->mod_section.unbuffered.addr_mapping & 0x1)
pdimm->mirrored_dimm = 1;
{
unsigned long long ddrsize;
const char *prompt = "FSL DDR>";
- unsigned int len;
char buffer[CONFIG_SYS_CBSIZE];
char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
int argc;
* No need to worry for buffer overflow here in
* this function; readline() maxes out at CFG_CBSIZE
*/
- len = readline_into_buffer(prompt, buffer);
+ readline_into_buffer(prompt, buffer);
argc = parse_line(buffer, argv);
if (argc == 0)
continue;
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P2041)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#else
#error Processor type not defined for this platform
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
#else
PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
LDFLAGS_FINAL += --gc-sections -pie
+LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
+LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
+
+NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC))
+
+export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC))
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
+#include <linux/compiler.h>
/*
* Constructor for a conventional segment GDT (or LDT) entry
struct gdt_ptr {
u16 len;
u32 ptr;
-} __attribute__((packed));
+} __packed;
static void reload_gdt(void)
{
reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */
- cpu_init_interrupts ();
+ cpu_init_interrupts();
return 0;
}
int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- printf ("resetting ...\n");
+ printf("resetting ...\n");
/* wait 50 ms */
udelay(50000);
return 0;
}
-void flush_cache (unsigned long dummy1, unsigned long dummy2)
+void flush_cache(unsigned long dummy1, unsigned long dummy2)
{
asm("wbinvd\n");
}
/* segment 0x70 is an arbitrary segment which does not exist */
asm(".globl generate_gpf\n"
- ".hidden generate_gpf\n"
- ".type generate_gpf, @function\n"
- "generate_gpf:\n"
- "ljmp $0x70, $0x47114711\n");
+ ".hidden generate_gpf\n"
+ ".type generate_gpf, @function\n"
+ "generate_gpf:\n"
+ "ljmp $0x70, $0x47114711\n");
void __reset_cpu(ulong addr)
{
printf("Resetting using x86 Triple Fault\n");
- set_vector(13, generate_gpf); /* general protection fault handler */
- set_vector(8, generate_gpf); /* double fault handler */
- generate_gpf(); /* start the show */
+ set_vector(13, generate_gpf); /* general protection fault handler */
+ set_vector(8, generate_gpf); /* double fault handler */
+ generate_gpf(); /* start the show */
}
void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/processor-flags.h>
+#include <linux/compiler.h>
#define DECLARE_INTERRUPT(x) \
".globl irq_"#x"\n" \
switch (regno) {
case 0:
- asm("mov %%db0, %0" :"=r" (val));
+ asm("mov %%db0, %0" : "=r" (val));
break;
case 1:
- asm("mov %%db1, %0" :"=r" (val));
+ asm("mov %%db1, %0" : "=r" (val));
break;
case 2:
- asm("mov %%db2, %0" :"=r" (val));
+ asm("mov %%db2, %0" : "=r" (val));
break;
case 3:
- asm("mov %%db3, %0" :"=r" (val));
+ asm("mov %%db3, %0" : "=r" (val));
break;
case 6:
- asm("mov %%db6, %0" :"=r" (val));
+ asm("mov %%db6, %0" : "=r" (val));
break;
case 7:
- asm("mov %%db7, %0" :"=r" (val));
+ asm("mov %%db7, %0" : "=r" (val));
break;
default:
val = 0;
printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
regs->esi, regs->edi, regs->ebp, regs->esp);
printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
- (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
+ (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
+ (u16)regs->xgs, (u16)regs->xss);
cr0 = read_cr0();
cr2 = read_cr2();
u8 res;
u8 access;
u16 base_high;
-} __attribute__ ((packed));
+} __packed;
struct desc_ptr {
unsigned short size;
unsigned long address;
unsigned short segment;
-} __attribute__((packed));
+} __packed;
-struct idt_entry idt[256];
+struct idt_entry idt[256] __attribute__((aligned(16)));
struct desc_ptr idt_ptr;
static inline void load_idt(const struct desc_ptr *dtr)
{
- asm volatile("cs lidt %0"::"m" (*dtr));
+ asm volatile("cs lidt %0" : : "m" (*dtr));
}
void set_vector(u8 intnum, void *routine)
idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
}
+/*
+ * Ideally these would be defined static to avoid a checkpatch warning, but
+ * the compiler cannot see them in the inline asm and complains that they
+ * aren't defined
+ */
void irq_0(void);
void irq_1(void);
disable_interrupts();
/* Setup the IDT */
- for (i=0;i<256;i++) {
+ for (i = 0; i < 256; i++) {
idt[i].access = 0x8e;
idt[i].res = 0;
idt[i].selector = 0x10;
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
- return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
+ return flags & X86_EFLAGS_IF;
}
/* IRQ Low-Level Service Routine */
case 0x00:
printf("Divide Error (Division by zero)\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x01:
printf("Debug Interrupt (Single step)\n");
case 0x04:
printf("Overflow\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x05:
printf("BOUND Range Exceeded\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x06:
printf("Invalid Opcode (UnDefined Opcode)\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x07:
printf("Device Not Available (No Math Coprocessor)\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x08:
printf("Double fault\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x09:
printf("Co-processor segment overrun\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x0a:
printf("Invalid TSS\n");
case 0x0b:
printf("Segment Not Present\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x0c:
printf("Stack Segment Fault\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x0d:
printf("General Protection\n");
case 0x0e:
printf("Page fault\n");
dump_regs(regs);
- while(1);
+ hang();
break;
case 0x0f:
printf("Floating-Point Error (Math Fault)\n");
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/sc520.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
+
+ DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
+ DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
+ DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
+ DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
+ DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
+ DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
+ DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
+ DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
+ DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
+ DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
+ DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10]));
+ DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11]));
+ DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12]));
+ DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13]));
+ DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14]));
+ DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15]));
+
+ return 0;
+}
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
- "loop 0b\n": : : "ecx");
+ "loop 0b\n" : : : "ecx");
return x86_cpu_init_f();
}
#include <config.h>
#include <asm/processor-flags.h>
#include <asm/arch/sc520.h>
+#include <generated/asm-offsets.h>
.section .text
/* Configure Cache-As-RAM PAR */
movl $CONFIG_SYS_SC520_CAR_PAR, %eax
- movl $SC520_PAR2, %edi
+ movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
movl %eax, (%edi)
/* Trash the cache then turn it on */
debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
- if (irq < 0 || irq > 15) {
+ if (irq < 0 || irq > 15)
return -1; /* illegal irq */
- }
- if (pci_pin < 0 || pci_pin > 15) {
+ if (pci_pin < 0 || pci_pin > 15)
return -1; /* illegal pci int pin */
- }
/* first disable any non-pci interrupt source that use
* this level */
/* PCI interrupt mapping (A through D)*/
- for (i=0; i<=3 ;i++) {
- if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
+ for (i = 0; i <= 3 ; i++) {
+ tmpb = readb(&sc520_mmcr->pci_int_map[i]);
+
+ if (tmpb == sc520_irq[irq].priority)
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
}
/* GP IRQ interrupt mapping */
- for (i=0; i<=10 ;i++) {
- if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
+ for (i = 0; i <= 10 ; i++) {
+ tmpb = readb(&sc520_mmcr->gp_int_map[i]);
+
+ if (tmpb == sc520_irq[irq].priority)
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
}
if (pci_pin < 4) {
/* PCI INTA-INTD */
/* route the interrupt */
- writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
+ writeb(sc520_irq[irq].priority,
+ &sc520_mmcr->pci_int_map[pci_pin]);
} else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
- writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
+ writeb(sc520_irq[irq].priority,
+ &sc520_mmcr->gp_int_map[pci_pin - 4]);
/* also set the polarity in this case */
tmpw = readw(&sc520_mmcr->intpinpol);
hose->last_busno = 0xff;
hose->region_count = pci_set_regions(hose);
- pci_setup_type1(hose,
- SC520_REG_ADDR,
- SC520_REG_DATA);
+ pci_setup_type1(hose);
pci_register_hose(hose);
static void sc520_set_dram_refresh_rate(void);
static void sc520_enable_dram_refresh(void);
static void sc520_enable_sdram(void);
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-static void sc520_enable_ecc(void)
-#endif
int dram_init_f(void)
{
sc520_set_dram_refresh_rate();
sc520_enable_dram_refresh();
sc520_enable_sdram();
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
- sc520_enable_ecc();
-#endif
return 0;
}
writel(0x00000000, &sc520_mmcr->par[4]);
}
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-static void sc520_enable_ecc(void)
-
- /* A nominal memory test: just a byte at each address line */
- movl %eax, %ecx
- shrl $0x1, %ecx
- movl $0x1, %edi
-memtest0:
- movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
- jne out
- shrl $0x1, %ecx
- andl %ecx, %ecx
- jz set_ecc
- shll $0x1, %edi
- jmp memtest0
-
-set_ecc:
- /* clear all ram with a memset */
- movl %eax, %ecx
- xorl %esi, %esi
- xorl %edi, %edi
- xorl %eax, %eax
- shrl $0x2, %ecx
- cld
- rep stosl
-
- /* enable read, write buffers */
- movb $0x11, %al
- movl $DBCTL, %edi
- movb %al, (%edi)
-
- /* enable NMI mapping for ECC */
- movl $ECCINT, %edi
- movb $0x10, %al
- movb %al, (%edi)
-
- /* Turn on ECC */
- movl $ECCCTL, %edi
- movb $0x05, %al
- movb %al,(%edi)
-
-out:
- jmp init_ecc_ret
-}
-#endif
-
int dram_init(void)
{
ulong dram_ctrl;
int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
{
- u8 temp=0;
+ u8 temp = 0;
- if (freq >= 8192) {
+ if (freq >= 8192)
temp |= CTL_CLK_SEL_4;
- } else if (freq >= 4096) {
+ else if (freq >= 4096)
temp |= CTL_CLK_SEL_8;
- } else if (freq >= 2048) {
+ else if (freq >= 2048)
temp |= CTL_CLK_SEL_16;
- } else if (freq >= 1024) {
+ else if (freq >= 1024)
temp |= CTL_CLK_SEL_32;
- } else if (freq >= 512) {
+ else if (freq >= 512)
temp |= CTL_CLK_SEL_64;
- } else if (freq >= 256) {
+ else if (freq >= 256)
temp |= CTL_CLK_SEL_128;
- } else if (freq >= 128) {
+ else if (freq >= 128)
temp |= CTL_CLK_SEL_256;
- } else {
+ else
temp |= CTL_CLK_SEL_512;
- }
- if (!lsb_first) {
+ if (!lsb_first)
temp |= MSBF_ENB;
- }
- if (inv_clock) {
+ if (inv_clock)
temp |= CLK_INV_ENB;
- }
- if (inv_phase) {
+ if (inv_phase)
temp |= PHS_INV_ENB;
- }
writeb(temp, &sc520_mmcr->ssictl);
u8 ssi_txrx_byte(u8 data)
{
writeb(data, &sc520_mmcr->ssixmit);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
return readb(&sc520_mmcr->ssircv);
}
void ssi_tx_byte(u8 data)
{
writeb(data, &sc520_mmcr->ssixmit);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
}
u8 ssi_rx_byte(void)
{
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
return readb(&sc520_mmcr->ssircv);
}
int timer_init(void)
{
/* Register the SC520 specific timer interrupt handler */
- register_timer_isr (sc520_timer_isr);
+ register_timer_isr(sc520_timer_isr);
/* Install interrupt handler for GP Timer 1 */
irq_install_handler (0, timer_isr, NULL);
writew(100, &sc520_mmcr->gptmr1maxcmpa);
writew(0xe009, &sc520_mmcr->gptmr1ctl);
- unmask_irq (0);
+ unmask_irq(0);
/* Clear the GP Timer 1 status register to get the show rolling*/
writeb(0x02, &sc520_mmcr->gptmrsta);
#include <version.h>
#include <asm/global_data.h>
#include <asm/processor-flags.h>
+#include <generated/asm-offsets.h>
.section .text
.code32
cli
cld
- /* Turn of cache (this might require a 486-class CPU) */
+ /* Turn off cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
- /* Tell 32-bit code it is being entered from an in-RAM copy */
- movw $GD_FLG_WARM_BOOT, %bx
_start:
/* This is the 32-bit cold-reset entry point */
/* Setup call address of in-RAM copy of board_init_r() */
movl $board_init_r, %ebp
- addl (GD_RELOC_OFF * 4)(%edx), %ebp
+ addl (GENERATED_GD_RELOC_OFF)(%edx), %ebp
/* Setup parameters to board_init_r() */
movl %edx, %eax
/* Jump to in-RAM copy of board_init_r() */
call *%ebp
-die: hlt
+die:
+ hlt
jmp die
hlt
blank_idt_ptr:
.word 0 /* limit */
.long 0 /* base */
+
+ .p2align 2 /* force 4-byte alignment */
+
+multiboot_header:
+ /* magic */
+ .long 0x1BADB002
+ /* flags */
+ .long (1 << 16)
+ /* checksum */
+ .long -0x1BADB002 - (1 << 16)
+ /* header addr */
+ .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE
+ /* load addr */
+ .long CONFIG_SYS_TEXT_BASE
+ /* load end addr */
+ .long 0
+ /* bss end addr */
+ .long 0
+ /* entry addr */
+ .long CONFIG_SYS_TEXT_BASE
.code16
.globl start16
start16:
- /* Set the Cold Boot / Hard Reset flag */
- movl $GD_FLG_COLD_BOOT, %ebx
-
/*
* First we let the BSP do some early initialization
* this code have to map the flash to its final position
/* Memory Mapped Control Registers (MMCR) Base Address */
#define SC520_MMCR_BASE 0xfffef000
-/* MMCR Addresses (required for assembler code) */
-#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
-#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
-#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
-#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
-#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
-#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
-#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
-
-#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
-#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
-#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
-#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
-#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
-#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
-#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
-#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
-#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
-#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
-#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
-#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
-#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
-#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
-#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
-#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
-
/*
* PARs for maximum allowable 256MB of SDRAM @ 0x00000000
* Two PARs are required due to maximum PAR size of 128MB
#endif
-/* Word Offsets into Global Data - MUST match struct gd_t */
-#define GD_BD 0
-#define GD_FLAGS 1
-#define GD_BAUDRATE 2
-#define GD_HAVE_CONSOLE 3
-#define GD_RELOC_OFF 4
-#define GD_LOAD_OFF 5
-#define GD_ENV_ADDR 6
-#define GD_ENV_VALID 7
-#define GD_CPU_CLK 8
-#define GD_BUS_CLK 9
-#define GD_RELOC_ADDR 10
-#define GD_START_ADDR_SP 11
-#define GD_RAM_SIZE 12
-#define GD_RESET_STATUS 13
-#define GD_JT 14
-
-#define GD_SIZE 15
-
/*
* Global Data Flags
*/
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
-#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
-#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
#if 0
#define DECLARE_GLOBAL_DATA_PTR
#ifndef _PCI_I386_H_
#define _PCI_I386_H_ 1
-void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
+#define DEFINE_PCI_DEVICE_TABLE(_table) \
+ const struct pci_device_id _table[]
+
+void pci_setup_type1(struct pci_controller *hose);
int pci_enable_legacy_video_ports(struct pci_controller* hose);
int pci_shadow_rom(pci_dev_t dev, unsigned char *dest);
void pci_remove_rom_window(struct pci_controller* hose, u32 addr);
#define __ASM_REALMODE_H_
#include <asm/ptrace.h>
+extern ulong __realmode_start;
+extern ulong __realmode_size;
+extern char realmode_enter;
+
int bios_setup(void);
int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out);
int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out);
#undef __HAVE_ARCH_MEMCHR
extern void * memchr(const void *, int, __kernel_size_t);
-#undef __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMSET
extern void * memset(void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMZERO
#ifndef _U_BOOT_I386_H_
#define _U_BOOT_I386_H_ 1
+/* Exports from the Linker Script */
+extern ulong __text_start;
+extern ulong __data_end;
+extern ulong __rel_dyn_start;
+extern ulong __rel_dyn_end;
+extern ulong __bss_start;
+extern ulong __bss_end;
+
/* cpu/.../cpu.c */
int x86_cpu_init_r(void);
int cpu_init_r(void);
LIB = $(obj)lib$(ARCH).o
-SOBJS-y += bios.o
-SOBJS-y += bios_pci.o
-SOBJS-y += realmode_switch.o
+SOBJS-$(CONFIG_SYS_PC_BIOS) += bios.o
+SOBJS-$(CONFIG_SYS_PCI_BIOS) += bios_pci.o
+SOBJS-$(CONFIG_SYS_X86_REALMODE) += realmode_switch.o
-COBJS-y += bios_setup.o
+COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o
COBJS-y += board.o
COBJS-y += bootm.o
+COBJS-y += gcc.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_PCI) += pci_type1.o
-COBJS-y += realmode.o
-COBJS-y += timer.o
-COBJS-y += video_bios.o
-COBJS-y += video.o
-COBJS-y += zimage.o
+COBJS-$(CONFIG_SYS_X86_REALMODE) += realmode.o
+COBJS-y += string.o
+COBJS-$(CONFIG_SYS_X86_ISR_TIMER) += timer.o
+COBJS-$(CONFIG_VIDEO) += video_bios.o
+COBJS-$(CONFIG_VIDEO) += video.o
+COBJS-$(CONFIG_CMD_ZBOOT) += zimage.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(PREFIXED_LIBGCC): $(NORMAL_LIBGCC)
+ $(OBJCOPY) $< $@ --prefix-symbols=__normal_
+
+$(LIB): $(PREFIXED_LIBGCC)
+
#########################################################################
# defines $(obj).depend target
#ifndef _BIOS_H_
#define _BIOS_H_
-#define OFFS_ES 0 /* 16bit */
-#define OFFS_GS 2 /* 16bit */
-#define OFFS_DS 4 /* 16bit */
-#define OFFS_EDI 6 /* 32bit */
-#define OFFS_DI 6 /* low 16 bits of EDI */
-#define OFFS_ESI 10 /* 32bit */
-#define OFFS_SI 10 /* low 16 bits of ESI */
-#define OFFS_EBP 14 /* 32bit */
-#define OFFS_BP 14 /* low 16 bits of EBP */
-#define OFFS_ESP 18 /* 32bit */
-#define OFFS_SP 18 /* low 16 bits of ESP */
-#define OFFS_EBX 22 /* 32bit */
-#define OFFS_BX 22 /* low 16 bits of EBX */
-#define OFFS_BL 22 /* low 8 bits of BX */
-#define OFFS_BH 23 /* high 8 bits of BX */
-#define OFFS_EDX 26 /* 32bit */
-#define OFFS_DX 26 /* low 16 bits of EBX */
-#define OFFS_DL 26 /* low 8 bits of BX */
-#define OFFS_DH 27 /* high 8 bits of BX */
-#define OFFS_ECX 30 /* 32bit */
-#define OFFS_CX 30 /* low 16 bits of EBX */
-#define OFFS_CL 30 /* low 8 bits of BX */
-#define OFFS_CH 31 /* high 8 bits of BX */
-#define OFFS_EAX 34 /* 32bit */
-#define OFFS_AX 34 /* low 16 bits of EBX */
-#define OFFS_AL 34 /* low 8 bits of BX */
-#define OFFS_AH 35 /* high 8 bits of BX */
-#define OFFS_VECTOR 38 /* 16bit */
-#define OFFS_IP 40 /* 16bit */
-#define OFFS_CS 42 /* 16bit */
-#define OFFS_FLAGS 44 /* 16bit */
+#define OFFS_ES 0 /* 16bit */
+#define OFFS_GS 2 /* 16bit */
+#define OFFS_DS 4 /* 16bit */
+#define OFFS_EDI 6 /* 32bit */
+#define OFFS_DI 6 /* low 16 bits of EDI */
+#define OFFS_ESI 10 /* 32bit */
+#define OFFS_SI 10 /* low 16 bits of ESI */
+#define OFFS_EBP 14 /* 32bit */
+#define OFFS_BP 14 /* low 16 bits of EBP */
+#define OFFS_ESP 18 /* 32bit */
+#define OFFS_SP 18 /* low 16 bits of ESP */
+#define OFFS_EBX 22 /* 32bit */
+#define OFFS_BX 22 /* low 16 bits of EBX */
+#define OFFS_BL 22 /* low 8 bits of BX */
+#define OFFS_BH 23 /* high 8 bits of BX */
+#define OFFS_EDX 26 /* 32bit */
+#define OFFS_DX 26 /* low 16 bits of EBX */
+#define OFFS_DL 26 /* low 8 bits of BX */
+#define OFFS_DH 27 /* high 8 bits of BX */
+#define OFFS_ECX 30 /* 32bit */
+#define OFFS_CX 30 /* low 16 bits of EBX */
+#define OFFS_CL 30 /* low 8 bits of BX */
+#define OFFS_CH 31 /* high 8 bits of BX */
+#define OFFS_EAX 34 /* 32bit */
+#define OFFS_AX 34 /* low 16 bits of EBX */
+#define OFFS_AL 34 /* low 8 bits of BX */
+#define OFFS_AH 35 /* high 8 bits of BX */
+#define OFFS_VECTOR 38 /* 16bit */
+#define OFFS_IP 40 /* 16bit */
+#define OFFS_CS 42 /* 16bit */
+#define OFFS_FLAGS 44 /* 16bit */
-#define SEGMENT 0x40
-#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */
+/* stack at 0x40:0x800 -> 0x800 */
+#define SEGMENT 0x40
+#define STACK 0x800
-/* save general registers */
-/* save some segments */
-/* save callers stack segment .. */
-/* ... in gs */
- /* setup my segments */
- /* setup BIOS stackpointer */
-
-#define MAKE_BIOS_STACK \
- pushal; \
- pushw %ds; \
- pushw %gs; \
- pushw %es; \
- pushw %ss; \
- popw %gs; \
- movw $SEGMENT, %ax; \
- movw %ax, %ds; \
- movw %ax, %es; \
- movw %ax, %ss; \
- movw %sp, %bp; \
+/*
+ * save general registers
+ * save some segments
+ * save callers stack segment
+ * setup BIOS segments
+ * setup BIOS stackpointer
+ */
+#define MAKE_BIOS_STACK \
+ pushal; \
+ pushw %ds; \
+ pushw %gs; \
+ pushw %es; \
+ pushw %ss; \
+ popw %gs; \
+ movw $SEGMENT, %ax; \
+ movw %ax, %ds; \
+ movw %ax, %es; \
+ movw %ax, %ss; \
+ movw %sp, %bp; \
movw $STACK, %sp
-#define RESTORE_CALLERS_STACK \
- pushw %gs; /* restore callers stack segment */ \
- popw %ss; \
- movw %bp, %sp; /* restore stackpointer */ \
- popw %es; /* restore segment selectors */ \
- popw %gs; \
- popw %ds; \
- popal /* restore GP registers */
+/*
+ * restore callers stack segment
+ * restore some segments
+ * restore general registers
+ */
+#define RESTORE_CALLERS_STACK \
+ pushw %gs; \
+ popw %ss; \
+ movw %bp, %sp; \
+ popw %es; \
+ popw %gs; \
+ popw %ds; \
+ popal
+
+#ifndef __ASSEMBLY__
+#define BIOS_DATA ((char *)0x400)
+#define BIOS_DATA_SIZE 256
+#define BIOS_BASE ((char *)0xf0000)
+#define BIOS_CS 0xf000
+
+extern ulong __bios_start;
+extern ulong __bios_size;
+
+/* these are defined in a 16bit segment and needs
+ * to be accessed with the RELOC_16_xxxx() macros below
+ */
+extern u16 ram_in_64kb_chunks;
+extern u16 bios_equipment;
+extern u8 pci_last_bus;
+
+extern void *rm_int00;
+extern void *rm_int01;
+extern void *rm_int02;
+extern void *rm_int03;
+extern void *rm_int04;
+extern void *rm_int05;
+extern void *rm_int06;
+extern void *rm_int07;
+extern void *rm_int08;
+extern void *rm_int09;
+extern void *rm_int0a;
+extern void *rm_int0b;
+extern void *rm_int0c;
+extern void *rm_int0d;
+extern void *rm_int0e;
+extern void *rm_int0f;
+extern void *rm_int10;
+extern void *rm_int11;
+extern void *rm_int12;
+extern void *rm_int13;
+extern void *rm_int14;
+extern void *rm_int15;
+extern void *rm_int16;
+extern void *rm_int17;
+extern void *rm_int18;
+extern void *rm_int19;
+extern void *rm_int1a;
+extern void *rm_int1b;
+extern void *rm_int1c;
+extern void *rm_int1d;
+extern void *rm_int1e;
+extern void *rm_int1f;
+extern void *rm_def_int;
+
+extern void *realmode_reset;
+extern void *realmode_pci_bios_call_entry;
+
+#define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off))
+#define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off))
+#define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off))
+
+#ifdef PCI_BIOS_DEBUG
+extern u32 num_pci_bios_present;
+extern u32 num_pci_bios_find_device;
+extern u32 num_pci_bios_find_class;
+extern u32 num_pci_bios_generate_special_cycle;
+extern u32 num_pci_bios_read_cfg_byte;
+extern u32 num_pci_bios_read_cfg_word;
+extern u32 num_pci_bios_read_cfg_dword;
+extern u32 num_pci_bios_write_cfg_byte;
+extern u32 num_pci_bios_write_cfg_word;
+extern u32 num_pci_bios_write_cfg_dword;
+extern u32 num_pci_bios_get_irq_routing;
+extern u32 num_pci_bios_set_irq;
+extern u32 num_pci_bios_unknown_function;
+#endif
+
+#endif
#endif
#endif
movl $0x20494350, %eax
gs movl %eax, OFFS_EDX(%bp)
+
+ /* We support cfg type 1 version 2.10 */
movb $0x01, %al
-gs movb %al, OFFS_AL(%bp) /* We support cfg type 1 */
- movw $0x0210, %ax /* version 2.10 */
+gs movb %al, OFFS_AL(%bp)
+ movw $0x0210, %ax
gs movw %ax, OFFS_BX(%bp)
-cs movb pci_last_bus, %al /* last bus number */
+
+ /* last bus number */
+cs movb pci_last_bus, %al
gs movb %al, OFFS_CL(%bp)
jmp clear_carry
#endif
gs movw OFFS_CX(%bp), %di
shll $16, %edi
-gs movw OFFS_DX(%bp), %di /* edi now holds device in upper 16
- * bits and vendor in lower 16 bits */
+gs movw OFFS_DX(%bp), %di
+ /* edi now holds device in upper 16 bits and vendor in lower 16 bits */
+
gs movw OFFS_SI(%bp), %si
- xorw %bx, %bx /* start at bus 0 dev 0 function 0 */
+
+ /* start at bus 0 dev 0 function 0 */
+ xorw %bx, %bx
pfd_loop:
- xorw %ax, %ax /* dword 0 is vendor/device */
+ /* dword 0 is vendor/device */
+ xorw %ax, %ax
call __pci_bios_select_register
movw $0xcfc, %dx
inl %dx, %eax
- cmpl %edi, %eax /* our device ? */
+
+ /* our device ? */
+ cmpl %edi, %eax
je pfd_found_one
pfd_next_dev:
/* check for multi function devices */
andb $0x80, %al
jz pfd_not_multi_function
pfd_function_not_zero:
- incw %bx /* next function, overflows in to
- * device number, then bus number */
+ /* next function, overflows in to device number, then bus number */
+ incw %bx
jmp pfd_check_bus
pfd_not_multi_function:
- andw $0xfff8, %bx /* remove function bits */
- addw $0x0008, %bx /* next device, overflows in to bus number */
+ /* remove function bits */
+ andw $0xfff8, %bx
+
+ /* next device, overflows in to bus number */
+ addw $0x0008, %bx
pfd_check_bus:
cs movb pci_last_bus, %ah
cmpb %ah, %bh
jmp clear_carry
pfd_not_found:
- movb $0x86, %ah /* device not found */
+ /* device not found */
+ movb $0x86, %ah
jmp set_carry
/*****************************************************************************/
cs incl num_pci_bios_find_class
#endif
gs movl OFFS_ECX(%bp), %edi
- andl $0x00ffffff, %edi /* edi now holds class-code in lower 24 bits */
+
+ /* edi now holds class-code in lower 24 bits */
+ andl $0x00ffffff, %edi
gs movw OFFS_SI(%bp), %si
- xorw %bx, %bx /* start at bus 0 dev 0 function 0 */
+
+ /* start at bus 0 dev 0 function 0 */
+ xorw %bx, %bx
pfc_loop:
- movw $8, %ax /* dword 8 is class-code high 24bits */
+ /* dword 8 is class-code high 24bits */
+ movw $8, %ax
call __pci_bios_select_register
movw $0xcfc, %dx
inl %dx, %eax
shrl $8, %eax
andl $0x00ffffff, %eax
- cmpl %edi, %eax /* our device ? */
+
+ /* our device ? */
+ cmpl %edi, %eax
je pfc_found_one
pfc_next_dev:
/* check for multi function devices */
andb $0x80, %al
jz pfc_not_multi_function
pfc_function_not_zero:
- incw %bx /* next function, overflows in to
- * device number, then bus number */
+ /* next function, overflows in to device number, then bus number */
+ incw %bx
jmp pfc_check_bus
pfc_not_multi_function:
- andw $0xfff8, %bx /* remove function bits */
- addw $0x0008, %bx /* next device, overflows in to bus number */
+ /* remove function bits */
+ andw $0xfff8, %bx
+
+ /* next device, overflows in to bus number */
+ addw $0x0008, %bx
pfc_check_bus:
cs movb pci_last_bus, %ah
cmpb %ah, %bh
jmp clear_carry
pfc_not_found:
- movb $0x86, %ah /* device not found */
+ /* device not found */
+ movb $0x86, %ah
jmp set_carry
/*****************************************************************************/
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_generate_special_cycle
#endif
- movb $0x81, %ah /* function not supported */
+ /* function not supported */
+ movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_get_irq_routing
#endif
- movb $0x81, %ah /* function not supported */
+ /* function not supported */
+ movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_set_irq
#endif
- movb $0x81, %ah /* function not supported */
+ /* function not supported */
+ movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_unknown_function
#endif
- movb $0x81, %ah /* function not supported */
+ /* function not supported */
+ movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
gs movw OFFS_BX(%bp), %bx
gs movw OFFS_DI(%bp), %ax
/* destroys eax, dx */
-__pci_bios_select_register: /* BX holds device id, AX holds register index */
+__pci_bios_select_register:
+ /* BX holds device id, AX holds register index */
pushl %ebx
andl $0xfc, %eax
andl $0xffff, %ebx
clear_carry:
gs movw OFFS_FLAGS(%bp), %ax
- andw $0xfffe, %ax /* clear carry -- function succeeded */
+
+ /* clear carry -- function succeeded */
+ andw $0xfffe, %ax
gs movw %ax, OFFS_FLAGS(%bp)
xorw %ax, %ax
gs movb %ah, OFFS_AH(%bp)
set_carry:
gs movb %ah, OFFS_AH(%bp)
gs movw OFFS_FLAGS(%bp), %ax
- orw $1, %ax /* return carry -- function not supported */
+
+ /* return carry -- function not supported */
+ orw $1, %ax
gs movw %ax, OFFS_FLAGS(%bp)
movw $-1, %ax
ret
#include <pci.h>
#include <asm/realmode.h>
#include <asm/io.h>
+#include "bios.h"
DECLARE_GLOBAL_DATA_PTR;
#define NUMVECTS 256
-#define BIOS_DATA ((char*)0x400)
-#define BIOS_DATA_SIZE 256
-#define BIOS_BASE ((char*)0xf0000)
-#define BIOS_CS 0xf000
-
-extern ulong __bios_start;
-extern ulong __bios_size;
-
-/* these are defined in a 16bit segment and needs
- * to be accessed with the RELOC_16_xxxx() macros below
- */
-extern u16 ram_in_64kb_chunks;
-extern u16 bios_equipment;
-extern u8 pci_last_bus;
-
-extern void *rm_int00;
-extern void *rm_int01;
-extern void *rm_int02;
-extern void *rm_int03;
-extern void *rm_int04;
-extern void *rm_int05;
-extern void *rm_int06;
-extern void *rm_int07;
-extern void *rm_int08;
-extern void *rm_int09;
-extern void *rm_int0a;
-extern void *rm_int0b;
-extern void *rm_int0c;
-extern void *rm_int0d;
-extern void *rm_int0e;
-extern void *rm_int0f;
-extern void *rm_int10;
-extern void *rm_int11;
-extern void *rm_int12;
-extern void *rm_int13;
-extern void *rm_int14;
-extern void *rm_int15;
-extern void *rm_int16;
-extern void *rm_int17;
-extern void *rm_int18;
-extern void *rm_int19;
-extern void *rm_int1a;
-extern void *rm_int1b;
-extern void *rm_int1c;
-extern void *rm_int1d;
-extern void *rm_int1e;
-extern void *rm_int1f;
-extern void *rm_def_int;
-
-extern void *realmode_reset;
-extern void *realmode_pci_bios_call_entry;
-
static int set_jmp_vector(int entry_point, void *target)
{
- if (entry_point & ~0xffff) {
+ if (entry_point & ~0xffff)
return -1;
- }
- if (((u32)target-0xf0000) & ~0xffff) {
+ if (((u32)target - 0xf0000) & ~0xffff)
return -1;
- }
+
printf("set_jmp_vector: 0xf000:%04x -> %p\n",
- entry_point, target);
+ entry_point, target);
/* jmp opcode */
writeb(0xea, 0xf0000 + entry_point);
return 0;
}
-
-/*
- ************************************************************
- * Install an interrupt vector
- ************************************************************
- */
-
+/* Install an interrupt vector */
static void setvector(int vector, u16 segment, void *handler)
{
- u16 *ptr = (u16*)(vector*4);
- ptr[0] = ((u32)handler - (segment << 4))&0xffff;
+ u16 *ptr = (u16 *)(vector * 4);
+ ptr[0] = ((u32)handler - (segment << 4)) & 0xffff;
ptr[1] = segment;
#if 0
printf("setvector: int%02x -> %04x:%04x\n",
- vector, ptr[1], ptr[0]);
+ vector, ptr[1], ptr[0]);
#endif
}
-#define RELOC_16_LONG(seg, off) *(u32*)(seg << 4 | (u32)&off)
-#define RELOC_16_WORD(seg, off) *(u16*)(seg << 4 | (u32)&off)
-#define RELOC_16_BYTE(seg, off) *(u8*)(seg << 4 | (u32)&off)
-
int bios_setup(void)
{
- ulong bios_start = (ulong)&__bios_start + gd->reloc_off;
+ /* The BIOS section is not relocated and still in the ROM. */
+ ulong bios_start = (ulong)&__bios_start;
ulong bios_size = (ulong)&__bios_size;
- static int done=0;
+ static int done;
int vector;
#ifdef CONFIG_PCI
struct pci_controller *pri_hose;
#endif
- if (done) {
+ if (done)
return 0;
- }
+
done = 1;
if (bios_size > 65536) {
printf("BIOS too large (%ld bytes, max is 65536)\n",
- bios_size);
+ bios_size);
return -1;
}
- memcpy(BIOS_BASE, (void*)bios_start, bios_size);
+ memcpy(BIOS_BASE, (void *)bios_start, bios_size);
/* clear bda */
memset(BIOS_DATA, 0, BIOS_DATA_SIZE);
/* setup realmode interrupt vectors */
- for (vector = 0; vector < NUMVECTS; vector++) {
+ for (vector = 0; vector < NUMVECTS; vector++)
setvector(vector, BIOS_CS, &rm_def_int);
- }
setvector(0x00, BIOS_CS, &rm_int00);
setvector(0x01, BIOS_CS, &rm_int01);
#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
-
-/* Exports from the Linker Script */
-extern ulong __text_start;
-extern ulong __data_end;
-extern ulong __rel_dyn_start;
-extern ulong __rel_dyn_end;
-extern ulong __bss_start;
-extern ulong __bss_end;
-
/************************************************************************
* Init Utilities *
************************************************************************
* or dropped completely,
* but let's get it working (again) first...
*/
-static int init_baudrate (void)
+static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
return 0;
}
-static int display_banner (void)
+static int display_banner(void)
{
- printf ("\n\n%s\n\n", version_string);
-/*
- printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n"
- " BSS: %08lX -> %08lX stack: %08lX -> %08lX\n",
- i386boot_start, i386boot_romdata_start-1,
- i386boot_romdata_dest, i386boot_romdata_dest+i386boot_romdata_size-1,
- i386boot_bss_start, i386boot_bss_start+i386boot_bss_size-1,
- i386boot_bss_start+i386boot_bss_size,
- i386boot_bss_start+i386boot_bss_size+CONFIG_SYS_STACK_SIZE-1);
-
-*/
+ printf("\n\n%s\n\n", version_string);
- return (0);
+ return 0;
}
-static int display_dram_config (void)
+static int display_dram_config(void)
{
int i;
- puts ("DRAM Configuration:\n");
+ puts("DRAM Configuration:\n");
- for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
- printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
- print_size (gd->bd->bi_dram[i].size, "\n");
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+ print_size(gd->bd->bi_dram[i].size, "\n");
}
- return (0);
+ return 0;
}
-static void display_flash_config (ulong size)
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
{
- puts ("Flash: ");
- print_size (size, "\n");
+ puts("Flash: ");
+ print_size(size, "\n");
}
+#endif
/*
* Breath some life into the board...
static int calculate_relocation_address(void)
{
- void *text_start = &__text_start;
- void *bss_end = &__bss_end;
- void *dest_addr;
+ ulong text_start = (ulong)&__text_start;
+ ulong bss_end = (ulong)&__bss_end;
+ ulong dest_addr;
ulong rel_offset;
/* Calculate destination RAM Address and relocation offset */
- dest_addr = (void *)gd->ram_size;
+ dest_addr = gd->ram_size;
dest_addr -= CONFIG_SYS_STACK_SIZE;
dest_addr -= (bss_end - text_start);
+
+ /*
+ * Round destination address down to 16-byte boundary to keep
+ * IDT and GDT 16-byte aligned
+ */
+ dest_addr &= ~15;
+
rel_offset = dest_addr - text_start;
gd->start_addr_sp = gd->ram_size;
- gd->relocaddr = (ulong)dest_addr;
+ gd->relocaddr = dest_addr;
gd->reloc_off = rel_offset;
return 0;
void *bss_end = &__bss_end;
ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off);
- ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
+ ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);
while (dst_addr < end_addr)
*dst_addr++ = 0x00000000;
Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
+ Elf32_Addr *offset_ptr_rom;
+ Elf32_Addr *offset_ptr_ram;
+
+ /* The size of the region of u-boot that runs out of RAM. */
+ uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+
do {
- if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
- if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE)
- *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off;
+ /* Get the location from the relocation entry */
+ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+
+ /* Check that the location of the relocation is in .text */
+ if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE) {
+
+ /* Switch to the in-RAM version */
+ offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
+ gd->reloc_off);
+
+ /* Check that the target points into .text */
+ if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE &&
+ *offset_ptr_ram <
+ (CONFIG_SYS_TEXT_BASE + size)) {
+ *offset_ptr_ram += gd->reloc_off;
+ }
+ }
} while (re_src++ < re_end);
return 0;
relocate_code(gd->start_addr_sp, gd, gd->relocaddr);
/* NOTREACHED - relocate_code() does not return */
- while(1);
+ while (1)
+ ;
}
void board_init_r(gd_t *id, ulong dest_addr)
{
+#if defined(CONFIG_CMD_NET)
char *s;
+#endif
+#ifndef CONFIG_SYS_NO_FLASH
ulong size;
+#endif
static bd_t bd_data;
static gd_t gd_data;
init_fnc_t **init_fnc_ptr;
memcpy(gd, id, sizeof(gd_t));
/* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("": : :"memory");
+ __asm__ __volatile__("" : : : "memory");
gd->bd = &bd_data;
- memset (gd->bd, 0, sizeof (bd_t));
+ memset(gd->bd, 0, sizeof(bd_t));
show_boot_progress(0x22);
gd->baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0)
- hang ();
+ hang();
}
show_boot_progress(0x23);
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
size = flash_init();
display_flash_config(size);
show_boot_progress(0x24);
+#endif
show_boot_progress(0x25);
/* initialize environment */
- env_relocate ();
+ env_relocate();
show_boot_progress(0x26);
#ifdef CONFIG_CMD_NET
/* IP Address */
- bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr");
+ bd_data.bi_ip_addr = getenv_IPaddr("ipaddr");
#endif
#if defined(CONFIG_PCI)
show_boot_progress(0x27);
- stdio_init ();
+ stdio_init();
- jumptable_init ();
+ jumptable_init();
/* Initialize the console (after the relocation and devices init) */
console_init_r();
#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
- puts ("PCMCIA:");
+ puts("PCMCIA:");
pcmcia_init();
#endif
show_boot_progress(0x28);
#ifdef CONFIG_STATUS_LED
- status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#if defined(CONFIG_CMD_NET)
- if ((s = getenv ("bootfile")) != NULL) {
- copy_filename (BootFile, s, sizeof (BootFile));
- }
+ s = getenv("bootfile");
+
+ if (s != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
#endif
WATCHDOG_RESET();
eth_initialize(gd->bd);
#endif
-#if ( defined(CONFIG_CMD_NET)) && (0)
+#if (defined(CONFIG_CMD_NET)) && (0)
WATCHDOG_RESET();
# ifdef DEBUG
- puts ("Reset Ethernet PHY\n");
+ puts("Reset Ethernet PHY\n");
# endif
reset_phy();
#endif
#ifdef CONFIG_POST
- post_run (NULL, POST_RAM | post_bootmode_get(0));
+ post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
-
show_boot_progress(0x29);
/* main_loop() can return to retry autoboot, if so just run it again. */
- for (;;) {
+ for (;;)
main_loop();
- }
/* NOTREACHED - no way out of command loop except booting */
}
-void hang (void)
+void hang(void)
{
- puts ("### ERROR ### Please RESET the board ###\n");
- for (;;);
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
}
-unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[])
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+ int argc, char * const argv[])
{
unsigned long ret = 0;
char **argv_tmp;
#include <asm/zimage.h>
/*cmd_boot.c*/
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
- void *base_ptr;
+ void *base_ptr = NULL;
ulong os_data, os_len;
image_header_t *hdr;
if (images->legacy_hdr_valid) {
hdr = images->legacy_hdr_os;
- if (image_check_type (hdr, IH_TYPE_MULTI)) {
+ if (image_check_type(hdr, IH_TYPE_MULTI)) {
/* if multi-part image, we need to get first subimage */
- image_multi_getimg (hdr, 0, &os_data, &os_len);
+ image_multi_getimg(hdr, 0, &os_data, &os_len);
} else {
/* otherwise get image data */
- os_data = image_get_data (hdr);
- os_len = image_get_data_size (hdr);
+ os_data = image_get_data(hdr);
+ os_len = image_get_data_size(hdr);
}
#if defined(CONFIG_FIT)
} else if (images->fit_uname_os) {
- ret = fit_image_get_data (images->fit_hdr_os,
+ ret = fit_image_get_data(images->fit_hdr_os,
images->fit_noffset_os, &data, &len);
if (ret) {
- puts ("Can't get image data/size!\n");
+ puts("Can't get image data/size!\n");
goto error;
}
os_data = (ulong)data;
os_len = (ulong)len;
#endif
} else {
- puts ("Could not find kernel image!\n");
+ puts("Could not find kernel image!\n");
goto error;
}
- base_ptr = load_zimage ((void*)os_data, os_len,
+#ifdef CONFIG_CMD_ZBOOT
+ base_ptr = load_zimage((void *)os_data, os_len,
images->rd_start, images->rd_end - images->rd_start, 0);
+#endif
if (NULL == base_ptr) {
- printf ("## Kernel loading failed ...\n");
+ printf("## Kernel loading failed ...\n");
goto error;
}
#ifdef DEBUG
- printf ("## Transferring control to Linux (at address %08x) ...\n",
+ printf("## Transferring control to Linux (at address %08x) ...\n",
(u32)base_ptr);
#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 or later of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifdef __GNUC__
+
+/*
+ * GCC's libgcc handling is quite broken. While the libgcc functions
+ * are always regparm(0) the code that calls them uses whatever the
+ * compiler call specifies. Therefore we need a wrapper around those
+ * functions. See gcc bug PR41055 for more information.
+ */
+#define WRAP_LIBGCC_CALL(type, name) \
+ type __normal_##name(type a, type b) __attribute__((regparm(0))); \
+ type __wrap_##name(type a, type b); \
+ type __wrap_##name(type a, type b) { return __normal_##name(a, b); }
+
+WRAP_LIBGCC_CALL(long long, __divdi3)
+WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
+WRAP_LIBGCC_CALL(long long, __moddi3)
+WRAP_LIBGCC_CALL(unsigned long long, __umoddi3)
+
+#endif
};
static struct irq_action irq_handlers[CONFIG_SYS_NUM_IRQS] = { {0} };
-static int spurious_irq_cnt = 0;
-static int spurious_irq = 0;
+static int spurious_irq_cnt;
+static int spurious_irq;
void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
{
if (irq_handlers[irq].handler != NULL)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
- (ulong) handler,
- (ulong) irq_handlers[irq].handler);
+ (ulong) handler,
+ (ulong) irq_handlers[irq].handler);
- status = disable_interrupts ();
+ status = disable_interrupts();
irq_handlers[irq].handler = handler;
irq_handlers[irq].arg = arg;
return;
}
- status = disable_interrupts ();
+ status = disable_interrupts();
mask_irq(irq);
int irq;
printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
- spurious_irq_cnt, spurious_irq);
+ spurious_irq_cnt, spurious_irq);
- printf ("Interrupt-Information:\n");
- printf ("Nr Routine Arg Count\n");
+ printf("Interrupt-Information:\n");
+ printf("Nr Routine Arg Count\n");
for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) {
if (irq_handlers[irq].handler != NULL) {
- printf ("%02d %08lx %08lx %d\n",
+ printf("%02d %08lx %08lx %d\n",
irq,
(ulong)irq_handlers[irq].handler,
(ulong)irq_handlers[irq].arg,
* Enable cascaded interrupts by unmasking the cascade IRQ pin of
* the master PIC
*/
- unmask_irq (2);
+ unmask_irq(2);
enable_interrupts();
#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
#define TIMER2_VALUE 0x0a8e /* 440Hz */
-static int timer_init_done = 0;
+static int timer_init_done;
int timer_init(void)
{
* (to stasrt a beep: write 3 to port 0x61,
* to stop it again: write 0)
*/
- outb (PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
- PIT_BASE + PIT_COMMAND);
- outb (TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
- outb (TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
+ outb(PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
+ PIT_BASE + PIT_COMMAND);
+ outb(TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
+ outb(TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
- outb (PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
- PIT_BASE + PIT_COMMAND);
- outb (TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
- outb (TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
+ outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
+ PIT_BASE + PIT_COMMAND);
+ outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
+ outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
- irq_install_handler (0, timer_isr, NULL);
- unmask_irq (0);
+ irq_install_handler(0, timer_isr, NULL);
+ unmask_irq(0);
timer_init_done = 1;
{
u8 low;
- outb (PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
- low = inb (PIT_BASE + PIT_T0);
+ outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
+ low = inb(PIT_BASE + PIT_T0);
- return ((inb (PIT_BASE + PIT_T0) << 8) | low);
+ return (inb(PIT_BASE + PIT_T0) << 8) | low;
}
/* this is not very exact */
-void __udelay (unsigned long usec)
+void __udelay(unsigned long usec)
{
int counter;
int wraps;
- if (timer_init_done)
- {
- counter = read_pit ();
+ if (timer_init_done) {
+ counter = read_pit();
wraps = usec / 1000;
usec = usec % 1000;
}
while (1) {
- int new_count = read_pit ();
+ int new_count = read_pit();
if (((new_count < usec) && !wraps) || wraps < 0)
break;
u16 device;
u32 class_code;
+ u32 pci_data;
+
hose = pci_bus_to_hose(PCI_BUS(dev));
-#if 0
- printf("pci_shadow_rom() asked to shadow device %x to %x\n",
+
+ debug("pci_shadow_rom() asked to shadow device %x to %x\n",
dev, (u32)dest);
-#endif
+
pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
pci_read_config_word(dev, PCI_DEVICE_ID, &device);
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code);
return -1;
}
- size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1;
+ size = (~(addr_reg&PCI_ROM_ADDRESS_MASK)) + 1;
debug("ROM is %d bytes\n", size);
|PCI_ROM_ADDRESS_ENABLE);
- for (i=rom_addr;i<rom_addr+size; i+=512) {
-
-
+ for (i = rom_addr; i < rom_addr + size; i += 512) {
if (readw(i) == 0xaa55) {
- u32 pci_data;
#ifdef PCI_ROM_SCAN_VERBOSE
printf("ROM signature found\n");
#endif
- pci_data = readw(0x18+i);
+ pci_data = readw(0x18 + i);
pci_data += i;
- if (0==memcmp((void*)pci_data, "PCIR", 4)) {
+ if (0 == memcmp((void *)pci_data, "PCIR", 4)) {
#ifdef PCI_ROM_SCAN_VERBOSE
- printf("Fount PCI rom image at offset %d\n", i-rom_addr);
+ printf("Fount PCI rom image at offset %d\n",
+ i - rom_addr);
printf("Vendor %04x device %04x class %06x\n",
- readw(pci_data+4), readw(pci_data+6),
- readl(pci_data+0x0d)&0xffffff);
+ readw(pci_data + 4), readw(pci_data + 6),
+ readl(pci_data + 0x0d) & 0xffffff);
printf("%s\n",
- (readw(pci_data+0x15) &0x80)?
- "Last image":"More images follow");
- switch (readb(pci_data+0x14)) {
+ (readw(pci_data + 0x15) & 0x80) ?
+ "Last image" : "More images follow");
+ switch (readb(pci_data + 0x14)) {
case 0:
printf("X86 code\n");
break;
printf("PARISC code\n");
break;
}
- printf("Image size %d\n", readw(pci_data+0x10) * 512);
+ printf("Image size %d\n",
+ readw(pci_data + 0x10) * 512);
#endif
- /* FixMe: I think we should compare the class code
- * bytes as well but I have no reference on the
- * exact order of these bytes in the PCI ROM header */
- if (readw(pci_data+4) == vendor &&
- readw(pci_data+6) == device &&
- /* (readl(pci_data+0x0d)&0xffffff) == class_code && */
- readb(pci_data+0x14) == 0 /* x86 code image */ ) {
+ /*
+ * FixMe: I think we should compare the class
+ * code bytes as well but I have no reference
+ * on the exact order of these bytes in the PCI
+ * ROM header
+ */
+ if (readw(pci_data + 4) == vendor &&
+ readw(pci_data + 6) == device &&
+ readb(pci_data + 0x14) == 0) {
#ifdef PCI_ROM_SCAN_VERBOSE
- printf("Suitable ROM image found, copying\n");
+ printf("Suitable ROM image found\n");
#endif
- memmove(dest, (void*)rom_addr, readw(pci_data+0x10) * 512);
+ memmove(dest, (void *)rom_addr,
+ readw(pci_data + 0x10) * 512);
res = 0;
break;
}
- if (readw(pci_data+0x15) &0x80) {
+
+ if (readw(pci_data + 0x15) & 0x80)
break;
- }
}
}
}
#ifdef PCI_ROM_SCAN_VERBOSE
- if (res) {
+ if (res)
printf("No suitable image found\n");
- }
#endif
/* disable PAR register and PCI device ROM address devocer */
pci_remove_rom_window(hose, rom_addr);
return res;
}
+
+#ifdef PCI_BIOS_DEBUG
+
+void print_bios_bios_stat(void)
+{
+ printf("16 bit functions:\n");
+ printf("pci_bios_present: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_present));
+ printf("pci_bios_find_device: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_find_device));
+ printf("pci_bios_find_class: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_find_class));
+ printf("pci_bios_generate_special_cycle: %d\n",
+ RELOC_16_LONG(0xf000,
+ num_pci_bios_generate_special_cycle));
+ printf("pci_bios_read_cfg_byte: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte));
+ printf("pci_bios_read_cfg_word: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word));
+ printf("pci_bios_read_cfg_dword: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword));
+ printf("pci_bios_write_cfg_byte: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte));
+ printf("pci_bios_write_cfg_word: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word));
+ printf("pci_bios_write_cfg_dword: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword));
+ printf("pci_bios_get_irq_routing: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing));
+ printf("pci_bios_set_irq: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_set_irq));
+ printf("pci_bios_unknown_function: %d\n",
+ RELOC_16_LONG(0xf000, num_pci_bios_unknown_function));
+}
+#endif
#include <asm/io.h>
#include <pci.h>
-#define cfg_read(val, addr, op) *val = op((int)(addr))
+#define cfg_read(val, addr, op) (*val = op((int)(addr)))
#define cfg_write(val, addr, op) op((val), (int)(addr))
#define TYPE1_PCI_OP(rw, size, type, op, mask) \
return 0; \
}
-
TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
TYPE1_PCI_OP(read, word, u16 *, inw, 2)
TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
-void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+/* bus mapping constants (used for PCI core initialization) */
+#define PCI_REG_ADDR 0x00000cf8
+#define PCI_REG_DATA 0x00000cfc
+
+void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,
type1_read_config_byte,
type1_write_config_word,
type1_write_config_dword);
- hose->cfg_addr = (unsigned int *) cfg_addr;
- hose->cfg_data = (unsigned char *) cfg_data;
+ hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
+ hose->cfg_data = (unsigned char *)PCI_REG_DATA;
}
#include <asm/ptrace.h>
#include <asm/realmode.h>
-#define REALMODE_MAILBOX ((char*)0xe00)
-
-extern ulong __realmode_start;
-extern ulong __realmode_size;
-extern char realmode_enter;
+#define REALMODE_MAILBOX ((char *)0xe00)
int realmode_setup(void)
{
- ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off;
+ /* The realmode section is not relocated and still in the ROM. */
+ ulong realmode_start = (ulong)&__realmode_start;
ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
in->eip = off;
in->xcs = seg;
- if (3>(in->esp & 0xffff)) {
+ if ((in->esp & 0xffff) < 4)
printf("Warning: entering realmode with sp < 4 will fail\n");
- }
memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs));
asm("wbinvd\n");
__asm__ volatile (
- "lcall $0x20,%0\n" : : "i" (&realmode_enter) );
+ "lcall $0x20,%0\n" : : "i" (&realmode_enter));
asm("wbinvd\n");
memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs));
return out->eax;
}
-
-/* This code is supposed to access a realmode interrupt
- * it does currently not work for me */
+/*
+ * This code is supposed to access a realmode interrupt
+ * it does currently not work for me
+ */
int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out)
{
/* place two instructions at 0x700 */
enter_realmode(0x00, 0x700, in, out);
- return out->eflags&1;
+ return out->eflags & 0x00000001;
}
--- /dev/null
+/*
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* From glibc-2.14, sysdeps/i386/memset.c */
+
+#include <compiler.h>
+#include <asm/string.h>
+#include <linux/types.h>
+
+typedef uint32_t op_t;
+
+void *memset(void *dstpp, int c, size_t len)
+{
+ int d0;
+ unsigned long int dstp = (unsigned long int) dstpp;
+
+ /* This explicit register allocation improves code very much indeed. */
+ register op_t x asm("ax");
+
+ x = (unsigned char) c;
+
+ /* Clear the direction flag, so filling will move forward. */
+ asm volatile("cld");
+
+ /* This threshold value is optimal. */
+ if (len >= 12) {
+ /* Fill X with four copies of the char we want to fill with. */
+ x |= (x << 8);
+ x |= (x << 16);
+
+ /* Adjust LEN for the bytes handled in the first loop. */
+ len -= (-dstp) % sizeof(op_t);
+
+ /*
+ * There are at least some bytes to set. No need to test for
+ * LEN == 0 in this alignment loop.
+ */
+
+ /* Fill bytes until DSTP is aligned on a longword boundary. */
+ asm volatile(
+ "rep\n"
+ "stosb" /* %0, %2, %3 */ :
+ "=D" (dstp), "=c" (d0) :
+ "0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
+ "memory");
+
+ /* Fill longwords. */
+ asm volatile(
+ "rep\n"
+ "stosl" /* %0, %2, %3 */ :
+ "=D" (dstp), "=c" (d0) :
+ "0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
+ "memory");
+ len %= sizeof(op_t);
+ }
+
+ /* Write the last few bytes. */
+ asm volatile(
+ "rep\n"
+ "stosb" /* %0, %2, %3 */ :
+ "=D" (dstp), "=c" (d0) :
+ "0" (dstp), "1" (len), "a" (x) :
+ "memory");
+
+ return dstpp;
+}
timer_fnc_t *isr_func;
};
-static struct timer_isr_function *first_timer_isr = NULL;
-static volatile unsigned long system_ticks = 0;
+static struct timer_isr_function *first_timer_isr;
+static unsigned long system_ticks;
/*
* register_timer_isr() allows multiple architecture and board specific
* functions to be called every millisecond. Keep the execution time of
* each function as low as possible
*/
-int register_timer_isr (timer_fnc_t *isr_func)
+int register_timer_isr(timer_fnc_t *isr_func)
{
struct timer_isr_function *new_func;
struct timer_isr_function *temp;
* Don't allow timer interrupts while the
* linked list is being modified
*/
- flag = disable_interrupts ();
+ flag = disable_interrupts();
if (first_timer_isr == NULL) {
first_timer_isr = new_func;
}
if (flag)
- enable_interrupts ();
+ enable_interrupts();
return 0;
}
/* Execute each registered function */
while (temp != NULL) {
- temp->isr_func ();
+ temp->isr_func();
temp = temp->next;
}
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return (system_ticks - base);
+ return system_ticks - base;
}
static void video_putc(const char c)
{
- int x,y,pos;
+ int x, y, pos;
x = orig_x;
y = orig_y;
static void video_puts(const char *s)
{
- int x,y,pos;
+ int x, y, pos;
char c;
x = orig_x;
printf("pos %x %d %d\n", pos, orig_x, orig_y);
#endif
if (orig_y > lines)
- orig_x = orig_y =0;
+ orig_x = orig_y = 0;
memset(&vga_dev, 0, sizeof(vga_dev));
strcpy(vga_dev.name, "vga");
#include <asm/realmode.h>
#include <asm/io.h>
#include <asm/pci.h>
+#include "bios.h"
#undef PCI_BIOS_DEBUG
#undef VGA_BIOS_DEBUG
#ifdef VGA_BIOS_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...)
#endif
-#ifdef CONFIG_PCI
+#define PCI_CLASS_VIDEO 3
+#define PCI_CLASS_VIDEO_STD 0
+#define PCI_CLASS_VIDEO_PROG_IF_VGA 0
-#ifdef PCI_BIOS_DEBUG
-#define RELOC_16(seg, off) *(u32*)(seg << 4 | (u32)&off)
-extern u32 num_pci_bios_present;
-extern u32 num_pci_bios_find_device;
-extern u32 num_pci_bios_find_class;
-extern u32 num_pci_bios_generate_special_cycle;
-extern u32 num_pci_bios_read_cfg_byte;
-extern u32 num_pci_bios_read_cfg_word;
-extern u32 num_pci_bios_read_cfg_dword;
-extern u32 num_pci_bios_write_cfg_byte;
-extern u32 num_pci_bios_write_cfg_word;
-extern u32 num_pci_bios_write_cfg_dword;
-extern u32 num_pci_bios_get_irq_routing;
-extern u32 num_pci_bios_set_irq;
-extern u32 num_pci_bios_unknown_function;
-
-void print_bios_bios_stat(void)
-{
- printf("16 bit functions:\n");
- printf("pci_bios_present: %d\n", RELOC_16(0xf000, num_pci_bios_present));
- printf("pci_bios_find_device: %d\n", RELOC_16(0xf000, num_pci_bios_find_device));
- printf("pci_bios_find_class: %d\n", RELOC_16(0xf000, num_pci_bios_find_class));
- printf("pci_bios_generate_special_cycle: %d\n", RELOC_16(0xf000, num_pci_bios_generate_special_cycle));
- printf("pci_bios_read_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_byte));
- printf("pci_bios_read_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_word));
- printf("pci_bios_read_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_dword));
- printf("pci_bios_write_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_byte));
- printf("pci_bios_write_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_word));
- printf("pci_bios_write_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_dword));
- printf("pci_bios_get_irq_routing: %d\n", RELOC_16(0xf000, num_pci_bios_get_irq_routing));
- printf("pci_bios_set_irq: %d\n", RELOC_16(0xf000, num_pci_bios_set_irq));
- printf("pci_bios_unknown_function: %d\n", RELOC_16(0xf000, num_pci_bios_unknown_function));
-
-}
-#endif
-
-#ifdef CONFIG_VIDEO
-
-#define PCI_CLASS_VIDEO 3
-#define PCI_CLASS_VIDEO_STD 0
-#define PCI_CLASS_VIDEO_PROG_IF_VGA 0
-
-static struct pci_device_id supported[] = {
+DEFINE_PCI_DEVICE_TABLE(supported) = {
{PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID},
{}
};
static u32 probe_pci_video(void)
{
- pci_dev_t devbusfn;
+ struct pci_controller *hose;
+ pci_dev_t devbusfn = pci_find_devices(supported, 0);
- if ((devbusfn = pci_find_devices(supported, 0) != -1)) {
+ if ((devbusfn != -1)) {
u32 old;
u32 addr;
/* PCI video device detected */
printf("Found PCI VGA device at %02x.%02x.%x\n",
- PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn));
+ PCI_BUS(devbusfn),
+ PCI_DEV(devbusfn),
+ PCI_FUNC(devbusfn));
/* Enable I/O decoding as well, PCI viudeo boards
* support I/O accesses, but they provide no
* bar register for this since the ports are fixed.
*/
- pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+ pci_write_config_word(devbusfn,
+ PCI_COMMAND,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_IO |
+ PCI_COMMAND_MASTER);
/* Test the ROM decoder, do the device support a rom? */
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
- pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
+ pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS,
+ (u32)PCI_ROM_ADDRESS_MASK);
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
}
/* device have a rom */
- if (pci_shadow_rom(devbusfn, (void*)0xc0000)) {
+ if (pci_shadow_rom(devbusfn, (void *)0xc0000)) {
printf("Shadowing of PCI VGA BIOS failed\n");
return 0;
}
/* Now enable lagacy VGA port access */
- if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) {
+ hose = pci_bus_to_hose(PCI_BUS(devbusfn));
+ if (pci_enable_legacy_video_ports(hose)) {
printf("PCI VGA enable failed\n");
return 0;
}
/* return the pci device info, that we'll need later */
return PCI_BUS(devbusfn) << 8 |
- PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7);
+ PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7);
}
return 0;
u32 ptr;
char *buf;
- if (0 == (ptr = isa_map_rom(0xc0000, 0x8000))) {
+ ptr = isa_map_rom(0xc0000, 0x8000);
+
+ if (!ptr)
return -1;
- }
- if (NULL == (buf=malloc(0x8000))) {
+
+ buf = malloc(0x8000);
+ if (!buf) {
isa_unmap_rom(ptr);
return -1;
}
+
if (readw(ptr) != 0xaa55) {
free(buf);
isa_unmap_rom(ptr);
}
/* shadow the rom */
- memcpy(buf, (void*)ptr, 0x8000);
+ memcpy(buf, (void *)ptr, 0x8000);
isa_unmap_rom(ptr);
- memcpy((void*)0xc0000, buf, 0x8000);
+ memcpy((void *)0xc0000, buf, 0x8000);
free(buf);
int video_bios_init(void)
{
struct pt_regs regs;
+ int size;
+ int i;
+ u8 sum;
/* clear the video bios area in case we warmbooted */
- memset((void*)0xc0000, 0, 0x8000);
+ memset((void *)0xc0000, 0, 0x8000);
memset(®s, 0, sizeof(struct pt_regs));
- if (probe_isa_video()) {
+ if (probe_isa_video())
/* No ISA board found, try the PCI bus */
regs.eax = probe_pci_video();
- }
/* Did we succeed in mapping any video bios */
if (readw(0xc0000) == 0xaa55) {
- int size;
- int i;
- u8 sum;
-
PRINTF("Found video bios signature\n");
- size = 512*readb(0xc0002);
+ size = readb(0xc0002) * 512;
PRINTF("size %d\n", size);
- sum=0;
- for (i=0;i<size;i++) {
+ sum = 0;
+
+ for (i = 0; i < size; i++)
sum += readb(0xc0000 + i);
- }
- PRINTF("Checksum is %sOK\n",sum?"NOT ":"");
- if (sum) {
+
+ PRINTF("Checksum is %sOK\n", sum ? "NOT " : "");
+
+ if (sum)
return 1;
- }
- /* some video bioses (ATI Mach64) seem to think that
+ /*
+ * Some video bioses (ATI Mach64) seem to think that
* the original int 10 handler is always at
* 0xf000:0xf065 , place an iret instruction there
*/
regs.esp = 0x8000;
regs.xss = 0x2000;
enter_realmode(0xc000, 3, ®s, ®s);
+
PRINTF("INT 0x10 vector after: %04x:%04x\n",
readw(0x42), readw(0x40));
- PRINTF("BIOS returned %scarry\n", regs.eflags & 1?"":"NOT ");
+ PRINTF("BIOS returned %scarry\n",
+ regs.eflags & 0x00000001 ? "" : "NOT ");
#ifdef PCI_BIOS_DEBUG
print_bios_bios_stat();
#endif
- return (regs.eflags & 1);
+ return regs.eflags & 0x00000001;
}
return 1;
}
-#endif
-#endif
* 0x8000-0x8FFF Stack and heap
* 0x9000-0x90FF Kernel command line
*/
-#define DEFAULT_SETUP_BASE 0x90000
-#define COMMAND_LINE_OFFSET 0x9000
-#define HEAP_END_OFFSET 0x8e00
+#define DEFAULT_SETUP_BASE 0x90000
+#define COMMAND_LINE_OFFSET 0x9000
+#define HEAP_END_OFFSET 0x8e00
-#define COMMAND_LINE_SIZE 2048
+#define COMMAND_LINE_SIZE 2048
static void build_command_line(char *command_line, int auto_boot)
{
env_command_line = getenv("bootargs");
/* set console= argument if we use a serial console */
- if (NULL == strstr(env_command_line, "console=")) {
- if (0==strcmp(getenv("stdout"), "serial")) {
+ if (!strstr(env_command_line, "console=")) {
+ if (!strcmp(getenv("stdout"), "serial")) {
/* We seem to use serial console */
sprintf(command_line, "console=ttyS0,%s ",
- getenv("baudrate"));
+ getenv("baudrate"));
}
}
- if (auto_boot) {
+ if (auto_boot)
strcat(command_line, "auto ");
- }
- if (NULL != env_command_line) {
+ if (env_command_line)
strcat(command_line, env_command_line);
- }
-
printf("Kernel command line: \"%s\"\n", command_line);
}
int bootproto;
int big_image;
void *load_address;
+ struct setup_header *hdr;
- struct setup_header *hdr = (struct setup_header *)(image + SETUP_SECTS_OFF);
+ hdr = (struct setup_header *)(image + SETUP_SECTS_OFF);
- setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */
+ /* base address for real-mode segment */
+ setup_base = (void *)DEFAULT_SETUP_BASE;
if (KERNEL_MAGIC != hdr->boot_flag) {
printf("Error: Invalid Boot Flag (found 0x%04x, expected 0x%04x)\n",
- hdr->boot_flag, KERNEL_MAGIC);
+ hdr->boot_flag, KERNEL_MAGIC);
return 0;
} else {
printf("Valid Boot Flag\n");
printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size);
- if (setup_size > SETUP_MAX_SIZE) {
+ if (setup_size > SETUP_MAX_SIZE)
printf("Error: Setup is too large (%d bytes)\n", setup_size);
- }
/* Determine image type */
- big_image = (bootproto >= 0x0200) && (hdr->loadflags & BIG_KERNEL_FLAG);
+ big_image = (bootproto >= 0x0200) &&
+ (hdr->loadflags & BIG_KERNEL_FLAG);
/* Determine load address */
- load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR : ZIMAGE_LOAD_ADDR);
+ load_address = (void *)(big_image ?
+ BZIMAGE_LOAD_ADDR :
+ ZIMAGE_LOAD_ADDR);
/* load setup */
- printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", (ulong)setup_base, setup_size);
+ printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n",
+ (ulong)setup_base, setup_size);
memmove(setup_base, image, setup_size);
printf("Using boot protocol version %x.%02x\n",
(bootproto & 0xff00) >> 8, bootproto & 0xff);
if (bootproto == 0x0100) {
+ *(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
+ *(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
- *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
- *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
-
- /* A very old kernel MUST have its real-mode code
- * loaded at 0x90000 */
-
+ /*
+ * A very old kernel MUST have its real-mode code
+ * loaded at 0x90000
+ */
if ((u32)setup_base != 0x90000) {
/* Copy the real-mode kernel */
- memmove((void*)0x90000, setup_base, setup_size);
+ memmove((void *)0x90000, setup_base, setup_size);
+
/* Copy the command line */
- memmove((void*)0x99000, setup_base+COMMAND_LINE_OFFSET,
- COMMAND_LINE_SIZE);
+ memmove((void *)0x99000,
+ setup_base + COMMAND_LINE_OFFSET,
+ COMMAND_LINE_SIZE);
- setup_base = (void*)0x90000; /* Relocated */
+ /* Relocated */
+ setup_base = (void *)0x90000;
}
/* It is recommended to clear memory up to the 32K mark */
- memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size);
+ memset((void *)0x90000 + setup_size, 0,
+ SETUP_MAX_SIZE-setup_size);
}
/* We are now setting up the real-mode version of the header */
hdr->type_of_loader = 8;
if (hdr->setup_sects >= 15)
- printf("Linux kernel version %s\n", (char *)
- (setup_base + (hdr->kernel_version + 0x200)));
+ printf("Linux kernel version %s\n",
+ (char *)(setup_base +
+ (hdr->kernel_version + 0x200)));
else
printf("Setup Sectors < 15 - Cannot print kernel version.\n");
hdr->cmd_line_ptr = (u32)setup_base + COMMAND_LINE_OFFSET;
} else if (bootproto >= 0x0200) {
- *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
- *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
+ *(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
+ *(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
hdr->setup_move_size = 0x9100;
}
/* build command line at COMMAND_LINE_OFFSET */
build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot);
- printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ',
- (u32)load_address, kernel_size);
+ printf("Loading %czImage at address 0x%08x (%ld bytes)\n",
+ big_image ? 'b' : ' ', (u32)load_address, kernel_size);
memmove(load_address, image + setup_size, kernel_size);
regs.xss = regs.xds;
regs.esp = 0x9000;
regs.eflags = 0;
- enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s);
+ enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s,
+ ®s);
}
-int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
void *base_ptr;
void *bzImage_addr = NULL;
bzImage_size = simple_strtoul(argv[2], NULL, 16);
/* Lets look for*/
- base_ptr = load_zimage (bzImage_addr, bzImage_size, 0, 0, 0);
+ base_ptr = load_zimage(bzImage_addr, bzImage_size, 0, 0, 0);
- if (NULL == base_ptr) {
- printf ("## Kernel loading failed ...\n");
+ if (!base_ptr) {
+ printf("## Kernel loading failed ...\n");
} else {
- printf ("## Transferring control to Linux (at address %08x) ...\n",
+ printf("## Transferring control to Linux (at address %08x) ...\n",
(u32)base_ptr);
/* we assume that the kernel is in place */
#include "../include/mv_gen_reg.h"
#include <net.h>
#include <netdev.h>
+#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
void debug_led (int led, int mode)
{
volatile int *addr = 0;
- int dummy;
+ __maybe_unused int dummy;
if (mode == 1) {
switch (led) {
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
unsigned int port_num;
- u32 port_status, phy_reg_data;
+ u32 phy_reg_data;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
/* ronen - when we update the MAC env params we only update dev->enetaddr
*/
MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
- port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+ MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
/* Check Link status on phy */
eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
int mv64360_eth_stop (struct eth_device *dev)
{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
/* Disable all gigE address decoder */
MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
- unsigned int port_num;
PKT_INFO pkt_info;
ETH_FUNC_RET_STATUS status;
struct net_device_stats *stats;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
- unsigned int port_num;
PKT_INFO pkt_info;
struct net_device_stats *stats;
-
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
- unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
mv64360_eth_update_stat (dev);
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
struct net_device_stats *stats;
- unsigned int port_num;
- volatile unsigned int dummy;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
* But the unsigned long in PowerPC and MIPS are 32bit. So the next read
* is just a dummy read for proper work of the GigE port
*/
- dummy = eth_read_mib_counter (ethernet_private->port_num,
+ eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
stats->tx_bytes += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_LOW);
- dummy = eth_read_mib_counter (ethernet_private->port_num,
+ eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_HIGH);
stats->rx_errors += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
struct net_device_stats *stats;
- unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
static void eth_clear_mib_counters (ETH_PORT eth_port_num)
{
int i;
- unsigned int dummy;
/* Perform dummy reads from MIB counters */
for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
i += 4)
- dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
- (eth_port_num) + i));
+ MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
return;
}
DECLARE_GLOBAL_DATA_PTR;
-#undef DEBUG
#define MAP_PCI
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
int set_dfcdlInit (void); /* setup delay line of Mv64360 */
int mvDmaIsChannelActive (int);
int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
#else
uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
int ret;
- unsigned int i, j, density = 1, devicesForErrCheck = 0;
+ unsigned int i, j, density = 1;
#ifdef DEBUG
unsigned int k;
uchar supp_cal, cal_val;
ulong memclk, tmemclk;
ulong tmp;
- uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+ uchar trp_clocks = 0, tras_clocks;
uchar data[128];
memclk = gd->bus_clk;
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
- DP (puts ("before i2c read\n"));
+ debug("before i2c read\n");
ret = i2c_read (addr, 0, 1, data, 128);
- DP (puts ("after i2c read\n"));
+ debug("after i2c read\n");
/* zero all the values */
memset (dimmInfo, 0, sizeof (*dimmInfo));
}
if (ret) {
- DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+ debug("No DIMM in slot %d [err = %x]\n", slot, ret);
return 0;
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
switch (i) {
case 2: /* Memory type (DDR / SDRAM) */
dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
-#ifdef DEBUG
if (dimmInfo->memoryType == 0)
- DP (printf
+ debug
("Dram_type in slot %d is: SDRAM\n",
- dimmInfo->slot));
+ dimmInfo->slot);
if (dimmInfo->memoryType == 1)
- DP (printf
+ debug
("Dram_type in slot %d is: DDRAM\n",
- dimmInfo->slot));
-#endif
+ dimmInfo->slot);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 3: /* Number Of Row Addresses */
dimmInfo->numOfRowAddresses = data[i];
- DP (printf
+ debug
("Module Number of row addresses: %d\n",
- dimmInfo->numOfRowAddresses));
+ dimmInfo->numOfRowAddresses);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 4: /* Number Of Column Addresses */
dimmInfo->numOfColAddresses = data[i];
- DP (printf
+ debug
("Module Number of col addresses: %d\n",
- dimmInfo->numOfColAddresses));
+ dimmInfo->numOfColAddresses);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 5: /* Number Of Module Banks */
dimmInfo->numOfModuleBanks = data[i];
- DP (printf
+ debug
("Number of Banks on Mod. : %d\n",
- dimmInfo->numOfModuleBanks));
+ dimmInfo->numOfModuleBanks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 6: /* Data Width */
dimmInfo->dataWidth = data[i];
- DP (printf
+ debug
("Module Data Width: %d\n",
- dimmInfo->dataWidth));
+ dimmInfo->dataWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
switch (data[i]) {
case 0x0:
dimmInfo->voltageInterface = TTL_5V_TOLERANT;
- DP (printf
- ("Module is TTL_5V_TOLERANT\n"));
+ debug
+ ("Module is TTL_5V_TOLERANT\n");
break;
case 0x1:
dimmInfo->voltageInterface = LVTTL;
- DP (printf
- ("Module is LVTTL\n"));
+ debug
+ ("Module is LVTTL\n");
break;
case 0x2:
dimmInfo->voltageInterface = HSTL_1_5V;
- DP (printf
- ("Module is TTL_5V_TOLERANT\n"));
+ debug
+ ("Module is TTL_5V_TOLERANT\n");
break;
case 0x3:
dimmInfo->voltageInterface = SSTL_3_3V;
- DP (printf
- ("Module is HSTL_1_5V\n"));
+ debug
+ ("Module is HSTL_1_5V\n");
break;
case 0x4:
dimmInfo->voltageInterface = SSTL_2_5V;
- DP (printf
- ("Module is SSTL_2_5V\n"));
+ debug
+ ("Module is SSTL_2_5V\n");
break;
default:
dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
- DP (printf
- ("Module is VOLTAGE_UNKNOWN\n"));
+ debug
+ ("Module is VOLTAGE_UNKNOWN\n");
break;
}
break;
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
rightOfPoint;
- DP (printf
+ debug
("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
- leftOfPoint, rightOfPoint));
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOut_LoP = leftOfPoint;
dimmInfo->clockToDataOut_RoP = rightOfPoint;
- DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */
+ debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
/*#ifdef CONFIG_ECC */
case 11: /* Error Check Type */
dimmInfo->errorCheckType = data[i];
- DP (printf
+ debug
("Error Check Type (0=NONE): %d\n",
- dimmInfo->errorCheckType));
+ dimmInfo->errorCheckType);
break;
/* #endif */
/*------------------------------------------------------------------------------------------------------------------------------*/
case 12: /* Refresh Interval */
dimmInfo->RefreshInterval = data[i];
- DP (printf
+ debug
("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
- dimmInfo->RefreshInterval));
+ dimmInfo->RefreshInterval);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 13: /* Sdram Width */
dimmInfo->sdramWidth = data[i];
- DP (printf
+ debug
("Sdram Width: %d\n",
- dimmInfo->sdramWidth));
+ dimmInfo->sdramWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 14: /* Error Check Data Width */
dimmInfo->errorCheckDataWidth = data[i];
- DP (printf
+ debug
("Error Check Data Width: %d\n",
- dimmInfo->errorCheckDataWidth));
+ dimmInfo->errorCheckDataWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 15: /* Minimum Clock Delay */
dimmInfo->minClkDelay = data[i];
- DP (printf
+ debug
("Minimum Clock Delay: %d\n",
- dimmInfo->minClkDelay));
+ dimmInfo->minClkDelay);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
dimmInfo->burstLengthSupported = data[i];
#ifdef DEBUG
- DP (printf
- ("Burst Length Supported: "));
+ debug
+ ("Burst Length Supported: ");
if (dimmInfo->burstLengthSupported & 0x01)
- DP (printf ("1, "));
+ debug("1, ");
if (dimmInfo->burstLengthSupported & 0x02)
- DP (printf ("2, "));
+ debug("2, ");
if (dimmInfo->burstLengthSupported & 0x04)
- DP (printf ("4, "));
+ debug("4, ");
if (dimmInfo->burstLengthSupported & 0x08)
- DP (printf ("8, "));
- DP (printf (" Bit \n"));
+ debug("8, ");
+ debug(" Bit \n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 17: /* Number Of Banks On Each Device */
dimmInfo->numOfBanksOnEachDevice = data[i];
- DP (printf
+ debug
("Number Of Banks On Each Chip: %d\n",
- dimmInfo->numOfBanksOnEachDevice));
+ dimmInfo->numOfBanksOnEachDevice);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
********************************************************/
dimmInfo->suportedCasLatencies = data[i];
#ifdef DEBUG
- DP (printf
- ("Suported Cas Latencies: (CL) "));
+ debug
+ ("Suported Cas Latencies: (CL) ");
if (dimmInfo->memoryType == 0) { /* SDRAM */
for (k = 0; k <= 7; k++) {
if (dimmInfo->
suportedCasLatencies & (1 << k))
- DP (printf
+ debug
("%d, ",
- k + 1));
+ k + 1);
}
} else { /* DDR-RAM */
if (dimmInfo->suportedCasLatencies & 1)
- DP (printf ("1, "));
+ debug("1, ");
if (dimmInfo->suportedCasLatencies & 2)
- DP (printf ("1.5, "));
+ debug("1.5, ");
if (dimmInfo->suportedCasLatencies & 4)
- DP (printf ("2, "));
+ debug("2, ");
if (dimmInfo->suportedCasLatencies & 8)
- DP (printf ("2.5, "));
+ debug("2.5, ");
if (dimmInfo->suportedCasLatencies & 16)
- DP (printf ("3, "));
+ debug("3, ");
if (dimmInfo->suportedCasLatencies & 32)
- DP (printf ("3.5, "));
+ debug("3.5, ");
}
- DP (printf ("\n"));
+ debug("\n");
#endif
/* Calculating MAX CAS latency */
for (j = 7; j > 0; j--) {
/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
switch (j) {
case 7:
- DP (printf
- ("Max. Cas Latencies (DDR): ERROR !!!\n"));
+ debug
+ ("Max. Cas Latencies (DDR): ERROR !!!\n");
dimmInfo->
maxClSupported_DDR
=
hang ();
break;
case 6:
- DP (printf
- ("Max. Cas Latencies (DDR): ERROR !!!\n"));
+ debug
+ ("Max. Cas Latencies (DDR): ERROR !!!\n");
dimmInfo->
maxClSupported_DDR
=
hang ();
break;
case 5:
- DP (printf
- ("Max. Cas Latencies (DDR): 3.5 clk's\n"));
+ debug
+ ("Max. Cas Latencies (DDR): 3.5 clk's\n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_3_5;
break;
case 4:
- DP (printf
- ("Max. Cas Latencies (DDR): 3 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 3 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_3;
break;
case 3:
- DP (printf
- ("Max. Cas Latencies (DDR): 2.5 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 2.5 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_2_5;
break;
case 2:
- DP (printf
- ("Max. Cas Latencies (DDR): 2 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 2 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_2;
break;
case 1:
- DP (printf
- ("Max. Cas Latencies (DDR): 1.5 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 1.5 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_1_5;
dimmInfo->
maxClSupported_DDR
>> 1;
- DP (printf
- ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
+ debug
+ ("*** Change actual Cas Latencies cause of minimumCycleTime n");
}
/* ronen - checkif the Dimm frequency compared to the Sysclock. */
if ((dimmInfo->
dimmInfo->
maxCASlatencySupported_RoP
= 0;
- DP (printf
+ debug
("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
dimmInfo->
maxCASlatencySupported_LoP,
dimmInfo->
- maxCASlatencySupported_RoP));
+ maxCASlatencySupported_RoP);
break;
case SDRAM:
/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
- DP (printf
+ debug
("Max. Cas Latencies (SD): %d\n",
dimmInfo->
- maxClSupported_SD));
+ maxClSupported_SD);
dimmInfo->
maxCASlatencySupported_LoP
= j;
dimmInfo->
maxCASlatencySupported_RoP
= 0;
- DP (printf
+ debug
("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
dimmInfo->
maxCASlatencySupported_LoP,
dimmInfo->
- maxCASlatencySupported_RoP));
+ maxCASlatencySupported_RoP);
break;
}
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 21: /* Buffered Address And Control Inputs */
- DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+ debug("\nModul Attributes (SPD Byte 21): \n");
dimmInfo->bufferedAddrAndControlInputs =
data[i] & BIT0;
dimmInfo->registeredAddrAndControlInputs =
(data[i] & BIT6) >> 6;
#ifdef DEBUG
if (dimmInfo->bufferedAddrAndControlInputs == 1)
- DP (printf
- (" - Buffered Address/Control Input: Yes \n"));
+ debug
+ (" - Buffered Address/Control Input: Yes \n");
else
- DP (printf
- (" - Buffered Address/Control Input: No \n"));
+ debug
+ (" - Buffered Address/Control Input: No \n");
if (dimmInfo->registeredAddrAndControlInputs == 1)
- DP (printf
- (" - Registered Address/Control Input: Yes \n"));
+ debug
+ (" - Registered Address/Control Input: Yes \n");
else
- DP (printf
- (" - Registered Address/Control Input: No \n"));
+ debug
+ (" - Registered Address/Control Input: No \n");
if (dimmInfo->onCardPLL == 1)
- DP (printf
- (" - On-Card PLL (clock): Yes \n"));
+ debug
+ (" - On-Card PLL (clock): Yes \n");
else
- DP (printf
- (" - On-Card PLL (clock): No \n"));
+ debug
+ (" - On-Card PLL (clock): No \n");
if (dimmInfo->bufferedDQMBinputs == 1)
- DP (printf
- (" - Bufferd DQMB Inputs: Yes \n"));
+ debug
+ (" - Bufferd DQMB Inputs: Yes \n");
else
- DP (printf
- (" - Bufferd DQMB Inputs: No \n"));
+ debug
+ (" - Bufferd DQMB Inputs: No \n");
if (dimmInfo->registeredDQMBinputs == 1)
- DP (printf
- (" - Registered DQMB Inputs: Yes \n"));
+ debug
+ (" - Registered DQMB Inputs: Yes \n");
else
- DP (printf
- (" - Registered DQMB Inputs: No \n"));
+ debug
+ (" - Registered DQMB Inputs: No \n");
if (dimmInfo->differentialClockInput == 1)
- DP (printf
- (" - Differential Clock Input: Yes \n"));
+ debug
+ (" - Differential Clock Input: Yes \n");
else
- DP (printf
- (" - Differential Clock Input: No \n"));
+ debug
+ (" - Differential Clock Input: No \n");
if (dimmInfo->redundantRowAddressing == 1)
- DP (printf
- (" - redundant Row Addressing: Yes \n"));
+ debug
+ (" - redundant Row Addressing: Yes \n");
else
- DP (printf
- (" - redundant Row Addressing: No \n"));
+ debug
+ (" - redundant Row Addressing: No \n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 22: /* Suported AutoPreCharge */
- DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+ debug("\nModul Attributes (SPD Byte 22): \n");
dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
dimmInfo->suportedAutoPreCharge =
(data[i] & BIT1) >> 1;
(data[i] & BIT5) >> 5;
#ifdef DEBUG
if (dimmInfo->suportedEarlyRasPreCharge == 1)
- DP (printf
- (" - Early Ras Precharge: Yes \n"));
+ debug
+ (" - Early Ras Precharge: Yes \n");
else
- DP (printf
- (" - Early Ras Precharge: No \n"));
+ debug
+ (" - Early Ras Precharge: No \n");
if (dimmInfo->suportedAutoPreCharge == 1)
- DP (printf
- (" - AutoPreCharge: Yes \n"));
+ debug
+ (" - AutoPreCharge: Yes \n");
else
- DP (printf
- (" - AutoPreCharge: No \n"));
+ debug
+ (" - AutoPreCharge: No \n");
if (dimmInfo->suportedPreChargeAll == 1)
- DP (printf
- (" - Precharge All: Yes \n"));
+ debug
+ (" - Precharge All: Yes \n");
else
- DP (printf
- (" - Precharge All: No \n"));
+ debug
+ (" - Precharge All: No \n");
if (dimmInfo->suportedWrite1ReadBurst == 1)
- DP (printf
- (" - Write 1/ReadBurst: Yes \n"));
+ debug
+ (" - Write 1/ReadBurst: Yes \n");
else
- DP (printf
- (" - Write 1/ReadBurst: No \n"));
+ debug
+ (" - Write 1/ReadBurst: No \n");
if (dimmInfo->suported5PercentLowVCC == 1)
- DP (printf
- (" - lower VCC tolerance: 5 Percent \n"));
+ debug
+ (" - lower VCC tolerance: 5 Percent \n");
else
- DP (printf
- (" - lower VCC tolerance: 10 Percent \n"));
+ debug
+ (" - lower VCC tolerance: 10 Percent \n");
if (dimmInfo->suported5PercentUpperVCC == 1)
- DP (printf
- (" - upper VCC tolerance: 5 Percent \n"));
+ debug
+ (" - upper VCC tolerance: 5 Percent \n");
else
- DP (printf
- (" - upper VCC tolerance: 10 Percent \n"));
+ debug
+ (" - upper VCC tolerance: 10 Percent \n");
#endif
break;
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
rightOfPoint;
- DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+ debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
- DP (printf
+ debug
("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
rightOfPoint;
- DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+ debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
- DP (printf
+ debug
("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
trp_clocks =
(dimmInfo->minRowPrechargeTime +
(tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
- tmemclk, tmemclk / 100, tmemclk % 100));
- DP (printf
+ tmemclk, tmemclk / 100, tmemclk % 100);
+ debug
("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- trrd_clocks =
- (dimmInfo->minRowActiveRowActiveDelay +
- (tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- trcd_clocks =
- (dimmInfo->minRowActiveRowActiveDelay +
- (tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
tras_clocks =
(NSto10PS (data[i]) +
(tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
- dimmInfo->minRasPulseWidth, tras_clocks));
+ dimmInfo->minRasPulseWidth, tras_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 31: /* Module Bank Density */
dimmInfo->moduleBankDensity = data[i];
- DP (printf
+ debug
("Module Bank Density: %d\n",
- dimmInfo->moduleBankDensity));
+ dimmInfo->moduleBankDensity);
#ifdef DEBUG
- DP (printf
- ("*** Offered Densities (more than 1 = Multisize-Module): "));
+ debug
+ ("*** Offered Densities (more than 1 = Multisize-Module): ");
{
if (dimmInfo->moduleBankDensity & 1)
- DP (printf ("4MB, "));
+ debug("4MB, ");
if (dimmInfo->moduleBankDensity & 2)
- DP (printf ("8MB, "));
+ debug("8MB, ");
if (dimmInfo->moduleBankDensity & 4)
- DP (printf ("16MB, "));
+ debug("16MB, ");
if (dimmInfo->moduleBankDensity & 8)
- DP (printf ("32MB, "));
+ debug("32MB, ");
if (dimmInfo->moduleBankDensity & 16)
- DP (printf ("64MB, "));
+ debug("64MB, ");
if (dimmInfo->moduleBankDensity & 32)
- DP (printf ("128MB, "));
+ debug("128MB, ");
if ((dimmInfo->moduleBankDensity & 64)
|| (dimmInfo->moduleBankDensity & 128)) {
- DP (printf ("ERROR, "));
+ debug("ERROR, ");
hang ();
}
}
- DP (printf ("\n"));
+ debug("\n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->addrAndCommandSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Address And Command Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->addrAndCommandHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Address And Command Hold Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->dataInputSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Data Input Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->dataInputHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Data Input Hold Time [ns]: %d.%d\n\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->numberOfDevices =
(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
dimmInfo->numOfModuleBanks;
- devicesForErrCheck =
- (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
if ((dimmInfo->errorCheckType == 0x1)
|| (dimmInfo->errorCheckType == 0x2)
|| (dimmInfo->errorCheckType == 0x3)) {
tmp *= dimmInfo->sdramWidth;
tmp = tmp >> 24; /* div by 0x4000000 (64M) */
dimmInfo->drb_size = (uchar) tmp;
- DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+ debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
/* try a CAS latency of 3 first... */
cal_val = 2;
}
- DP (printf ("cal_val = %d\n", cal_val));
+ debug("cal_val = %d\n", cal_val);
/* bummer, did't work... */
if (cal_val == 0) {
- DP (printf ("Couldn't find a good CAS latency\n"));
+ debug("Couldn't find a good CAS latency\n");
hang ();
return 0;
}
/* delay line */
set_dfcdlInit (); /* may be its not needed */
- DP (printf ("Delay line set done\n"));
+ debug("Delay line set done\n");
/* set SDRAM mode NOP */ /* To_do check it */
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+ debug
+ ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
}
/* SDRAM configuration */
hang ();
break;
}
- DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
+ debug("calculated refresh interval %0x\n", sdram_config_reg);
/* make sure the refresh value is only 14 bits */
if (sdram_config_reg > 0x1fff)
sdram_config_reg = 0x1fff;
- DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
+ debug("adjusted refresh interval %0x\n", sdram_config_reg);
/* we want physical bank interleaving and */
/* virtual bank interleaving enabled so do nothing */
if (info->registeredAddrAndControlInputs == 1) {
/* it's registered DRAM, so set the reg. DRAM bit */
sdram_config_reg = sdram_config_reg | BIT17;
- DP (printf ("Enabling registered DRAM bit\n"));
+ debug("Enabling registered DRAM bit\n");
}
/* turn on DRAM ECC? */
#ifdef CONFIG_MV64360_ECC
if (info->errorCheckType == 0x2) {
/* DRAM has ECC, so turn it on */
sdram_config_reg = sdram_config_reg | BIT18;
- DP (printf ("Enabling ECC\n"));
+ debug("Enabling ECC\n");
}
#endif
/* set the data DQS pin configuration */
switch (info->sdramWidth) {
case 0x4: /* memory is x4 */
sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
- DP (printf ("Data DQS pins set for 16 pins\n"));
+ debug("Data DQS pins set for 16 pins\n");
break;
case 0x8: /* memory is x8 or x16 */
case 0x10:
sdram_config_reg = sdram_config_reg | BIT21;
- DP (printf ("Data DQS pins set for 8 pins\n"));
+ debug("Data DQS pins set for 8 pins\n");
break;
case 0x20: /* memory is x32 */
/* both bits are cleared for x32 so nothing to do */
- DP (printf ("Data DQS pins set for 2 pins\n"));
+ debug("Data DQS pins set for 2 pins\n");
break;
default: /* memory width unsupported */
printf ("DRAM chip width is unknown!\n");
/* write the value into the SDRAM configuration register */
GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
- DP (printf
+ debug
("OOOOOOOOO sdram_conf 0x1400: %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
+ GTREGREAD (SDRAM_CONFIG));
/* SDRAM open pages control keep open as much as I can */
GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
- DP (printf
+ debug
("sdram_open_pages_controll 0x1414: %08x\n",
- GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+ GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
if (tmp == 0)
- DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+ debug("Core Signals are sync (by HW-Setting)!!!\n");
else
- DP (printf
- ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+ debug
+ ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
/* SDRAM set CAS Latency according to SPD information */
switch (info->memoryType) {
/* Calculate the settings for SDRAM mode and Dunit control low registers */
/* Values set according to technical bulletin TB-92 rev. c */
case DDR:
- DP (printf ("### SET-CL for DDR-RAM\n"));
+ debug("### SET-CL for DDR-RAM\n");
switch (info->maxClSupported_DDR) {
case DDR_CL_3:
tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
tmp_dunit_control_low = 0x05110051;
else
tmp_dunit_control_low = 0x24110051;
- DP (printf
+ debug
("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
tmp_dunit_control_low = 0x2C1107F2;
else
tmp_dunit_control_low = 0x3C1107d2;
- DP (printf
+ debug
("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
case DDR_CL_2_5:
tmp_dunit_control_low = 0x25110051;
else
tmp_dunit_control_low = 0x24110051;
- DP (printf
+ debug
("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
hang ();
} else
tmp_dunit_control_low = 0x1B1107d2;
- DP (printf
+ debug
("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
case DDR_CL_2:
tmp_dunit_control_low = 0x04110051;
else
tmp_dunit_control_low = 0x03110051;
- DP (printf
+ debug
("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
hang ();
} else
tmp_dunit_control_low = 0x3B1107d2;
- DP (printf
+ debug
("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
case DDR_CL_1_5:
tmp_dunit_control_low = 0x24110051;
else
tmp_dunit_control_low = 0x23110051;
- DP (printf
+ debug
("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
hang ();
} else
tmp_dunit_control_low = 0x1A1107d2;
- DP (printf
+ debug
("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
/* set SDRAM mode SetCommand 0x1418 */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug
+ ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
/* set SDRAM mode SetCommand 0x1418 */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+ debug
+ ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
}
/*------------------------------------------------------------------------------ */
/* program this with the default value */
tmp = 0x02; /* power-up default address select decoding value */
- DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+ debug("drb_size (n*64Mbit): %d\n", info->drb_size);
/* figure out the DRAM chip size */
sdram_chip_size =
(1 << (info->numOfRowAddresses + info->numOfColAddresses));
sdram_chip_size *= info->sdramWidth;
sdram_chip_size *= 4;
- DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
+ debug("computed sdram chip size is %#lx\n", sdram_chip_size);
/* divide sdram chip size by 64 Mbits */
sdram_chip_size = sdram_chip_size / 0x4000000;
switch (sdram_chip_size) {
case 1: /* 64 Mbit */
case 2: /* 128 Mbit */
- DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+ debug("RAM-Device_size 64Mbit or 128Mbit)\n");
tmp |= (0x00 << 4);
break;
case 4: /* 256 Mbit */
case 8: /* 512 Mbit */
- DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+ debug("RAM-Device_size 256Mbit or 512Mbit)\n");
tmp |= (0x01 << 4);
break;
case 16: /* 1 Gbit */
case 32: /* 2 Gbit */
- DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+ debug("RAM-Device_size 1Gbit or 2Gbit)\n");
tmp |= (0x02 << 4);
break;
default:
/* SDRAM address control */
GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
- DP (printf
+ debug
("setting up sdram address control (0x1410) with: %08lx \n",
- tmp));
+ tmp);
/* ------------------------------------------------------------------------------ */
/* same settings for registerd & non-registerd DDR SDRAM */
- DP (printf
+ debug
("setting up sdram_timing_control_low (0x1408) with: %08x \n",
- 0x11511220));
+ 0x11511220);
GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
if (info->registeredAddrAndControlInputs
|| info->registeredDQMBinputs) {
tmp |= (1 << 17);
- DP (printf
+ debug
("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
info->registeredAddrAndControlInputs,
- info->registeredDQMBinputs));
+ info->registeredDQMBinputs);
}
/* Use buffer 1 to return read data to the CPU
* Page 426 MV64360 */
tmp |= (1 << 26);
- DP (printf
+ debug
("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
- DP (printf
+ GTREGREAD (SDRAM_CONFIG));
+ debug
("After Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
+ GTREGREAD (SDRAM_CONFIG));
/* SDRAM timing To_do: */
/* ------------------------------------------------------------------------------ */
- DP (printf
+ debug
("setting up sdram_timing_control_high (0x140c) with: %08x \n",
- 0x9));
+ 0x9);
GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
- DP (printf
+ debug
("setting up sdram address pads control (0x14c0) with: %08x \n",
- 0x7d5014a));
+ 0x7d5014a);
GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
- DP (printf
- indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *"
-
-indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *"
-
+ debug
("setting up sdram data pads control (0x14c4) with: %08x \n",
- 0x7d5014a));
+ 0x7d5014a);
GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
/* ------------------------------------------------------------------------------ */
/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
{
i = info->slot;
- DP (printf
- ("\n*** Running a MRS cycle for bank %d ***\n", i));
+ debug
+ ("\n*** Running a MRS cycle for bank %d ***\n", i);
/* map the bank */
memory_map_bank (i, 0, GB / 4);
/* set SDRAM mode */ /* To_do check it */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
check = GTREGREAD (SDRAM_OPERATION);
- DP (printf
+ debug
("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check));
+ check);
/* switch back to normal operation mode */
GT_REG_WRITE (SDRAM_OPERATION, 0);
check = GTREGREAD (SDRAM_OPERATION);
- DP (printf
+ debug
("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check));
+ check);
/* unmap the bank */
memory_map_bank (i, 0, 0);
*b = save2;
if (val != cnt) {
- DP (printf
+ debug
("Found %08x at Address %08x (failure)\n",
- (unsigned int) val, (unsigned int) addr));
+ (unsigned int) val, (unsigned int) addr);
/* fix boundary condition.. STARTVAL means zero */
if (cnt == STARTVAL / sizeof (long))
cnt = 0;
* controlling logic happens */
phys_size_t initdram (int board_type)
{
- int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };
- ulong realsize, total, check;
+ ulong realsize, total;
AUX_MEM_DIMM_INFO dimmInfo1;
AUX_MEM_DIMM_INFO dimmInfo2;
int nhr, bank_no;
printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
} else {
/* DIMM0 */
- s0 = check_dimm (0, &dimmInfo1);
+ check_dimm (0, &dimmInfo1);
/* DIMM1 */
- s1 = check_dimm (1, &dimmInfo2);
+ check_dimm (1, &dimmInfo2);
memory_map_bank (0, 0, 0);
memory_map_bank (1, 0, 0);
/* next, size the SDRAM banks */
realsize = total = 0;
- check = GB / 4;
if (dimmInfo1.numOfModuleBanks > 0) {
checkbank[0] = 1;
}
#include "../include/mv_gen_reg.h"
#include <net.h>
#include <netdev.h>
+#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
void debug_led (int led, int mode)
{
volatile int *addr = 0;
- int dummy;
+ __maybe_unused int dummy;
if (mode == 1) {
switch (led) {
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
unsigned int port_num;
- u32 port_status, phy_reg_data;
+ u32 phy_reg_data;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
/* ronen - when we update the MAC env params we only update dev->enetaddr
*/
MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
- port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+ MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
/* Check Link status on phy */
eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
int mv64460_eth_stop (struct eth_device *dev)
{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
/* Disable all gigE address decoder */
MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
- unsigned int port_num;
PKT_INFO pkt_info;
ETH_FUNC_RET_STATUS status;
struct net_device_stats *stats;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
- unsigned int port_num;
PKT_INFO pkt_info;
struct net_device_stats *stats;
-
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
- unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
mv64460_eth_update_stat (dev);
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
struct net_device_stats *stats;
- unsigned int port_num;
- volatile unsigned int dummy;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
* But the unsigned long in PowerPC and MIPS are 32bit. So the next read
* is just a dummy read for proper work of the GigE port
*/
- dummy = eth_read_mib_counter (ethernet_private->port_num,
+ eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
stats->tx_bytes += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_LOW);
- dummy = eth_read_mib_counter (ethernet_private->port_num,
+ eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_HIGH);
stats->rx_errors += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
struct net_device_stats *stats;
- unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
static void eth_clear_mib_counters (ETH_PORT eth_port_num)
{
int i;
- unsigned int dummy;
/* Perform dummy reads from MIB counters */
for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
i += 4)
- dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
- (eth_port_num) + i));
+ MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
return;
}
DECLARE_GLOBAL_DATA_PTR;
-#undef DEBUG
#define MAP_PCI
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
int set_dfcdlInit (void); /* setup delay line of Mv64460 */
int mvDmaIsChannelActive (int);
int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
#endif
-#ifdef DEBUG
if (bankLength > 0) {
- printf ("mapping bank %d at %08x - %08x\n",
+ debug("mapping bank %d at %08x - %08x\n",
bankNo, bankBase, bankBase + bankLength - 1);
} else {
- printf ("unmapping bank %d\n", bankNo);
+ debug("unmapping bank %d\n", bankNo);
}
-#endif
memoryMapBank (bankNo, bankBase, bankLength);
#else
uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
int ret;
- unsigned int i, j, density = 1, devicesForErrCheck = 0;
+ unsigned int i, j, density = 1;
#ifdef DEBUG
unsigned int k;
uchar supp_cal, cal_val;
ulong memclk, tmemclk;
ulong tmp;
- uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+ uchar trp_clocks = 0, tras_clocks;
uchar data[128];
memclk = gd->bus_clk;
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
- DP (puts ("before i2c read\n"));
+ debug("before i2c read\n");
ret = i2c_read (addr, 0, 1, data, 128);
- DP (puts ("after i2c read\n"));
+ debug("after i2c read\n");
/* zero all the values */
memset (dimmInfo, 0, sizeof (*dimmInfo));
}
if (ret) {
- DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+ debug("No DIMM in slot %d [err = %x]\n", slot, ret);
return 0;
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
#ifdef DEBUG
if (dimmInfo->memoryType == 0)
- DP (printf
+ debug
("Dram_type in slot %d is: SDRAM\n",
- dimmInfo->slot));
+ dimmInfo->slot);
if (dimmInfo->memoryType == 1)
- DP (printf
+ debug
("Dram_type in slot %d is: DDRAM\n",
- dimmInfo->slot));
+ dimmInfo->slot);
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 3: /* Number Of Row Addresses */
dimmInfo->numOfRowAddresses = data[i];
- DP (printf
+ debug
("Module Number of row addresses: %d\n",
- dimmInfo->numOfRowAddresses));
+ dimmInfo->numOfRowAddresses);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 4: /* Number Of Column Addresses */
dimmInfo->numOfColAddresses = data[i];
- DP (printf
+ debug
("Module Number of col addresses: %d\n",
- dimmInfo->numOfColAddresses));
+ dimmInfo->numOfColAddresses);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 5: /* Number Of Module Banks */
dimmInfo->numOfModuleBanks = data[i];
- DP (printf
+ debug
("Number of Banks on Mod. : %d\n",
- dimmInfo->numOfModuleBanks));
+ dimmInfo->numOfModuleBanks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 6: /* Data Width */
dimmInfo->dataWidth = data[i];
- DP (printf
+ debug
("Module Data Width: %d\n",
- dimmInfo->dataWidth));
+ dimmInfo->dataWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
switch (data[i]) {
case 0x0:
dimmInfo->voltageInterface = TTL_5V_TOLERANT;
- DP (printf
- ("Module is TTL_5V_TOLERANT\n"));
+ debug
+ ("Module is TTL_5V_TOLERANT\n");
break;
case 0x1:
dimmInfo->voltageInterface = LVTTL;
- DP (printf
- ("Module is LVTTL\n"));
+ debug
+ ("Module is LVTTL\n");
break;
case 0x2:
dimmInfo->voltageInterface = HSTL_1_5V;
- DP (printf
- ("Module is TTL_5V_TOLERANT\n"));
+ debug
+ ("Module is TTL_5V_TOLERANT\n");
break;
case 0x3:
dimmInfo->voltageInterface = SSTL_3_3V;
- DP (printf
- ("Module is HSTL_1_5V\n"));
+ debug
+ ("Module is HSTL_1_5V\n");
break;
case 0x4:
dimmInfo->voltageInterface = SSTL_2_5V;
- DP (printf
- ("Module is SSTL_2_5V\n"));
+ debug
+ ("Module is SSTL_2_5V\n");
break;
default:
dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
- DP (printf
- ("Module is VOLTAGE_UNKNOWN\n"));
+ debug
+ ("Module is VOLTAGE_UNKNOWN\n");
break;
}
break;
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
rightOfPoint;
- DP (printf
+ debug
("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
- leftOfPoint, rightOfPoint));
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOut_LoP = leftOfPoint;
dimmInfo->clockToDataOut_RoP = rightOfPoint;
- DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */
+ debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
/*#ifdef CONFIG_ECC */
case 11: /* Error Check Type */
dimmInfo->errorCheckType = data[i];
- DP (printf
+ debug
("Error Check Type (0=NONE): %d\n",
- dimmInfo->errorCheckType));
+ dimmInfo->errorCheckType);
break;
/* #endif */
/*------------------------------------------------------------------------------------------------------------------------------*/
case 12: /* Refresh Interval */
dimmInfo->RefreshInterval = data[i];
- DP (printf
+ debug
("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
- dimmInfo->RefreshInterval));
+ dimmInfo->RefreshInterval);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 13: /* Sdram Width */
dimmInfo->sdramWidth = data[i];
- DP (printf
+ debug
("Sdram Width: %d\n",
- dimmInfo->sdramWidth));
+ dimmInfo->sdramWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 14: /* Error Check Data Width */
dimmInfo->errorCheckDataWidth = data[i];
- DP (printf
+ debug
("Error Check Data Width: %d\n",
- dimmInfo->errorCheckDataWidth));
+ dimmInfo->errorCheckDataWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 15: /* Minimum Clock Delay */
dimmInfo->minClkDelay = data[i];
- DP (printf
+ debug
("Minimum Clock Delay: %d\n",
- dimmInfo->minClkDelay));
+ dimmInfo->minClkDelay);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
dimmInfo->burstLengthSupported = data[i];
#ifdef DEBUG
- DP (printf
- ("Burst Length Supported: "));
+ debug
+ ("Burst Length Supported: ");
if (dimmInfo->burstLengthSupported & 0x01)
- DP (printf ("1, "));
+ debug("1, ");
if (dimmInfo->burstLengthSupported & 0x02)
- DP (printf ("2, "));
+ debug("2, ");
if (dimmInfo->burstLengthSupported & 0x04)
- DP (printf ("4, "));
+ debug("4, ");
if (dimmInfo->burstLengthSupported & 0x08)
- DP (printf ("8, "));
- DP (printf (" Bit \n"));
+ debug("8, ");
+ debug(" Bit \n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 17: /* Number Of Banks On Each Device */
dimmInfo->numOfBanksOnEachDevice = data[i];
- DP (printf
+ debug
("Number Of Banks On Each Chip: %d\n",
- dimmInfo->numOfBanksOnEachDevice));
+ dimmInfo->numOfBanksOnEachDevice);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
********************************************************/
dimmInfo->suportedCasLatencies = data[i];
#ifdef DEBUG
- DP (printf
- ("Suported Cas Latencies: (CL) "));
+ debug
+ ("Suported Cas Latencies: (CL) ");
if (dimmInfo->memoryType == 0) { /* SDRAM */
for (k = 0; k <= 7; k++) {
if (dimmInfo->
suportedCasLatencies & (1 << k))
- DP (printf
+ debug
("%d, ",
- k + 1));
+ k + 1);
}
} else { /* DDR-RAM */
if (dimmInfo->suportedCasLatencies & 1)
- DP (printf ("1, "));
+ debug("1, ");
if (dimmInfo->suportedCasLatencies & 2)
- DP (printf ("1.5, "));
+ debug("1.5, ");
if (dimmInfo->suportedCasLatencies & 4)
- DP (printf ("2, "));
+ debug("2, ");
if (dimmInfo->suportedCasLatencies & 8)
- DP (printf ("2.5, "));
+ debug("2.5, ");
if (dimmInfo->suportedCasLatencies & 16)
- DP (printf ("3, "));
+ debug("3, ");
if (dimmInfo->suportedCasLatencies & 32)
- DP (printf ("3.5, "));
+ debug("3.5, ");
}
- DP (printf ("\n"));
+ debug("\n");
#endif
/* Calculating MAX CAS latency */
for (j = 7; j > 0; j--) {
/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
switch (j) {
case 7:
- DP (printf
- ("Max. Cas Latencies (DDR): ERROR !!!\n"));
+ debug
+ ("Max. Cas Latencies (DDR): ERROR !!!\n");
dimmInfo->
maxClSupported_DDR
=
hang ();
break;
case 6:
- DP (printf
- ("Max. Cas Latencies (DDR): ERROR !!!\n"));
+ debug
+ ("Max. Cas Latencies (DDR): ERROR !!!\n");
dimmInfo->
maxClSupported_DDR
=
hang ();
break;
case 5:
- DP (printf
- ("Max. Cas Latencies (DDR): 3.5 clk's\n"));
+ debug
+ ("Max. Cas Latencies (DDR): 3.5 clk's\n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_3_5;
break;
case 4:
- DP (printf
- ("Max. Cas Latencies (DDR): 3 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 3 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_3;
break;
case 3:
- DP (printf
- ("Max. Cas Latencies (DDR): 2.5 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 2.5 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_2_5;
break;
case 2:
- DP (printf
- ("Max. Cas Latencies (DDR): 2 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 2 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_2;
break;
case 1:
- DP (printf
- ("Max. Cas Latencies (DDR): 1.5 clk's \n"));
+ debug
+ ("Max. Cas Latencies (DDR): 1.5 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_1_5;
dimmInfo->
maxClSupported_DDR
>> 1;
- DP (printf
- ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
+ debug
+ ("*** Change actual Cas Latencies cause of minimumCycleTime n");
}
/* ronen - checkif the Dimm frequency compared to the Sysclock. */
if ((dimmInfo->
dimmInfo->
maxCASlatencySupported_RoP
= 0;
- DP (printf
+ debug
("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
dimmInfo->
maxCASlatencySupported_LoP,
dimmInfo->
- maxCASlatencySupported_RoP));
+ maxCASlatencySupported_RoP);
break;
case SDRAM:
/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
- DP (printf
+ debug
("Max. Cas Latencies (SD): %d\n",
dimmInfo->
- maxClSupported_SD));
+ maxClSupported_SD);
dimmInfo->
maxCASlatencySupported_LoP
= j;
dimmInfo->
maxCASlatencySupported_RoP
= 0;
- DP (printf
+ debug
("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
dimmInfo->
maxCASlatencySupported_LoP,
dimmInfo->
- maxCASlatencySupported_RoP));
+ maxCASlatencySupported_RoP);
break;
}
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 21: /* Buffered Address And Control Inputs */
- DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+ debug("\nModul Attributes (SPD Byte 21): \n");
dimmInfo->bufferedAddrAndControlInputs =
data[i] & BIT0;
dimmInfo->registeredAddrAndControlInputs =
(data[i] & BIT6) >> 6;
#ifdef DEBUG
if (dimmInfo->bufferedAddrAndControlInputs == 1)
- DP (printf
- (" - Buffered Address/Control Input: Yes \n"));
+ debug
+ (" - Buffered Address/Control Input: Yes \n");
else
- DP (printf
- (" - Buffered Address/Control Input: No \n"));
+ debug
+ (" - Buffered Address/Control Input: No \n");
if (dimmInfo->registeredAddrAndControlInputs == 1)
- DP (printf
- (" - Registered Address/Control Input: Yes \n"));
+ debug
+ (" - Registered Address/Control Input: Yes \n");
else
- DP (printf
- (" - Registered Address/Control Input: No \n"));
+ debug
+ (" - Registered Address/Control Input: No \n");
if (dimmInfo->onCardPLL == 1)
- DP (printf
- (" - On-Card PLL (clock): Yes \n"));
+ debug
+ (" - On-Card PLL (clock): Yes \n");
else
- DP (printf
- (" - On-Card PLL (clock): No \n"));
+ debug
+ (" - On-Card PLL (clock): No \n");
if (dimmInfo->bufferedDQMBinputs == 1)
- DP (printf
- (" - Bufferd DQMB Inputs: Yes \n"));
+ debug
+ (" - Bufferd DQMB Inputs: Yes \n");
else
- DP (printf
- (" - Bufferd DQMB Inputs: No \n"));
+ debug
+ (" - Bufferd DQMB Inputs: No \n");
if (dimmInfo->registeredDQMBinputs == 1)
- DP (printf
- (" - Registered DQMB Inputs: Yes \n"));
+ debug
+ (" - Registered DQMB Inputs: Yes \n");
else
- DP (printf
- (" - Registered DQMB Inputs: No \n"));
+ debug
+ (" - Registered DQMB Inputs: No \n");
if (dimmInfo->differentialClockInput == 1)
- DP (printf
- (" - Differential Clock Input: Yes \n"));
+ debug
+ (" - Differential Clock Input: Yes \n");
else
- DP (printf
- (" - Differential Clock Input: No \n"));
+ debug
+ (" - Differential Clock Input: No \n");
if (dimmInfo->redundantRowAddressing == 1)
- DP (printf
- (" - redundant Row Addressing: Yes \n"));
+ debug
+ (" - redundant Row Addressing: Yes \n");
else
- DP (printf
- (" - redundant Row Addressing: No \n"));
+ debug
+ (" - redundant Row Addressing: No \n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 22: /* Suported AutoPreCharge */
- DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+ debug("\nModul Attributes (SPD Byte 22): \n");
dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
dimmInfo->suportedAutoPreCharge =
(data[i] & BIT1) >> 1;
(data[i] & BIT5) >> 5;
#ifdef DEBUG
if (dimmInfo->suportedEarlyRasPreCharge == 1)
- DP (printf
- (" - Early Ras Precharge: Yes \n"));
+ debug
+ (" - Early Ras Precharge: Yes \n");
else
- DP (printf
- (" - Early Ras Precharge: No \n"));
+ debug
+ (" - Early Ras Precharge: No \n");
if (dimmInfo->suportedAutoPreCharge == 1)
- DP (printf
- (" - AutoPreCharge: Yes \n"));
+ debug
+ (" - AutoPreCharge: Yes \n");
else
- DP (printf
- (" - AutoPreCharge: No \n"));
+ debug
+ (" - AutoPreCharge: No \n");
if (dimmInfo->suportedPreChargeAll == 1)
- DP (printf
- (" - Precharge All: Yes \n"));
+ debug
+ (" - Precharge All: Yes \n");
else
- DP (printf
- (" - Precharge All: No \n"));
+ debug
+ (" - Precharge All: No \n");
if (dimmInfo->suportedWrite1ReadBurst == 1)
- DP (printf
- (" - Write 1/ReadBurst: Yes \n"));
+ debug
+ (" - Write 1/ReadBurst: Yes \n");
else
- DP (printf
- (" - Write 1/ReadBurst: No \n"));
+ debug
+ (" - Write 1/ReadBurst: No \n");
if (dimmInfo->suported5PercentLowVCC == 1)
- DP (printf
- (" - lower VCC tolerance: 5 Percent \n"));
+ debug
+ (" - lower VCC tolerance: 5 Percent \n");
else
- DP (printf
- (" - lower VCC tolerance: 10 Percent \n"));
+ debug
+ (" - lower VCC tolerance: 10 Percent \n");
if (dimmInfo->suported5PercentUpperVCC == 1)
- DP (printf
- (" - upper VCC tolerance: 5 Percent \n"));
+ debug
+ (" - upper VCC tolerance: 5 Percent \n");
else
- DP (printf
- (" - upper VCC tolerance: 10 Percent \n"));
+ debug
+ (" - upper VCC tolerance: 10 Percent \n");
#endif
break;
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
rightOfPoint;
- DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+ debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
- DP (printf
+ debug
("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
rightOfPoint;
- DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+ debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
- DP (printf
+ debug
("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
trp_clocks =
(dimmInfo->minRowPrechargeTime +
(tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
- tmemclk, tmemclk / 100, tmemclk % 100));
- DP (printf
+ tmemclk, tmemclk / 100, tmemclk % 100);
+ debug
("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- trrd_clocks =
- (dimmInfo->minRowActiveRowActiveDelay +
- (tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- trcd_clocks =
- (dimmInfo->minRowActiveRowActiveDelay +
- (tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
tras_clocks =
(NSto10PS (data[i]) +
(tmemclk - 1)) / tmemclk;
- DP (printf
+ debug
("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
- dimmInfo->minRasPulseWidth, tras_clocks));
+ dimmInfo->minRasPulseWidth, tras_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 31: /* Module Bank Density */
dimmInfo->moduleBankDensity = data[i];
- DP (printf
+ debug
("Module Bank Density: %d\n",
- dimmInfo->moduleBankDensity));
+ dimmInfo->moduleBankDensity);
#ifdef DEBUG
- DP (printf
- ("*** Offered Densities (more than 1 = Multisize-Module): "));
+ debug
+ ("*** Offered Densities (more than 1 = Multisize-Module): ");
{
if (dimmInfo->moduleBankDensity & 1)
- DP (printf ("4MB, "));
+ debug("4MB, ");
if (dimmInfo->moduleBankDensity & 2)
- DP (printf ("8MB, "));
+ debug("8MB, ");
if (dimmInfo->moduleBankDensity & 4)
- DP (printf ("16MB, "));
+ debug("16MB, ");
if (dimmInfo->moduleBankDensity & 8)
- DP (printf ("32MB, "));
+ debug("32MB, ");
if (dimmInfo->moduleBankDensity & 16)
- DP (printf ("64MB, "));
+ debug("64MB, ");
if (dimmInfo->moduleBankDensity & 32)
- DP (printf ("128MB, "));
+ debug("128MB, ");
if ((dimmInfo->moduleBankDensity & 64)
|| (dimmInfo->moduleBankDensity & 128)) {
- DP (printf ("ERROR, "));
+ debug("ERROR, ");
hang ();
}
}
- DP (printf ("\n"));
+ debug("\n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->addrAndCommandSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Address And Command Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->addrAndCommandHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Address And Command Hold Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->dataInputSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Data Input Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->dataInputHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
+ debug
("Data Input Hold Time [ns]: %d.%d\n\n",
- sign * leftOfPoint, rightOfPoint));
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
dimmInfo->numberOfDevices =
(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
dimmInfo->numOfModuleBanks;
- devicesForErrCheck =
- (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
if ((dimmInfo->errorCheckType == 0x1)
|| (dimmInfo->errorCheckType == 0x2)
|| (dimmInfo->errorCheckType == 0x3)) {
tmp *= dimmInfo->sdramWidth;
tmp = tmp >> 24; /* div by 0x4000000 (64M) */
dimmInfo->drb_size = (uchar) tmp;
- DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+ debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
/* try a CAS latency of 3 first... */
cal_val = 2;
}
- DP (printf ("cal_val = %d\n", cal_val));
+ debug("cal_val = %d\n", cal_val);
/* bummer, did't work... */
if (cal_val == 0) {
- DP (printf ("Couldn't find a good CAS latency\n"));
+ debug("Couldn't find a good CAS latency\n");
hang ();
return 0;
}
/* delay line */
set_dfcdlInit (); /* may be its not needed */
- DP (printf ("Delay line set done\n"));
+ debug("Delay line set done\n");
/* set SDRAM mode NOP */ /* To_do check it */
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+ debug
+ ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
}
/* SDRAM configuration */
hang ();
break;
}
- DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
+ debug("calculated refresh interval %0x\n", sdram_config_reg);
/* make sure the refresh value is only 14 bits */
if (sdram_config_reg > 0x1fff)
sdram_config_reg = 0x1fff;
- DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
+ debug("adjusted refresh interval %0x\n", sdram_config_reg);
/* we want physical bank interleaving and */
/* virtual bank interleaving enabled so do nothing */
if (info->registeredAddrAndControlInputs == 1) {
/* it's registered DRAM, so set the reg. DRAM bit */
sdram_config_reg = sdram_config_reg | BIT17;
- DP (printf ("Enabling registered DRAM bit\n"));
+ debug("Enabling registered DRAM bit\n");
}
/* turn on DRAM ECC? */
#ifdef CONFIG_MV64460_ECC
if (info->errorCheckType == 0x2) {
/* DRAM has ECC, so turn it on */
sdram_config_reg = sdram_config_reg | BIT18;
- DP (printf ("Enabling ECC\n"));
+ debug("Enabling ECC\n");
}
#endif
/* set the data DQS pin configuration */
switch (info->sdramWidth) {
case 0x4: /* memory is x4 */
sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
- DP (printf ("Data DQS pins set for 16 pins\n"));
+ debug("Data DQS pins set for 16 pins\n");
break;
case 0x8: /* memory is x8 or x16 */
case 0x10:
sdram_config_reg = sdram_config_reg | BIT21;
- DP (printf ("Data DQS pins set for 8 pins\n"));
+ debug("Data DQS pins set for 8 pins\n");
break;
case 0x20: /* memory is x32 */
/* both bits are cleared for x32 so nothing to do */
- DP (printf ("Data DQS pins set for 2 pins\n"));
+ debug("Data DQS pins set for 2 pins\n");
break;
default: /* memory width unsupported */
printf ("DRAM chip width is unknown!\n");
/* write the value into the SDRAM configuration register */
GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
- DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
+ debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
/* SDRAM open pages control keep open as much as I can */
GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
- DP (printf
+ debug
("sdram_open_pages_controll 0x1414: %08x\n",
- GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+ GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
if (tmp == 0)
- DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+ debug("Core Signals are sync (by HW-Setting)!!!\n");
else
- DP (printf
- ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+ debug
+ ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
/* SDRAM set CAS Latency according to SPD information */
switch (info->memoryType) {
/* Calculate the settings for SDRAM mode and Dunit control low registers */
/* Values set according to technical bulletin TB-92 rev. c */
case DDR:
- DP (printf ("### SET-CL for DDR-RAM\n"));
+ debug("### SET-CL for DDR-RAM\n");
/* ronen db64460 - change the tmp_dunit_control_low setting!!! */
switch (info->maxClSupported_DDR) {
case DDR_CL_3:
tmp_dunit_control_low = 0x05110051;
else
tmp_dunit_control_low = 0x24110051;
- DP (printf
+ debug
("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
} else { /* clk sync. bypassed */
tmp_dunit_control_low = 0xC5000540;
else
tmp_dunit_control_low = 0xC4000540;
- DP (printf
+ debug
("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
case DDR_CL_2_5:
tmp_dunit_control_low = 0x25110051;
else
tmp_dunit_control_low = 0x24110051;
- DP (printf
+ debug
("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
} else { /* clk sync. bypassed */
/* hang();1 */
} else
tmp_dunit_control_low = 0xC4000540;
- DP (printf
+ debug
("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
case DDR_CL_2:
tmp_dunit_control_low = 0x04110051;
else
tmp_dunit_control_low = 0x03110051;
- DP (printf
+ debug
("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
} else { /* clk sync. bypassed */
tmp_dunit_control_low = 0xC4000540;
} else
tmp_dunit_control_low = 0xC3000540;;
- DP (printf
+ debug
("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
case DDR_CL_1_5:
tmp_dunit_control_low = 0x24110051;
else
tmp_dunit_control_low = 0x23110051;
- DP (printf
+ debug
("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
} else { /* clk sync. bypassed */
tmp_dunit_control_low = 0xC4000540;
} else
tmp_dunit_control_low = 0xC3000540;
- DP (printf
+ debug
("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
/* set SDRAM mode SetCommand 0x1418 */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug
+ ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
/* set SDRAM mode SetCommand 0x1418 */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+ debug
+ ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
}
/*------------------------------------------------------------------------------ */
/* program this with the default value */
tmp = 0x02; /* power-up default address select decoding value */
- DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+ debug("drb_size (n*64Mbit): %d\n", info->drb_size);
/* figure out the DRAM chip size */
sdram_chip_size =
(1 << (info->numOfRowAddresses + info->numOfColAddresses));
sdram_chip_size *= info->sdramWidth;
sdram_chip_size *= 4;
- DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
+ debug("computed sdram chip size is %#lx\n", sdram_chip_size);
/* divide sdram chip size by 64 Mbits */
sdram_chip_size = sdram_chip_size / 0x4000000;
switch (sdram_chip_size) {
case 1: /* 64 Mbit */
case 2: /* 128 Mbit */
- DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+ debug("RAM-Device_size 64Mbit or 128Mbit)\n");
tmp |= (0x00 << 4);
break;
case 4: /* 256 Mbit */
case 8: /* 512 Mbit */
- DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+ debug("RAM-Device_size 256Mbit or 512Mbit)\n");
tmp |= (0x01 << 4);
break;
case 16: /* 1 Gbit */
case 32: /* 2 Gbit */
- DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+ debug("RAM-Device_size 1Gbit or 2Gbit)\n");
tmp |= (0x02 << 4);
break;
default:
/* SDRAM address control */
GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
- DP (printf
+ debug
("setting up sdram address control (0x1410) with: %08lx \n",
- tmp));
+ tmp);
/* ------------------------------------------------------------------------------ */
/* same settings for registerd & non-registerd DDR SDRAM */
- DP (printf
+ debug
("setting up sdram_timing_control_low (0x1408) with: %08x \n",
- 0x01501220));
+ 0x01501220);
/*ronen db64460 */
GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
if (info->registeredAddrAndControlInputs
|| info->registeredDQMBinputs) {
tmp |= (1 << 17);
- DP (printf
+ debug
("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
info->registeredAddrAndControlInputs,
- info->registeredDQMBinputs));
+ info->registeredDQMBinputs);
}
/* Use buffer 1 to return read data to the CPU
4460 */
tmp |= (1 << 26);
- DP (printf
+ debug
("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
- DP (printf
+ GTREGREAD (SDRAM_CONFIG));
+ debug
("After Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
+ GTREGREAD (SDRAM_CONFIG));
/* SDRAM timing To_do: */
/* ------------------------------------------------------------------------------ */
/* ronen db64460 */
- DP (printf
+ debug
("setting up sdram_timing_control_high (0x140c) with: %08x \n",
- 0xc));
+ 0xc);
GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
- DP (printf
+ debug
("setting up sdram address pads control (0x14c0) with: %08x \n",
- 0x7d5014a));
+ 0x7d5014a);
GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
- DP (printf
+ debug
("setting up sdram data pads control (0x14c4) with: %08x \n",
- 0x7d5014a));
+ 0x7d5014a);
GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
/* ------------------------------------------------------------------------------ */
/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
{
i = info->slot;
- DP (printf
- ("\n*** Running a MRS cycle for bank %d ***\n", i));
+ debug
+ ("\n*** Running a MRS cycle for bank %d ***\n", i);
/* map the bank */
memory_map_bank (i, 0, GB / 4);
/* set SDRAM mode */ /* To_do check it */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
check = GTREGREAD (SDRAM_OPERATION);
- DP (printf
+ debug
("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check));
+ check);
/* switch back to normal operation mode */
GT_REG_WRITE (SDRAM_OPERATION, 0);
check = GTREGREAD (SDRAM_OPERATION);
- DP (printf
+ debug
("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check));
+ check);
/* unmap the bank */
memory_map_bank (i, 0, 0);
*b = save2;
if (val != cnt) {
- DP (printf
+ debug
("Found %08x at Address %08x (failure)\n",
- (unsigned int) val, (unsigned int) addr));
+ (unsigned int) val, (unsigned int) addr);
/* fix boundary condition.. STARTVAL means zero */
if (cnt == STARTVAL / sizeof (long))
cnt = 0;
* controlling logic happens */
phys_size_t initdram (int board_type)
{
- int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };
- ulong realsize, total, check;
+ ulong realsize, total;
AUX_MEM_DIMM_INFO dimmInfo1;
AUX_MEM_DIMM_INFO dimmInfo2;
int nhr, bank_no;
printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
} else {
/* DIMM0 */
- s0 = check_dimm (0, &dimmInfo1);
+ check_dimm (0, &dimmInfo1);
/* DIMM1 */
- s1 = check_dimm (1, &dimmInfo2);
+ check_dimm (1, &dimmInfo2);
memory_map_bank (0, 0, 0);
memory_map_bank (1, 0, 0);
/* next, size the SDRAM banks */
realsize = total = 0;
- check = GB / 4;
if (dimmInfo1.numOfModuleBanks > 0) {
checkbank[0] = 1;
}
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword)
{
-
- cfiptr_t ctladdr;
cfiptr_t cptr;
int flag;
- ctladdr.cp = flash_make_addr (info, 0, 0);
cptr.cp = (uchar *) dest;
/* Check if Flash is (sufficiently) erased */
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2);
+ addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+ printf("Erasing sector %p\n", addr2);
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7(info, sect);
}
}
* active low polarity on PIC interrupt pins,
* active high polarity on all other irq pins
*/
- writew(0x0000,&sc520_mmcr->intpinpol);
+ writew(0x0000, &sc520_mmcr->intpinpol);
/*
* PIT 0 -> IRQ0
void enet_timer_isr(void)
{
- static long enet_ticks = 0;
+ static long enet_ticks;
enet_ticks++;
void enet_toggle_run_led(void)
{
- unsigned char leds_state= inb(LED_LATCH_ADDRESS);
+ unsigned char leds_state = inb(LED_LATCH_ADDRESS);
if (leds_state & LED_RUN_BITMASK)
- outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
+ outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
else
outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
}
CONFIG_SYS_THIRD_PCI_IRQ,
CONFIG_SYS_FORTH_PCI_IRQ
};
- static int next_irq_index=0;
+ static int next_irq_index;
uchar tmp_pin;
int pin;
pin = tmp_pin;
pin -= 1; /* PCI config space use 1-based numbering */
- if (pin == -1) {
+ if (pin == -1)
return; /* device use no irq */
- }
/* map device number + pin to a pin on the sc520 */
switch (PCI_DEV(dev)) {
if (sc520_pci_ints[pin] == -1) {
/* re-route one interrupt for us */
- if (next_irq_index > 3) {
+ if (next_irq_index > 3)
return;
- }
- if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+
+ if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
return;
- }
+
next_irq_index++;
}
- if (-1 != sc520_pci_ints[pin]) {
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+ if (-1 != sc520_pci_ints[pin])
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
sc520_pci_ints[pin]);
- }
+
printf("fixup_irq: device %d pin %c irq %d\n",
PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
}
#include "config.h"
#include "hardware.h"
#include <asm/arch/sc520.h>
+#include <generated/asm-offsets.h>
.text
.section .start16, "ax"
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
- movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
+ movl $GENERATED_SC520_PAR14, %edi
movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
- movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
+ movl $GENERATED_SC520_PAR15, %edi
movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
movl %eax, (%di)
#include <common.h>
#include <commproc.h>
#include <mpc8xx.h>
+#include <asm/io.h>
/*****************************************************************************
* UPM table for 60ns EDO RAM at 25 MHz bus/external clock
*/
if ((ulong) initdram & 0xff000000) {
volatile uint *addr1, *addr2;
- uint i, j;
+ uint i;
upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
*/
addr1 = (volatile uint *) 0;
addr2 = (volatile uint *) 0x00400000;
- for (i = 0, j = 0; i < 8; i++)
- j = addr1[0];
+ for (i = 0; i < 8; i++)
+ in_be32(addr1);
/*
* Now check whether we got 4MB or 16MB populated
#if defined(CONFIG_PRAM)
#include <environment.h>
-extern env_t *env_ptr;
+#include <search.h>
+#include <errno.h>
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 param;
ulong *lptr;
+ env_t *envp;
+ char *res;
+ int len;
+
v = getenv("pram");
if (v)
pram = simple_strtoul(v, NULL, 10);
/* env is first (4k aligned) */
nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
- memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+ envp = (env_t *)nextbase;
+ res = (char *)envp->data;
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
+ if (len < 0) {
+ error("Cannot export environment: errno = %d\n", errno);
+ return 1;
+ }
+ envp->crc = crc32(0, envp->data, ENV_SIZE);
+
*(--lptr) = CONFIG_ENV_SIZE; /* size */
*(--lptr) = base - nextbase; /* offset | type=0 */
/* No error reporting */
pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
if (!is_monarch()) {
/* Program the board's subsystem id/classcode */
pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
static void wait_for_pci_ready(void)
{
- int i;
- char *s = getenv("pcidelay");
- /*
- * We have our own handling of the pcidelay variable.
- * Using CONFIG_PCI_BOOTDELAY enables pausing for host
- * and adapter devices. For adapter devices we do not
- * want this.
- */
- if (s) {
- int ms = simple_strtoul(s, NULL, 10);
- printf("PCI: Waiting for %d ms\n", ms);
- for (i=0; i<ms; i++)
- udelay(1000);
- }
-
if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
while (1) {
COBJS-$(CONFIG_FMAN_ENET) += fman.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
+COBJS-$(CONFIG_FSL_QIXIS) += qixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
+COBJS-$(CONFIG_P3060QDS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include "ics307_clk.h"
-#ifdef CONFIG_FSL_NGPIXIS
+#if defined(CONFIG_FSL_NGPIXIS)
#include "ngpixis.h"
+#define fpga_reg pixis
+#elif defined(CONFIG_FSL_QIXIS)
+#include "qixis.h"
+#define fpga_reg ((struct qixis *)QIXIS_BASE)
#else
#include "pixis.h"
+#define fpga_reg pixis
#endif
/* define for SYS CLK or CLK1Frequency */
unsigned long get_board_sys_clk(void)
{
return ics307_clk_freq(
- in_8(&pixis->sclk[0]),
- in_8(&pixis->sclk[1]),
- in_8(&pixis->sclk[2]));
+ in_8(&fpga_reg->sclk[0]),
+ in_8(&fpga_reg->sclk[1]),
+ in_8(&fpga_reg->sclk[2]));
}
unsigned long get_board_ddr_clk(void)
{
return ics307_clk_freq(
- in_8(&pixis->dclk[0]),
- in_8(&pixis->dclk[1]),
- in_8(&pixis->dclk[2]));
+ in_8(&fpga_reg->dclk[0]),
+ in_8(&fpga_reg->dclk[1]),
+ in_8(&fpga_reg->dclk[2]));
}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "qixis.h"
+
+u8 qixis_read(unsigned int reg)
+{
+ void *p = (void *)QIXIS_BASE;
+
+ return in_8(p + reg);
+}
+
+void qixis_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)QIXIS_BASE;
+
+ out_8(p + reg, value);
+}
+
+void qixis_reset(void)
+{
+ QIXIS_WRITE(rst_ctl, 0x83);
+}
+
+void qixis_bank_reset(void)
+{
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+}
+
+/* Set the boot bank to the power-on default bank0 */
+void clear_altbank(void)
+{
+ u8 reg;
+
+ reg = QIXIS_READ(brdcfg[0]);
+ reg = reg & ~QIXIS_LBMAP_MASK;
+ QIXIS_WRITE(brdcfg[0], reg);
+}
+
+/* Set the boot bank to the alternate bank */
+void set_altbank(void)
+{
+ u8 reg;
+
+ reg = QIXIS_READ(brdcfg[0]);
+ reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
+ QIXIS_WRITE(brdcfg[0], reg);
+}
+
+#ifdef DEBUG
+static void qixis_dump_regs(void)
+{
+ int i;
+
+ printf("id = %02x\n", QIXIS_READ(id));
+ printf("arch = %02x\n", QIXIS_READ(arch));
+ printf("scver = %02x\n", QIXIS_READ(scver));
+ printf("model = %02x\n", QIXIS_READ(model));
+ printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
+ printf("aux = %02x\n", QIXIS_READ(aux));
+ for (i = 0; i < 16; i++)
+ printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
+ for (i = 0; i < 16; i++)
+ printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
+ printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
+ QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
+ printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
+ QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
+ printf("aux = %02x\n", QIXIS_READ(aux));
+ printf("watch = %02x\n", QIXIS_READ(watch));
+ printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
+ printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
+ printf("present = %02x\n", QIXIS_READ(present));
+ printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
+ printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
+ printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
+ printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
+ printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2));
+}
+#endif
+
+int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+
+ if (argc <= 1) {
+ clear_altbank();
+ qixis_reset();
+ } else if (strcmp(argv[1], "altbank") == 0) {
+ set_altbank();
+ qixis_bank_reset();
+ } else if (strcmp(argv[1], "watchdog") == 0) {
+ static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
+ "1min", "2min", "4min", "8min"};
+ u8 rcfg = QIXIS_READ(rcfg_ctl);
+
+ if (argv[2] == NULL) {
+ printf("qixis watchdog <watchdog_period>\n");
+ return 0;
+ }
+ for (i = 0; i < ARRAY_SIZE(period); i++) {
+ if (strcmp(argv[2], period[i]) == 0) {
+ /* disable watchdog */
+ QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
+ QIXIS_WRITE(watch, ((i<<2) - 1));
+ QIXIS_WRITE(rcfg_ctl, rcfg);
+ return 0;
+ }
+ }
+ }
+
+#ifdef DEBUG
+ else if (strcmp(argv[1], "dump") == 0) {
+ qixis_dump_regs();
+ return 0;
+ }
+#endif
+
+ else {
+ printf("Invalid option: %s\n", argv[1]);
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
+ "Reset the board using the FPGA sequencer",
+ "- hard reset to default bank\n"
+ "qixis_reset altbank - reset to alternate bank\n"
+ "qixis watchdog <watchdog_period> - set the watchdog period\n"
+ " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
+#ifdef DEBUG
+ "qixis_reset dump - display the QIXIS registers\n"
+#endif
+ );
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ */
+
+#ifndef __QIXIS_H_
+#define __QIXIS_H_
+
+struct qixis {
+ u8 id; /* ID value uniquely identifying each QDS board type */
+ u8 arch; /* Board version information */
+ u8 scver; /* QIXIS Version Register */
+ u8 model; /* Information of software programming model version */
+ u8 tagdata;
+ u8 ctl_sys;
+ u8 aux; /* Auxiliary Register,0x06 */
+ u8 clk_spd;
+ u8 stat_dut;
+ u8 stat_sys;
+ u8 stat_alrm;
+ u8 present;
+ u8 ctl_sys2;
+ u8 rcw_ctl;
+ u8 ctl_led;
+ u8 i2cblk;
+ u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
+ u8 rcfg_st;
+ u8 dcm_ad;
+ u8 dcm_da;
+ u8 dcmd;
+ u8 dmsg;
+ u8 gdc;
+ u8 gdd; /* DCM Debug Data Register,0x17 */
+ u8 dmack;
+ u8 res1[6];
+ u8 watch; /* Watchdog Register,0x1F */
+ u8 pwr_ctl[2]; /* Power Control Register,0x20 */
+ u8 res2[2];
+ u8 pwr_stat[4]; /* Power Status Register,0x24 */
+ u8 res3[8];
+ u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
+ u8 res4[2];
+ u8 sclk[3]; /* Clock Configuration Registers,0x34 */
+ u8 res5;
+ u8 dclk[3];
+ u8 res6;
+ u8 clk_dspd[3];
+ u8 res7;
+ u8 rst_ctl; /* Reset Control Register,0x40 */
+ u8 rst_stat; /* Reset Status Register */
+ u8 rst_rsn; /* Reset Reason Register */
+ u8 rst_frc[2]; /* Reset Force Registers,0x43 */
+ u8 res8[11];
+ u8 brdcfg[16]; /* Board Configuration Register,0x50 */
+ u8 dutcfg[16];
+ u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
+ u8 rcw_data;
+ u8 res9[5];
+ u8 post_ctl;
+ u8 post_stat;
+ u8 post_dat[2];
+ u8 pi_d[4];
+ u8 gpio_io[4];
+ u8 gpio_dir[4];
+ u8 res10[20];
+ u8 rjtag_ctl;
+ u8 rjtag_dat;
+ u8 res11[2];
+ u8 trig_src[4];
+ u8 trig_dst[4];
+ u8 trig_stat;
+ u8 res12[3];
+ u8 trig_ctr[4];
+ u8 res13[48];
+ u8 aux2[4]; /* Auxiliary Registers,0xE0 */
+ u8 res14[10];
+ u8 aux_ad;
+ u8 aux_da;
+ u8 res15[16];
+};
+
+#define QIXIS_BASE 0xffdf0000
+#define QIXIS_LBMAP_SWITCH 7
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_ALTBANK 0x04
+
+u8 qixis_read(unsigned int reg);
+void qixis_write(unsigned int reg, u8 value);
+
+#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+
+#endif
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr;
+ u32 devdisr;
int first_free_busno;
int pci_agent;
devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
first_free_busno = fsl_pcie_init_board(0);
--- /dev/null
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * Set DDR_SDRAM_CLK_CNTL = 0x02800000
+ *
+ * Clock is launched 5/8 applied cycle after address/command
+ */
+ popts->clk_adjust = 5;
+}
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
+ * the DDR SPD setup code runs.
+ *
+ * This table would be empty, except that it is used before the BSS section is
+ * initialized, and therefore must have at least one entry to push it into
+ * the DATA section.
+ */
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/mpc85xx_gpio.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_PCI)
+#include <asm/fsl_pci.h>
+#include <pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void ft_pci_board_setup(void *blob)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif
+
+#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
+ SGMII_PHY_RST_SET | PCIE_RST_SET | \
+ RGMII_PHY_RST_SET)
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+#define BOARDREV_B 0x10100000
+#define BOARDREV_C 0x00100000
+#define BOARDREV_D 0x00000000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_50 50000000
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+ ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ switch (ddr_ratio) {
+ case 0x0C:
+ return SYSCLK_66;
+ case 0x0A:
+ case 0x08:
+ return SYSCLK_100;
+ default:
+ puts("ERROR: unknown DDR ratio\n");
+ return SYSCLK_100;
+ }
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+ ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ switch (ddr_ratio) {
+ case 0x0C:
+ case 0x0A:
+ return SYSCLK_66;
+ case 0x08:
+ return SYSCLK_100;
+ default:
+ puts("ERROR: unknown DDR ratio\n");
+ return SYSCLK_100;
+ }
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+
+ /* All the device are enable except for SRIO12 */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
+ return 0;
+}
+#endif
+
+#define GPIO_DIR 0x0f3a0000
+#define GPIO_ODR 0x00000000
+#define GPIO_DAT 0x001a0000
+
+int checkboard(void)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
+
+ /*
+ * GPIO
+ * 0 - 3: CarryBoard Input;
+ * 4 - 7: CarryBoard Output;
+ * 8 : Mux as SDHC_CD (card detection)
+ * 9 : Mux as SDHC_WP
+ * 10 : Clear Watchdog timer
+ * 11 : LED Input
+ * 12 : Output to 1
+ * 13 : Open Drain
+ * 14 : LED Output
+ * 15 : Switch Input
+ *
+ * Set GPIOs 11, 12, 14 to 1.
+ */
+ out_be32(&pgpio->gpodr, GPIO_ODR);
+ mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
+
+ puts("Board: Freescale COM Express P2020\n");
+ return 0;
+}
+
+#define M41ST85W_I2C_BUS 1
+#define M41ST85W_I2C_ADDR 0x68
+#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
+
+static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
+{
+ u8 data;
+
+ if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
+ M41ST85W_ERROR("unable to read %s bit\n", name);
+ return;
+ }
+
+ if (data & mask) {
+ data &= ~mask;
+ if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
+ M41ST85W_ERROR("unable to clear %s bit\n", name);
+ return;
+ }
+ }
+}
+
+#define M41ST85W_REG_SEC2 0x01
+#define M41ST85W_REG_SEC2_ST 0x80
+
+#define M41ST85W_REG_ALHOUR 0x0c
+#define M41ST85W_REG_ALHOUR_HT 0x40
+
+/*
+ * The P2020COME board has a STMicro M41ST85W RTC/watchdog
+ * at i2c bus 1 address 0x68.
+ */
+static void start_rtc(void)
+{
+ unsigned int bus = i2c_get_bus_num();
+
+ if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
+ M41ST85W_ERROR("unable to set i2c bus\n");
+ goto out;
+ }
+
+ /* ensure ST (stop) and HT (halt update) bits are cleared */
+ m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
+ m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
+
+out:
+ /* reset the i2c bus */
+ i2c_set_bus_num(bus);
+}
+
+int board_early_init_r(void)
+{
+ start_rtc();
+ return 0;
+}
+
+#define M41ST85W_REG_WATCHDOG 0x09
+#define M41ST85W_REG_WATCHDOG_WDS 0x80
+#define M41ST85W_REG_WATCHDOG_BMB0 0x04
+
+void board_reset(void)
+{
+ u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
+
+ /* set the hardware watchdog timeout to 1/16 second, then hang */
+ i2c_set_bus_num(M41ST85W_I2C_BUS);
+ i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
+
+ while (1)
+ /* hang */;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ ft_pci_board_setup(blob);
+#endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_dr_usb(blob, bd);
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_PCI)
+ /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * *I*G* - PCI I/O
+ *
+ * PCI3 => 0xFFC10000
+ * PCI2 => 0xFFC2,0000
+ * PCI1 => 0xFFC3,0000
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+#endif /* #if defined(CONFIG_PCI) */
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += eth.o
+COBJS-y += fixed_ddr.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+#include "p3060qds.h"
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ unsigned int lawbar1_target_id;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+ /*
+ * setup laws for DDR. If not interleaving, presuming half memory on
+ * DDR1 and the other half on DDR2
+ */
+ if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ LAW_TRGT_IF_DDR_INTRLV) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ } else {
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ }
+ return ddr_size;
+}
+
+struct board_specific_params {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_params udimm[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
+ */
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 5, 6, 0xff, 2, 0},
+ {2, 950, 5, 7, 0xff, 2, 0},
+ {2, 1250, 4, 6, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0xff, 2, 0},
+ {1, 850, 4, 5, 0xff, 2, 0},
+ {1, 950, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_params rdimm[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
+ */
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 4, 6, 0xff, 2, 0},
+ {2, 1050, 4, 7, 0xff, 2, 0},
+ {2, 1666, 4, 8, 0xff, 2, 0},
+ {1, 850, 4, 5, 0xff, 2, 0},
+ {1, 950, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_params *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ if (popts->registered_dimm_en)
+ pbsp = rdimm;
+ else
+ pbsp = udimm;
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+
+found:
+
+ /*
+ * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
+ * However SPD still claims CL=7 is supported. Extensive tests
+ * confirmed this board cannot work stably with CL=7 with this
+ * particular DIMM.
+ */
+ if (ddr_freq >= 800 && ddr_freq < 1066 && \
+ !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
+ popts->cas_latency_override = 1;
+ popts->cas_latency_override_value = 8;
+ debug("Override CL to 8\n");
+ }
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 60 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....");
+
+ if (fsl_use_spd()) {
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+ } else {
+ puts("using fixed parameters\n");
+ dram_size = fixed_sdram();
+ }
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ debug(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+
+#include "p3060qds_qixis.h"
+
+#define EMI_NONE 0xffffffff
+#define EMI1_RGMII1 0
+#define EMI1_SLOT1 1
+#define EMI1_SLOT2 2
+#define EMI1_SLOT3 3
+#define EMI1_RGMII2 4
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static char *mdio_names[5] = {
+ "P3060QDS_MDIO0",
+ "P3060QDS_MDIO1",
+ "P3060QDS_MDIO2",
+ "P3060QDS_MDIO3",
+ "P3060QDS_MDIO4",
+};
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots.
+ * A value of '0' here means that the mapping must be determined
+ * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
+ */
+static u8 lane_to_slot[] = {
+ 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
+};
+
+static char *p3060qds_mdio_name_for_muxval(u32 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u32 muxval)
+{
+ struct mii_dev *bus;
+ char *name = p3060qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct p3060qds_mdio {
+ u32 muxval;
+ struct mii_dev *realbus;
+};
+
+static void p3060qds_mux_mdio(u32 muxval)
+{
+ u8 brdcfg4;
+
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << 4);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct p3060qds_mdio *priv = bus->priv;
+
+ p3060qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct p3060qds_mdio *priv = bus->priv;
+
+ p3060qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int p3060qds_mdio_reset(struct mii_dev *bus)
+{
+ struct p3060qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int p3060qds_mdio_init(char *realbusname, u32 muxval)
+{
+ struct p3060qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate P3060QDS MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate P3060QDS private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = p3060qds_mdio_read;
+ bus->write = p3060qds_mdio_write;
+ bus->reset = p3060qds_mdio_reset;
+ sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+ enum fm_port port, int offset)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ if (mdio_mux[port] == EMI1_RGMII1)
+ fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
+
+ if (mdio_mux[port] == EMI1_RGMII2)
+ fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
+
+ if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
+ || (srds_prtcl == 0x6))) {
+ switch (port) {
+ case FM2_DTSEC4:
+ fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
+ break;
+ case FM1_DTSEC4:
+ fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (mdio_mux[port] == EMI1_SLOT3) {
+ switch (port) {
+ case FM2_DTSEC3:
+ fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
+ break;
+ case FM1_DTSEC3:
+ fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i, lane, idx;
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ if (lane >= 14) {
+ fdt_status_okay_by_alias(fdt,
+ "emi1_slot1");
+ fdt_status_disabled_by_alias(fdt,
+ "emi1_slot1_bk1");
+ } else {
+ fdt_status_disabled_by_alias(fdt,
+ "emi1_slot1");
+ fdt_status_okay_by_alias(fdt,
+ "emi1_slot1_bk1");
+ }
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC1)
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+
+ if (i == FM1_DTSEC2)
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
+ break;
+ default:
+ break;
+ }
+ }
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ idx = i - FM2_DTSEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+ if (lane >= 0) {
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ if (lane >= 14)
+ fdt_status_okay_by_alias(fdt,
+ "emi1_slot1");
+ else
+ fdt_status_okay_by_alias(fdt,
+ "emi1_slot1_bk1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt,
+ "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt,
+ "emi1_slot3");
+ break;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+#endif
+}
+
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int sdprtl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ switch (sdprtl) {
+ case 0x03:
+ case 0x06:
+ lane_to_slot[8] = 1;
+ lane_to_slot[9] = lane_to_slot[8];
+ lane_to_slot[16] = 5;
+ lane_to_slot[17] = lane_to_slot[16];
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1C:
+ lane_to_slot[8] = 5;
+ lane_to_slot[9] = lane_to_slot[8];
+ lane_to_slot[16] = 1;
+ lane_to_slot[17] = lane_to_slot[16];
+ break;
+ default:
+ puts("Invalid SerDes protocol for P3060QDS\n");
+ break;
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
+ int i;
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int srds_cfg = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ initialize_lane_to_slot();
+
+ /*
+ * Set TBIPA on FM1@DTSEC1. This is needed for configurations
+ * where FM1@DTSEC1 isn't used directly, since it provides
+ * MDIO for other ports.
+ */
+ out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ /* Register the 5 muxing front-ends to the MDIO buses */
+ if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
+ p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+
+ if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
+ p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+
+ if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
+ fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
+ else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
+
+ if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
+ fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
+ else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
+
+ switch (srds_cfg) {
+ case 0x03:
+ case 0x06:
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1C:
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ default:
+ puts("Invalid SerDes protocol for P3060QDS\n");
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ if (QIXIS_READ(present) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC1) {
+ mdio_mux[i] = EMI1_RGMII1;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ } else if (i == FM1_DTSEC2) {
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ int idx = i - FM2_DTSEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ if (QIXIS_READ(present) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4 0x00000001
+#define CONFIG_SYS_DDR_TIMING_5 0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {850, 950, &ddr_cfg_regs_900},
+ {950, 1050, &ddr_cfg_regs_1000},
+ {1050, 1250, &ddr_cfg_regs_1200},
+ {0, 0, NULL}
+};
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <configs/P3060QDS.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/qixis.h"
+#include "p3060qds.h"
+#include "p3060qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ u8 sw;
+ struct cpu_type *cpu = gd->cpu;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ unsigned int i;
+
+ printf("Board: %s", cpu->name);
+ puts("QDS, ");
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+#ifdef CONFIG_PHYS_64BIT
+ puts("36-bit Addressing\n");
+#endif
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
+ puts("SERDES Reference Clocks: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < 3; i++) {
+ static const char * const freq[] = {"100", "125", "Reserved",
+ "156.25"};
+ unsigned int clock = (sw >> (2 * i)) & 3;
+
+ printf("Bank%u=%sMhz ", i+1, freq[clock]);
+ }
+ puts("\n");
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
+ setbits_be32(&gur->ddrclkdr, 0x00030000);
+
+ return 0;
+}
+
+void board_config_serdes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int cfg = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ switch (cfg) {
+ case 0x03:
+ case 0x06:
+ /* set Lane I,J as SGMII */
+ QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
+ BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1c:
+ /* set Lane I,J as Aurora Debug */
+ QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
+ BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
+ break;
+ default:
+ puts("Invalid SerDes protocol for P3060QDS\n");
+ break;
+ }
+}
+
+void board_config_usb_mux(void)
+{
+ u8 brdcfg4, brdcfg5, brdcfg7;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
+ u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
+ u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
+
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
+ if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
+ (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
+ brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
+
+ } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
+ ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
+ (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
+ brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
+
+ } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
+ (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
+ brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
+
+ } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
+ ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
+ (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
+ brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
+ } else {
+ brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
+ }
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+ brdcfg5 = QIXIS_READ(brdcfg[5]);
+ brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
+ brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
+ QIXIS_WRITE(brdcfg[5], brdcfg5);
+
+ brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
+ BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
+ QIXIS_WRITE(brdcfg[7], brdcfg7);
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+ board_config_serdes_mux();
+ board_config_usb_mux();
+
+ return 0;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ default:
+ return "150";
+ }
+}
+
+#define NUM_SRDS_BANKS 3
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *srds_regs;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ u8 sw;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < 3; i++) {
+ unsigned int clock = (sw >> (2 * i)) & 3;
+ switch (clock) {
+ case 0:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 3:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ default:
+ printf("Warning: SDREFCLK%u switch setting of '10' is "
+ "unsupported\n", i + 1);
+ break;
+ }
+ }
+
+ srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
+ u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
+ * 18 means CVDD is 1.8v.
+ */
+static u8 IO_VSEL[] = {
+ 33, 33, 33, 25, 25, 25, 18, 18, 18,
+ 33, 33, 33, 25, 25, 25, 18, 18, 18,
+ 33, 33, 33, 25, 25, 25, 18, 18, 18,
+ 33, 33, 33, 33, 33
+};
+
+#define IO_VSEL_MASK 0x1f
+
+/*
+ * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
+ * then set status of spi flash nodes to 'disabled' according to CVDD.
+ * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
+ * flash2, CVDD '18' will select spi flash3.
+ */
+void fdt_fixup_board_spi(void *blob)
+{
+ u8 sw5 = QIXIS_READ(dutcfg[3]);
+
+ switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
+ /* 3.3v */
+ case 33:
+ do_fixup_by_compat(blob, "atmel,at45db081d", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ break;
+ /* 2.5v */
+ case 25:
+ do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ do_fixup_by_compat(blob, "spansion,en25q32", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ break;
+ /* 1.8v */
+ case 18:
+ do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ do_fixup_by_compat(blob, "spansion,en25q32", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ do_fixup_by_compat(blob, "atmel,at45db081d", "status",
+ "disabled", strlen("disabled") + 1, 1);
+ break;
+ }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_board_spi(blob);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3060QDS_H__
+#define __P3060QDS_H__
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/u-boot.h>
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+
+#endif
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3060QDS_QIXIS_H__
+#define __P3060QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for P3060QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EC_MODE_MASK 0x0F
+#define BRDCFG4_EC2_MII_EC1_MII 0x00
+#define BRDCFG4_EC2_MII_EC1_USB 0x03
+#define BRDCFG4_EC2_USB_EC1_MII 0x0C
+#define BRDCFG4_EC2_USB_EC1_USB 0x0F
+#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E
+#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B
+#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A
+#define BRDCFG4_EMISEL_MASK 0xF0
+
+#define BRDCFG5_ECLKS_MASK 0x80
+#define BRDCFG5_USB1ID_MASK 0x40
+#define BRDCFG5_USB2ID_MASK 0x20
+#define BRDCFG5_GC2MX_MASK 0x0C
+#define BRDCFG5_T15MX_MASK 0x03
+#define BRDCFG5_ECLKS_IEEE1588_CM 0x80
+#define BRDCFG5_USB1ID_CTRL 0x40
+#define BRDCFG5_USB2ID_CTRL 0x20
+
+#define BRDCFG6_SD1MX_A 0x01
+#define BRDCFG6_SD1MX_B 0x00
+#define BRDCFG6_SD2MX_A 0x02
+#define BRDCFG6_SD2MX_B 0x00
+#define BRDCFG6_SD3MX_A 0x04
+#define BRDCFG6_SD3MX_B 0x00
+#define BRDCFG6_SD4MX_A 0x08
+#define BRDCFG6_SD4MX_B 0x00
+
+#define BRDCFG7_JTAGMX_MASK 0xC0
+#define BRDCFG7_IQ1MX_MASK 0x20
+#define BRDCFG7_G1MX_MASK 0x10
+#define BRDCFG7_D1MX_MASK 0x0C
+#define BRDCFG7_I3MX_MASK 0x03
+#define BRDCFG7_JTAGMX_AURORA 0x00
+#define BRDCFG7_JTAGMX_FPGA 0x80
+#define BRDCFG7_JTAGMX_COP_JTAG 0xC0
+#define BRDCFG7_IQ1MX_IRQ_EVT 0x00
+#define BRDCFG7_IQ1MX_USB2 0x20
+#define BRDCFG7_G1MX_USB1 0x00
+#define BRDCFG7_G1MX_TSEC3 0x10
+#define BRDCFG7_D1MX_DMA 0x00
+#define BRDCFG7_D1MX_TSEC3USB 0x04
+#define BRDCFG7_D1MX_HDLC2 0x08
+#define BRDCFG7_I3MX_UART2_I2C34 0x00
+#define BRDCFG7_I3MX_GPIO_EVT 0x01
+#define BRDCFG7_I3MX_USB1 0x02
+#define BRDCFG7_I3MX_TSEC3 0x03
+
+#endif
--- /dev/null
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include <gdsys_fpga.h>
+
+#include "405ex.h"
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ */
+ val = SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] = 0;
+
+ /*
+ * reset FPGA
+ */
+ gd405ex_init();
+
+ gd405ex_set_fpga_reset(1);
+
+ gd405ex_setup_hw();
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!gd405ex_get_fpga_done(k)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
+
+ udelay(10);
+
+ gd405ex_set_fpga_reset(0);
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+ u16 *reflection_target = &fpga->reflection_low;
+#else
+ u16 *reflection_target = &fpga->reflection_high;
+#endif
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ out_le16(&fpga->reflection_low,
+ REFLECTION_TESTPATTERN);
+
+ if (in_le16(reflection_target) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
--- /dev/null
+#ifndef __405EX_H_
+#define __405EX_H_
+
+/* functions to be provided by board implementation */
+void gd405ex_init(void);
+void gd405ex_set_fpga_reset(unsigned state);
+void gd405ex_setup_hw(void);
+int gd405ex_get_fpga_done(unsigned fpga);
+
+#endif /* __405EX_H_ */
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-$(CONFIG_IO64) += io64.o
+
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+
+COBJS := $(BOARD).o $(COBJS-y)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on kilauea.c
+ * by Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/ppc4xx-gpio.h>
+#include <flash.h>
+
+#include <pca9698.h>
+
+#include "405ex.h"
+#include <gdsys_fpga.h>
+
+#include <miiphy.h>
+#include <i2c.h>
+#include <dtt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PHYREG_CONTROL 0
+#define PHYREG_PAGE_ADDRESS 22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
+#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
+#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
+enum {
+ UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+};
+
+static inline void blank_string(int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ putc('\b');
+ for (i = 0; i < size; i++)
+ putc(' ');
+ for (i = 0; i < size; i++)
+ putc('\b');
+}
+
+/*
+ * Board early initialization function
+ */
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+static void print_fpga_info(unsigned dev)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
+ int fpga_state = get_fpga_state(dev);
+
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+ unsigned feature_expansion;
+
+ printf("FPGA%d: ", dev);
+ if (fpga_state & FPGA_STATE_PLATFORM)
+ printf("(legacy) ");
+
+ if (fpga_state & FPGA_STATE_DONE_FAILED) {
+ printf(" done timed out\n");
+ return;
+ }
+
+ if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+ printf(" refelectione test failed\n");
+ return;
+ }
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+ feature_expansion = fpga_features & (1<<15);
+
+ switch (unit_type) {
+ case UNITTYPE_CCD_SWITCH:
+ printf("CCD-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)", feature_channels);
+
+ printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: CATCenter Io64\n");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ return 0;
+}
+
+int configure_gbit_phy(char *bus, unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 0 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch to powerdown */
+ if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ &value))
+ goto err_out;
+ if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ value | 0x0004))
+ goto err_out;
+ /* select page 2 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* disable SGMII autonegotiation */
+ if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
+ goto err_out;
+ /* select page 0 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch from powerdown to normal operation */
+ if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ &value))
+ goto err_out;
+ if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ value & ~0x0004))
+ goto err_out;
+ /* reset phy so settings take effect */
+ if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+int verify_gbit_phy(char *bus, unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 2 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* verify SGMII link status */
+ if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
+ goto err_out;
+ if (!(value & (1 << 10)))
+ return -2;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+int last_stage_init(void)
+{
+ unsigned int k;
+ unsigned int fpga;
+ ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+ ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
+ int failed = 0;
+ char str_phys[] = "Setup PHYs -";
+ char str_serdes[] = "Start SERDES blocks";
+ char str_channels[] = "Start FPGA channels";
+ char str_locks[] = "Verify SERDES locks";
+ char str_status[] = "Verify PHY status -";
+ char slash[] = "\\|/-\\|/-";
+
+ print_fpga_info(0);
+ print_fpga_info(1);
+
+ /* setup Gbit PHYs */
+ puts("TRANS: ");
+ puts(str_phys);
+ miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k) {
+ configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+
+ miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k) {
+ configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ blank_string(strlen(str_phys));
+
+ /* take fpga serdes blocks out of reset */
+ puts(str_serdes);
+ udelay(500000);
+ out_le16(&fpga0->quad_serdes_reset, 0);
+ out_le16(&fpga1->quad_serdes_reset, 0);
+ blank_string(strlen(str_serdes));
+
+ /* take channels out of reset */
+ puts(str_channels);
+ udelay(500000);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
+ for (k = 0; k < 32; ++k)
+ out_le16(ch0_config_int + 4 * k, 0);
+ }
+ blank_string(strlen(str_channels));
+
+ /* verify channels serdes lock */
+ puts(str_locks);
+ udelay(500000);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
+ for (k = 0; k < 32; ++k) {
+ u16 status = in_le16(ch0_status_int + 4*k);
+ if (!(status & (1 << 4))) {
+ failed = 1;
+ printf("fpga %d channel %d: no serdes lock\n",
+ fpga, k);
+ }
+ /* reset events */
+ out_le16(ch0_status_int + 4*k, status);
+ }
+ }
+ blank_string(strlen(str_locks));
+
+ /* verify phy status */
+ puts(str_status);
+ for (k = 0; k < 32; ++k) {
+ if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
+ printf("verify baseboard phy %d failed\n", k);
+ failed = 1;
+ }
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ for (k = 0; k < 32; ++k) {
+ if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
+ printf("verify extensionboard phy %d failed\n", k);
+ failed = 1;
+ }
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ blank_string(strlen(str_status));
+
+ printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
+
+ return 0;
+}
+
+void gd405ex_init(void)
+{
+ unsigned int k;
+
+ if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
+ } else {
+ pca9698_direction_output(0x22, 39, 1);
+ }
+}
+
+void gd405ex_set_fpga_reset(unsigned state)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy) {
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+ } else {
+ pca9698_set_value(0x22, 39, state ? 0 : 1);
+ }
+}
+
+void gd405ex_setup_hw(void)
+{
+ gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
+}
+
+int gd405ex_get_fpga_done(unsigned fpga)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy)
+ return in_le16((void *)LATCH3_BASE)
+ & CONFIG_SYS_FPGA_DONE(fpga);
+ else
+ return pca9698_get_value(0x22, fpga ? 9 : 8);
+}
LIB = $(obj)lib$(VENDOR).o
COBJS-$(CONFIG_IO) += miiphybb.o
+COBJS-$(CONFIG_IO64) += miiphybb.o
COBJS-$(CONFIG_IOCON) += osd.o
COBJS-$(CONFIG_DLVISION_10G) += osd.o
#include <asm/io.h>
+struct io_bb_pinset {
+ int mdio;
+ int mdc;
+};
+
static int io_bb_mii_init(struct bb_miiphy_bus *bus)
{
return 0;
static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
{
+ struct io_bb_pinset *pins = bus->priv;
+
out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_TCR) | pins->mdio);
return 0;
}
static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
+ struct io_bb_pinset *pins = bus->priv;
+
out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_TCR) & ~pins->mdio);
return 0;
}
static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
+ struct io_bb_pinset *pins = bus->priv;
+
if (v)
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_OR) | pins->mdio);
else
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
+ in_be32((void *)GPIO0_OR) & ~pins->mdio);
return 0;
}
static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
- *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
+ struct io_bb_pinset *pins = bus->priv;
+
+ *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
return 0;
}
static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
+ struct io_bb_pinset *pins = bus->priv;
+
if (v)
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
+ in_be32((void *)GPIO0_OR) | pins->mdc);
else
out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
+ in_be32((void *)GPIO0_OR) & ~pins->mdc);
return 0;
}
return 0;
}
+struct io_bb_pinset io_bb_pinsets[] = {
+ {
+ .mdio = CONFIG_SYS_MDIO_PIN,
+ .mdc = CONFIG_SYS_MDC_PIN,
+ },
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+ {
+ .mdio = CONFIG_SYS_MDIO1_PIN,
+ .mdc = CONFIG_SYS_MDC1_PIN,
+ },
+#endif
+};
+
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = CONFIG_SYS_GBIT_MII_BUSNAME,
.get_mdio = io_bb_get_mdio,
.set_mdc = io_bb_set_mdc,
.delay = io_bb_delay,
- }
+ .priv = &io_bb_pinsets[0],
+ },
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+ {
+ .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
+ .init = io_bb_mii_init,
+ .mdio_active = io_bb_mdio_active,
+ .mdio_tristate = io_bb_mdio_tristate,
+ .set_mdio = io_bb_set_mdio,
+ .get_mdio = io_bb_get_mdio,
+ .set_mdc = io_bb_set_mdc,
+ .delay = io_bb_delay,
+ .priv = &io_bb_pinsets[1],
+ },
+#endif
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
int i;
#if !defined(CONFIG_PATI)
- unsigned long size_b1,flashcr,size_reg;
+ unsigned long flashcr,size_reg;
int mode;
extern char version_string;
char *p = &version_string;
#if !defined(CONFIG_PATI)
/* protect reset vector */
flash_info[0].protect[flash_info[0].sector_count-1] = 1;
- size_b1 = 0 ;
flash_info[0].size = size_b0;
/* set up flash cs according to the size */
size_reg=(flash_info[0].size >>20);
/* PROGRAM_SEL_DPR = LOW */
int fpga_pre_fn(int cookie)
{
- unsigned long reg;
-
- reg = in32(GPIO0_IR);
/* Enable the FPGA Chain */
SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
static int alpr_nand_dev_ready(struct mtd_info *mtd)
{
- volatile u_char val;
-
/*
* Blocking read to wait for NAND to be ready
*/
- val = readb(&(alpr_ndfc->addr_wait));
+ (void)readb(&(alpr_ndfc->addr_wait));
/*
* Return always true
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
{
- cfiptr_t ctladdr;
cfiptr_t cptr;
int flag;
- ctladdr.cp = flash_make_addr(info, 0, 0);
cptr.cp = (uchar *)dest;
-
/* Check if Flash is (sufficiently) erased */
switch(info->portwidth) {
case FLASH_CFI_8BIT:
P2020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,NAND
P2020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD
P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH
+P2020COME_SDCARD powerpc mpc85xx p2020come freescale - P2020COME:SDCARD
+P2020COME_SPIFLASH powerpc mpc85xx p2020come freescale - P2020COME:SPIFLASH
P2041RDB powerpc mpc85xx p2041rdb freescale
P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT
P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+P3060QDS powerpc mpc85xx p3060qds freescale
+P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT
P4080DS powerpc mpc85xx corenet_ds freescale
P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
gdppc440etx powerpc ppc4xx - gdsys
intip powerpc ppc4xx intip gdsys - intip:INTIB
io powerpc ppc4xx 405ep gdsys
+io64 powerpc ppc4xx 405ex gdsys
iocon powerpc ppc4xx 405ep gdsys
neo powerpc ppc4xx - gdsys
icon powerpc ppc4xx - mosaixtech
static void print_num(const char *, ulong);
-#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K) || defined(CONFIG_SANDBOX)) \
+#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K) || \
+ defined(CONFIG_SANDBOX) || defined(CONFIG_X86)) \
|| defined(CONFIG_CMD_NET)
#define HAVE_PRINT_ETH
static void print_eth(int idx);
return 1;
}
+ if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
+ images.os.load = images.os.image_start;
+ images.ep += images.os.load;
+ }
+
if (((images.os.type == IH_TYPE_KERNEL) ||
+ (images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
(images.os.type == IH_TYPE_MULTI)) &&
(images.os.os == IH_OS_LINUX)) {
/* find ramdisk */
ulong image_start = os.image_start;
ulong image_len = os.image_len;
__maybe_unused uint unc_len = CONFIG_SYS_BOOTM_LEN;
+ int no_overlap = 0;
#if defined(CONFIG_LZMA) || defined(CONFIG_LZO)
int ret;
#endif /* defined(CONFIG_LZMA) || defined(CONFIG_LZO) */
case IH_COMP_NONE:
if (load == blob_start || load == image_start) {
printf(" XIP %s ... ", type_name);
+ no_overlap = 1;
} else {
printf(" Loading %s ... ", type_name);
memmove_wd((void *)load, (void *)image_start,
if (boot_progress)
show_boot_progress(7);
- if ((load < blob_end) && (*load_end > blob_start)) {
+ if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) {
debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n",
blob_start, blob_end);
debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load,
}
show_boot_progress(106);
- if (!fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL)) {
+ if (!fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL) &&
+ !fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL_NOLOAD)) {
puts("Not a kernel image\n");
show_boot_progress(-106);
return 0;
/* get os_data and os_len */
switch (image_get_type(hdr)) {
case IH_TYPE_KERNEL:
+ case IH_TYPE_KERNEL_NOLOAD:
*os_data = image_get_data(hdr);
*os_len = image_get_data_size(hdr);
break;
{ IH_TYPE_FIRMWARE, "firmware", "Firmware", },
{ IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", },
{ IH_TYPE_KERNEL, "kernel", "Kernel Image", },
+ { IH_TYPE_KERNEL_NOLOAD, "kernel_noload", "Kernel Image (no loading done)", },
{ IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",},
{ IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",},
{ IH_TYPE_INVALID, NULL, "Invalid Image", },
--- /dev/null
+Overview
+=========
+The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
+
+The P3060 Processor combines six e500mc Power Architecture processor
+cores(1.2GHz) with high-performance datapath acceleration
+architecture(DPAA), CoreNet fabric infrastructure, as well as network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and military/aerospace applications.
+
+
+P3060QDS Board Specifications:
+==============================
+Memory subsystem:
+ * 2G Bytes UDIMM DDR3(64bit bus) with ECC on
+ * 128M Bytes NOR flash single-chip memory
+ * 16M Bytes SPI flash
+ * 8K Bytes AT24C64 I2C EEPROM for RCW
+
+Ethernet(Default SERDES 0x19):
+ * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
+ * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
+ * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
+ * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
+ * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
+ * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
+ * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
+ * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
+
+PCIe:
+ * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
+ * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
+
+RapidIO:
+ * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
+ * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
+
+USB:
+ * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
+ * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
+
+I2C:
+ * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
+ AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
+ * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
+ ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
+ * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
+ * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
+ * I2C1_CH4: PCIe SLOT1
+ * I2C1_CH5: PCIe SLOT2
+ * I2C1_CH6: PCIe SLOT3
+ * I2C1_CH7: PCIe SLOT4
+ * I2C2: NULL
+ * I2C3: NULL
+
+UART:
+ * Supports two UARTs up to 115200 bps for console
+
+
+Boot from NOR flash
+===================
+1. Build image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
+ make P3060QDS_config
+ make
+
+2. Program image
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff80000 efffffff
+ => cp.b 1000000 eff80000 80000
+
+3. Program RCW
+ => tftp 1000000 rcw.bin
+ => protect off all
+ => erase e8000000 e801ffff
+ => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => protect off all
+ => erase ef000000 ef0fffff
+ => cp.b 1000000 ef000000 2000
+
+5. Change DIP-switch
+ RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+ dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
+
+Or use the following command:
+ {linux-2.6}/make p3060qds.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+ {linux-2.6}/arch/powerpc/boot/p3060qds.dtb
+
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp 3000000 p3060rdb.dtb
+ bootm 1000000 2000000 3000000
+
/* Wait the controller offline */
ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
- /*
- * For P1022/1013 Rev1.0 silicon, after power on SATA host
- * controller is configured in legacy mode instead of the
- * expected enterprise mode. software needs to clear bit[28]
- * of HControl register to change to enterprise mode from
- * legacy mode.
- */
- {
- u32 svr = get_svr();
- if (IS_SVR_REV(svr, 1, 0) &&
- ((SVR_SOC_VER(svr) == SVR_P1022) ||
- (SVR_SOC_VER(svr) == SVR_P1022_E) ||
- (SVR_SOC_VER(svr) == SVR_P1013) ||
- (SVR_SOC_VER(svr) == SVR_P1013_E))) {
- out_le32(®->hstatus, 0x20000000);
- out_le32(®->hcontrol, 0x00000100);
- }
- }
-#endif
-
/* Set the command header base address to CHBA register to tell DMA */
out_le32(®->chba, (u32)cmd_hdr & ~0x3);
*/
#define HCONTROL_ONOFF 0x80000000 /* Online or offline request */
#define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */
+#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */
#define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */
#define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */
u8 status;
const u16 *id;
struct ata_device *ata_dev = &ata_device;
- unsigned long pio_mask, mwdma_mask, udma_mask;
+ unsigned long pio_mask, mwdma_mask;
char revbuf[7];
u16 iobuf[ATA_SECTOR_WORDS];
mwdma_mask |= (1 << 4);
}
- udma_mask = 0;
- if (id[ATA_ID_FIELD_VALID] & (1 << 2))
- udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
-
if (ata_dev->class == ATA_DEV_ATA) {
if (ata_id_is_cfa(id)) {
if (id[162] & 1)
#include <common.h>
#ifdef CONFIG_USE_CPCIDVI
-extern u8 gt_cpcidvi_in8(u32 offset);
+extern u8 gt_cpcidvi_in8(u32 offset);
extern void gt_cpcidvi_out8(u32 offset, u8 data);
#define in8(a) gt_cpcidvi_in8(a)
-#define out8(a, b) gt_cpcidvi_out8(a,b)
+#define out8(a, b) gt_cpcidvi_out8(a, b)
#endif
#include <i8042.h>
/* defines */
#ifdef CONFIG_CONSOLE_CURSOR
-extern void console_cursor (int state);
+extern void console_cursor(int state);
static int blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
-static int cursor_state = 0;
+static int cursor_state;
#endif
/* locals */
static int kbd_input = -1; /* no input yet */
static int kbd_mapping = KBD_US; /* default US keyboard */
static int kbd_flags = NORMAL; /* after reset */
-static int kbd_state = 0; /* unshift code */
-
-static void kbd_conv_char (unsigned char scan_code);
-static void kbd_led_set (void);
-static void kbd_normal (unsigned char scan_code);
-static void kbd_shift (unsigned char scan_code);
-static void kbd_ctrl (unsigned char scan_code);
-static void kbd_num (unsigned char scan_code);
-static void kbd_caps (unsigned char scan_code);
-static void kbd_scroll (unsigned char scan_code);
-static void kbd_alt (unsigned char scan_code);
-static int kbd_input_empty (void);
-static int kbd_reset (void);
-
-static unsigned char kbd_fct_map [144] =
- { /* kbd_fct_map table for scan code */
- 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */
- AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */
- AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */
- AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */
- AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */
- AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */
- AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */
- AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */
- ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */
- ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */
- 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */
- AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */
- AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */
- };
-
-static unsigned char kbd_key_map [2][5][144] =
- {
- { /* US keyboard */
- { /* unshift code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
- '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
- 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
- '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* shift code */
- 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */
- '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */
- 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */
- 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */
- '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */
- 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* control code */
- 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
- 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
- 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
- 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
- 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
- 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
- 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
- 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- },
- { /* non numeric code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
- '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
- 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
- '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
- 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
- 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* right alt mode - not used in US keyboard */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- }
- },
- { /* german keyboard */
- { /* unshift code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
- '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
- 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
- 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
- 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* shift code */
- 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */
- '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */
- 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
- 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
- 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
- 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* control code */
- 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
- 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
- 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
- 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
- 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
- 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
- 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
- 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- },
- { /* non numeric code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
- '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
- 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
- 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
- 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
- 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
- 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* Right alt mode - is used in German keyboard */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
- '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */
- '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
- 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
- 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- }
- }
- };
-
-static unsigned char ext_key_map [] =
- {
- 0x1c, /* keypad enter */
- 0x1d, /* right control */
- 0x35, /* keypad slash */
- 0x37, /* print screen */
- 0x38, /* right alt */
- 0x46, /* break */
- 0x47, /* editpad home */
- 0x48, /* editpad up */
- 0x49, /* editpad pgup */
- 0x4b, /* editpad left */
- 0x4d, /* editpad right */
- 0x4f, /* editpad end */
- 0x50, /* editpad dn */
- 0x51, /* editpad pgdn */
- 0x52, /* editpad ins */
- 0x53, /* editpad del */
- 0x00 /* map end */
- };
+static int kbd_state; /* unshift code */
+
+static void kbd_conv_char(unsigned char scan_code);
+static void kbd_led_set(void);
+static void kbd_normal(unsigned char scan_code);
+static void kbd_shift(unsigned char scan_code);
+static void kbd_ctrl(unsigned char scan_code);
+static void kbd_num(unsigned char scan_code);
+static void kbd_caps(unsigned char scan_code);
+static void kbd_scroll(unsigned char scan_code);
+static void kbd_alt(unsigned char scan_code);
+static int kbd_input_empty(void);
+static int kbd_reset(void);
+
+static unsigned char kbd_fct_map[144] = {
+ /* kbd_fct_map table for scan code */
+ 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */
+ AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */
+ AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */
+ AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */
+ AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */
+ AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */
+ AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */
+ AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */
+ ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */
+ ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */
+ 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */
+ AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */
+ AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */
+ };
+
+static unsigned char kbd_key_map[2][5][144] = {
+ { /* US keyboard */
+ { /* unshift code */
+ 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
+ '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
+ 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
+ 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
+ '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
+ 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
+ ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
+ '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
+ '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
+ 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
+ },
+ { /* shift code */
+ 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */
+ '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */
+ 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */
+ 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */
+ 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */
+ '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */
+ 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */
+ ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
+ '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
+ '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
+ 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
+ },
+ { /* control code */
+ 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
+ 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
+ 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
+ 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
+ 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
+ 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
+ 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
+ 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
+ },
+ { /* non numeric code */
+ 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
+ '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
+ 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
+ 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
+ '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
+ 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
+ ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
+ 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
+ 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
+ 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
+ },
+ { /* right alt mode - not used in US keyboard */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
+ }
+ },
+ { /* german keyboard */
+ { /* unshift code */
+ 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
+ '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
+ 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
+ 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
+ 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
+ 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
+ ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
+ '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
+ '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
+ 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
+ },
+ { /* shift code */
+ 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */
+ '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */
+ 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
+ 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */
+ 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
+ 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
+ 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */
+ ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
+ '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
+ '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
+ 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
+ },
+ { /* control code */
+ 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
+ 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
+ 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
+ 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
+ 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
+ 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
+ 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
+ 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
+ },
+ { /* non numeric code */
+ 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
+ '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
+ 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
+ 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
+ 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */
+ 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
+ ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
+ 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
+ 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
+ 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
+ '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
+ 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
+ },
+ { /* Right alt mode - is used in German keyboard */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
+ '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */
+ '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
+ 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
+ 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
+ }
+ }
+ };
+
+static unsigned char ext_key_map[] = {
+ 0x1c, /* keypad enter */
+ 0x1d, /* right control */
+ 0x35, /* keypad slash */
+ 0x37, /* print screen */
+ 0x38, /* right alt */
+ 0x46, /* break */
+ 0x47, /* editpad home */
+ 0x48, /* editpad up */
+ 0x49, /* editpad pgup */
+ 0x4b, /* editpad left */
+ 0x4d, /* editpad right */
+ 0x4f, /* editpad end */
+ 0x50, /* editpad dn */
+ 0x51, /* editpad pgdn */
+ 0x52, /* editpad ins */
+ 0x53, /* editpad del */
+ 0x00 /* map end */
+ };
+
+/******************************************************************************/
+
+static int kbd_controller_present(void)
+{
+ return in8(I8042_STATUS_REG) != 0xff;
+}
/*******************************************************************************
*
* i8042_kbd_init - reset keyboard and init state flags
*/
-int i8042_kbd_init (void)
+int i8042_kbd_init(void)
{
- int keymap, try;
- char *penv;
+ int keymap, try;
+ char *penv;
+
+ if (!kbd_controller_present())
+ return -1;
#ifdef CONFIG_USE_CPCIDVI
- if ((penv = getenv ("console")) != NULL) {
- if (strncmp (penv, "serial", 7) == 0) {
- return -1;
- }
- }
+ penv = getenv("console");
+ if (penv != NULL) {
+ if (strncmp(penv, "serial", 7) == 0)
+ return -1;
+ }
#endif
- /* Init keyboard device (default US layout) */
- keymap = KBD_US;
- if ((penv = getenv ("keymap")) != NULL)
- {
- if (strncmp (penv, "de", 3) == 0)
- keymap = KBD_GER;
- }
-
- for (try = 0; try < KBD_RESET_TRIES; try++)
- {
- if (kbd_reset() == 0)
- {
- kbd_mapping = keymap;
- kbd_flags = NORMAL;
- kbd_state = 0;
- kbd_led_set();
- return 0;
- }
- }
- return -1;
+ /* Init keyboard device (default US layout) */
+ keymap = KBD_US;
+ penv = getenv("keymap");
+ if (penv != NULL) {
+ if (strncmp(penv, "de", 3) == 0)
+ keymap = KBD_GER;
+ }
+
+ for (try = 0; try < KBD_RESET_TRIES; try++) {
+ if (kbd_reset() == 0) {
+ kbd_mapping = keymap;
+ kbd_flags = NORMAL;
+ kbd_state = 0;
+ kbd_led_set();
+ return 0;
+ }
+ }
+ return -1;
}
* i8042_tstc - test if keyboard input is available
* option: cursor blinking if called in a loop
*/
-int i8042_tstc (void)
+int i8042_tstc(void)
{
- unsigned char scan_code = 0;
+ unsigned char scan_code = 0;
#ifdef CONFIG_CONSOLE_CURSOR
- if (--blinkCount == 0)
- {
- cursor_state ^= 1;
- console_cursor (cursor_state);
- blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
- udelay (10);
- }
+ if (--blinkCount == 0) {
+ cursor_state ^= 1;
+ console_cursor(cursor_state);
+ blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
+ udelay(10);
+ }
#endif
- if ((in8 (I8042_STATUS_REG) & 0x01) == 0)
+ if ((in8(I8042_STATUS_REG) & 0x01) == 0) {
+ return 0;
+ } else {
+ scan_code = in8(I8042_DATA_REG);
+ if (scan_code == 0xfa)
+ return 0;
+
+ kbd_conv_char(scan_code);
+
+ if (kbd_input != -1)
+ return 1;
+ }
return 0;
- else
- {
- scan_code = in8 (I8042_DATA_REG);
- if (scan_code == 0xfa)
- return 0;
-
- kbd_conv_char(scan_code);
-
- if (kbd_input != -1)
- return 1;
- }
- return 0;
}
* i8042_getc - wait till keyboard input is available
* option: turn on/off cursor while waiting
*/
-int i8042_getc (void)
+int i8042_getc(void)
{
- int ret_chr;
- unsigned char scan_code;
+ int ret_chr;
+ unsigned char scan_code;
- while (kbd_input == -1)
- {
- while ((in8 (I8042_STATUS_REG) & 0x01) == 0)
- {
+ while (kbd_input == -1) {
+ while ((in8(I8042_STATUS_REG) & 0x01) == 0) {
#ifdef CONFIG_CONSOLE_CURSOR
- if (--blinkCount==0)
- {
- cursor_state ^= 1;
- console_cursor (cursor_state);
- blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
- }
- udelay (10);
+ if (--blinkCount == 0) {
+ cursor_state ^= 1;
+ console_cursor(cursor_state);
+ blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
+ }
+ udelay(10);
#endif
+ }
+ scan_code = in8(I8042_DATA_REG);
+ if (scan_code != 0xfa)
+ kbd_conv_char (scan_code);
}
-
- scan_code = in8 (I8042_DATA_REG);
-
- if (scan_code != 0xfa)
- kbd_conv_char (scan_code);
- }
- ret_chr = kbd_input;
- kbd_input = -1;
- return ret_chr;
+ ret_chr = kbd_input;
+ kbd_input = -1;
+ return ret_chr;
}
/******************************************************************************/
-static void kbd_conv_char (unsigned char scan_code)
+static void kbd_conv_char(unsigned char scan_code)
{
- if (scan_code == 0xe0)
- {
- kbd_flags |= EXT;
- return;
- }
-
- /* if high bit of scan_code, set break flag */
- if (scan_code & 0x80)
- kbd_flags |= BRK;
- else
- kbd_flags &= ~BRK;
-
- if ((scan_code == 0xe1) || (kbd_flags & E1))
- {
- if (scan_code == 0xe1)
- {
- kbd_flags ^= BRK; /* reset the break flag */
- kbd_flags ^= E1; /* bitwise EXOR with E1 flag */
+ if (scan_code == 0xe0) {
+ kbd_flags |= EXT;
+ return;
}
- return;
- }
- scan_code &= 0x7f;
+ /* if high bit of scan_code, set break flag */
+ if (scan_code & 0x80)
+ kbd_flags |= BRK;
+ else
+ kbd_flags &= ~BRK;
+
+ if ((scan_code == 0xe1) || (kbd_flags & E1)) {
+ if (scan_code == 0xe1) {
+ kbd_flags ^= BRK; /* reset the break flag */
+ kbd_flags ^= E1; /* bitwise EXOR with E1 flag */
+ }
+ return;
+ }
- if (kbd_flags & EXT)
- {
- int i;
+ scan_code &= 0x7f;
+
+ if (kbd_flags & EXT) {
+ int i;
+
+ kbd_flags ^= EXT;
+ for (i = 0; ext_key_map[i]; i++) {
+ if (ext_key_map[i] == scan_code) {
+ scan_code = 0x80 + i;
+ break;
+ }
+ }
+ /* not found ? */
+ if (!ext_key_map[i])
+ return;
+ }
- kbd_flags ^= EXT;
- for (i=0; ext_key_map[i]; i++)
- {
- if (ext_key_map[i] == scan_code)
- {
- scan_code = 0x80 + i;
+ switch (kbd_fct_map[scan_code]) {
+ case AS:
+ kbd_normal(scan_code);
+ break;
+ case SH:
+ kbd_shift(scan_code);
+ break;
+ case CN:
+ kbd_ctrl(scan_code);
+ break;
+ case NM:
+ kbd_num(scan_code);
+ break;
+ case CP:
+ kbd_caps(scan_code);
+ break;
+ case ST:
+ kbd_scroll(scan_code);
+ break;
+ case AK:
+ kbd_alt(scan_code);
break;
- }
}
- /* not found ? */
- if (!ext_key_map[i])
- return;
- }
-
- switch (kbd_fct_map [scan_code])
- {
- case AS: kbd_normal (scan_code);
- break;
- case SH: kbd_shift (scan_code);
- break;
- case CN: kbd_ctrl (scan_code);
- break;
- case NM: kbd_num (scan_code);
- break;
- case CP: kbd_caps (scan_code);
- break;
- case ST: kbd_scroll (scan_code);
- break;
- case AK: kbd_alt (scan_code);
- break;
- }
- return;
+ return;
}
/******************************************************************************/
-static void kbd_normal (unsigned char scan_code)
+static void kbd_normal(unsigned char scan_code)
{
- unsigned char chr;
-
- if ((kbd_flags & BRK) == NORMAL)
- {
- chr = kbd_key_map [kbd_mapping][kbd_state][scan_code];
- if ((chr == 0xff) || (chr == 0x00))
- {
- return;
+ unsigned char chr;
+
+ if ((kbd_flags & BRK) == NORMAL) {
+ chr = kbd_key_map[kbd_mapping][kbd_state][scan_code];
+ if ((chr == 0xff) || (chr == 0x00))
+ return;
+
+ /* if caps lock convert upper to lower */
+ if (((kbd_flags & CAPS) == CAPS) &&
+ (chr >= 'a' && chr <= 'z')) {
+ chr -= 'a' - 'A';
+ }
+ kbd_input = chr;
}
-
- /* if caps lock convert upper to lower */
- if (((kbd_flags & CAPS) == CAPS) && (chr >= 'a' && chr <= 'z'))
- {
- chr -= 'a' - 'A';
- }
- kbd_input = chr;
- }
}
/******************************************************************************/
-static void kbd_shift (unsigned char scan_code)
+static void kbd_shift(unsigned char scan_code)
{
- if ((kbd_flags & BRK) == BRK)
- {
- kbd_state = AS;
- kbd_flags &= (~SHIFT);
- }
- else
- {
- kbd_state = SH;
- kbd_flags |= SHIFT;
- }
+ if ((kbd_flags & BRK) == BRK) {
+ kbd_state = AS;
+ kbd_flags &= (~SHIFT);
+ } else {
+ kbd_state = SH;
+ kbd_flags |= SHIFT;
+ }
}
/******************************************************************************/
-static void kbd_ctrl (unsigned char scan_code)
+static void kbd_ctrl(unsigned char scan_code)
{
- if ((kbd_flags & BRK) == BRK)
- {
- kbd_state = AS;
- kbd_flags &= (~CTRL);
- }
- else
- {
- kbd_state = CN;
- kbd_flags |= CTRL;
- }
+ if ((kbd_flags & BRK) == BRK) {
+ kbd_state = AS;
+ kbd_flags &= (~CTRL);
+ } else {
+ kbd_state = CN;
+ kbd_flags |= CTRL;
+ }
}
/******************************************************************************/
-static void kbd_caps (unsigned char scan_code)
+static void kbd_caps(unsigned char scan_code)
{
- if ((kbd_flags & BRK) == NORMAL)
- {
- kbd_flags ^= CAPS;
- kbd_led_set (); /* update keyboard LED */
- }
+ if ((kbd_flags & BRK) == NORMAL) {
+ kbd_flags ^= CAPS;
+ kbd_led_set(); /* update keyboard LED */
+ }
}
/******************************************************************************/
-static void kbd_num (unsigned char scan_code)
+static void kbd_num(unsigned char scan_code)
{
- if ((kbd_flags & BRK) == NORMAL)
- {
- kbd_flags ^= NUM;
- kbd_state = (kbd_flags & NUM) ? AS : NM;
- kbd_led_set (); /* update keyboard LED */
- }
+ if ((kbd_flags & BRK) == NORMAL) {
+ kbd_flags ^= NUM;
+ kbd_state = (kbd_flags & NUM) ? AS : NM;
+ kbd_led_set(); /* update keyboard LED */
+ }
}
/******************************************************************************/
-static void kbd_scroll (unsigned char scan_code)
+static void kbd_scroll(unsigned char scan_code)
{
- if ((kbd_flags & BRK) == NORMAL)
- {
- kbd_flags ^= STP;
- kbd_led_set (); /* update keyboard LED */
- if (kbd_flags & STP)
- kbd_input = 0x13;
- else
- kbd_input = 0x11;
- }
+ if ((kbd_flags & BRK) == NORMAL) {
+ kbd_flags ^= STP;
+ kbd_led_set(); /* update keyboard LED */
+ if (kbd_flags & STP)
+ kbd_input = 0x13;
+ else
+ kbd_input = 0x11;
+ }
}
/******************************************************************************/
-static void kbd_alt (unsigned char scan_code)
+static void kbd_alt(unsigned char scan_code)
{
- if ((kbd_flags & BRK) == BRK)
- {
- kbd_state = AS;
- kbd_flags &= (~ALT);
- }
- else
- {
- kbd_state = AK;
- kbd_flags &= ALT;
- }
+ if ((kbd_flags & BRK) == BRK) {
+ kbd_state = AS;
+ kbd_flags &= (~ALT);
+ } else {
+ kbd_state = AK;
+ kbd_flags &= ALT;
+ }
}
/******************************************************************************/
-static void kbd_led_set (void)
+static void kbd_led_set(void)
{
- kbd_input_empty();
- out8 (I8042_DATA_REG, 0xed); /* SET LED command */
- kbd_input_empty();
- out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */
+ kbd_input_empty();
+ out8(I8042_DATA_REG, 0xed); /* SET LED command */
+ kbd_input_empty();
+ out8(I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */
}
/******************************************************************************/
-static int kbd_input_empty (void)
+static int kbd_input_empty(void)
{
- int kbdTimeout = KBD_TIMEOUT;
+ int kbdTimeout = KBD_TIMEOUT;
- /* wait for input buf empty */
- while ((in8 (I8042_STATUS_REG) & 0x02) && kbdTimeout--)
- udelay(1000);
+ /* wait for input buf empty */
+ while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--)
+ udelay(1000);
- return kbdTimeout;
+ return kbdTimeout != -1;
}
/******************************************************************************/
-static int kbd_reset (void)
+static int kbd_reset(void)
{
- if (kbd_input_empty() == 0)
- return -1;
+ if (kbd_input_empty() == 0)
+ return -1;
- out8 (I8042_DATA_REG, 0xff);
+ out8(I8042_DATA_REG, 0xff);
- udelay(250000);
+ udelay(250000);
- if (kbd_input_empty() == 0)
- return -1;
+ if (kbd_input_empty() == 0)
+ return -1;
#ifdef CONFIG_USE_CPCIDVI
- out8 (I8042_COMMAND_REG, 0x60);
+ out8(I8042_COMMAND_REG, 0x60);
#else
- out8 (I8042_DATA_REG, 0x60);
+ out8(I8042_DATA_REG, 0x60);
#endif
- if (kbd_input_empty() == 0)
- return -1;
+ if (kbd_input_empty() == 0)
+ return -1;
- out8 (I8042_DATA_REG, 0x45);
+ out8(I8042_DATA_REG, 0x45);
- if (kbd_input_empty() == 0)
- return -1;
+ if (kbd_input_empty() == 0)
+ return -1;
- out8 (I8042_COMMAND_REG, 0xae);
+ out8(I8042_COMMAND_REG, 0xae);
- if (kbd_input_empty() == 0)
- return -1;
+ if (kbd_input_empty() == 0)
+ return -1;
- return 0;
+ return 0;
}
#include "fm.h"
#include "../../qe/qe.h" /* For struct qe_firmware */
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
#include <spi_flash.h>
-#elif defined(CONFIG_SYS_QE_FW_IN_MMC)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
#include <mmc.h>
#endif
{
int rc;
char env_addr[32];
-#if defined(CONFIG_SYS_FMAN_FW_ADDR)
- void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
-#elif defined(CONFIG_SYS_QE_FW_IN_NAND)
- size_t fw_length = CONFIG_SYS_FMAN_FW_LENGTH;
- void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
+#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
+ void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+ void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
- CONFIG_SYS_QE_FW_IN_NAND, rc);
+ CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
}
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
- void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
+ void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
- ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FW_IN_SPIFLASH,
- CONFIG_SYS_FMAN_FW_LENGTH, addr);
+ ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
+ CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
if (ret)
printf("SF: read for ucode failed\n");
spi_flash_free(ucode_flash);
}
-#elif defined(CONFIG_SYS_QE_FW_IN_MMC)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
int dev = CONFIG_SYS_MMC_ENV_DEV;
- void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
- u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512;
- u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512;
+ void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc)
/* Init the QE IMMR base */
qe_immr = (qe_map_t *)qe_base;
-#ifdef CONFIG_SYS_QE_FW_ADDR
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
/*
* Upload microcode to IRAM for those SOCs which do not have ROM in QE.
*/
- qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR);
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
/* enable the microcode in IRAM */
out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
__u8 *bufp = data_buf;
int len = 0;
int status = 0;
-
__u16 bmRType_bReq;
- __u16 wValue;
- __u16 wIndex;
- __u16 wLength;
+ __u16 wValue = le16_to_cpu (cmd->value);
+ __u16 wLength = le16_to_cpu (cmd->length);
+#ifdef SL811_DEBUG
+ __u16 wIndex = le16_to_cpu (cmd->index);
+#endif
if (usb_pipeint(pipe)) {
PDEBUG(0, "interrupt transfer unimplemented!\n");
}
bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = le16_to_cpu (cmd->value);
- wIndex = le16_to_cpu (cmd->index);
- wLength = le16_to_cpu (cmd->length);
PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n",
bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength);
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000
/*
* BOOTP options
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
-#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#else
-#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000
#endif
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
--- /dev/null
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* The P2020COME board is only booted via the Freescale On-Chip ROM */
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+
+#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD 1
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH 1
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
+#define CONFIG_P2020 1
+#define CONFIG_P2020COME 1
+#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
+#define CONFIG_MP
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
+
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+/*
+ * For P2020COME DDRCLK and SYSCLK are from the same oscillator
+ * For DA phase the SYSCLK is 66MHz
+ * For EA phase the SYSCLK is 100MHz
+ */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch prediction */
+
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+
+
+
+
+
+
+ /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
+ + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
+#define CONFIG_SYS_DDR_SBE 0x00ff0000
+
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS 0x53
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
+ * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
+ * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
+ * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
+ * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
+ * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
+ *
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* There is no NOR Flash on P2020COME */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* the assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#if defined(CONFIG_PCI)
+
+/* controller 3, Slot 3, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x) (x)
+#define _IO_BASE 0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 2
+#define TSEC3_PHY_ADDR 1
+
+#undef CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH
+ #define CONFIG_ENV_SPI_BUS 0
+ #define CONFIG_ENV_SPI_CS 0
+ #define CONFIG_ENV_SPI_MAX_HZ 10000000
+ #define CONFIG_ENV_SPI_MODE 0
+ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+ #define CONFIG_ENV_SECT_SIZE 0x10000
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif /* CONFIG_MMC */
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Misc Extra Settings */
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+#define CONFIG_CMD_DHCP 1
+
+#define CONFIG_CMD_DATE 1
+#define CONFIG_RTC_M41T62 1
+#define CONFIG_SYS_RTC_BUS_NUM 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ecc=on\0" \
+ "bootcmd=run sdboot\0" \
+ "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
+ "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+ "$othbootargs; mmcinfo; " \
+ "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
+ "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
+ "bootm $loadaddr - $fdtaddr\0" \
+ "sdfatboot=setenv bootargs root=/dev/ram rw " \
+ "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+ "$othbootargs; mmcinfo; " \
+ "fatload mmc 0:1 $loadaddr $bootfile; " \
+ "fatload mmc 0:1 $fdtaddr $fdtfile; " \
+ "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "usbboot=setenv bootargs root=/dev/sda1 rw " \
+ "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+ "$othbootargs; " \
+ "usb start; " \
+ "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
+ "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
+ "bootm $loadaddr - $fdtaddr\0" \
+ "usbfatboot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start; " \
+ "fatload usb 0:2 $loadaddr $bootfile; " \
+ "fatload usb 0:2 $fdtaddr $fdtfile; " \
+ "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "usbext2boot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start; " \
+ "ext2load usb 0:4 $loadaddr $bootfile; " \
+ "ext2load usb 0:4 $fdtaddr $fdtfile; " \
+ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "upgradespi=sf probe 0; " \
+ "setenv startaddr 0; " \
+ "setenv erasesize a0000; " \
+ "tftp 1000000 $tftppath/$uboot_spi; " \
+ "sf erase $startaddr $erasesize; " \
+ "sf write 1000000 $startaddr $filesize; " \
+ "sf erase 100000 120000\0" \
+ "clearspienv=sf probe 0;sf erase 100000 20000\0" \
+ "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
+ "netdev=eth0\0" \
+ "rootdelaysecond=15\0" \
+ "uboot_nor=u-boot-nor.bin\0" \
+ "uboot_spi=u-boot-p2020.spi\0" \
+ "uboot_sd=u-boot-p2020.bin\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs-dev.ext2.img\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=uImage-2.6.32-p2020.dtb\0" \
+ "tftppath=p2020\0"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "usb start;" \
+ "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
+ "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $tftppath/$bootfile;" \
+ "tftp $fdtaddr $tftppath/$fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
+ "tftp $loadaddr $tftppath/$bootfile;" \
+ "tftp $fdtaddr $tftppath/$fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
*/
-#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#endif
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#endif /* CONFIG_PCI */
/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LIBATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P3060 QDS board configuration file
+ */
+#define CONFIG_P3060QDS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P3060
+#define CONFIG_FSL_QIXIS
+
+#define CONFIG_NAND_FSL_ELBC
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_SST
+
+#include "corenet_ds.h"
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
+#define CONFIG_I2C_MUX
+#define CONFIG_I2C_MULTI_BUS
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
+#define CONFIG_PCI_BOOTDELAY 0
+
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
+#ifdef CONFIG_P3060QDS
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#else
#define CONFIG_SYS_SPD_BUS_NUM 1
+#endif
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
*/
-#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#endif
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_P4080DS)
+#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
#define __USB_PHY_TYPE ulpi
#else
#define __USB_PHY_TYPE utmi
#define CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_ZBOOT
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
#undef CONFIG_SYS_GENERIC_TIMER
#define CONFIG_SYS_PCAT_INTERRUPTS
#define CONFIG_SYS_NUM_IRQS 16
+#define CONFIG_SYS_PC_BIOS
+#define CONFIG_SYS_PCI_BIOS
+#define CONFIG_SYS_X86_REALMODE
+#define CONFIG_SYS_X86_ISR_TIMER
/*-----------------------------------------------------------------------
* Memory organization:
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on kilauea.h
+ * by Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * and Grant Erickson <gerickson@nuovations.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_IO64 1 /* Board is Io64 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EX 1 /* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
+/*
+ * CHIP_21 errata
+ */
+#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME io64
+#define CONFIG_IDENT_STRING " io64 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_NVRAM_BASE 0xF0000000
+#define CONFIG_SYS_FPGA0_BASE 0xF0100000
+#define CONFIG_SYS_FPGA1_BASE 0xF0108000
+#define CONFIG_SYS_LATCH_BASE 0xF0200000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ * There are traditionally three options for the primordial
+ * (i.e. initial) stack usage on the 405-series:
+ *
+ * 1) On-chip Memory (OCM) (i.e. SRAM)
+ * 2) Data cache
+ * 3) SDRAM
+ *
+ * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ * the latter of which is less than desireable since it requires
+ * setting up the SDRAM and ECC in assembly code.
+ *
+ * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
+ * select on the External Bus Controller (EBC) and then select a
+ * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
+ * physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_DCACHE_CS 4
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+#define CONFIG_SYS_INIT_RAM_SIZE \
+ (4 << 10) /* 4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_WORD_ADDR \
+ (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CONFIG_SYS_INIT_EXTRA_SIZE 16
+# define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
+#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
+
+#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
+#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
+
+#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
+
+/*
+ * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+ *
+ * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
+ * SDRAM Controller DDR autocalibration values and takes a lot longer
+ * to run than Method_B.
+ * (See the Method_A and Method_B algorithm discription in the file:
+ * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
+ *
+ * DDR Autocalibration Method_B is the default.
+ */
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
+ SDRAM_MCOPT1_4_BANKS | \
+ SDRAM_MCOPT1_DDR2_TYPE | \
+ SDRAM_MCOPT1_QDEP | \
+ SDRAM_MCOPT1_DCOO_DISABLED)
+#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
+ SDRAM_MODT_EB0R_ENABLE)
+#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
+#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
+ SDRAM_CODT_CKLZ_36OHM | \
+ SDRAM_CODT_DQS_1_8_V_DDR2 | \
+ SDRAM_CODT_IO_NMODE)
+#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(80) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
+ SDRAM_INITPLR_IMA_ENCODE(0))
+#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_75OHM))
+#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+ JEDEC_MA_MR_BLEN_4 | \
+ JEDEC_MA_MR_DLL_RESET))
+#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(0x0) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+ JEDEC_MA_MR_BLEN_4))
+#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
+ SDRAM_RQDC_RQFD_ENCODE(56))
+#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
+#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
+ SDRAM_DLCR_DLCS_CONT_DONE | \
+ SDRAM_DLCR_DLCV_ENCODE(165))
+#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
+#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
+ SDRAM_SDTR1_RTW_2_CLK | \
+ SDRAM_SDTR1_WTWO_1_CLK | \
+ SDRAM_SDTR1_RTRO_1_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
+ SDRAM_SDTR2_WTR_2_CLK | \
+ SDRAM_SDTR2_XSNR_32_CLK | \
+ SDRAM_SDTR2_WPC_4_CLK | \
+ SDRAM_SDTR2_RPC_2_CLK | \
+ SDRAM_SDTR2_RP_3_CLK | \
+ SDRAM_SDTR2_RRD_2_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
+ SDRAM_SDTR3_RC_ENCODE(12) | \
+ SDRAM_SDTR3_XCS | \
+ SDRAM_SDTR3_RFC_ENCODE(21))
+#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
+ SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
+ SDRAM_MMODE_BLEN_4)
+#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
+ SDRAM_MEMODE_RTT_75OHM)
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+
+#define CONFIG_PCA9698 1 /* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
+ { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
+#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0 1
+
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 0x13
+
+/* Debug messages for the DDR autocalibration */
+#define CONFIG_AUTOCALIB "silent\0"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "logversion=2\0" \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DTT
+
+#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
+
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY_ON | \
+ CONFIG_SYS_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(11) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(2) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+ EBC_BXCR_BS_64MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (NVRAM/Uart) */
+#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_8BIT)
+
+/* Memory Bank 2 (FPGA) */
+#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(5) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+ (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+ (k ? 0x0040 : 0x0080)
+
+#define CONFIG_SYS_FPGA_COUNT 2
+
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
+} \
+}
+
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
+
+#endif /* __CONFIG_H */
#ifdef CONFIG_QE
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FW_LENGTH 0x10000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
#ifdef CONFIG_P1025RDB
#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04)
#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05)
#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06)
+#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07)
+#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
+#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
+#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A)
+#define DDR3_SPD_MODULETYPE_LRDIMM (0x0B)
+#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
+#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
#endif /* _DDR_SPD_H_ */
#ifndef __GDSYS_FPGA_H
#define __GDSYS_FPGA_H
+int init_func_fpga(void);
+
enum {
FPGA_STATE_DONE_FAILED = 1 << 0,
FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+ FPGA_STATE_PLATFORM = 1 << 2,
};
int get_fpga_state(unsigned dev);
} ihs_fpga_t;
#endif
+#ifdef CONFIG_IO64
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_features; /* 0x0004 */
+ u16 fpga_version; /* 0x0006 */
+ u16 reserved_0[5]; /* 0x0008 */
+ u16 quad_serdes_reset; /* 0x0012 */
+ u16 reserved_1[502]; /* 0x0014 */
+ u16 ch0_status_int; /* 0x0400 */
+ u16 ch0_config_int; /* 0x0402 */
+ u16 reserved_2[7677]; /* 0x0404 */
+ u16 reflection_high; /* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
#ifdef CONFIG_IOCON
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
#define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */
#define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */
#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */
+#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
/*
* Compression Types
/* test write/read og a given LIME Register */
static int gdc_test_reg_one(uint value)
{
- int ret;
uint read_value;
/* write test pattern */
out_be32((void *)GDC_SCRATCH_REG, value);
/* read other location (protect against data lines capacity) */
- ret = in_be32((void *)GDC_RAM_START);
+ in_be32((void *)GDC_RAM_START);
/* verify test pattern */
read_value = in_be32((void *)GDC_SCRATCH_REG);
if (read_value != value) {
static int image_check_image_types(uint8_t type)
{
- if ((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT))
+ if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) ||
+ (type == IH_TYPE_KERNEL_NOLOAD))
return EXIT_SUCCESS;
else
return EXIT_FAILURE;
projects / people / ms / u-boot.git / commitdiff
