]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
arm: zynq: Enable FPGA/FPGA_XILINX via Kconfig
authorMichal Simek <michal.simek@xilinx.com>
Fri, 3 Nov 2017 14:53:56 +0000 (15:53 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 28 Nov 2017 15:08:45 +0000 (16:08 +0100)
Enabling fpga via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
17 files changed:
configs/syzygy_hub_defconfig
configs/topic_miami_defconfig
configs/topic_miamilite_defconfig
configs/topic_miamiplus_defconfig
configs/zynq_cc108_defconfig
configs/zynq_microzed_defconfig
configs/zynq_picozed_defconfig
configs/zynq_z_turn_defconfig
configs/zynq_zc702_defconfig
configs/zynq_zc706_defconfig
configs/zynq_zc770_xm010_defconfig
configs/zynq_zc770_xm011_defconfig
configs/zynq_zc770_xm012_defconfig
configs/zynq_zc770_xm013_defconfig
configs/zynq_zed_defconfig
configs/zynq_zybo_defconfig
include/configs/zynq-common.h

index 544a31fabe6bbe54bdb525109ee878a85112c539..d25b48b6c9a9b1c8aa9a786fd7a949070414551d 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_ZYNQ_GEM=y
index fc06dc93c5fefeb9e84008ba166b8e3090b8cb6a..60623ff1158d02fdc019c1179804ee858e971276 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index 6a5348ed504fc08a57458701a900453a4dd0856e..1d6318906501f9567e79d884d24f23d442c23330 100644 (file)
@@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index d8f6fcf782b921c203c1ee2ede22d3a28209c453..2c080bc3d6018a1cc21df4f40c1d309f664c42ea 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index 9d7ba63a0dc944812bfa9c8ed64c0be333755336..6fe20ba4723a2145697f6b4b64e8c5d61270a42f 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index ad0ecc65b0c62707cb826ab8c3b938663d821f2f..a6a37f87d8f2cef3cf4243c944659adaeb671c37 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index d4344d96dcf0b1a0efe6f029c5c1e10cea0aa6ee..0d7b9d68972b6f46d7312bd2143d3931a0f4af4e 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_ZYNQ_GEM=y
index af959275febd5611140c55815f3a0e16c3d1dd97..2ab0d86ca3b02469e54927738d8187ecb0886dc1 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index 54fcbfae7ae65e4ccbdac104027c58de4d49aa02..edd8f22bd820dc40dae4f7a68e8285f6cef830db 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index e1b8c226c8e5f5942d6271c8cd2147c7012b585e..1e0733023cc08d77ad8370cda470274b1d403d9e 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index a00919faf80ea8752f01a8a9593baad67795553c..95e4a24eb16aeb085c4c2f7e044088a56631b2c6 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index 193c118c5743eda57b4b87237ed00e75507a76f6..095ee2fe86767c92a6e2079c5cff44b1744ef4c5 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 # CONFIG_MMC is not set
 CONFIG_NAND=y
 CONFIG_NAND_ZYNQ=y
index c62bdb1ef4535c14b7d8c8aca659afd282c94b56..946cfc785db76f0d00c7aaeca4b7156e8f33f568 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_ZYNQ_GEM=y
index 39f6199c47f9d18763b6df1d2584e6edd8336f94..6d34b2169a87ae1217afbc3d2f24aec90e205a02 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
index 8fafe081408a3bbbcf8e1ce4c9809e97f1417c0d..42012021c09fec0a33c4ef4870cb13ee38f0afbf 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index 9157d0cb8079c5c8b5518a5fa980d3e283549c56..d0ef2238388f968c609df3fbc121903ba8d31a07 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
index 8de2ac351ca881902ccb2ee01233323025b283a7..e68067319d6dc9cbf3c1b23c1c5b3ba82ac5d56f 100644 (file)
                                        GENERATED_GBL_DATA_SIZE)
 
 /* Enable the PL to be downloaded */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_ZYNQPL
 
 /* FIT support */
 /* Disable dcache for SPL just for sure */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_FPGA
 #endif
 
 /* Address in RAM where the parameters must be copied by SPL. */