]> git.ipfire.org Git - ipfire-2.x.git/commitdiff
suricata: Fix check for level one cache line size
authorMichael Tremer <michael.tremer@ipfire.org>
Tue, 22 Feb 2022 12:51:32 +0000 (12:51 +0000)
committerPeter Müller <peter.mueller@ipfire.org>
Tue, 22 Feb 2022 19:41:39 +0000 (19:41 +0000)
riscv64 does not return any value on our machine (maybe because it is
emulated?). "undefined" is however seen as a valid value, which makes
the build fail.

Signed-off-by: Michael Tremer <michael.tremer@ipfire.org>
lfs/suricata
src/patches/suricata-5.0.8-fix-level1-cache-line-size-detection.patch [new file with mode: 0644]

index a870e3668c63216096e02dc9a6221c146d9ce10a..65f5e504c95931f11c317685e818bab3f9b3a28c 100644 (file)
@@ -72,6 +72,7 @@ $(TARGET) : $(patsubst %,$(DIR_DL)/%,$(objects))
        @rm -rf $(DIR_APP) && cd $(DIR_SRC) && tar zxf $(DIR_DL)/$(DL_FILE)
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/suricata-5.0-stream-tcp-Handle-retransmitted-SYN-with-TSval.patch
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/suricata-disable-sid-2210059.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/suricata-5.0.8-fix-level1-cache-line-size-detection.patch
        cd $(DIR_APP) && LDFLAGS="$(LDFLAGS)" ./configure \
                --prefix=/usr \
                --sysconfdir=/etc \
diff --git a/src/patches/suricata-5.0.8-fix-level1-cache-line-size-detection.patch b/src/patches/suricata-5.0.8-fix-level1-cache-line-size-detection.patch
new file mode 100644 (file)
index 0000000..a6747a2
--- /dev/null
@@ -0,0 +1,13 @@
+diff --git a/configure.ac b/configure.ac
+index d56d3a550..81abf8f00 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -2313,7 +2313,7 @@ fi
+     AC_PATH_PROG(HAVE_GETCONF_CMD, getconf, "no")
+     if test "$HAVE_GETCONF_CMD" != "no"; then
+         CLS=$(getconf LEVEL1_DCACHE_LINESIZE)
+-        if [test "$CLS" != "" && test "$CLS" != "0"]; then
++        if [test "$CLS" != "" && test "$CLS" != "0" && test "$CLS" != "undefined"]; then
+             AC_DEFINE_UNQUOTED([CLS],[${CLS}],[L1 cache line size])
+         else
+             AC_DEFINE([CLS],[64],[L1 cache line size])