prctl.2: srcfix: rewrap lines

Signed-off-by: Michael Kerrisk <mtk.manpages@gmail.com>

diff --git a/man2/prctl.2 b/man2/prctl.2
index 954641c1290a851de3c1f9689a05564058c2ade2..58f9daeb4a90bcc2193695cd545f7cf03da126c7 100644 (file)
--- a/man2/prctl.2
+++ b/man2/prctl.2
@@ -266,15 +266,19 @@ in the location pointed to by
 .\" 9791554b45a2acc28247f66a5fd5bbc212a6b8c8
 .TP
 .BR PR_SET_FP_MODE " (since Linux 4.0, only on MIPS)"
-On MIPS, user land code can be built using ABI which permits linking with a code
-with a more restrictive floating point requirements.  For example, user land
-code may be built to target the O32 FPXX ABI and linked with code built for
-either one of the more restrictive FP32 or FP64. When more restrictive code is
-linked in, the overall requirement for the process is to use this more
-restrictive floating point mode. Since kernel has no means of knowing in advance
-which mode process should be executed in, and having possibility that these
-restrictions can be changed during the process' lifetime, the ability to control
-it from the user space via this option is provided.
+On MIPS, user land code can be built using ABI which permits linking
+with a code with a more restrictive floating point requirements.
+For example, user land code may be built to target the O32 FPXX ABI
+and linked with code built for either one of the more restrictive
+FP32 or FP64.
+When more restrictive code is linked in,
+the overall requirement for the process is to use this more
+restrictive floating point mode.
+Since kernel has no means of knowing in advance
+which mode process should be executed in,
+and having possibility that these restrictions can
+be changed during the process' lifetime,
+the ability to control it from the user space via this option is provided.
 
 .\" https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
 The
@@ -287,14 +291,17 @@ When this bit is
 .I unset
 (so called
 .BR FR=0 " or " FR0
-mode), 32 FP registers are 32-bit wide, and 64-bit registers are represented as
-pair of registers (even- and odd- numbered, with even-numbered register
-containing lower 32 bits, and odd-numbered register containing higher 32 bits).
+mode), 32 FP registers are 32-bit wide,
+and 64-bit registers are represented as pair of registers
+(even- and odd- numbered,
+with even-numbered register containing lower 32 bits,
+and odd-numbered register containing higher 32 bits).
 When this bit is
 .I set
 (on supported hardware), 32 FP registers are 64-bit wide (so called
 .BR FR=1 " or " FR1
-mode). Note that modern MIPS implementations (MIPS R6 and newer) support
+mode)
+Note that modern MIPS implementations (MIPS R6 and newer) support
 .B FR=1
 mode only.
 
@@ -310,35 +317,40 @@ only when this bit is
 Applications that use O32 FPXX ABI can operate in both cases.
 .TP
 .BR PR_FP_MODE_FRE " = " "(1 << 1)"
-Compatibility with 32-bit FP mode. When this mode is enabled, it emulates 32-bit
-FP operations by raising reserved instruction exception on every instruction
-that uses 32-bit formats and kernel then handles the instruction in software
-(the problem lies in discrepancy of handling odd-numbered registers which are
-high 32 bits of 64-bit registers with even numbers in
+Compatibility with 32-bit FP mode.
+When this mode is enabled,
+it emulates 32-bit FP operations by raising reserved instruction exception
+on every instruction that uses 32-bit formats and
+kernel then handles the instruction in software
+(the problem lies in discrepancy of handling odd-numbered registers
+which are high 32 bits of 64-bit registers with even numbers in
 .B FR=0
 mode and lower 32-bit parts of odd-numbered 64-bit registers in
 .B FR=1
-mode). Enabling of this bit is needed when code with O32 FP32 ABI should operate
+mode).
+Enabling of this bit is needed when code with O32 FP32 ABI should operate
 with code with compatible O32 FPXX or O32 FP64A ABIs (which require
 .B FR=1
-FPU mode) or when it is executed on newer hardware (MIPS R6 onwards) which lacks
+FPU mode) or when it is executed on newer hardware (MIPS R6 onwards)
+which lacks
 .B FR=0
 mode support when binary with FP32 ABI is used.
 .IP
 Note that this mode only makes sense when FPU is in 64-bit mode
 .RB ( FR=1 .)
 .IP
-Note that usage of emulation inherently has a significant performance hit and
-should be avoided if possible.
+Note that usage of emulation inherently has a significant performance hit
+and should be avoided if possible.
 .RE
 .IP
-Note that for N32/N64 ABI is a different story and does not need FPU emulation
-and always operates in
+Note that for N32/N64 ABI is a different story and
+does not need FPU emulation and always operates in
 .B FR=1
 mode.
 .IP
-This option is mainly intended for use by dynamic loader, but may be of use by
-applications in case library loading during runtime (via
+This option is mainly intended for use by dynamic loader,
+but may be of use by applications in case library loading
+during runtime (via
 .BR dlopen (3),
 for example) is used.
 .IP