+commit 135e19bc2773ebca487e9a8371f67e1ba202313a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Sep 18 21:36:35 2007 +0200
+
+ Avoid compiler warning.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8a783a65851bc7421ab69f442261215e21b8891a
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Sep 18 12:24:57 2007 -0600
+
+ Bugfix: remove embedded null (\0) from CFG_BOOTFILE macro in TQM8540_config
+
+ /bin/bash and /bin/dash (which /bin/sh is linked to on ubuntu) handle embedded
+ nulls in a string differently. For example, the following statement:
+ echo "this is a string\0" > afile
+ Will produce the following with /bin/bash:
+ "this is a string\0"
+ But with /bin/dash, will produce:
+ "this is a string
+
+ Bug fixed by moving the embedded null out of the makefile and into the
+ config header. Also renamed the macro to avoid usage colision with the same
+ macro used by other board ports.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit f8d3ca7b6fa322ac57e8e831f07dbeea039a9f35
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Sep 18 17:40:27 2007 +0200
+
+ MCC200: fix build warning
+
+ The MCC200 board config file includes version.h for some customer-
+ specific setting, which causes warnings with "make depend"; build
+ version.h before depend.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 67c31036acaaaa992fc346cc89db0909a7e733c4
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Sep 16 17:10:04 2007 +0200
+
+ TQM8xx[LM]: Fix broken environment alignment.
+
+ With recent toolchains, the environment sectors were no longer aligned to
+ sector boundaries. The reason was a combination of two bugs:
+
+ 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined
+ for all TQM8xxL and TQM8xxM boards. But "include/common.h", where
+ this gets defined, is not included here (and cannot be included
+ without causing lots of problems).
+
+ Added a new #define CFG_USE_PPCENV for all boards which really
+ want to put the environment is a ".ppcenv" section.
+
+ 2) The linker scripts just include environment.o, silently assuming
+ that the objects in that file are really in the order in which
+ they are coded in the C file, i. e. "environment" first, then
+ "redundand_environment", and "env_size" last. However, current
+ toolchains (GCC-4.x) reorder the objects, causing the environment
+ data not to start on a flash sector boundary:
+
+ Instead of: we got:
+
+ 40008000 T environment 40008000 T env_size
+ 4000c000 T redundand_environment 40008004 T redundand_environment
+ 40010000 T env_size 4000c004 T environment
+
+ Note: this patch fixes just the first part, and cures the alignment
+ problem by making sure that "env_size" gets placed correctly. However,
+ we still have a potential issue because primary and redundant
+ environment sectors are actually swapped, i. e. we have now:
+
+ 40008000 T redundand_environment
+ 4000c000 T environment
+ 40010000 T env_size
+
+ This shall be fixed in the next version.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit eb6da8050797c204c9d010548424186c7ce32fc1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Sep 16 02:39:35 2007 +0200
+
+ TQM8xx/FPS8xx: adjust flash partitions for 2.6 ARCH=powerpc kernels
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cd2d1602c54cc6957bdef3872272a4b264893960
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date: Mon Sep 10 14:54:56 2007 -0400
+
+ Typo fix in tsec.c
+
+ Fixup for the break statement in wrong place.
+
+ [Patch by urwithsughosh@gmail.com]
+ Acked-by: Andy Fleming <afleming@freescale.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5bd7fe9aeb76906371f40b8fd07613f10922e3e7
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Tue Sep 11 17:04:00 2007 +0200
+
+ Fix do_div() usage in nand process output
+
+ Fix usage of do_div() in nand erase|read|write process output.
+
+ The last patch to nand_util.c introduced do_div() instead of libgcc's
+ implementation. But do_div() returns the quotient in its first
+ macro parameter and not as result.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit c750d2e6692a000a82f29de7bf24e3dc21239161
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Wed Sep 12 12:36:53 2007 +0200
+
+ NAND: Add CFG_NAND_QUIET option
+
+ This config option sets the default for the progress information
+ output behavior that can also be configured through the 'quiet'
+ environment variable.
+
+ The legacy NAND code does not print the current progress info
+ on the console. So this option is for backward compatibility for
+ units that are in the field and where setting the quiet variable
+ is not an option. With CFG_NAND_QUIET set to '1' the console
+ progress info is turned off. This can still be overwritten
+ through the environment variable.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit dcb88630290d2bcd803386dd4c2be73142994c4f
+Author: Liew Tsi Chung-r5aahp <Tsi-chung.Liew@freescale.com>
+Date: Thu Sep 13 16:06:05 2007 -0700
+
+ ColdFire: fix build error becasue of bad type of mii_init()
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 314d5b6ce52a4ed19dd295d1364e246c5e605017
+Author: Liew Tsi Chung-r5aahp <Tsi-chung.Liew@freescale.com>
+Date: Thu Sep 13 16:04:05 2007 -0700
+
+ ColdFire: Fix build error caused by pixis.c
+
+ Moved the #include <asm/cache.h> inside the #ifdef CONFIG_FSL_PIXIS.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit e21659e30660a1377c42af135a6114efe39801d9
+Author: Sam Sparks <SSparks@twacs.com>
+Date: Fri Sep 14 11:14:42 2007 -0600
+
+ Update MPC8349ITX*_config to place config.tmp in right place.
+
+ MPC834ITX*_config does not store config.tmp at the correct locatation,
+ causing MPC8349ITXGP to have the wrong TEXT_BASE.
+
+ Signed-off-by: Sam Sparks <SSparks@twacs.com>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 1218abf1b5817a39a82399b4b928b00750575bda
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Sep 15 20:48:41 2007 +0200
+
+ Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 66b3f24d665be678a9dbb125b1e84185400f63b5
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sat Sep 15 11:55:42 2007 +0200
+
+ Make DECLARE_GLOBAL_DATA_PTR global for DaVinci
+
+ As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not
+ function local.
+
+ Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+ [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805
+
+commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Thu Sep 13 18:21:48 2007 +0200
+
+ cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit f34024d4a328e6edd906456da98d2c537155c4f7
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Sep 12 00:48:57 2007 +0200
+
+ Fix memory corruption problem on STX GP3 SSA Board.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Sep 11 15:42:11 2007 +0200
+
+ [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to
+ scan on second pci bus.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 6c2f4f388e8181655ea8b69343ea00b68aa6e8d0
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Sep 11 12:57:52 2007 +0200
+
+ [ppc4xx] Individual handling of sdram.c for bamboo_nand build
+
+ Bamboo has a file sdram.c which needs special treatment when building in
+ separate directory. It has to be linked to build directory otherwise it is
+ not seen.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 38c1ef728d19950414a8ab1ccfc53767848fa346
+Author: Sean MCGOOGAN <sean.mcgoogan@st.com>
+Date: Mon Sep 10 16:55:59 2007 +0100
+
+ Allocate CPU Architecture Code for STMicroelectronics' ST200.
+
+ Signed-off-by: Sean McGoogan <Sean.McGoogan@st.com>
+ ---------------------------------------------------
+
+commit 754bac48156f8958d8f6a53a51eda88ab5758929
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Sep 10 20:42:31 2007 +0200
+
+ Update version to match current state.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7a888d6b3c32a126dbb504ef146bb4c26574ca7b
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Mon Sep 10 17:39:08 2007 +0200
+
+ [MPC512x] Streamline frame handling in the FEC driver
+
+ - convert frame size settings to be derived from a single base
+ - set frame size to the recommended default value
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit e251e00d0db4b36d1d2b7e38fec43a7296b529a2
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 11:34:00 2007 +0900
+
+ Remove compiler warning: target CPU does not support interworking
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 1d9e31e04911a6bb7cc66dd91132c699101c32e2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Sep 9 21:21:33 2007 +0200
+
+ Fix compile error in spc1920 config.
+
+ Signed-off-by: Markus Klotzbücher <mk@denx.de>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a7d7eca791a37f452c9da10fef4b31dd7aa9a622
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Fri Sep 7 09:25:07 2007 -0600
+
+ Bugfix: make bootm+libfdt compile on boards with no flash
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 18:35:37 2007 +0200
+
+ [PPC440SPe] PCIe environment settings for Katmai and Yucca
+
+ - 'pciconfighost' is set by default in order to be able to scan bridges
+ behind the primary host/PCIe
+
+ - 'pciscandelay' env variable is recognized to allow for user-controlled
+ delay before the PCIe bus enumeration; some peripheral devices require a
+ significant delay before they can be scanned (e.g. LSI8408E); without the
+ delay they are not detected
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 7f1913938984ef6c6a46cb53e003719196d9c5de
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 18:20:23 2007 +0200
+
+ [PPC440SPe] Improve PCIe configuration space access
+
+ - correct configuration space mapping
+ - correct bus numbering
+ - better access to config space
+
+ Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
+ first device on the first bus. We now allow to configure up to 16 buses;
+ also, scanning for devices behind the PCIe-PCIe bridge is supported, so
+ peripheral devices farther in hierarchy can be identified.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 15ee4734e4e08003d73d9ead3ca80e2a0672e427
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 17:46:18 2007 +0200
+
+ [PPC440SPe] Convert machine check exceptions handling
+
+ Convert using fixup mechanism to suppressing MCK for the duration of config
+ read/write transaction: while fixups work fine with the case of a precise
+ exception, we identified a major drawback with this approach when there's
+ an imprecise case. In this scenario there is the following race condition:
+ the fixup is (by design) set to catch the instruction following the one
+ actually causing the exception; if an interrupt (e.g. decrementer) happens
+ between those two instructions, the ISR code is executed before the fixup
+ handler the machine check is no longer protected by the fixup handler as it
+ appears as within the ISR code. In consequence the fixup approach is being
+ phased out and replaced with explicit suppressing of MCK during a PCIe
+ config read/write cycle.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit ff7640c9ead8806b5d827f2b29f9cb2632add729
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Sep 7 17:43:36 2007 +0200
+
+ Fix typo in MAKEALL script.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 08e2e5fcd2e06670b62e1680a3934c0e55c72810
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Fri Sep 7 17:09:21 2007 +0200
+
+ [MPC512x] Proper handling of larger frames in the FEC driver
+
+ When frame larger than local RX buffer is received, it is split and handled
+ by two buffer descriptors. Prior to this patch the FEC driver discarded
+ contents of a buffer descriptor without the 'LAST' bit set, so the first
+ part of the frame was lost in case of larger frames. This fix allows to
+ safely combine the two pieces into the whole frame.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 8d17979d0359492a822a0a409d26e3a3549b4cd4
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Sep 7 17:05:36 2007 +0200
+
+ [MPC512x] Correct fixup relocation
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit a89cbbd27a60e6740772000fd0688ffba1c2576a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Sep 7 01:21:25 2007 +0200
+
+ Update CHANGELOG, minor coding style cleanup.
+
+commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3
+Author: stefano babic <sbabic@denx.de>
+Date: Thu Aug 30 23:01:49 2007 +0200
+
+ PXA270: Added support for TrizepsIV board.
+
+ This patch add support for the Trizeps IV module (520Mhz).
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 80172c6181c912fbb34ea3ba0c22b232b419b47f
+Author: stefano babic <sbabic@denx.de>
+Date: Thu Aug 30 22:57:04 2007 +0200
+
+ PXA270: Add support for multiple serial ports.
+
+ This patch adds support for multiple serial ports to the PXA target.
+ FFUART, BTUART and STUART are supported.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e
+Author: stefano babic <sbabic@denx.de>
+Date: Thu Aug 30 22:48:47 2007 +0200
+
+ PXA270: fix compile issue (invalid lvalue)
+
+ Code is broken for PXA270 due to "invalid lvalue in assignment".
+
+ This patch fix it in pxa-regs.h
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 1d2ca446e1a731df420206d04fe278c27ea6b8e8
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Thu Aug 30 18:19:05 2007 +0800
+
+ Add BUILD_DIR support for bios emulator.
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit b4d8a55145442f136982634862341a3e02002bda
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Fri Aug 31 14:41:51 2007 +0900
+
+ [MIPS] Remove inline asm string functions
+
+ Stop using inline string functions on MIPS as other ARCHs do so,
+ since the optimized inline asm versions are not small.
+
+ This change is triggered by a following MIPS build error:
+ common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init':
+ common/exports.c:32: undefined reference to `strcmp'
+ make: *** [u-boot] Error 1
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Fri Aug 31 14:41:45 2007 +0900
+
+ [MIPS] Update asm string header
+
+ This patches contains several bugfixes and cleanups in the latest upstream:
+
+ - Don't include linux/config.h
+ - Remove buggy inline version of memscan.
+ - Merge with Linux 2.6.11-rc3.
+ - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4.
+ - Goodbye mips64. 31704 lines of code bite the dust.
+ - Replace extern inline with static inline.
+ - Fix return value of strncpy.
+ - Remove a bunch more "$1" clobbers.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Sep 4 17:31:22 2007 +0200
+
+ Fix do_bootm_linux() so that multi-file images with FDT blob boot.
+
+ Fix incorrect blob address calculation in do_bootm_linux() that prevents
+ booting the kernel from a multi-file image (kernel + initrd + blob).
+
+ Also, make minor updates to the U-Boot's output and to the coding style.
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 041a2554ad619e80dce520c1a33210affcb6a3f2
+Author: Gary Jennejohn <gary.jennejohn@freenet.de>
+Date: Fri Aug 31 14:29:04 2007 +0200
+
+ Add support for Sil680 IDE controller.
+
+ o add drivers/sil680.c to support the Sil680 IDE-controller.
+ o drivers/Makefile: add sil680.o.
+
+ Signed-off-by: Gary Jennejohn <garyj@denx.de>
+
+commit e79021223bc339df655e360645a52c457a74b067
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Sep 6 09:47:40 2007 -0600
+
+ bootm/fdt: Only process the fdt if an fdt address was provided
+
+ Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style
+ kernels using the board info structure (instead of passing a device tree)
+ This change allows the old style booting to be used if the fdt argument
+ was not passed to 'bootm'.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Sep 6 09:46:23 2007 -0600
+
+ Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT
+
+ Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200
+
+ Tested on: lite5200b
+
+ Note: the fixup functions have not been moved to a common place. This
+ patch is targeted for immediate merging as in solves a build issue, but
+ the final name/location of the fixups is still subject to debate. I
+ propose to merge this now, and move the fixups in the next merge window
+ to be usable by all targets.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 41bb76e941929f54a73206fb132f7a4c275543a3
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Sep 6 09:46:17 2007 -0600
+
+ libfdt: add convenience function fdt_find_and_setprop()
+
+ Given the path to a node, fdt_find_and_setprop() allows a property value
+ to be set directly.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 56a9270521baaa00e12639a978302a67f61ef060
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Aug 30 16:18:18 2007 -0500
+
+ Fix ULI RTC support on MPC8544 DS
+
+ The RTC on the M1575 ULI chipset requires a dummy read before
+ we are able to talk to the RTC. We accomplish this by adding a
+ second memory region to the PHB the ULI is on and read from it.
+
+ The second region is added to maintain compatiabilty with Linux's
+ view of the PCI memory map.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f75e89e9b5714db2b0e80074071dfbdd6f59488a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Thu Aug 30 01:58:48 2007 -0500
+
+ ft_board_setup update 85xx/86xx of pci/pcie bus-range property.
+
+ pcie is now differentiated from pci. Add 8641 bus-range updates.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 81b73dec16fd1227369a191e725e10044a9d56b8
+Author: Gary Jennejohn <garyj@denx.de>
+Date: Fri Aug 31 15:21:46 2007 +0200
+
+ ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
+
+ The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
+ set to non-zero, because it doesn't support MRM (memory-read-
+ multiple) correctly. We now added the possibility to configure
+ this register in the board config file, so that the default value
+ of 8 can be overridden.
+
+ Here the details of this patch:
+
+ o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
+ board-specific settings. As an example the sequoia board requires 0.
+ Idea from Stefan Roese <sr@denx.de>.
+ o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
+ PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
+ o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
+ CFG_PCI_CACHE_LINE_SIZE to 0.
+
+ Signed-off-by: Gary Jennejohn <garyj@denx.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 60174746c668b309378a91488dded898e9553eae
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Aug 31 10:01:51 2007 +0200
+
+ Fix TFTP OACK code for short packets.
+
+ The old code had a loop limit overflow bug which caused a semi-
+ infinite loop for small packets, because in "i<len-8", "i" was signed,
+ but "len" was unsigned, and "len-8" became a huge number for small
+ values of "len".
+
+ This is a workaround which replaces broken commit 8f1bc284.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit ff13ac8c7bbebb238e339592de765c546dba1073
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Aug 30 14:42:15 2007 +0200
+
+ Backout commit 8f1bc284 as it causes TFTP to fail.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1900fbf255acba8b94fb442a16408ea85a1d46a6
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Thu Aug 30 02:26:17 2007 -0500
+
+ Revert "Fix MPC8544DS PCIe3 scsi."
+
+ This reverts commit 9468e680.
+ Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 8f1bc28408ded213418d9bc0780c7d8fb8a03774
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Wed Aug 29 18:26:24 2007 -0600
+
+ tftp: don't implicity trust the format of recevied packets
+
+ The TFTP OACK code trusts that the incoming packet is formated as
+ ASCII text and can be processed by string functions. It also has a
+ loop limit overflow bug where if the packet length is less than 8, it
+ ends up looping over *all* of memory to find the 'blksize' string.
+
+ This patch solves the problem by forcing the packet to be null
+ terminated and using strstr() to search for the sub string.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 2602a5c40ae37ab965a4e240854fdaffb51328a4
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 29 09:06:05 2007 -0500
+
+ sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE
+
+ this had slipped through the cracks, since the sbc board was added
+ after I wrote the original patch to remove all these symbols, and
+ before it was merged.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c5bded3c88e48ae648a75d357dc81a8255fa81f1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Aug 29 14:05:30 2007 +0200
+
+ Add mii_init() prototype
+
+ to get rid of a *lot* of compiler warnings.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Aug 29 13:35:03 2007 +0200
+
+ Disable network support on cmi_mpc5xx board
+
+ ..because it caused compiler errors and there seems to be no
+ board maintainer to take care of this.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 9468e6804b7e25b0f6f52e53f47bce3175400a16
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Aug 20 09:44:00 2007 -0500
+
+ Fix MPC8544DS PCIe3 scsi.
+
+ <ed.swarthout@freescale.com>
+
+ The problem is pciauto_setup_device() getting called from fsl_pci_init.c
+ is allocating memory space it doesn't need.
+
+ Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 4bf4abb8a4e9955556b120a1aafa30c03e74032a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Tue Aug 21 09:38:59 2007 -0500
+
+ 8548cds fixes
+
+ Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the
+ correct consoledev needed for linux boot.
+ Standardize on fdt{file,addr} var to hold dtb file name.
+
+ Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Thu Aug 23 15:20:54 2007 -0400
+
+ Enable L2 cache for MPC8568MDS board
+
+ The L2 cache size is 512KB for 8568, print out the correct informaiton.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Wed Aug 22 17:54:49 2007 +0800
+
+ Remove the bios emulator binary files from MAI board
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 7608d75f9c87c9eb5b3a43219d0506d3e979a13f
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Tue Aug 21 17:00:17 2007 -0500
+
+ support board vendor-common makefiles
+
+ if a board/$(VENDOR)/common/Makefile exists, build it.
+
+ also add the first such case, board/freescale/common/Makefile, to
+ handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
+ dictated by board configuration.
+
+ thusly get rid of alternate build dir errors such as:
+
+ FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
+
+ by putting the common/ mkdir command in its proper place (the common
+ Makefile). Common bits from existing individual board Makefiles have
+ been removed.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd
+Author: stefano babic <sbabic@denx.de>
+Date: Tue Aug 21 15:52:33 2007 +0200
+
+ Fix: TFTP is not working on little endian systems
+
+ TFTP does not work anymore after multicast tftp
+ patch was applied on little endian systems.
+ This patch fix it.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 5f470948570526e9186f053a3003da7719604e90
+Author: stefano babic <sbabic@denx.de>
+Date: Tue Aug 21 15:50:33 2007 +0200
+
+ Fix MAC address setting in DM9000 driver.
+
+ The logic to check if there is a correct MAC address in the DM9000
+ EEPROM, added in the last patch, is wrong. Now the MAC address is
+ always taken from the environment, even if a suitable MAC is present
+ in the EEPROM.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 4a8527ef086ec7c89f40674ef024ae6f988a614a
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Tue Aug 21 12:40:34 2007 +0200
+
+ MPC5xxx: fix some compiler warnings in USB code
+
+ Fix the following warnings:
+ - usb.c:xx: warning: function declaration isn't a prototype
+ - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer
+ from pointer wihtout a cast
+
+ Signed-off-by: Martin Krause <martin.krase@tqs.de>
+
+commit 16e23c3f5dab6937f5109365416808c7f15c122b
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Mon Aug 20 23:55:33 2007 -0500
+
+ fsl_pci_init - Remove self PCSRBAR allocation
+
+ CPU physical address space was being wasted by allocating a
+ PCSRBAR PCI inbound region to it's memory space.
+
+ As a rule, PCSRBAR should be left alone since it does not affect
+ transactions from self and other masters may have changed it.
+
+ Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
+
+commit 0e700ce03a23bb1921149bc77008ace7103d5289
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Aug 20 13:56:47 2007 +0200
+
+ Fix compiler warning in include/s3c2410.h
+
+ This patch fixes the "type qualifiers ignored on fuction return tpye"
+ warning for include/s3c2410.h
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 9bb8b209ed2058a5756ecbeb544c067e44a42aea
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Mon Aug 20 07:09:05 2007 +0200
+
+ Fix compilation error for omap2420h4_config.
+
+ omap2420h4 switched to cfi, so remove old (already disabled) flash.c
+ and flash_probe() calls in env_flash.c.
+
+ Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+commit 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Fri Aug 10 14:34:14 2007 -0500
+
+ fdt: remove unused OF_FLAT_TREE_MAX_SIZE references
+
+ and make some minor corrections to the FDT part of the README.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Aug 29 01:32:05 2007 +0200
+
+ Minor coding style cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a861558c65f65f1cf1302f3a35e9db7686b9e1a3
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date: Tue Aug 28 17:40:33 2007 +0200
+
+ [UC101] Fix: if no CF in the board, U-Boot resets sometimes.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit f98984cb194bb34dbe1db9429d3b51133af30d07
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date: Tue Aug 28 17:39:14 2007 +0200
+
+ IDE: - make ide_inb () and ide_outb () "weak", so boards can
+ define there own I/O functions.
+ (Needed for the pcs440ep board).
+ - The default I/O Functions are again 8 Bit accesses.
+ - Added CONFIG_CMD_IDE for the pcs440ep Board.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9c02defc29b57945b600714cf61ddfd02b02fb14
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date: Sat Aug 25 05:07:16 2007 +0200
+
+ POST: limit memory test area to not touch global data anymore
+
+ As experienced on lwmon5, on some boards the POST memory test can
+ corrupt the global data buffer (bd). This patch fixes this issue
+ by checking and limiting this area.
+
+ Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 75e1a84d483e36be10e206e539b028c4889e1158
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Aug 24 15:41:42 2007 +0200
+
+ ppc4xx: Add RTC POST test to lwmon5 board configuration
+
+ Since this RTC POST test is taking quite a while to complete
+ it's only initiated upon special keypress same as the complete
+ memory POST.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d7bfa620037a6d2210159387571bdf93aa32c162
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Aug 24 15:19:10 2007 +0200
+
+ ppc4xx: Change GPIO signal for watchdog triggering on lwmon5
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c25dd8fc25e9ca3695db996a257d9ba4dab414db
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 23 11:02:37 2007 +0200
+
+ ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board
+
+ This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
+ board. Now the "eeprom" command can be used to read/write from/to this
+ device. Additionally a new command was added "eepromwp" to en-/disable
+ the write-protect of this 2nd EEPROM.
+
+ The 1st EEPROM is not affected by this write-protect command.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c64fb30e4c5976007d56fc1789c7a0666082b536
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Aug 22 08:56:09 2007 +0200
+
+ ppc4xx: Remove unused option CFG_INIT_RAM_OCM
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3ad63878737a5a2b1e60825bf0a7d601d7a695e7
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 21 16:27:57 2007 +0200
+
+ ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)
+
+ This patch adds support for the matrix keyboard on the lwmon5 board.
+ Since the implementation in the dsPCI is kind of compatible with the
+ "old" lwmon board, most of the code is copied from the lwmon
+ board directory.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3e66c078003607a7d1d214c15a5f262bc1b4032f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Aug 19 10:27:34 2007 +0200
+
+ Fix some build errors.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 05675735ef77dc23b5e0eb782bad1ff477b55e86
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Aug 18 22:00:38 2007 +0200
+
+ Update CHANGELOG.
+
+commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Thu Aug 16 22:52:39 2007 -0500
+
+ lib_ppc: make board_add_ram_info weak
+
+ platforms wishing to display RAM diagnostics in addition to size,
+ can do so, on one line, in their own board_add_ram_info()
+ implementation.
+
+ this consequently eliminates CONFIG_ADD_RAM_INFO.
+
+ Thanks to Stefan for the hint.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 815b5bd5b18569917c3e04b9757511e6ed23b9f6
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Fri Aug 17 12:43:44 2007 +0900
+
+ PCI_READ_VIA_DWORD_OP: Fix *val uninitialized bug
+
+ This patch has been sent on:
+ - 6 Jun 2007
+
+ Many users of PCI config read routines tend to ignore the function
+ ret value, and are only concerned about the contents of *val. Based
+ on this, pci_hose_read_config_{byte,word}_via_dword should initialize
+ the *val on dword read error.
+
+ Without this fix, for example, we'll go on scanning bus with vendor or
+ header_type uninitialized. This brings many unnecessary config trials.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 26667b7fa05a8bf2fc65fb9f3230b02b1a10c367
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Aug 18 14:37:52 2007 +0200
+
+ ColdFire: Fix some remaining problems with CFG_CMD_
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8280f6a1c43247616b68224675188e5ccd124650
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Aug 18 14:33:02 2007 +0200
+
+ Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4a442d3186b31893b4f77c6e82f63c4517a5224b
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Aug 16 19:23:50 2007 -0500
+
+ ColdFire: Add M5235EVB Platform for MCF523x
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 4cc1cd5941827a04cf5c51a07fcc42e8945894aa
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Fri Aug 17 09:30:00 2007 -0500
+
+ mpc83xx: fix typo in DDR2 programming
+
+ introduced in the implement board_add_ram_info patch as I was cleaning out the
+ magic numbers. sorry.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit e58fe95784d2514fc9c21028dc59f2b319a35d80
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Thu Aug 16 22:53:09 2007 -0500
+
+ mpc83xx: move freescale boards to boards/freescale
+
+ includes build fixes.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 5aa4ad8d8e7e9468219990c7875d5fdc9e962f47
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Thu Aug 16 22:52:59 2007 -0500
+
+ mpc83xx: suppress unused variable 'val8' warning
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit bbea46f76f767b919070b4829bf34c86bd223248
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Thu Aug 16 22:52:48 2007 -0500
+
+ mpc83xx: implement board_add_ram_info
+
+ add board_add_ram_info, to make memory diagnostic output more
+ consistent. u-boot banner output now looks like:
+
+ DRAM: 256 MB (DDR1, 64-bit, ECC on)
+
+ and for boards with SDRAM on the local bus, a line such as this is
+ added:
+
+ SDRAM: 64 MB (local bus)
+
+ also replaced some magic numbers with their equivalent define names.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 14778585d1389d86d5846efec29e5fce892680ce
+Author: Tony Li <tony.li@freescale.com>
+Date: Fri Aug 17 10:35:59 2007 +0800
+
+ mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support
+
+ The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
+ And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.
+
+ Signed-off-by Tony Li <tony.li@freescale.com>
+
+commit 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Aug 16 15:05:11 2007 -0500
+
+ ColdFire: Add M54455EVB for MCF5445x
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit a1436a842654a8d3927d082a8ae9ee0a10da62d7
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Aug 16 13:20:50 2007 -0500
+
+ ColdFire: Add M5253EVBE platform for MCF52x2
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit a605aacd8324094199402816cc6d9124aba57b8d
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Aug 16 05:04:31 2007 -0500
+
+ ColdFire: Add M5249EVB platform for MCF52x2
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit f28e1bd9daa6de5eb33ae4822bda6b008ccb4e9e
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 20:32:06 2007 -0500
+
+ ColdFire: Update Freescale MCF52x2 platforms
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 870470dbf6f4bb9864e0d97aeedbc17c167c6d1c
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:55:10 2007 -0500
+
+ ColdFire: Update EB+MCF-EV123 platform
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit aa93d859d9b1fcd8eea52d51b06e86c38f72111b
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:46:38 2007 -0500
+
+ ColdFire: update TASREG platform for MCF52x2
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit a9505510bf56a9b5558248dd8b73ec9d9a1556a2
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:45:51 2007 -0500
+
+ ColdFire: update r5200 platform for MCF52x2
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 6cfd3c7bc813fb317ab7c0781f0d1874b1c0877c
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:43:20 2007 -0500
+
+ ColdFire: idmr platform MCF52x2 update
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 6706424d0bb851fb52af00cd1c3301e91ee7f2b0
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:41:06 2007 -0500
+
+ ColdFire: cobra5272 platform for MCF52x2 update
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 56115665b4a64c10c01440c57749b265e0908fa4
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:38:15 2007 -0500
+
+ ColdFire: MCF52x2 Header files update
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 83ec20bc4380eebddfde45da6e3a69a92d4db21d
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 19:21:21 2007 -0500
+
+ ColdFire: MCF52x2 update
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit f52e78304dcc0ac459c0ea1fa5be275c7d1642cf
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 18:46:11 2007 -0500
+
+ ColdFire: MCF5329 update cache
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 7171977fb8fd77cfb6676953fa9a05789c450513
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 15:40:20 2007 -0500
+
+ ColdFire: MCF5329 header file clean up
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit ab77bc547ba561c25ea34457ed17aa0b2f7c2723
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Aug 15 15:39:17 2007 -0500
+
+ ColdFire: MCF5329 Update and cleanup
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 10327dc5541f947c0cf7e31fef86c4706169607a
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Aug 16 16:35:02 2007 -0500
+
+ Add CONFIG_HAS_ETH0 to all boards with TSEC
+
+ The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether
+ to update TSEC1's device-tree node, so we need to add it
+ to all the boards with TSECs. Do this for 83xx and 86xx, too,
+ since they will eventually do something similar.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit d64ee908a1b525e5bb2b4cbeb5c449ad6a469666
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Aug 16 15:05:04 2007 -0500
+
+ Update MPC8544 DS PCI memory map
+
+ The PCIe bus that the ULI M1575 is connected to has no possible way of
+ needing more than the fixed amount of IO & Memory space needed by the ULI.
+
+ So make it use far less IO & memory space and have it use the shared LAW. This
+ free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed
+ by each bus.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ea5877e31ed63ade948fd1293895ec23fe01472e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Aug 16 11:01:21 2007 -0500
+
+ Fix up some fdt issues on 8544DS
+
+ It looks like we had a merge issue that duplicated a bit of code
+ in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get
+ the MAC address properly set in the device tree on boot for TSEC1
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 07bc20560cb9d3d186cca268c05c82762e8c55ad
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date: Thu Aug 16 15:16:03 2007 +0200
+
+ PPC4xx:HCU4/5 cleanup
+
+ Minor cleanups to confirm to the u-boot coding style.
+ Some german expressions -> english.
+ HCU5 enforces a unique IP adress for a given slot in the rack.
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 1e6b07c64967c1eb2cd84faa4c32bf2a769bc8eb
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date: Thu Aug 16 15:16:02 2007 +0200
+
+ PPC4xx:HCU4/5 cleanup ecc/sdram init
+
+ Make ecc initialisation robust, as DDR2-ECC errors may be generated
+ while zeroing the RAM.
+
+ Return 16 bytes (a cacheline) less than the available memory, as the
+ board and/or PPC440EPx might have problems accessing the last bytes.
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit d35b508a55508535b6e8445b718585d27df733d3
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:29:56 2007 -0500
+
+ fdt: suppress unused variable 'bd' warning
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 82bd9ee77490588d4da785d75829ca63d0176baf
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Aug 15 20:06:50 2007 -0500
+
+ Fix warnings from of_data copy fix
+
+ Forgot to cast of_flat_tree to ulong.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 7613afda77d5eec0f47d303025b0c661b70e4c73
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Aug 15 20:03:44 2007 -0500
+
+ Don't wait for disconnected TSECs
+
+ The TSEC driver's PHY code waits a long time for autonegotiation to
+ complete, even if the link is down. The PHY knows the link is
+ down or up before autonegotiation completes, so we can short-circuit
+ the process if the link is down.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit b96c83d4ae475a70ef2635cd0e748174c44c8601
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Aug 15 20:03:34 2007 -0500
+
+ Fix numerous bugs in the 8568 UEC support
+
+ Actually, fixed a large bug in the UEC for *all* platforms.
+ How did this ever work?
+
+ uec_init() did not follow the spec for eth_init(), and returned
+ 0 on success. Switch it to return the link like tsec_init()
+ (and 0 on error)
+
+ The immap for the 8568 was defined based on MPC8568, rather than
+ CONFIG_MPC8568
+
+ CONFIG_QE was off
+
+ CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0"
+
+ Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
+ enabled
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 3a79013e2adda53332dfd0b511066a805e929a9d
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Aug 15 20:03:25 2007 -0500
+
+ Define tsec flag values in config files
+
+ The tsec_info structure and array has a "flags" field for each
+ ethernet controller. This field is the only reason there are
+ settings. Switch to defining TSECn_FLAGS for each controller
+ in the config header, and we can greatly simplify the array, and
+ also simplify the addition of future boards.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit ec7238229507e7f47533a611ea8c53319d234cf3
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Aug 15 20:03:13 2007 -0500
+
+ Add support for building all boards with a TSEC
+
+ Changes to the TSEC driver affect almost all 83xx, 85xx, and 86xx boards.
+ Now we can do a MAKEALL test on all of them!
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 10aaf716cb0dc6614df54ef78bed5144afd23ef8
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Aug 15 17:30:56 2007 -0500
+
+ Fix of_data copying for CONFIG_OF_FLAT_TREE-using boards
+
+ The fix, "Fix where the #ifdef CFG_BOOTMAPSZ is placed"
+ neglected to *also* put the code inside the similar #ifdef
+ for CONFIG_OF_FLAT_TREE.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 78f9fef7f406078c8bf7191e665a73f795157746
+Author: Scott Wood <scottwood@freescale.com>
+Date: Wed Aug 15 15:46:46 2007 -0500
+
+ mpc885ads: Don't define CONFIG_BZIP2.
+
+ bzip2 requires a significant chunk of malloc space, and there isn't
+ enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area
+ and a downloaded image at 0x400000.
+
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 002275a3ed8b114885f6702d6d544d0780dfe689
+Author: Michal Simek <Monstr@seznam.cz>
+Date: Thu Aug 16 08:54:10 2007 +0200
+
+ Bios emulator - fix microblaze toolchain problem
+
+ microblaze CPU have problem with bios_emulator code.
+ Microblaze toolchain doesn't support PRAGMA PACK.
+
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit a5a38f4fd7e5366d706ff6a985f9b6715ddbc98b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Aug 16 11:51:04 2007 +0200
+
+ Minor Coding Style fix; Update CHANGELOG file.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8fb6e80c06849e3013ac5c9350d8ed9e52967991
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 16 11:21:49 2007 +0200
+
+ ppc4xx: Remove #warning in esd auto_update.c
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2d78074d2e806edc380c1464eb9e5df335ece65e
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Jun 22 17:32:28 2007 +0200
+
+ ppc7xx: Update CPCI750 board
+
+ This small CPCI750 update extends the board specific command
+ "show_config" to display the Marvell strapping registers and
+ extends the PCI IDE controller.
+
+ Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9de469bd960cc1870bb40d6672ed42726b8b50d7
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 16 10:18:33 2007 +0200
+
+ ppc4xx: Only enable POST FPU test on Sequoia and not Rainier
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6da0c5bd4a53e40eb4f7eb72a4c051ecabad783c
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 16 09:54:51 2007 +0200
+
+ Add missing rainier (PPC440GRx) target to MAKEALL and MAINTAINERs files
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 02ba7022f62bb75908296c58c63866e1d294b69a
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 16 09:52:29 2007 +0200
+
+ ppc4xx: Update Sequoia/Rainier bootstrap command
+
+ As suggested by David Mitchell, here an update for the Sequoia/Rainier
+ bootstrap command.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 35cc4e4823668e8745854899cfaedd4489beb0ef
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:30:39 2007 -0500
+
+ mpc83xx: enable libfdt by default on freescale boards
+
+ this enables libfdt code by default for the
+ freescale mpc8313erdb, mpc832xemds, mpc8349emds,
+ mpc8349itx and gp boards.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 3fde9e8b22cfbd7af489214758f9839a206576cb
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:30:33 2007 -0500
+
+ mpc83xx: migrate remaining freescale boards to libfdt
+
+ this adds libfdt support code for the freescale
+ mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx,
+ and gp boards.
+
+ Boards remain compatible with OF_FLAT_TREE.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 6a16e0dfcc4119b46adb1dce2d6c8fb3c5d108e1
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:30:26 2007 -0500
+
+ mpc83xx: move common /memory node update mechanism to cpu.c
+
+ also adds common prototypes to include/common.h.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 8f9e0e9f339aee4ce31a338d5f27356eb5457f85
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:30:19 2007 -0500
+
+ mpc83xx: remaining 8360 libfdt fixes
+
+ PCI clocks and QE frequencies weren't being updated, and the core clock
+ was being updated incorrectly. This patch also adds a /memory node if
+ it doesn't already exist prior to update.
+
+ plus some cosmetic trimming to single line comments.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit f4b2ac5ed9aaff9920d487bff8a59696c083a524
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:30:12 2007 -0500
+
+ mpc83xx: fix UEC2->1 typo in libfdt setup code
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 19fa1c35368484d4ed10ddce8a7793c21862e3a3
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Aug 15 22:30:05 2007 -0500
+
+ mpc83xx: add MAINTAINER and MAKEALL entries for the mpc8323erdb
+
+ and reorder the existing 83xx maintainers alpha.
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 15 11:55:35 2007 -0500
+
+ 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h
+
+ Remove a leftover in net/tftp.c while we're at it.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 4ce917742b1e48faa9bf9a9757545e56fb4cfe44
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 15 12:20:40 2007 -0500
+
+ Move the MPC8641HPCN board under board/freescale.
+
+ Minor path corrections needed to ensure buildability.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 8662577fe36fdb6a44b55b998d9daac6392a736a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 15 11:46:22 2007 -0500
+
+ 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h
+
+ Remove a leftover in net/tftp.c while we're at it.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 210f463c71917b7a4495c2103c228b9c179ae64d
+Author: Jerry Van Baren <gvb.uboot@gmail.com>
+Date: Wed Aug 15 11:13:15 2007 -0400
+
+ Fix where the #ifdef CFG_BOOTMAPSZ is placed.
+
+ Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb
+ interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT)
+ when it should have gone inside of the conditional. As a result, it
+ broke non-LIBFDT board builds.
+
+ Also added a missing "not." to the comment.
+
+ Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 0e19209767194a97cec6d93dba9e64d1da8d548e
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date: Wed Aug 15 12:14:23 2007 +0200
+
+ PPC4xx:HCU4/5-Board fix compile warning
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Tue Aug 14 14:06:45 2007 -0500
+
+ Fix malloc size error in ahci_init_one.
+
+ Typically this causes scsi init to corrupt the
+ devlist and break the coninfo command.
+ Fix a compiler size warning.
+
+ Signed-off-by: Jason Jin <jason.jin@freescale.com>
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit b361acd64fd2525c081b9b288b0804efe209c0e9
+Author: ksi@koi8.net <ksi@koi8.net>
+Date: Tue Aug 14 10:02:16 2007 -0700
+
+ TI DaVinci - fix unsupported %hhx format
+
+ Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
+
+commit f01dbb5424a81453c81190dd30e945891466f621
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Aug 14 18:42:36 2007 +0200
+
+ Coding style cleanup. Update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924
+Author: Andy Fleming <afleming@freescale.com>
+Date: Tue Aug 14 10:32:59 2007 -0500
+
+ Fix initrd/dtb interaction
+
+ The original code would wrongly relocate the blob to be right before
+ the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ,
+ if it is defined. So we make two changes:
+
+ 1) flag the blob for relocation whenever its address is above BOOTMAPSZ
+
+ 2) If the blob is being relocated, relocate it before kbd, not initrd
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit e54b970173769307a116bd34028b6d0c2eea2a4e
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Aug 14 15:40:00 2007 +0100
+
+ Supply spi interface in at45.c
+
+commit 4ce846ec59f36b85d6644a769690ad3feb667575
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 14 15:12:01 2007 +0200
+
+ POST: Fix merge problem
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 429d9571f60631ae8a2fe12b11be4c75b0c2b37c
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 14 15:03:17 2007 +0200
+
+ Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 779e975117a75e91fcebe226a63104dbfb924ab1
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 14 14:44:41 2007 +0200
+
+ ppc4xx: Add initial Zeus (PPC405EP) board support
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c5a172a5fd636c12467429e3f7910e53773979c6
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 14 14:41:55 2007 +0200
+
+ POST: Add option for external ethernet loopback test
+
+ When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
+ is not done using an internal loopback connection, but by assuming
+ that an external loopback connector is plugged into the board.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit eb2b4010ae426245172988804ee8d9193fb41038
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Aug 14 14:39:44 2007 +0200
+
+ POST: Add ppc405 support to cache and UART POST
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Aug 14 10:46:32 2007 +0100
+
+ Replace lost end of at45.c.
+
+commit 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Aug 14 10:30:06 2007 +0100
+
+ Update Makefiles for merged and split at45.c.
+
+commit 3454cece2db57cb9eb7087995f7e73066a163f71
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Aug 14 10:21:06 2007 +0100
+
+ Delete the merged files.
+
+commit dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Aug 14 10:14:05 2007 +0100
+
+ Add the files.
+
+commit d4fc6012fd0a5c211b825691f44b06f8032c0551
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Aug 14 10:10:52 2007 +0100
+
+ Add MACH_TYPE records for several AT91 boards.
+ Merge to two at45.c files into a common file, split to at45.c and spi.c
+ Fix spelling error in DM9161 PHY Support.
+ Initialize at91rm9200 board (and set LED).
+ Add PIO control for at91rm9200dk LEDs and Mux.
+ Change dataflash partition boundaries to be compatible with Linux 2.6.
+
+ Signed-off-by: Peter Pearse <peter.pearse@arm.com>
+ Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
+
+commit 4ef35e53c693556c54b0c22d6f873de87bade253
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Aug 14 09:54:46 2007 +0200
+
+ Coding style cleanup, update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Aug 14 09:47:27 2007 +0200
+
+ Coding style cleanup; rebuild CHANGELOG
+
+commit 7f3f2bd2dc08e0b05e185662ca2e2d283757104a
+Author: Randy Vinson <rvinson@linuxbox.(none)>
+Date: Tue Feb 27 19:42:22 2007 -0700
+
+ 85xxCDS: Add make targets for legacy systems.
+
+ The PCI ID select values on the Arcadia main board differ depending
+ on the version of the hardware. The standard configuration supports
+ Rev 3.1. The legacy target supports Rev 2.x.
+
+ Signed-off-by Randy Vinson <rvinson@mvista.com>
+
+commit e41094c7e38177c755fbd9b182018069614f080d
+Author: Andy Fleming <afleming@freescale.com>
+Date: Tue Aug 14 01:50:09 2007 -0500
+
+ 85xxCDS: Enable the VIA PCI-to-ISA bridge.
+
+ Author: Randy Vinson <rvinson@linuxbox.(none)>
+
+ Enable the PCI-to-ISA bridge in the VIA Southbridge located on the
+ Arcadia main board.
+
+ Signed-off-by: Randy Vinson <rvinson@mvista.com>
+ Signed-off-by: York Sun <yorksun@freescale.com>
+
+commit da9d4610d76e52c4d20a8f3d8433439a7fcf5b71
+Author: Andy Fleming <afleming@freescale.com>
+Date: Tue Aug 14 00:14:25 2007 -0500
+
+ Add support for UEC to 8568
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit c59e4091ffe0148398b9e9ff14a019ea038b7432
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue Jun 19 14:18:34 2007 -0400
+
+ Add PCI support for MPC8568MDS board
+
+ This patch is against u-boot-mpc85xx.git of www.denx.com
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
+
+commit d111d6382c99fdea08c2312eeeae8786945e189a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue Jun 19 14:18:32 2007 -0400
+
+ Empirically set cpo and clk_adjust for mpc85xx DDR2 support
+
+ This patch is against u-boot-mpc85xx.git of www.denx.com
+
+ Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
+ both MPC8548CDS board and MPC8568MDS board, especially for supporting
+ 533MHz DDR2.
+
+ Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
+ DDR2 on all current board versions especially ver 1.92 or later to bring
+ up.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 3db0bef59eab1155801618cef5c481e97553b597
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Aug 7 18:07:27 2007 -0500
+
+ Use an absolute address when jumping out of 4k boot page
+
+ On e500 when we leave the 4k boot page we should use an absolute address since
+ we don't know where the board code may want us to be really running at.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a
+Author: Andy Fleming <afleming@freescale.com>
+Date: Mon Aug 13 14:49:59 2007 -0500
+
+ MPC85xx BA bits not set for 3-bit bank address DIMM
+
+ The current implementation does not set the number of bank address bits
+ (BA) in the processor. The default assumes 2 logical bank bits. This
+ works fine for a DIMM that uses devices with 4 internal banks (SPD
+ byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
+ devices with 8 internal banks (SPD byte17 = 0x8).
+
+ Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
+
+commit 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1
+Author: Andy Fleming <afleming@freescale.com>
+Date: Mon Aug 13 14:38:06 2007 -0500
+
+ Fix minor 85xx warnings
+
+ Some patches had inserted warnings into the build:
+ * mpc8560ads declared data without using it
+ * cpu_init declared ecm and immap without using it in all CONFIGs
+ * MPC8548CDS.h had its default filenames changed so that they contained
+ "\m" in the paths. Made the defaults not Windows-specific (or
+ anything-specific)
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit f2cff6b104f82b993bef6086ce0c97159bbe1add
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:52 2007 -0500
+
+ 8548cds PCIE support.
+
+ Make the early L1 cache stack region guarded to prevent speculative
+ fetches outside the locked range.
+
+ Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions.
+ init.S whitespace cleanup.
+
+ Allow TEXT_BASE value to be specified on command line. This allows it
+ to be set to 0xfffc0000 which cuts the uboot binary in half.
+
+ Clear and enable lbc and ecm errors.
+
+ Update last_busno in device-tree for pci and pcie.
+
+ Remove load of obsolete cpu/mpc85xx/pci.0
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:51 2007 -0500
+
+ 8544ds PCIE support
+
+ PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
+
+ Enable LBC and ECM errors and clear error registers.
+
+ Add tftpflash env var to get uboot from tftp server and flash it.
+
+ Add pci/pcie convenience env vars to display register space:
+ "run pcie3regs" to see all pcie3 ccsr registers
+ "run pcie3cfg" to see all cfg registers
+ Whitespace cleanup and MPC8544DS.h
+
+ Enable CONFIG_INTERRUPTS.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 61a21e980a7b9188424d04f1c265fdc5c21c7e85
+Author: Andy Fleming <afleming@freescale.com>
+Date: Tue Aug 14 01:34:21 2007 -0500
+
+ 85xx start.S cleanup and exception support
+
+ From: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+ Support external interrupts from platform to eliminate system hangs.
+ Define CONFIG_INTERRUPTS board configure option to enable.
+ Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.
+
+ Remove extra cpu initialization redundant with hardware initialization.
+ Whitespace cleanup.
+
+ Define and use _START_OFFSET consistent with other processors using
+ ppc_asm.tmpl
+
+ Move additional code from .text to boot page to make room for
+ exception vectors at start of image.
+
+ Handle Machine Check, External and Critical exceptions.
+
+ Fix e500 machine check error determination in traps.c
+
+ TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 7bd30fc4a6475b41d6679ae3aafc9fa505260c47
+Author: Andy Fleming <afleming@freescale.com>
+Date: Tue Aug 14 01:33:18 2007 -0500
+
+ Add MPC8544DS README
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 40c7f9b0de4e300370adfc704128fa0f79a143b6
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:48 2007 -0500
+
+ 85xx allow debugger to configure ddr.
+
+ Only check for mpc8548 rev 1 when compiled for 8548.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 29372ff38c5baab7d0e3a8c14fe11fa194a38704
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:47 2007 -0500
+
+ mpc85xx L2 cache reporting and SRAM relocation option.
+
+ Allow debugger to override flash cs0/cs1 settings to enable alternate
+ boot regions
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 41f0f8fb1ab92f0cba7d329de90070f822f8299f
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:46 2007 -0500
+
+ e500 needs ppc_asm.tmp MCK_EXCEPTION
+
+ Always define MCK_EXCEPTION macro - so e500 can use it too.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 53a5c424bf8655b7b4e2c305a441963259a26a81
+Author: David Updegraff <dave@cray.com>
+Date: Mon Jun 11 10:41:07 2007 -0500
+
+ multicast tftp: RFC2090
+
+ Implemented IETF RFC2090, Multicast TFTP. Initial implementation
+ on Realtek RTL8139 and Freescale TSEC.
+
+ Signed-off-by: David Updegraff <dave@cray.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit 5d110f0aa69f065ee386ec1840dfee1e8cc46bc1
+Author: Wilson Callan <wcallan@savantav.com>
+Date: Sat Jul 28 10:56:13 2007 -0400
+
+ New CONFIG_BOOTP_SERVERIP option
+
+ Added CONFIG_BOOTP_SERVERIP to allow the tftp server to be different
+ from the bootp server
+
+ Signed-off-by: Wilson Callan <wcallan@savantav.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit 50cca8b976ec74069860208c36e64ce8f4d5e4c1
+Author: Mike Rapoport <mike@compulab.co.il>
+Date: Sun Aug 12 08:48:27 2007 +0300
+
+ Add ability to take MAC address from the environment to DM9000 driver
+
+ Signed-off-by: Mike Rapoport <mike@compulab.co.il>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit be5d72d10d47609326226225181e301fb9a33b58
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Aug 13 21:57:53 2007 +0200
+
+ Minor coding style cleanup. Update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cca34967cbd13ff6bd352be29e3f1cc88ab24c05
+Author: Joe Hamman <joe.hamman@embeddedspecialties.com>
+Date: Sat Aug 11 06:54:58 2007 -0500
+
+ Modify SBC8641D to use new Freescale PCI routines
+
+ PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT
+ adapter.
+
+ Signed-off-by: Joe Hamman <joe.hamman@embeddedspecialties.com>
+ Signde-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit a08458303e7f9db67f296980036d3292c35cb45c
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Jun 29 18:38:51 2007 +0200
+
+ atmel_mci: Fix data timeout value
+
+ Calculate the data timeout based on values from the CSD instead of
+ just using a hardcoded DTOR value. This is a backport of a similar fix
+ in BSP 2.0, with one additional fix: the DTOCYC value is rounded up
+ instead of down.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 0ba8eed28b575626b17e0a7882f923b83e0d7584
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Aug 13 17:22:31 2007 +0200
+
+ AVR32: Include <div64.h> instead of <asm/div64.h>
+
+ include/asm-avr32/div64.h was recently moved to include/div64.h, but
+ cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of
+ the patch was merged perhaps?)
+
+ This patch updates cpu/at32ap/interrupts.c so that the avr32 port
+ compiles again.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit f0d1246ed7cb5a88522244c596d7ae7e6f161283
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed Jun 27 13:34:26 2007 +0200
+
+ atmel_mci: Use 512 byte blocksize if possible
+
+ Instead of always using the largest blocksize the card supports, check
+ if it can support smaller block sizes and use 512 bytes if possible.
+ Most cards do support this, and other parts of u-boot seem to have
+ trouble with block sizes different from 512 bytes.
+
+ Also enable underrun/overrun protection.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+ Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+
+commit 273db7e1bdd1937e32f1d4507321bb721ebd3118
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Aug 13 09:05:33 2007 +0200
+
+ ppc4xx: Fix problem in PLL clock calculation
+
+ This patch was originall provided by David Mitchell <dmitchell@amcc.com>
+ and fixes a bug in the PLL clock calculation.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Aug 12 21:34:50 2007 +0200
+
+ Update CHANGELOG
+
commit 77d19a8bf3b0b1e401cb9f23c81e2ef419705c1a
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Aug 12 21:34:34 2007 +0200
Signed-off-by: Dave Liu <daveliu@freescale.com>
+commit c646bba6465a45c60746d4cc1602cd06c1960f2d
+Author: Joe Hamman <joe.hamman@embeddedspecialties.com>
+Date: Thu Aug 9 15:11:03 2007 -0500
+
+ Add support for SBC8641D. Config files.
+
+ Add support for Wind River's SBC8641D reference board.
+
+ Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
+ Acked-by: Wolfgang Denk <wd@denx.de>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 8ac273271d57321f90505c7a51cdb1ef2113b628
+Author: Joe Hamman <joe.hamman@embeddedspecialties.com>
+Date: Thu Aug 9 15:10:53 2007 -0500
+
+ Add support for SBC8641D. Board files.
+
+ Add support for Wind River's SBC8641D reference board.
+
+ Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
+ Acked-by: Wolfgang Denk <wd@denx.de>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
commit c2c0ab4aff86622b837a48a0e560351f9afafb95
Author: Stefan Roese <sr@denx.de>
Date: Fri Aug 10 20:34:58 2007 +0200
Acked-by: Zach Sadecki <Zach.Sadecki@ripcode.com>
Acked-by: Stefan Roese <sr@denx.de>
+commit 2e4d94f1e3c2961428967a33b6ff2520568391b3
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:45 2007 -0500
+
+ fsl_pci_init cleanup.
+
+ Do not enable normal errors created during probe (master abort, perr,
+ and pcie Invalid Configuration access).
+
+ Add CONFIG_PCI_NOSCAN board option to prevent bus scan.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 936b3e69b667c3eb9a61ece4e78647d3fce9fc2a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Jul 27 01:50:44 2007 -0500
+
+ pciauto_setup_device bars_num fix
+
+ Passing bars_num=0 to pciauto_setup_device should assign no bars.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+ Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit cf0b185e58ca0aec8ae2b2a8804ec0ef58ee21d4
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon Aug 6 17:39:44 2007 -0500
+
+ 8641hpcn: Do correct sized pointer math.
+
+ When I rebased Ed's patch and cleaned up a few compilation
+ problems, I apparently rebased my brain on crack first.
+ Fix that by doing (char *) sized pointer math as needed.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit cfc7a7f5bb3273c9951173c788001d45118f141f
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Aug 2 14:42:20 2007 -0500
+
+ cpu/86xx fixes.
+
+ Remove rev 1 fixes.
+ Always set PICGCR_MODE.
+ Enable machine check and provide board config option
+ to set and handle SoC error interrupts.
+
+ Include MSSSR0 in error message.
+
+ Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 35d22f957a85a22bb3cd1ad084fa5404620d1c42
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Aug 10 10:42:25 2007 +0200
+
+ Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f
Author: Dirk Behme <dirk.behme@googlemail.com>
Date: Thu Aug 2 17:42:08 2007 +0200
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+commit 157cda4d0c3d592ccbb19bbfc07d9251894f0894
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:31:22 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: HCU5 files
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 6e5de26c6e7580faf16e87745cd488b92b492d0c
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:30:33 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: HCU4 files
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit e8397fc78c9394d71de233a4d810fbc9047e4c76
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:38:26 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: common files
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit ac982ea5a4f2f993efcf52dca122f5a59df047d8
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:28:44 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: make related
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 137fdd9f474ecb853efdace5200576308c67f18d
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:28:03 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: HCU5 config
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 714bc55b35b6f6a65cc8740a3842a543e88cdef2
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:27:15 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: HCU4 config
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:25:31 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: READMEs
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 641cca9569ce351ddb287fd3343d8b1dcb591db4
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date: Fri Jul 27 11:37:40 2007 +0200
+
+ Add PPC4xx-HCU4 and HCU5 boards: Infrastructure
+
+ This series of patches adds support for 2 boards from Netstal Maschinen.
+
+ The HCU4 has a PPC405Gpr and
+ the HCU5 has a PPC440EPX.
+
+ The HCU4 has a somehow complicated flash setup, as the booteprom is
+ only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more
+ elegant solution.
+
+ The HCU5 has only a booteprom as the whole code will be downloaded from a
+ different board which has HD, CD-ROM, etc and where all code is stored.
+
+ This is my third try. I incorporated all suggestions made by Wolfgang and Stefan.
+ Thanks them a lot.
+
+ Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 3e4c90c6233618fc1806e63fde68df5f3d6a0171
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Aug 10 08:42:55 2007 +0200
+
+ ppc4xx: Update lwmon5 POST configuration
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date: Fri Aug 10 08:25:22 2007 +0200
+
+ POST: Add ppc4xx UART POST support without external uart clock (lwmon5)
+
+ The patch adds support for UART POST on ppc44x-based boards with no
+ external serial clocks installed.
+
+ Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+ Acked-by: Stefan Roese <sr@denx.de>
+
commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Mon Aug 6 18:18:34 2007 -0500
Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
+commit 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Aug 8 09:54:26 2007 +0200
+
+ Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a41de1f0d373e09c782dea558385a06247111ba5
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 05:15:18 2007 -0500
+
+ Port enabled for I2C signals and chipselects port configuration.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 1a33ce65a4c51a69190dd8c408f9e1c62a66e94f
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 04:31:18 2007 -0500
+
+ Added NAND support
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit eaf9e447beb3e498818ef8ad0b8c1597cd506149
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 04:11:20 2007 -0500
+
+ Added I2C support
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 99c03c175d2689093176facf17c58ce2cb320001
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 03:58:52 2007 -0500
+
+ Changed CFG_CLK to gd->bus_clk for CFG_TIMER_PRESCALER. Added DECLARE_GLOBAL_DATA_PTR for time.c
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 8d1d66af54d305de29d0bbf4aa8c9e6375f7f731
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 03:55:21 2007 -0500
+
+ Added uart_gpio_conf() in serial_init(), seperated uart port configuration from cpu_init() to uart_gpio_conf()
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 6fde84a44b7e575ea80fe0e2d5be3b6f73d1e630
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 03:43:30 2007 -0500
+
+ Moved sync() from board file to include/asm-m68k/io.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 9e737d8476e7d6a596d16caaf6a3853a9a1190a2
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 03:30:44 2007 -0500
+
+ Declared attributes of void __mii_init(void) as an alias for int mii_init(void)
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 9998bd37ead85e93953559720710d3b0685c81e6
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Sun Aug 5 03:19:10 2007 -0500
+
+ Renamed CONFIG_MCFSERIAL to CONFIG_MCFUART
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
commit 7c4c3722a38d40b0cf537ddae72b04f4088b190c
Author: Jason Jin <Jason.jin@freescale.com>
Date: Tue Aug 7 16:17:06 2007 +0800
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit 537223afa61f64480df31ce440a9cb386df4a814
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Aug 6 21:10:17 2007 +0200
+
+ ppc4xx: Update AMCC Bamboo README doc/README.bamboo
+
+ As suggested by Eugene O'Brien <Eugene.O'Brien@advantechamt.com>,
+ here an updated Bamboo README.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 9c7e4b06214db61bb21f1bcbe57c97519669baae
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Aug 6 02:17:36 2007 +0200
Minor cleanup of <board>_nand build rules.
-commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197
-Author: Wolfgang Denk <wd@denx.de>
-Date: Thu Aug 2 00:48:45 2007 +0200
+commit 9ca8d79de096c65b9b9c867259b3ff4685f775ef
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Aug 2 08:33:56 2007 +0200
+
+ ppc4xx: Code cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c92409812206ac67a7fa7aae298539a9c3804a46
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Jul 31 18:51:48 2007 +0200
+
+ [ppc440SPe] Graceful recovery from machine check during PCIe configuration
+
+ During config transactions on the PCIe bus an attempt to scan for a
+ non-existent device can lead to a machine check exception with certain
+ peripheral devices. In order to avoid crashing in such scenarios the
+ instrumented versions of the config cycle read routines are introduced, so
+ the exceptions fixups framework can gracefully recover.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+ Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit dec99558b9ea75a37940d07f41a3565a50b54ad1
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Tue Jul 31 18:19:54 2007 +0200
+
+ [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A
+
+ This brings back separate settings for PCIe bus numbers depending on chip
+ revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa
+ commit. 440SPe rev. A does NOT work properly with the same settings as for
+ the rev. B (no devices are seen on the bus during enumeration).
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Aug 2 00:48:45 2007 +0200
+
+ Fix build errors and warnings / code cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d2f68006627eda6cb6c7f364bddf621dbfd2fc68
+Author: Eugene OBrien <eugene.obrien@advantechamt.com>
+Date: Tue Jul 31 10:24:56 2007 +0200
+
+ ppc4xx: Update AMCC Bamboo 440EP support
+
+ Changed storage type of cfg_simulate_spd_eeprom to const
+ Changed storage type of gpio_tab to stack storage
+ (Cannot access global data declarations in .bss until afer code relocation)
+
+ Improved SDRAM tests to catch problems where data is not uniquely addressable
+ (e.g. incorrectly programmed SDRAM row or columns)
+
+ Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
+ Fixed AM29LV320DT (OpCode Flash) sector map
+
+ Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ea9f6bce383cc9fbcdee28b5836109b1a6dba574
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 31 08:37:01 2007 +0200
+
+ ppc4xx: Update 440EPx lwmon5 board support
+
+ - Clear ECC status regs after ECC POST test
+ - Set dcbz for ECC generation with caches enabled as default
+ - Code cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 30 11:04:57 2007 +0200
+
+ ppc4xx: Only print ECC related info when the error bis are set
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e36220a4baf1f188ba60f17e9d0f043069b1362a
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Fri Jul 27 16:44:31 2007 +0200
+
+ new FPGA image for PLU405 board
- Fix build errors and warnings / code cleanup.
+ new FPGA image for PLU405 board with improved CompactFlash timing
- Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
Author: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+commit d4024bb72dd81695ec099b2199eda0d27c623e62
+Author: John Otken <john@softadvances.com>
+Date: Thu Jul 26 17:49:11 2007 +0200
+
+ ppc4xx: Add support for AMCC 405EP Taihu board
+
+ Signed-off-by: John Otken <john@softadvances.com>
+
+commit b66091de6c7390620312c2501db23d8391e7cabb
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Thu Jul 26 15:08:01 2007 +0200
+
+ ppc4xx: lwmon5: Update Lime initialization
+
+ Change Lime SDRAM initialization to now support 100MHz and
+ 133MHz (if enabled). Also the framebuffer is initialized to
+ display a blue rectangle with a white border.
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9f24a808f17fc0f37b7fb4805f734741335caecc
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 24 09:52:52 2007 +0200
+
+ ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added
+
+ The used Intel NOR FLASH chips have internally two dies, and are now
+ treated as two seperate chips.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit aedf5bde179ecfbd0a96130d18996a96518b785f
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Jul 24 07:20:09 2007 +0200
+
+ ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...)
+
+ As suggested by Hakan Eryigit, here an updated setup for the lwmon5
+ interrupt controller.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a71d96eac8130b53a91f93cd10c70fca0db18d52
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Jul 20 15:03:44 2007 +0200
+
+ ppc4xx: Fix bug with default GPIO output value
+
+ As spotted by Matthias Fuchs, the default output values for all GPIO1
+ outputs were not setup correctly. This patch fixes this issue.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 531e3e8b831f357056448fa573137d5fb37000fd
+Author: Pavel Kolesnikov <concord@emcraft.com>
+Date: Fri Jul 20 15:03:03 2007 +0200
+
+ POST: Add ECC POST for the lwmon5 board
+
+ This patch adds ECC Post test for the Lwmon5 board based
+ on PPC440EPx to U-Boot.
+
+ Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
+ Acked-by: Yuri Tikhonov <yur@emcraft.com>
+ Acked-by: Stefan Roese <sr@denx.de>
+
commit cc3023b9f95d7ac959a764471a65001062aecf41
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Thu Jul 19 17:12:28 2007 +0200
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+commit c883f6ea32dce91f07670b3aafecf6c99b1e5341
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 16 13:11:12 2007 +0200
+
+ Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 16 10:02:12 2007 +0200
+
+ ppc4xx: Code cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2a49fc17d09020e7ebd9536694d99d20e419fcb8
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 16 10:01:38 2007 +0200
+
+ ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 16 10:00:43 2007 +0200
+
+ ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c
+
+ The new boardspecific DDR2 controller configuration is used for the Yucca
+ board. Now the Yucca board with 440SPe Rev. A chips is also supported.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 16 09:57:00 2007 +0200
+
+ ppc4xx: Add new weak functions to support boardspecific DDR2 configuration
+
+ The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better
+ support non default, boardspecific DDR(2) controller configuration.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5743a9207a370b90f09b20ebd61167c806b937f3
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 16 08:53:51 2007 +0200
+
+ ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup
+
+ The new function remove_tlb() can be used to remove the TLB's used to
+ map a specific memory region. This is especially useful for the DDR(2)
+ setup routines which configure the SDRAM area temporarily as a cached
+ area (for speedup on auto-calibration and ECC generation) and later
+ need this area uncached for normal usage.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 3a6cab844cf74f76639d795e0be8717e02c86af7
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Jul 14 22:51:02 2007 +0200
Signed-off-by: Heiko Schocher <hs@denx.de>
+commit a2e1c7098cf9574386b0c96841dfc8ea5cc93578
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jul 12 16:32:08 2007 +0200
+
+ ppc4xx: Change receive buffer handling in the 4xx emac driver
+
+ This change fixes a bug in the receive buffer handling, that
+ could lead to problems upon high network traffic (broadcasts...).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360
Author: Wolfgang Denk <wd@denx.de>
Date: Thu Jul 12 01:45:34 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 0dca874db62718e41253659e60f3a1de7eb418ce
+Author: TsiChung <tcliew@Goku.(none)>
+Date: Tue Jul 10 15:45:43 2007 -0500
+
+ Cache update and added CFG_UNIFY_CACHE
+
+ Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only.
+
+ Signed-off-by: TsiChung <tcliew@Goku.(none)>
+
+commit 52b017604a8f4d4a795880ef6e7861d7f2f1b005
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:36:16 2007 -0500
+
+ Update header file. Include dtimer_intr_setup(). Changed timer divider to global define.
+
+ Include immap.h and timer.h. Moved dtimer interrupt setup to dtimer_intr_setup() from cpu/mcf532x/interrupts.c. Changed (CFG_CLK /1000000) -1 << 8 to CFG_TIMER_PRESCALER
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 5cdc07c7ef8f08ea55d3c47ed9221d91aa6d5fac
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:31:25 2007 -0500
+
+ Update header files
+
+ Include immap.h and renamed mcfrtc.h to rtc.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2870e98ac8e5553e9187b12a47e5f46babb53990
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:29:21 2007 -0500
+
+ Add mcffec_initialize()
+
+ Added mcffec_initialize() in eth_initialize()
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 45a25bfd0c52f8a3fa137216bc94d32f90bedc5d
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:27:40 2007 -0500
+
+ Update header file and clean up
+
+ Include immap.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 0cee9c66318602c856a899ae5fa7579ccba6443a
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:23:15 2007 -0500
+
+ New uart structure and defines
+
+ Seperated from mcfuart.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit a90e79de8d99e9c9d69d60bfff9f24c337165900
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:22:31 2007 -0500
+
+ New timer structure and defines
+
+ Seperated from mcftimer.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit e04acb2eba4782489417240eff76e20e176aec10
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:21:09 2007 -0500
+
+ Rename mcfrtc to rtc
+
+ Since it is already in m68k folder, un-necessary to pad mcf. Replaced immap_5329.h and m5329.h to immap.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2bd806fe4fc23958b8f78778199e7a6e3f8f6ad5
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:17:36 2007 -0500
+
+ Rename mcfserial.c. Update include header
+
+ Renamed mcfserial.c to mcfuart.c. Modified Makefile for mcfuart.o from mcfserial.o. Replace immap_5329.h and m5329.h to immap.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit f2208fbc2eb9de3f4285bfaa021c6ebae16c9b0e
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:13:58 2007 -0500
+
+ Header file update, clean up and cache handling
+
+ Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2e3f25ae9082daa9f5d181db45dfbc2e52ce0f97
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:10:40 2007 -0500
+
+ Create interrupts.c and modify Makefile
+
+ interrupt_init() and dtimer_intr_setup() are placed in interrupts.c. Added interrupts.o to Makefile
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit ddd104f1ed655eda50c06ba636237a83ed943f34
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:06:55 2007 -0500
+
+ Enable Icache
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit b9bf3de377b2bae70c983c9b97feae914999e735
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:05:31 2007 -0500
+
+ Update header file and some clean up
+
+ Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 84a015b52ec820a5ae173717d78516de731c89c2
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:03:28 2007 -0500
+
+ Update header file and enable icache
+
+ Replaced immap_5329.h and m5329.h with immap.h. Enabled icache_enable() in cpu_init_r().
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 7a17e759c7a8b58e910daf54df611e94fc8ca074
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 23:01:22 2007 -0500
+
+ Update header file and removed interrupt_init()
+
+ Replace immap_5329.h and m5329.h with immap.h. Removed interrupt_init() and placed it in interrupts.c
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 3b635492c95bd0d6e08f93f699821cba1f602a64
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:57:46 2007 -0500
+
+ Update for flash.o and mii.o
+
+ Removed flash.o and added mii.o
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit c5ded275d839e4ff79f41718d50a835d989f57bc
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:56:19 2007 -0500
+
+ MII functions calls.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 427c814104560e29bda14955c67703245aaaa5b4
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:54:42 2007 -0500
+
+ Removed MII functions and replaced immap_5329.h and m5329.h with immap.h.
+
+ The removed MII routines will be placed in mii.c.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 01a793fda09c63df5a496f09dc1c7cb26e6751a2
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:51:05 2007 -0500
+
+ Duplicate code
+
+ There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2744354a8437b8f78db178e30660215688bff570
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:46:38 2007 -0500
+
+ Seperate old structure defines and new structure defines
+
+ Removed new uart structure and defines to uart.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2bd58608dbcff8890ca9a0c59e861ac24f8bb230
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:45:01 2007 -0500
+
+ Seperate old structure defines and new structure defines
+
+ New timer structure and defines will move to new timer.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 8cd5cd6de4ff92e03978338ed7aeb3ce7b7b9784
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:42:23 2007 -0500
+
+ Clean up
+
+ Removed whitespace
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 514871f565dd8bd1121e4a3ac1665a790e20b8f2
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:41:24 2007 -0500
+
+ Clean up
+
+ Replaced whitespace with tabs
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 48dbfeabc7afffe30609a4489f10c22cb67ef7dd
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:39:07 2007 -0500
+
+ Create new header file and move peripherals base address from configs file to new header file.
+
+ Create new header file to include immap_5xxx.h and m5xxx.h and to share among drivers without update in driver file each processor is added. Moved peripherals base address and defines from configs file to immap.h.
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit be296e31c4411f96d9cb3d2afc8fcb006867abfa
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Jul 5 22:24:58 2007 -0500
+
+ Revert file mode
+
+ Changed MAKEALL file mode to executable, removed executable file mode from Makefile
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582
Author: Jon Loeliger <jdl@freescale.com>
Date: Tue Jul 10 11:19:50 2007 -0500
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit c8603cfbd4573379a6076c9c208545ba2bbf019a
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jul 9 11:00:24 2007 +0200
+
+ Small coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Mon Jul 9 10:10:08 2007 +0200
+
+ Migrate esd 405EP boards to new NAND subsystem
+
+ Remove unused CFG_NAND_LEGACY define
+
+ These boards to not have NAND.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Mon Jul 9 10:10:06 2007 +0200
+
+ Migrate esd 405EP boards to new NAND subsystem
+
+ Migrate esd 405EP boards to new NAND subsystem
+
+ -cleanup
+ -use correct io accessors (in/out_be32())
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit e09f7ab5749c345f924da272bea0521a73af5b11
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Mon Jul 9 10:10:04 2007 +0200
+
+ Migrate esd 405EP boards to new NAND subsystem
+
+ This patch prepares the migration from the legacy NAND driver
+ to U-Boot's new NAND subsystem for esd boards.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
commit c3517f919d0f61650cf3027fd4faf0f631142f6c
Author: Jon Loeliger <jdl@freescale.com>
Date: Sun Jul 8 18:10:08 2007 -0500
Signed-off-by: Jon Loeliger <jdl@freescale.com>
+commit 10e038932f22ee80ebd53de312531e70e6590a2f
+Author: Thomas Knobloch <knobloch@siemens.com>
+Date: Fri Jul 6 14:58:39 2007 +0200
+
+ [NAND] Bad block skipping for command nboot
+
+ The old implementation of command nboot does not support reading the image from
+ NAND flash with skipping of bad blocks. The patch implements a new version of
+ the nboot command: by calling nboot.jffs2 from the u-boot command line the
+ command will load the image from NAND flash with respect to bad blocks (by using
+ nand_read_opts()). This is similar to e.g. the NAND read command: "nand
+ read.jffs2 ...".
+
+ Signed-off-by: Thomas Knobloch <knobloch@siemens.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 334043f601a90ac53e5ecc846fbb73a1ef38cb1f
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Jul 6 12:26:51 2007 +0200
+
+ ppc4xx: Update lwmon5 default environment
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5d187430a055d62f17ca84d75e7245439d1f7e75
+Author: Stefan Roese <sr@denx.de>
+Date: Fri Jul 6 11:48:24 2007 +0200
+
+ ppc4xx: Update lwmon5 board
+
+ Add unlock=yes environment variable to default variables to unlock
+ the CFI flash by default.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e
Author: Stefan Roese <sr@denx.de>
Date: Fri Jul 6 09:45:47 2007 +0200
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
+commit d677b32855f577ae2690dcd64a172cdd706e0ffc
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Jun 22 10:34:12 2007 +0200
+
+ [patch] add nand_init() prototype to nand.h
+
+ since nand_init() is expected to be called by other parts of u-boot, there
+ should be a prototype for it in nand.h
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jun 20 18:14:24 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 8e585f02f82c17cc66cd229dbf0fd3066bbbf658
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date: Mon Jun 18 13:50:13 2007 -0500
+
+ Added M5329AFEE and M5329BFEE Platforms
+
+ Added board/freescale/m5329evb, cpu/mcf532x, drivers/net,
+ drivers/serial, immap_5329.h, m5329.h, mcfrtc.h,
+ include/configs/M5329EVB.h, lib_m68k/interrupts.c, and
+ rtc/mcfrtc.c
+
+ Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c,
+ common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h,
+ include/asm-m68k/io.h, include/asm-m68k/mcftimer.h,
+ include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h,
+ include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c,
+ lib_m68k/time.c, net/eth.c and rtc/Makefile
+
+ Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 15 11:33:41 2007 +0200
Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
+commit f539edc076cfe52bff919dd512ba8d7af0e22092
+Author: Vadim Bendebury <vbendeb@google.com>
+Date: Thu May 24 15:52:25 2007 -0700
+
+ cosmetic changes to bcm570x driver
+
+ This is a cosmetic only changes submission.
+ It affects files relevant to bcm570x driver.
+ the commands used to generate this change was
+
+ cd drivers
+ Lindent -pcs -l80 bcm570x.c bcm570x_lm.h bcm570x_mm.h tigon3.c tigon3.h
+
+ The BMW target (the only one using this chip so far) builds cleanly, the
+ `before and after' generated object files for drivers/bcm570x.c and
+ drivers/tigon3.o are identical as reported by objdump -d
+
+ Signed-off-by: Vadim Bendebury <vbendeb@google.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jun 6 16:26:56 2007 +0200
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
+commit 7ebb4479b07ff294eb4d76e420753a0349f7c93b
+Author: Ulf Samuelsson <ulf@atmel.com>
+Date: Thu May 24 12:12:47 2007 +0200
+
+ [PATCH][NAND] Define the Vendor Id for Micron NAND Flash
+
+ Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit d756894722c888d09a9fa1df8323753772d3dcce
Author: Stefan Roese <sr@denx.de>
Date: Thu May 24 09:49:00 2007 +0200
Signed-off-by Dan Malek, <dan@embeddedalley.com>
+commit f2134f8e9eb006bdcd729e89f309c07b2fa45180
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed May 2 13:31:53 2007 +0200
+
+ macb: Don't restart autonegotiation if we already have link
+
+ Rework macb_phy_init so that it doesn't attempt to re-negotiate if the
+ link is already up.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 04fcb5d38bc90779cd9a710d60702075986f0e29
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed May 2 13:22:38 2007 +0200
+
+ macb: Introduce a few barriers when dealing with DMA descriptors
+
+ There were a few theoretical possibilities that the compiler might
+ optimize away DMA descriptor reads and/or writes and thus cause
+ synchronization problems with the hardware. Insert barriers where
+ we depend on reads/writes actually hitting memory.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
commit ffa621a0d12a1ccd81c936c567f8917a213787a8
Author: Andy Fleming <afleming@freescale.com>
Date: Sat Feb 24 01:08:13 2007 -0600
E: daniel@omicron.se
D: x86 port, Support for sc520_cdp board
+N: Hayden Fraser
+E: Hayden.Fraser@freescale.com
+D: Support for ColdFire MCF5253
+W: www.freescale.com
+
N: Dr. Wolfgang Grandegger
E: wg@denx.de
D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
E: ThomasF@hyperion-entertainment.com
D: Support for AmigaOne
+N: Niklaus Giger
+E: niklaus.giger@netstal.com
+D: Support for HCU(x) boards
+W: www.netstal.com
+
N: Paul Gortmaker
E: paul.gortmaker@windriver.com
D: Support for WRS SBC8347/8349 boards
D: Support for LEOX boards, DS164x RTC
W: http://www.leox.org
+N: TsiChung Liew
+E: Tsi-Chung.Liew@freescale.com
+D: Support for ColdFire MCF523x, MCF532x, MCF5445x
+W: www.freescale.com
+
N: Leif Lindholm
E: leif.lindholm@i3micro.com
D: Support for AMD dbau1550 board.
E: lo@routefree.com
D: Support for DOS partitions
+N: James MacAulay
+E: james.macaulay@amirix.com
+D: Suppport for Amirix AP1000
+W: www.amirix.com
+
N: Dan Malek
E: dan@embeddedalley.com
D: FADSROM, the grandfather of all of this
W: http://www.windriver.com
N: Stefan Roese
-E: stefan.roese@esd-electronics.com
-D: AMCC PPC401/403/405GP Support; Windows environment support
+E: sr@denx.de
+D: AMCC PPC4xx Support
+W: http://www.denx.de
N: Erwin Rol
E: erwin@muffin.org
E: art@videon-central.com
D: Support for NetSilicon NS7520
+N: Michal Simek
+E: monstr@monstr.eu
+D: Support for Microblaze, ML401, XUPV2P board
+W: www.monstr.eu
+
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
D: Port to B2 board
W: www.dave-tech.it
+N: Timur Tabi
+E: timur@freescale.com
+D: Support for MPC8349E-mITX
+W: www.freescale.com
+
N: Rob Taylor
E: robt@flyingpig.com
D: Port to MBX860T and Sandpoint8240
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
-
-N: James MacAulay
-E: james.macaulay@amirix.com
-D: Suppport for Amirix AP1000
-W: www.amirix.com
-
-N: Timur Tabi
-E: timur@freescale.com
-D: Support for MPC8349E-mITX
-W: www.freescale.com
-
-N: Michal Simek
-E: monstr@monstr.eu
-D: Support for Microblaze, ML401, XUPV2P board
-W: www.monstr.eu
Rattler MPC8248
ZPC1900 MPC8265
+Michael Barkowski <michael.barkowski@freescale.com>
+
+ MPC8323ERDB MPC8323
+
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
sacsng MPC8260
VOH405 PPC405EP
VOM405 PPC405EP
WUH405 PPC405EP
- CMS700 PPC405EP
+ CMS700 PPC405EP
+
+Niklaus Giger <niklaus.giger@netstal.com>
+
+ HCU4 PPC405GPr
+ HCU5 PPC440EPx
Frank Gottschling <fgottschling@eltec.de>
MVS1 MPC823
+Joe Hamman <joe.hamman@embeddedspecialties.com>
+
+ sbc8641d MPC8641D
+
Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
ELPT860 MPC860T
+Dave Liu <daveliu@freescale.com>
+
+ MPC8360EMDS MPC8360
+
Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
John Otken <jotken@softadvances.com>
luan PPC440SP
+ taihu PPC405EP
Keith Outwater <Keith_Outwater@mvis.com>
MIP405 PPC4xx
PIP405 PPC4xx
+Kim Phillips <kim.phillips@freescale.com>
+
+ MPC8349EMDS MPC8349
+
Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
ocotea PPC440GX
p3p440 PPC440GP
pcs440ep PPC440EP
+ rainier PPC440GRx
sequoia PPC440EPx
sycamore PPC405GPr
taishan PPC440GX
walnut PPC405GP
yellowstone PPC440GR
yosemite PPC440EP
+ zeus PPC405EP
P3M750 PPC750FX/GX/GL
ML2 PPC4xx
+Timur Tabi <timur@freescale.com>
+
+ MPC8349E-mITX MPC8349
+ MPC8349E-mITX-GP MPC8349
+
Erik Theisen <etheisen@mindspring.com>
W7OLMC PPC4xx
svm_sc8xx MPC8xx
-Timur Tabi <timur@freescale.com>
-
- MPC8349E-mITX MPC8349
- MPC8349E-mITX-GP MPC8349
-
-Kim Phillips <kim.phillips@freescale.com>
-
- MPC8349EMDS MPC8349
-
-Dave Liu <daveliu@freescale.com>
-
- MPC8360EMDS MPC8360
-
-------------------------------------------------------------------------
Unknown / orphaned boards:
r5200 mcf52x2
+TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+ M5235EVB mcf52x2
+ M5329EVB mcf532x
+ M54455EVB mcf5445x
+
+Hayden Fraser <Hayden.Fraser@freescale.com>
+
+ M5253EVBE mcf52x2
+
#########################################################################
# AVR32 Systems: #
# #
ERIC \
EXBITGEN \
G2000 \
+ hcu4 \
+ hcu5 \
HH405 \
HUB405 \
JSE \
PLU405 \
PMC405 \
PPChameleonEVB \
+ rainier \
sbc405 \
sc3 \
sequoia \
sequoia_nand \
+ taihu \
taishan \
VOH405 \
VOM405 \
yellowstone \
yosemite \
yucca \
+ zeus \
"
#########################################################################
LIST_83xx=" \
MPC8313ERDB_33 \
MPC8313ERDB_66 \
+ MPC8323ERDB \
MPC832XEMDS \
MPC8349EMDS \
MPC8349ITX \
LIST_86xx=" \
MPC8641HPCN \
+ sbc8641d \
"
#########################################################################
ZUMA \
"
+LIST_TSEC=" \
+ ${LIST_85xx} \
+ ${LIST_86xx} \
+ ${LIST_83xx} \
+"
+
LIST_7xx=" \
BAB7xx \
CPCI750 \
EB+MCF-EV123 \
EB+MCF-EV123_internal \
idmr \
+ M5235EVB \
+ M5249EVB \
+ M5253EVB \
M5271EVB \
M5272C3 \
M5282EVB \
- TASREG \
+ M5329EVB \
+ M54455EVB \
r5200 \
+ TASREG \
"
#########################################################################
mips|mips_el| \
nios|nios2| \
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
- x86|I486)
+ x86|I486|TSEC)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
#
VERSION = 1
-PATCHLEVEL = 2
+PATCHLEVEL = 3
SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc2
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
OBJS := $(addprefix $(obj),$(OBJS))
LIBS = lib_generic/libgeneric.a
+LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
+ "board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
LIBS += board/$(BOARDDIR)/lib$(BOARD).a
LIBS += cpu/$(CPU)/lib$(CPU).a
ifdef SOC
LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/net/libnet.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
endif
+ifeq ($(CPU),mpc85xx)
+LIBS += drivers/qe/qe.a
+endif
+LIBS += drivers/serial/libserial.a
LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/drivers/libpostdrivers.a
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
env:
$(MAKE) -C tools/env all || exit 1
-depend dep:
+depend dep: version
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
tags ctags:
G2000_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
+hcu4_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
+
+hcu5_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
+
HH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
sc3_config:unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
+taihu_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
+
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
yucca_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
+zeus_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
+
#########################################################################
## MPC8220 Systems
#########################################################################
## Coldfire
#########################################################################
+M5235EVB_config \
+M5235EVB_Flash16_config \
+M5235EVB_Flash32_config: unconfig
+ @case "$@" in \
+ M5235EVB_config) FLASH=16;; \
+ M5235EVB_Flash16_config) FLASH=16;; \
+ M5235EVB_Flash32_config) FLASH=32;; \
+ esac; \
+ >include/config.h ; \
+ if [ "$${FLASH}" != "16" ] ; then \
+ echo "#define NORFLASH_PS32BIT 1" >> include/config.h ; \
+ echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
+ cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \
+ else \
+ echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
+ cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \
+ fi
+ @$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale
+
+M5249EVB_config : unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
+
+M5253EVBE_config : unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
+
cobra5272_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
r5200_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
+M5329AFEE_config \
+M5329BFEE_config : unconfig
+ @case "$@" in \
+ M5329AFEE_config) NAND=0;; \
+ M5329BFEE_config) NAND=16;; \
+ esac; \
+ >include/config.h ; \
+ if [ "$${NAND}" != "0" ] ; then \
+ echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
+
+M54455EVB_config \
+M54455EVB_atmel_config \
+M54455EVB_intel_config \
+M54455EVB_a33_config \
+M54455EVB_a66_config \
+M54455EVB_i33_config \
+M54455EVB_i66_config : unconfig
+ @case "$@" in \
+ M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \
+ M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \
+ M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \
+ M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \
+ M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \
+ M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
+ M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
+ esac; \
+ >include/config.h ; \
+ if [ "$${FLASH}" == "INTEL" ] ; then \
+ echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+ echo "... with INTEL boot..." ; \
+ else \
+ echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+ echo "... with ATMEL boot..." ; \
+ fi; \
+ echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
+ echo "... with $${FREQ}Hz input clock"
+ @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
+
#########################################################################
## MPC83xx Systems
#########################################################################
echo -n "...66M..." ; \
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
+ @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
MPC8323ERDB_config: unconfig
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
+ @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
MPC8349EMDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale
MPC8349ITX_config \
MPC8349ITX_LOWBOOT_config \
MPC8349ITXGP_config: unconfig
@mkdir -p $(obj)include
- @mkdir -p $(obj)board/mpc8349itx
+ @mkdir -p $(obj)board/freescale/mpc8349itx
@echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
@if [ "$(findstring GP,$@)" ] ; then \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+ echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
@if [ "$(findstring LOWBOOT,$@)" ] ; then \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+ echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
- @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx
+ @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
+ @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
MPC8560ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
+MPC8541CDS_legacy_config \
MPC8541CDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
+ if [ "$(findstring _legacy_,$@)" ] ; then \
+ echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+ echo "... legacy" ; \
+ fi
+ @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
MPC8544DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
+MPC8548CDS_legacy_config \
MPC8548CDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
+ if [ "$(findstring _legacy_,$@)" ] ; then \
+ echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+ echo "... legacy" ; \
+ fi
+ @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
+MPC8555CDS_legacy_config \
MPC8555CDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
+ if [ "$(findstring _legacy_,$@)" ] ; then \
+ echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+ echo "... legacy" ; \
+ fi
+ @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
- echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h
+ echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
#########################################################################
#########################################################################
MPC8641HPCN_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn
+ @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+sbc8641d_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
#########################################################################
## 74xx/7xx Systems
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
+trizepsiv_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
+
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
+ - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
+ - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- mips Files specific to MIPS CPUs
- mpc5xx Files specific to Freescale MPC5xx CPUs
- mpc5xxx Files specific to Freescale MPC5xxx CPUs
CONFIG_OF_LIBFDT
* New libfdt-based support
* Adds the "fdt" command
- * The bootm command does _not_ modify the fdt
+ * The bootm command automatically updates the fdt
CONFIG_OF_FLAT_TREE
* Deprecated, see CONFIG_OF_LIBFDT
* The environment variable "disable_of", when set,
disables this functionality.
- CONFIG_OF_FLAT_TREE_MAX_SIZE
-
- The maximum size of the constructed OF tree.
-
OF_CPU - The proper name of the cpus node.
OF_SOC - The proper name of the soc node.
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
+ boards with QUICC Engines require OF_QE to set UCC mac addresses
+
CONFIG_OF_HAS_BD_T
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
CONFIG_OF_HAS_UBOOT_ENV
- * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
+ * CONFIG_OF_LIBFDT - enables the "fdt env" command
* CONFIG_OF_FLAT_TREE - The resulting flat device tree
will have a copy of u-boot's environment variables
Defines a default value for theIP address of a TFTP
server to contact when using the "tftboot" command.
+- Multicast TFTP Mode:
+ CONFIG_MCAST_TFTP
+
+ Defines whether you want to support multicast TFTP as per
+ rfc-2090; for example to work with atftp. Lets lots of targets
+ tftp down the same boot image concurrently. Note: the ethernet
+ driver in use must provide a function: mcast() to join/leave a
+ multicast group.
+
+ CONFIG_BOOTP_RANDOM_DELAY
- BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY
CONFIG_BOOTP_TIMEOFFSET
CONFIG_BOOTP_VENDOREX
+ CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
+ environment variable, not the BOOTP server.
+
CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
serverip from a DHCP server, it is possible that more
than one DNS serverip is offered to the client.
CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
to do a dynamic update of a DNS server. To do this, they
need the hostname of the DHCP requester.
- If CONFIG_BOOP_SEND_HOSTNAME is defined, the content
+ If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
of the "hostname" environment variable is passed as
option 12 to the DHCP server.
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
+COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ MCFGPIO_PASPAR |= 0x0F00;
+ MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+ } else {
+ MCFGPIO_PASPAR &= 0xF0FF;
+ MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
+ }
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_AMD79C874VC "AMD79C874VC"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ strcpy(info->phy_name,
+ STR_ID_AMD79C874VC);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ printf(STR_ID_AMD79C874VC);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+int mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
{
cpu/mpc512x/start.o (.text)
*(.text)
- *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
-unsigned char cfg_simulate_spd_eeprom[128];
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+/*************************************************************************
+ *
+ * Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ * 13 row add bits, 10 column add bits (but 12 row used only).
+ * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ * 12 row add bits, 10 column add bits.
+ * Prepare a subset (only the used ones) of SPD data
+ *
+ * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ * the corresponding bank is divided by 2 due to number of Row addresses
+ * 12 in the ECC module
+ *
+ * Assumes: 64 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+const unsigned char cfg_simulate_spd_eeprom[128] = {
+ 0x80, /* number of SPD bytes used: 128 */
+ 0x08, /* total number bytes in SPD device = 256 */
+ 0x07, /* DDR ram */
+#ifdef CONFIG_DDR_ECC
+ 0x0C, /* num Row Addr: 12 */
+#else
+ 0x0D, /* num Row Addr: 13 */
+#endif
+ 0x09, /* numColAddr: 9 */
+ 0x01, /* numBanks: 1 */
+ 0x20, /* Module data width: 32 bits */
+ 0x00, /* Module data width continued: +0 */
+ 0x04, /* 2.5 Volt */
+ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+#ifdef CONFIG_DDR_ECC
+ 0x02, /* ECC ON : 02 OFF : 00 */
+#else
+ 0x00, /* ECC ON : 02 OFF : 00 */
+#endif
+ 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */
+ 0,
+ 0,
+ 0,
+ 0x01, /* wcsbc = 1 */
+ 0,
+ 0,
+ 0x0C, /* casBit (2,2.5) */
+ 0,
+ 0,
+ 0x00, /* not registered: 0 registered : 0x02*/
+ 0,
+ 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+ 0,
+ 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+ 0,
+ 0x50, /* tRpNs = 20 ns */
+ 0,
+ 0x50, /* tRcdNs = 20 ns */
+ 45, /* tRasNs */
+#ifdef CONFIG_DDR_ECC
+ 0x08, /* bankSizeID: 32MB */
+#else
+ 0x10, /* bankSizeID: 64MB */
+#endif
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+#endif
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
{
return (0);
}
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
-/*************************************************************************
- *
- * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- * 13 row add bits, 10 column add bits (but 12 row used only).
- * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- * 12 row add bits, 10 column add bits.
- * Prepare a subset (only the used ones) of SPD data
- *
- * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- * the corresponding bank is divided by 2 due to number of Row addresses
- * 12 in the ECC module
- *
- * Assumes: 64 MB, ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-static void init_spd_array(void)
-{
- cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
- cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
-
-#ifdef CONFIG_DDR_ECC
- cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
- cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
- cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
-#else
- cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
- cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
- cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
-#endif
-
- cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
- cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
- cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
- cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
- cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
- cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
- cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
- cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
- cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
- cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
-
- cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
-
- cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
-
- cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
- cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
- cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
- cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
-}
-#endif
long int initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
- /*
- * First write simulated values in eeprom array for onboard bank 0
- */
- init_spd_array();
-
dram_size = spd_sdram();
return dram_size;
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
- unsigned long k, n;
+ unsigned long k, n, *p32, ctr;
+ const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
mtmsr(0);
- for (k = 0; k < CFG_KBYTES_SDRAM;
+ for (k = 0; k < CFG_MBYTES_SDRAM*1024;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
}
}
+
+ /*
+ * Perform a sequence test to ensure that all
+ * memory locations are uniquely addressable
+ */
+ ctr = 0;
+ p32 = 0;
+ while ((unsigned long)p32 != bend) {
+ if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+ printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
+ *p32++ = ctr++;
+ }
+
+ ctr = 0;
+ p32 = 0;
+ while ((unsigned long)p32 != bend) {
+ if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+ printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
+
+ if (*p32 != ctr) {
+ printf("SDRAM test fails at: %08x\n", p32);
+ return 1;
+ }
+
+ ctr++;
+ p32++;
+ }
+
printf("SDRAM test passes\n");
return 0;
}
/*----------------------------------------------------------------------------+
| init_default_gpio
+----------------------------------------------------------------------------*/
-void init_default_gpio(void)
+void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
int i;
|
+----------------------------------------------------------------------------*/
-void update_uart_ios(uart_config_nb_t uart_config)
+void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
{
switch (uart_config)
{
/*----------------------------------------------------------------------------+
| update_ndfc_ios(void).
+----------------------------------------------------------------------------*/
-void update_ndfc_ios(void)
+void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
/* Update GPIO Configuration Table */
gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
/*----------------------------------------------------------------------------+
| update_zii_ios(void).
+----------------------------------------------------------------------------*/
-void update_zii_ios(void)
+void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
/* Update GPIO Configuration Table */
gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
/*----------------------------------------------------------------------------+
| update_uic_0_3_irq_ios().
+----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(void)
+void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
/*----------------------------------------------------------------------------+
| update_uic_4_9_irq_ios().
+----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(void)
+void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
/*----------------------------------------------------------------------------+
| update_dma_a_b_ios().
+----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(void)
+void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
/*----------------------------------------------------------------------------+
| update_dma_c_d_ios().
+----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(void)
+void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
/*----------------------------------------------------------------------------+
| update_ebc_master_ios().
+----------------------------------------------------------------------------*/
-void update_ebc_master_ios(void)
+void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
/*----------------------------------------------------------------------------+
| update_usb2_device_ios().
+----------------------------------------------------------------------------*/
-void update_usb2_device_ios(void)
+void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
/*----------------------------------------------------------------------------+
| update_pci_patch_ios().
+----------------------------------------------------------------------------*/
-void update_pci_patch_ios(void)
+void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
}
/*----------------------------------------------------------------------------+
- | set_chip_gpio_configuration(unsigned char gpio_core)
+ | set_chip_gpio_configuration(unsigned char gpio_core,
+ | gpio_param_s (*gpio_tab)[GPIO_MAX])
| Put the core impacted by clock modification and sharing in reset.
| Config the select registers to resolve the sharing depending of the config.
| Configure the GPIO registers.
|
+----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core)
+void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
{
unsigned char i=0, j=0, reg_offset = 0;
unsigned long gpio_reg, gpio_core_add;
CORE_NOT_SELECTED /* PCI_PATCH */
};
+ gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
/* Table Default Initialisation + FPGA Access */
- init_default_gpio();
- set_chip_gpio_configuration(GPIO0);
- set_chip_gpio_configuration(GPIO1);
+ init_default_gpio(gpio_tab);
+ set_chip_gpio_configuration(GPIO0, gpio_tab);
+ set_chip_gpio_configuration(GPIO1, gpio_tab);
/* Update Table */
force_bup_core_selection(ppc440ep_core_selection, &config_val);
/* UIC 0:3 Selection */
if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
{
- update_uic_0_3_irq_ios();
+ update_uic_0_3_irq_ios(gpio_tab);
dma_a_b_unselect_in_fpga();
}
if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
- update_uic_4_9_irq_ios();
+ update_uic_4_9_irq_ios(gpio_tab);
}
/* DMA AB Selection */
if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
- update_dma_a_b_ios();
+ update_dma_a_b_ios(gpio_tab);
dma_a_b_selection_in_fpga();
}
/* DMA CD Selection */
if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
{
- update_dma_c_d_ios();
+ update_dma_c_d_ios(gpio_tab);
dma_c_d_selection_in_fpga();
}
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_ebc_master_ios();
+ update_ebc_master_ios(gpio_tab);
}
/* PCI Patch Enable */
if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_pci_patch_ios();
+ update_pci_patch_ios(gpio_tab);
}
/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
/* USB2.0 Device Selection */
if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
{
- update_usb2_device_ios();
+ update_usb2_device_ios(gpio_tab);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
/* NAND Flash Selection */
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
- update_ndfc_ios();
+ update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
/* MII Selection */
if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
{
- update_zii_ios();
+ update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
mtsdr(sdr_mfr, sdr0_mfr);
/* RMII Selection */
if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
{
- update_zii_ios();
+ update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
mtsdr(sdr_mfr, sdr0_mfr);
/* SMII Selection */
if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
{
- update_zii_ios();
+ update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
mtsdr(sdr_mfr, sdr0_mfr);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
break;
}
- update_uart_ios(uart_configuration);
+ update_uart_ios(uart_configuration, gpio_tab);
/* UART Selection in all cases */
uart_selection_in_fpga(uart_configuration);
/* Perform effective access to hardware */
mtsdr(sdr_pfc1, sdr0_pfc1);
- set_chip_gpio_configuration(GPIO0);
- set_chip_gpio_configuration(GPIO1);
+ set_chip_gpio_configuration(GPIO0, gpio_tab);
+ set_chip_gpio_configuration(GPIO1, gpio_tab);
/* USB2.0 Device Reset must be done after GPIO setting */
if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#else
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-
/* PCI base & peripherals */
tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
*(COMMON)
}
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
_end = . ;
PROVIDE (end = .);
}
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-long int spd_sdram(void);
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
+
+long int spd_sdram(void);
int board_early_init_f(void)
{
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter if selected
+ */
+ if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
+ mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+ else
+ mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
+
return 0;
}
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
+ info->start[1] = base + 0x00002000;
+ info->start[2] = base + 0x00004000;
+ info->start[3] = base + 0x00006000;
+ info->start[4] = base + 0x00008000;
+ info->start[5] = base + 0x0000a000;
+ info->start[6] = base + 0x0000c000;
+ info->start[7] = base + 0x0000e000;
+ for (i = 8; i < info->sector_count; i++) {
info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
+ base + ((i-7) * 0x00010000);
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
#undef PCIE_ENDPOINT
/* #define PCIE_ENDPOINT 1 */
+DECLARE_GLOBAL_DATA_PTR;
+
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
+ char *env;
+ unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
- bus = 1;
+ bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for katmai card presence */
if (!katmai_pcie_card_present(i))
hose = &pcie_hose[i];
hose->first_busno = bus;
- hose->last_busno = bus;
- bus++;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
+
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul (env, NULL, 10);
+ if (delay > 5)
+ printf ("Warning, expect noticable delay before PCIe"
+ "scan due to 'pciscandelay' value!\n");
+ mdelay (delay * 1000);
+ }
+
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
#endif
}
}
************************************************************************/
int board_early_init_f(void)
{
- volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
- x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
-
return 0;
}
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
- x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+ /* set modes of operation */
+ x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+ EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+ /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+ x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+ /* put Ethernet+PHY in reset */
+ x->ethuart &= ~EPLD2_RESET_ETH_N;
+ udelay(10000);
+ /* take Ethernet+PHY out of reset */
+ x->ethuart |= EPLD2_RESET_ETH_N;
return 0;
}
return 0;
}
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
/*************************************************************************
* int testdram()
#include <command.h>
#include <i2c.h>
-static u8 boot_533_nor[] = {
- 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-};
+/*
+ * There are 2 versions of production Sequoia & Rainier platforms.
+ * The primary difference is the reference clock. Those with
+ * 33333333 reference clocks will also have 667MHz rated
+ * processors. Not enough differences to have unique clock
+ * settings.
+ *
+ * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
+ * values are independent of the rest of the clock settings.
+ *
+ * All Sequoias & Rainiers select from two possible EEPROMs in Boot
+ * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
+ * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
+ * the only value affected for a 66MHz PCI and simply needs a +0x10.
+ */
+
+#define NAND_COMPATIBLE 0x01
+#define NOR_COMPATIBLE 0x02
+
+/* check with Stefan on CFG_I2C_EEPROM_ADDR */
+#define I2C_EEPROM_ADDR 0x52
-static u8 boot_533_nand[] = {
- 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+static char *config_labels[] = {
+ "CPU: 333 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 333 PLB: 166 OPB: 83 EBC: 55",
+ "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 400 PLB: 160 OPB: 80 EBC: 53",
+ "CPU: 416 PLB: 166 OPB: 83 EBC: 55",
+ "CPU: 500 PLB: 166 OPB: 83 EBC: 55",
+ "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 667 PLB: 166 OPB: 83 EBC: 55",
+ NULL
};
-static u8 boot_667_nor[] = {
- 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+static u8 boot_configs[][17] = {
+ {
+ (NOR_COMPATIBLE),
+ 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
+ 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NOR_COMPATIBLE),
+ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NOR_COMPATIBLE),
+ 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
+ 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
+ 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NOR_COMPATIBLE),
+ 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
+ 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ }
};
-static u8 boot_667_nand[] = {
- 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+/*
+ * Bytes 6,8,9,11 change for NAND boot
+ */
+static u8 nand_boot[] = {
+ 0xd0, 0xa0, 0x68, 0x58
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- u8 chip;
- u8 *buf;
- int cpu_freq;
+ u8 *buf, bNAND;
+ int x, y, nbytes, selcfg;
+ extern char console_buffer[];
- if (argc < 3) {
+ if (argc < 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
- cpu_freq = simple_strtol(argv[1], NULL, 10);
- if (!((cpu_freq == 533) || (cpu_freq == 667))) {
- printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
+ if ((strcmp(argv[1], "nor") != 0) &&
+ (strcmp(argv[1], "nand") != 0)) {
+ printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
- /* use 0x52 as I2C EEPROM address for now */
- chip = 0x52;
+ /* set the nand flag based on provided input */
+ if ((strcmp(argv[1], "nand") == 0))
+ bNAND = 1;
+ else
+ bNAND = 0;
- if ((strcmp(argv[2], "nor") != 0) &&
- (strcmp(argv[2], "nand") != 0)) {
- printf("Unsupported boot-device - only nor|nand support\n");
- return 1;
- }
+ printf("Available configurations: \n\n");
- if (strcmp(argv[2], "nand") == 0) {
- switch (cpu_freq) {
- default:
- case 533:
- buf = boot_533_nand;
- break;
- case 667:
- buf = boot_667_nand;
- break;
+ if (bNAND) {
+ for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+ /* filter on nand compatible */
+ if (boot_configs[x][0] & NAND_COMPATIBLE) {
+ printf(" %d - %s\n", (y+1), config_labels[x]);
+ y++;
+ }
}
} else {
- switch (cpu_freq) {
- default:
- case 533:
- buf = boot_533_nor;
- break;
- case 667:
- buf = boot_667_nor;
- break;
+ for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+ /* filter on nor compatible */
+ if (boot_configs[x][0] & NOR_COMPATIBLE) {
+ printf(" %d - %s\n", (y+1), config_labels[x]);
+ y++;
+ }
}
}
- if (i2c_write(chip, 0, 1, buf, 16) != 0)
- printf("Error writing to EEPROM at address 0x%x\n", chip);
+ do {
+ nbytes = readline(" Selection [1-x / quit]: ");
+
+ if (nbytes) {
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+ selcfg = simple_strtol(console_buffer, NULL, 10);
+ if ((selcfg < 1) || (selcfg > y))
+ nbytes = 0;
+ }
+ } while (nbytes == 0);
+
+
+ y = (selcfg - 1);
+
+ for (x = 0; boot_configs[x][0] != 0; x++) {
+ if (bNAND) {
+ if (boot_configs[x][0] & NAND_COMPATIBLE) {
+ if (y > 0)
+ y--;
+ else if (y < 1)
+ break;
+ }
+ } else {
+ if (boot_configs[x][0] & NOR_COMPATIBLE) {
+ if (y > 0)
+ y--;
+ else if (y < 1)
+ break;
+ }
+ }
+ }
+
+ buf = &boot_configs[x][1];
+
+ if (bNAND) {
+ buf[6] = nand_boot[0];
+ buf[8] = nand_boot[1];
+ buf[9] = nand_boot[2];
+ buf[11] = nand_boot[3];
+ }
+
+ /* check CPLD register +5 for PCI 66MHz flag */
+ if (in8(CFG_BCSR_BASE + 5) & 0x01)
+ buf[5] += 0x10;
+
+ if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
+ printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
}
U_BOOT_CMD(
- bootstrap, 3, 0, do_bootstrap,
+ bootstrap, 2, 0, do_bootstrap,
"bootstrap - program the I2C bootstrap EEPROM\n",
- "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
+ "<nand|nor> - strap to boot from NAND or NOR flash\n"
);
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ /* TLB-entry PCI IO Space - from sr@denx.de */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o flash.o lcd.o update.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define CFG_FLASH_CHAR_SIZE unsigned char
+#define CFG_FLASH_CHAR_ADDR0 (0x0aaa)
+#define CFG_FLASH_CHAR_ADDR1 (0x0555)
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef FLASH_BASE1_PRELIM
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1=0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ if (size_b0) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+ /* Also protect sector containing initial power-up instruction */
+ /* (flash_protect() checks address range - other call ignored) */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+ }
+#ifdef FLASH_BASE1_PRELIM
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2;
+
+ if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+ size_b1, size_b1 << 20);
+ }
+
+ if (size_b1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
+ flash_info[1].size = size_b1;
+ }
+#endif
+ return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000*2);
+ }
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000*2);
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
+
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMLV128U:
+ printf("AM29LV128U (128 Mbit * 2, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_S29GL128N:
+ printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef FLASH_BASE1_PRELIM
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ if ((ulong)addr == FLASH_BASE1_PRELIM) {
+ return flash_get_size_2(addr, info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return 0; /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ }
+ else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000 * 2);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return info->size;
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return 0;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef FLASH_BASE1_PRELIM
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return 2;
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ CFG_FLASH_CHAR_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ udelay(1000);
+
+ value = (CFG_FLASH_CHAR_SIZE)addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return 0; /* no or unknown flash */
+ }
+
+ value = (CFG_FLASH_CHAR_SIZE)addr2[2]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
+ if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
+ && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
+ info->flash_id += FLASH_AMLV128U;
+ info->sector_count = 256;
+ info->size = 0x01000000;
+ } else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
+ && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
+ info->flash_id += FLASH_S29GL128N;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ }
+ else
+ info->flash_id = FLASH_UNKNOWN;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00020000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0;
+ return info->size;
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
+ (CFG_FLASH_WORD_SIZE) 0x80808080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return 2;
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#endif /* FLASH_BASE1_PRELIM */
--- /dev/null
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define LCD_CMD_ADDR 0x50100002
+#define LCD_DATA_ADDR 0x50100003
+#define LCD_BLK_CTRL CPLD_REG1_ADDR
+
+static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
+static int addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+ out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
+}
+
+static void lcd_putc(int val)
+{
+ int i = 100;
+ char addr;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ addr = in_8((u8 *) LCD_CMD_ADDR);
+ udelay(50);
+ if ((addr != 0) && (addr % 0x10 == 0)) {
+ addr_flag ^= 0x40;
+ out_8((u8 *) LCD_CMD_ADDR, addr_flag);
+ }
+
+ udelay(50);
+ out_8((u8 *) LCD_DATA_ADDR, val);
+ udelay(50);
+}
+
+static void lcd_puts(char *s)
+{
+ char *p = s;
+ int i = 100;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ while (*p)
+ lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+ int i = 100;
+ char *p = amcc_logo;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ while (*p)
+ lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+ puts("LCD: ");
+ out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
+ udelay(50);
+ out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
+ udelay(50);
+ out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
+ udelay(2000);
+ out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
+ udelay(50);
+ lcd_bl_ctrl(0x02); /* set backlight on */
+ lcd_put_logo();
+ puts("ready\n");
+
+ return 0;
+}
+
+static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ out_8((u8 *) LCD_CMD_ADDR, 0x01);
+ udelay(2000);
+
+ return 0;
+}
+
+static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc < 2) {
+ printf("%s", cmdtp->usage);
+ return 1;
+ }
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
+static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc < 2) {
+ printf("%s", cmdtp->usage);
+ return 1;
+ }
+ lcd_putc((char)argv[1][0]);
+
+ return 0;
+}
+
+static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ ulong count;
+ ulong dir;
+ char cur_addr;
+
+ if (argc < 3) {
+ printf("%s", cmdtp->usage);
+ return 1;
+ }
+
+ count = simple_strtoul(argv[1], NULL, 16);
+ if (count > 31) {
+ printf("unable to shift > 0x20\n");
+ count = 0;
+ }
+
+ dir = simple_strtoul(argv[2], NULL, 16);
+ cur_addr = in_8((u8 *) LCD_CMD_ADDR);
+ udelay(50);
+
+ if (dir == 0x0) {
+ if (addr_flag == 0x80) {
+ if (count >= (cur_addr & 0xf)) {
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ udelay(50);
+ count = 0;
+ }
+ } else {
+ if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ addr_flag = 0x80;
+ udelay(50);
+ count = 0x0;
+ } else if (count >= ( cur_addr & 0xf)) {
+ count -= cur_addr & 0xf ;
+ out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
+ addr_flag = 0x80;
+ udelay(50);
+ }
+ }
+ } else {
+ if (addr_flag == 0x80) {
+ if (count >= (0x1f - (cur_addr & 0xf))) {
+ count = 0x0;
+ addr_flag = 0xc0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
+ udelay(50);
+ } else if ((count + (cur_addr & 0xf ))>= 0x0f) {
+ count = count + (cur_addr & 0xf) - 0x0f;
+ addr_flag = 0xc0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xc0);
+ udelay(50);
+ }
+ } else if ((count + (cur_addr & 0xf )) >= 0x0f) {
+ count = 0x0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
+ udelay(50);
+ }
+ }
+ while (count--) {
+ if (dir == 0)
+ out_8((u8 *) LCD_CMD_ADDR, 0x10);
+ else
+ out_8((u8 *) LCD_CMD_ADDR, 0x14);
+ udelay(50);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lcd_cls, 1, 1, do_lcd_clear,
+ "lcd_cls - lcd clear display\n",
+ NULL
+ );
+
+U_BOOT_CMD(
+ lcd_puts, 2, 1, do_lcd_puts,
+ "lcd_puts - display string on lcd\n",
+ "<string> - <string> to be displayed\n"
+ );
+
+U_BOOT_CMD(
+ lcd_putc, 2, 1, do_lcd_putc,
+ "lcd_putc - display char on lcd\n",
+ "<char> - <char> to be displayed\n"
+ );
+
+U_BOOT_CMD(
+ lcd_cur, 3, 1, do_lcd_cur,
+ "lcd_cur - shift cursor on lcd\n",
+ "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
+ " <count> - 0..31\n"
+ " <dir> - 0=backward 1=forward\n"
+ );
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <asm/gpio.h>
+
+extern int lcd_init(void);
+
+/*
+ * board_early_init_f
+ */
+int board_early_init_f(void)
+{
+ lcd_init();
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000);
+ mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
+ mtdcr(uictr, 0x00000000); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+
+ mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
+ mtebc(pb3cr, CFG_EBC_PB3CR);
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter
+ */
+ mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+ return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
+}
+
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+ char stat;
+ int i;
+
+ stat = in_8((u8 *) CPLD_REG0_ADDR);
+ printf("SW2 status: ");
+ for (i=0; i<4; i++) /* 4-position */
+ printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
+ printf("\n");
+ return 0;
+}
+
+U_BOOT_CMD (
+ sw2_stat, 1, 1, do_sw_stat,
+ "sw2_stat - show status of switch 2\n",
+ NULL
+ );
+
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+ int led_no;
+
+ if (argc != 3) {
+ printf("%s", cmd_tp->usage);
+ return -1;
+ }
+
+ led_no = simple_strtoul(argv[1], NULL, 16);
+ if (led_no != 1 && led_no != 2) {
+ printf("%s", cmd_tp->usage);
+ return -1;
+ }
+
+ if (strcmp(argv[2],"off") == 0x0) {
+ if (led_no == 1)
+ gpio_write_bit(30, 1);
+ else
+ gpio_write_bit(31, 1);
+ } else if (strcmp(argv[2],"on") == 0x0) {
+ if (led_no == 1)
+ gpio_write_bit(30, 0);
+ else
+ gpio_write_bit(31, 0);
+ } else {
+ printf("%s", cmd_tp->usage);
+ return -1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ led_ctl, 3, 1, do_led_ctl,
+ "led_ctl - make led 1 or 2 on or off\n",
+ "<led_no> <on/off> - make led <led_no> on/off,\n"
+ "\tled_no is 1 or 2\t"
+ );
+
+#define SPI_CS_GPIO0 0
+#define SPI_SCLK_GPIO14 14
+#define SPI_DIN_GPIO15 15
+#define SPI_DOUT_GPIO16 16
+
+void spi_scl(int bit)
+{
+ gpio_write_bit(SPI_SCLK_GPIO14, bit);
+}
+
+void spi_sda(int bit)
+{
+ gpio_write_bit(SPI_DOUT_GPIO16, bit);
+}
+
+unsigned char spi_read(void)
+{
+ return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+}
+
+void taihu_spi_chipsel(int cs)
+{
+ gpio_write_bit(SPI_CS_GPIO0, cs);
+}
+
+spi_chipsel_type spi_chipsel[]= {
+ taihu_spi_chipsel
+};
+
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#ifdef CONFIG_PCI
+static unsigned char int_lines[32] = {
+ 29, 30, 27, 28, 29, 30, 25, 27,
+ 29, 30, 27, 28, 29, 30, 27, 28,
+ 29, 30, 27, 28, 29, 30, 27, 28,
+ 29, 30, 27, 28, 29, 30, 27, 28};
+
+static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+ hose->fixup_irq = taihu_pci_fixup_irq;
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+#ifdef CFG_DRAM_TEST
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+ unsigned long msr;
+ unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_EE));
+
+ for (k = 0; k < total_kbytes ;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0)
+ printf("%3d MB\r", k / 1024);
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ mtmsr(msr);
+
+ return 0;
+}
+#endif /* CFG_DRAM_TEST */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#define PCI_M66EN 0x10
+
+static uchar buf_33[] =
+{
+ 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+ 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x0d~0x0e:vendor id 0x1014*/
+ 0x14,
+ 0x00, /* 0x0f~0x10:device id 0x0000*/
+ 0x00,
+ 0x00, /* 0x11:revision 0x00 */
+ 0x00, /* 0x12~0x14:class 0x000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x15~0x16:subsystem vendor id */
+ 0xe8,
+ 0x00, /* 0x17~0x18:subsystem device id */
+ 0x00,
+ 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+ 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+ 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
+ 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+ 0xbe, /* 0x1d: tun[24-31]=0xbe */
+ 0x00,
+ 0x00
+};
+
+static uchar buf_66[] =
+{
+ 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+ 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x0d~0x0e:vendor id 0x1014*/
+ 0x14,
+ 0x00, /* 0x0f~0x10:device id 0x0000*/
+ 0x00,
+ 0x00, /* 0x11:revision 0x00 */
+ 0x00, /* 0x12~0x14:class 0x000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x15~0x16:subsystem vendor id */
+ 0xe8,
+ 0x00, /* 0x17~0x18:subsystem device id */
+ 0x00,
+ 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+ 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+ 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
+ 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+ 0xbe, /* 0x1d: tun[24-31]=0xbe */
+ 0x00,
+ 0x00
+};
+
+static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
+{
+ ulong len = 0x20;
+ uchar chip = CFG_I2C_EEPROM_ADDR;
+ uchar *pbuf;
+ uchar base;
+ int i;
+
+ if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
+ pbuf = buf_33;
+ base = 0x00;
+ } else {
+ pbuf = buf_66;
+ base = 0x40;
+ }
+
+ for (i = 0; i< len; i++, base++) {
+ if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
+ printf("i2c_write fail\n");
+ return 1;
+ }
+ udelay(11000);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ update_boot_eeprom, 1, 1, update_boot_eeprom,
+ "update_boot_eeprom - update boot eeprom content\n",
+ NULL
+ );
void show_reset_reg(void);
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int lcd_init(void);
int board_early_init_f (void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
#include "yucca.h"
#include "../cpu/ppc4xx/440spe_pcie.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#undef PCIE_ENDPOINT
/* #define PCIE_ENDPOINT 1 */
return 0;
}
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+ if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+ return 1;
+ else
+ return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+ /*
+ * Yucca boards with 440SPe rev. A need a slightly different setup
+ * for the MCIF0_WRDTR register.
+ */
+ if (ppc440spe_rev_a())
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+ return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+ /*
+ * Yucca boards with 440SPe rev. A need a slightly different setup
+ * for the MCIF0_CLKTR register.
+ */
+ if (ppc440spe_rev_a())
+ return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+ return default_val;
+}
+
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
+ char *env;
+ unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
- bus = 1;
+ bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
hose = &pcie_hose[i];
hose->first_busno = bus;
- hose->last_busno = bus;
- bus++;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
+
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul (env, NULL, 10);
+ if (delay > 5)
+ printf ("Warning, expect noticable delay before PCIe"
+ "scan due to 'pciscandelay' value!\n");
+ mdelay (delay * 1000);
+ }
+
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
#endif
}
}
LIB = $(obj)lib$(BOARD).a
-COBJS := at91rm9200dk.o at45.o flash.o
+COBJS := at91rm9200dk.o flash.o led.o mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
-the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS (0xC << 16)
-#define DATAFLASH_TCHS (0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY 200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */
-
-void AT91F_SpiInit(void) {
-
-/*-------------------------------------------------------------------*/
-/* SPI DataFlash Init */
-/*-------------------------------------------------------------------*/
- /* Configure PIOs */
- AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
- AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
- AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
- AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
- /* Enable CLock */
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
- /* Reset the SPI */
- AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
- /* Configure SPI in Master Mode with No CS selected !!! */
- AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
- /* Configure CS0 and CS3 */
- *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
- DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
- *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
- DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-}
-
-void AT91F_SpiEnable(int cs) {
- switch(cs) {
- case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
- AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
- break;
- case 3: /* Configure SPI CS3 for Serial DataFlash Card */
- /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
- AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */
- AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */
- /* Clear Output */
- AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
- /* Configure PCS */
- AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
- break;
- }
-
- /* SPI_Enable */
- AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-/*----------------------------------------------------------------------------*/
-/* \fn AT91F_SpiWrite */
-/* \brief Set the PDC registers for a transfert */
-/*----------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
- unsigned int timeout;
-
- pDesc->state = BUSY;
-
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
- /* Initialize the Transmit and Receive Pointer */
- AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
- AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
- /* Intialize the Transmit and Receive Counters */
- AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
- AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
- if ( pDesc->tx_data_size != 0 ) {
- /* Initialize the Next Transmit and Next Receive Pointer */
- AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
- AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
- /* Intialize the Next Transmit and Next Receive Counters */
- AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
- AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
- }
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked();
- timeout = 0;
-
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
- while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
- pDesc->state = IDLE;
-
- if (timeout >= CFG_SPI_WRITE_TOUT){
- printf("Error Timeout\n\r");
- return DATAFLASH_ERROR;
- }
-
- return DATAFLASH_OK;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashSendCommand */
-/* \brief Generic function to send a command to the dataflash */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
- AT91PS_DataFlash pDataFlash,
- unsigned char OpCode,
- unsigned int CmdSize,
- unsigned int DataflashAddress)
-{
- unsigned int adr;
-
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* process the address to obtain page address and byte address */
- adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
-
- /* fill the command buffer */
- pDataFlash->pDataFlashDesc->command[0] = OpCode;
- if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
- pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
- } else {
- pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
- pDataFlash->pDataFlashDesc->command[4] = 0;
- }
- pDataFlash->pDataFlashDesc->command[5] = 0;
- pDataFlash->pDataFlashDesc->command[6] = 0;
- pDataFlash->pDataFlashDesc->command[7] = 0;
-
- /* Initialize the SpiData structure for the spi write fuction */
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ;
-
- /* send the command and read the data */
- return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashGetStatus */
-/* \brief Read the status register of the dataflash */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
-{
- AT91S_DataFlashStatus status;
-
- /* if a transfert is in progress ==> return 0 */
- if( (pDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* first send the read status command (D7H) */
- pDesc->command[0] = DB_STATUS;
- pDesc->command[1] = 0;
-
- pDesc->DataFlash_state = GET_STATUS;
- pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
- pDesc->tx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_size = 2 ;
- pDesc->tx_cmd_size = 2 ;
- status = AT91F_SpiWrite (pDesc);
-
- pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
-
- return status;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashWaitReady */
-/* \brief wait for dataflash ready (bit7 of the status register == 1) */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
-{
- pDataFlashDesc->DataFlash_state = IDLE;
-
- do {
- AT91F_DataFlashGetStatus(pDataFlashDesc);
- timeout--;
- } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
-
- if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
- return DATAFLASH_ERROR;
-
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashContinuousRead */
-/* Object : Continuous stream Read */
-/* Input Parameters : DataFlash Service */
-/* : <src> = dataflash address */
-/* : <*dataBuffer> = data buffer pointer */
-/* : <sizeToRead> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
- int src,
- unsigned char *dataBuffer,
- int sizeToRead )
-{
- AT91S_DataFlashStatus status;
- /* Test the size to read in the device */
- if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
- return DATAFLASH_MEMORY_OVERFLOW;
-
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
-
- status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
- /* Send the command to the dataflash */
- return(status);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashPagePgmBuf */
-/* Object : Main memory page program through buffer 1 or buffer 2 */
-/* Input Parameters : DataFlash Service */
-/* : <*src> = Source buffer */
-/* : <dest> = dataflash destination address */
-/* : <SizeToWrite> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int SizeToWrite)
-{
- int cmdsize;
- pDataFlash->pDataFlashDesc->tx_data_pt = src ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->rx_data_pt = src;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
-
- cmdsize = 4;
- /* Send the command to the dataflash */
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_MainMemoryToBufferTransfert */
-/* Object : Read a page in the SRAM Buffer 1 or 2 */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int page)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
- return DATAFLASH_BAD_COMMAND;
-
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*----------------------------------------------------------------------------- */
-/* Function Name : AT91F_DataFlashWriteBuffer */
-/* Object : Write data to the internal sram buffer 1 or 2 */
-/* Input Parameters : DataFlash Service */
-/* : <BufferCommand> = command to write buffer1 or buffer2 */
-/* : <*dataBuffer> = data buffer to write */
-/* : <bufferAddress> = address in the internal buffer */
-/* : <SizeToWrite> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned char *dataBuffer,
- unsigned int bufferAddress,
- int SizeToWrite )
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
- return DATAFLASH_BAD_COMMAND;
-
- /* buffer address must be lower than page size */
- if (bufferAddress > pDataFlash->pDevice->pages_size)
- return DATAFLASH_BAD_ADDRESS;
-
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* Send first Write Command */
- pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
- pDataFlash->pDataFlashDesc->command[1] = 0;
- if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[2] = 0;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- cmdsize = 5;
- } else {
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- pDataFlash->pDataFlashDesc->command[4] = 0;
- cmdsize = 4;
- }
-
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
-
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
-
- return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_PageErase */
-/* Object : Erase a page */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PageErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int page)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_BlockErase */
-/* Object : Erase a Block */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_BlockErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int block)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_WriteBufferToMain */
-/* Object : Write buffer to the main memory */
-/* Input Parameters : DataFlash Service */
-/* : <BufferCommand> = command to send to buffer1 or buffer2 */
-/* : <dest> = main memory address */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int dest )
-{
- int cmdsize;
- /* Test if the buffer command is correct */
- if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
- (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
- return DATAFLASH_BAD_COMMAND;
-
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- /* Send the command to the dataflash */
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_PartialPageWrite */
-/* Object : Erase partielly a page */
-/* Input Parameters : <page> = page number */
-/* : <AdrInpage> = adr to begin the fading */
-/* : <length> = Number of bytes to erase */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int size)
-{
- unsigned int page;
- unsigned int AdrInPage;
-
- page = dest / (pDataFlash->pDevice->pages_size);
- AdrInPage = dest % (pDataFlash->pDevice->pages_size);
-
- /* Read the contents of the page in the Sram Buffer */
- AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- /*Update the SRAM buffer */
- AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Erase page if a 128 Mbits device */
- if (pDataFlash->pDevice->pages_number >= 16384) {
- AT91F_PageErase(pDataFlash, page);
- /* Rewrite the modified Sram Buffer in the main memory */
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- }
-
- /* Rewrite the modified Sram Buffer in the main memory */
- return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashWrite */
-/* Object : */
-/* Input Parameters : <*src> = Source buffer */
-/* : <dest> = dataflash adress */
-/* : <size> = data buffer size */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size )
-{
- unsigned int length;
- unsigned int page;
- unsigned int status;
-
- AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
- if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
- return DATAFLASH_MEMORY_OVERFLOW;
-
- /* If destination does not fit a page start address */
- if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
- length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
-
- if (size < length)
- length = size;
-
- if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Update size, source and destination pointers */
- size -= length;
- dest += length;
- src += length;
- }
-
- while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
- /* program dataflash page */
- page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
-
- status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- status = AT91F_PageErase(pDataFlash, page);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- if (!status)
- return DATAFLASH_ERROR;
-
- status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
- if(!status)
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Update size, source and destination pointers */
- size -= pDataFlash->pDevice->pages_size ;
- dest += pDataFlash->pDevice->pages_size ;
- src += pDataFlash->pDevice->pages_size ;
- }
-
- /* If still some bytes to read */
- if ( size > 0 ) {
- /* program dataflash page */
- if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- }
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashRead */
-/* Object : Read a block in dataflash */
-/* Input Parameters : */
-/* Return value : */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
- AT91PS_DataFlash pDataFlash,
- unsigned long addr,
- unsigned long size,
- char *buffer)
-{
- unsigned long SizeToRead;
-
- AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
- if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
- return -1;
-
- while (size) {
- SizeToRead = (size < 0x8000)? size:0x8000;
-
- if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
- return -1;
-
- if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK)
- return -1;
-
- size -= SizeToRead;
- addr += SizeToRead;
- buffer += SizeToRead;
- }
-
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataflashProbe */
-/* Object : */
-/* Input Parameters : */
-/* Return value : Dataflash status register */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
-{
- AT91F_SpiEnable(cs);
- AT91F_DataFlashGetStatus(pDesc);
- return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
-}
-
-#endif
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+
+#define GREEN_LED AT91C_PIO_PB0
+#define YELLOW_LED AT91C_PIO_PB1
+#define RED_LED AT91C_PIO_PB2
+
+void green_LED_on(void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ PIOB->PIO_CODR = GREEN_LED;
+}
+
+void yellow_LED_on(void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ PIOB->PIO_CODR = YELLOW_LED;
+}
+
+void red_LED_on(void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ PIOB->PIO_CODR = RED_LED;
+}
+
+void green_LED_off(void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ PIOB->PIO_SODR = GREEN_LED;
+}
+
+void yellow_LED_off(void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ PIOB->PIO_SODR = YELLOW_LED;
+}
+
+void red_LED_off(void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ PIOB->PIO_SODR = RED_LED;
+}
+
+
+void LED_init (void)
+{
+ AT91PS_PIO PIOB = AT91C_BASE_PIOB;
+ AT91PS_PMC PMC = AT91C_BASE_PMC;
+ PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */
+ /* Disable peripherals on LEDs */
+ PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+ /* Enable pins as outputs */
+ PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+ /* Turn all LEDs OFF */
+ PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+}
--- /dev/null
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+int AT91F_GetMuxStatus(void) {
+#ifdef DATAFLASH_MMC_SELECT
+ AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
+ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
+
+
+ if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) {
+ return 1;
+ } else {
+ return 0;
+ }
+#endif
+ return 0;
+}
+
+void AT91F_SelectMMC(void) {
+#ifdef DATAFLASH_MMC_SELECT
+ AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
+ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
+ /* Set Output */
+ AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT;
+#endif
+}
+
+void AT91F_SelectSPI(void) {
+#ifdef DATAFLASH_MMC_SELECT
+ AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
+ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
+ /* Clear Output */
+ AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT;
+#endif
+}
#include "psd4256.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF531)
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
#include <asm/io.h>
#include "bf533-stamp.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define STATUS_LED_OFF 0
#define STATUS_LED_ON 1
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
printf("SDRAM attributes:\n");
printf
#include <asm/io.h>
#include "ether_bf537.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define POST_WORD_ADDR 0xFF903FFC
/*
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
#include <common.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
printf("CPU: ADSP BF561\n");
long int initdram(int board_type)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
pci_dev_t dev, struct pci_config_table *tab)
{
pci_dev_t bridge;
+ unsigned int cmdstat;
/* Enable USB and IDE functions */
pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
- pciauto_config_device(hose, dev);
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/*
* Force the backplane P2P bridge to have a window
* This allows legacy I/O (i8259, etc) on the VIA
* southbridge to be accessed.
*/
- bridge = PCI_BDF(0,17,0);
+ bridge = PCI_BDF(0,BRIDGE_ID,0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
{},
};
#
-# Copyright 2004 Freescale Semiconductor.
+# Copyright 2004, 2007 Freescale Semiconductor.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# mpc8548cds board
#
+ifndef TEXT_BASE
TEXT_BASE = 0xfff80000
+endif
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright 2002,2003, Motorola Inc.
*
* See file CREDITS for list of people who contributed to this
#include <config.h>
#include <mpc85xx.h>
+#define LAWAR_TRGT_PCI1 0x00000000
+#define LAWAR_TRGT_PCI2 0x00100000
+#define LAWAR_TRGT_PCIE 0x00200000
+#define LAWAR_TRGT_RIO 0x00c00000
+#define LAWAR_TRGT_LBC 0x00400000
+#define LAWAR_TRGT_DDR 0x00f00000
/*
* TLB0 and TLB1 Entries
*/
#define entry_start \
- mflr r1 ; \
- bl 0f ;
+ mflr r1 ; \
+ bl 0f ;
#define entry_end \
0: mflr r0 ; \
#endif
/*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
*/
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
.long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+#ifdef CFG_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI2 MEM
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
- 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 3: 1GB Non-cacheable, guarded
- * 0xa0000000 256M PEX MEM First half
- * 0xb0000000 256M PEX MEM Second half
- * 0xc0000000 256M Rapid IO MEM First half
- * 0xd0000000 256M Rapid IO MEM Second half
+ * TLB 3: 256M Non-cacheable, guarded
*/
.long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: Reserved for future usage
- */
-
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 8M PCI1 IO
- * 0xe280_0000 8M PCI2 IO
- * 0xe300_0000 16M PEX IO
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xf8000000 64M CADMUS registers, relocated L2SRAM
*/
.long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
2:
entry_end
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M
- * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M
- * 0xa000_0000 0xbfff_ffff PEX MEM 512M
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
- * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M
- * 0xe300_0000 0xe3ff_ffff PEX IO 16M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
* 0xf000_0000 0xf3ff_ffff SDRAM 64M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ * LAW 0 is reserved for boot mapping
*/
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+ .long (4f-3f)/8
+3:
+ .long 0
+ .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+#ifdef CFG_PCI1_MEM_PHYS
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#ifdef CFG_PCI2_MEM_PHYS
+ .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+ .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
-#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#ifdef CFG_PCIE1_MEM_PHYS
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
- .section .bootpg, "ax"
- .globl law_entry
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-law_entry:
- entry_start
- .long (4f-3f)/8
-3:
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
- .long LAWBAR8,LAWAR8
+#ifdef CFG_RIO_MEM_PHYS
+ .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
4:
entry_end
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <miiphy.h>
#include "../common/eeprom.h"
#include "../common/via.h"
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern long int spd_sdram(void);
void local_bus_init(void);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
- uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
-
- uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
- printf (" PCI1: %d bit, %s MHz, %s\n",
- (pci1_32) ? 32 : 64,
- (pci1_speed == 33000000) ? "33" :
- (pci1_speed == 66000000) ? "66" : "unknown",
- pci1_clk_sel ? "sync" : "async");
-
- if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf (" PCI2: disabled\n");
- }
-
/*
* Initialize local bus.
*/
*/
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+ ecm->eedr = 0xffffffff; /* clear ecm errors */
+ ecm->eeer = 0xffffffff; /* enable ecm errors */
return 0;
}
lbc->lcrr |= 0x00030000;
asm("sync;isync;msync");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
}
/*
}
#endif
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.
*/
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller hose[] = {
- { config_table: pci_mpc85xxcds_config_table,},
-#ifdef CONFIG_MPC85XX_PCI2
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
{},
-#endif
};
+static struct pci_controller pci1_hose = {
+ config_table: pci_mpc85xxcds_config_table};
#endif /* CONFIG_PCI */
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
void
pci_init_board(void)
{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+ struct pci_config_table *table;
+
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+
+ /* relocate config table pointers */
+ hose->config_table = \
+ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+ for (table = hose->config_table; table && table->vendor; table++)
+ table->config_device += gd->reloc_off;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+ }
#endif
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
}
int last_stage_init(void)
return 0;
}
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+
+#ifdef CONFIG_PCI1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+
+#ifdef CONFIG_PCIE1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+}
+#endif
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
cpu/mpc85xx/cpu.o (.text)
drivers/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
{},
};
mem_conf_t *mem_conf;
mem_conf = get_mem_config(board_type);
-
+
/* configure SDRAM start/end for detection */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
hw_id_t hw_id_tmp;
char module_name_tmp[MODULE_NAME_MAXLEN] = "";
- /*
+ /*
* We need I2C to access HW ID data from EEPROM, so we call i2c_init()
* here despite the fact that it will be called again later on. We
* also use a little trick to silence I2C-related output.
else
printf("Board: unrecognized cm5200 module (%s)\n",
module_name_tmp);
-
+
return 0;
}
cmu1_qa_hw_id,
};
-/* indices to the above list - keep in sync */
+/* indices to the above list - keep in sync */
enum {
CM1_QA,
CM11_QA,
/*
* (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
*
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
#include <i2c.h>
#include <usb.h>
-#ifdef CONFIG_CMD_BSB
+#ifdef CONFIG_CMD_BSP
int do_i2c(char *argv[])
{
LIB = $(obj)lib$(BOARD).a
-COBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
+COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
-the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS (0xC << 16)
-#define DATAFLASH_TCHS (0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY 200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */
-
-void AT91F_SpiInit(void) {
-
-/*-------------------------------------------------------------------*/
-/* SPI DataFlash Init */
-/*-------------------------------------------------------------------*/
- /* Configure PIOs */
- AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
- AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
- AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
- AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
- /* Enable CLock */
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
- /* Reset the SPI */
- AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
- /* Configure SPI in Master Mode with No CS selected !!! */
- AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
- /* Configure CS0 and CS3 */
- *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
- DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
- *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
- DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-}
-
-void AT91F_SpiEnable(int cs) {
- switch(cs) {
- case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
- AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
- break;
- case 3: /* Configure SPI CS3 for Serial DataFlash Card */
- /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
- AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */
- AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */
- /* Clear Output */
- AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
- /* Configure PCS */
- AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
- break;
- }
-
- /* SPI_Enable */
- AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-/*----------------------------------------------------------------------------*/
-/* \fn AT91F_SpiWrite */
-/* \brief Set the PDC registers for a transfert */
-/*----------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
- unsigned int timeout;
-
- pDesc->state = BUSY;
-
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
- /* Initialize the Transmit and Receive Pointer */
- AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
- AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
- /* Intialize the Transmit and Receive Counters */
- AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
- AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
- if ( pDesc->tx_data_size != 0 ) {
- /* Initialize the Next Transmit and Next Receive Pointer */
- AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
- AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
- /* Intialize the Next Transmit and Next Receive Counters */
- AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
- AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
- }
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked();
- timeout = 0;
-
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
- while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
- pDesc->state = IDLE;
-
- if (timeout >= CFG_SPI_WRITE_TOUT){
- printf("Error Timeout\n\r");
- return DATAFLASH_ERROR;
- }
-
- return DATAFLASH_OK;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashSendCommand */
-/* \brief Generic function to send a command to the dataflash */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
- AT91PS_DataFlash pDataFlash,
- unsigned char OpCode,
- unsigned int CmdSize,
- unsigned int DataflashAddress)
-{
- unsigned int adr;
-
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* process the address to obtain page address and byte address */
- adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
-
- /* fill the command buffer */
- pDataFlash->pDataFlashDesc->command[0] = OpCode;
- if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
- pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
- } else {
- pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
- pDataFlash->pDataFlashDesc->command[4] = 0;
- }
- pDataFlash->pDataFlashDesc->command[5] = 0;
- pDataFlash->pDataFlashDesc->command[6] = 0;
- pDataFlash->pDataFlashDesc->command[7] = 0;
-
- /* Initialize the SpiData structure for the spi write fuction */
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ;
-
- /* send the command and read the data */
- return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashGetStatus */
-/* \brief Read the status register of the dataflash */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
-{
- AT91S_DataFlashStatus status;
-
- /* if a transfert is in progress ==> return 0 */
- if( (pDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* first send the read status command (D7H) */
- pDesc->command[0] = DB_STATUS;
- pDesc->command[1] = 0;
-
- pDesc->DataFlash_state = GET_STATUS;
- pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
- pDesc->tx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_size = 2 ;
- pDesc->tx_cmd_size = 2 ;
- status = AT91F_SpiWrite (pDesc);
-
- pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
-
- return status;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashWaitReady */
-/* \brief wait for dataflash ready (bit7 of the status register == 1) */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
-{
- pDataFlashDesc->DataFlash_state = IDLE;
-
- do {
- AT91F_DataFlashGetStatus(pDataFlashDesc);
- timeout--;
- } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
-
- if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
- return DATAFLASH_ERROR;
-
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashContinuousRead */
-/* Object : Continuous stream Read */
-/* Input Parameters : DataFlash Service */
-/* : <src> = dataflash address */
-/* : <*dataBuffer> = data buffer pointer */
-/* : <sizeToRead> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
- int src,
- unsigned char *dataBuffer,
- int sizeToRead )
-{
- AT91S_DataFlashStatus status;
- /* Test the size to read in the device */
- if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
- return DATAFLASH_MEMORY_OVERFLOW;
-
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
-
- status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
- /* Send the command to the dataflash */
- return(status);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashPagePgmBuf */
-/* Object : Main memory page program through buffer 1 or buffer 2 */
-/* Input Parameters : DataFlash Service */
-/* : <*src> = Source buffer */
-/* : <dest> = dataflash destination address */
-/* : <SizeToWrite> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int SizeToWrite)
-{
- int cmdsize;
- pDataFlash->pDataFlashDesc->tx_data_pt = src ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->rx_data_pt = src;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
-
- cmdsize = 4;
- /* Send the command to the dataflash */
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_MainMemoryToBufferTransfert */
-/* Object : Read a page in the SRAM Buffer 1 or 2 */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int page)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
- return DATAFLASH_BAD_COMMAND;
-
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*----------------------------------------------------------------------------- */
-/* Function Name : AT91F_DataFlashWriteBuffer */
-/* Object : Write data to the internal sram buffer 1 or 2 */
-/* Input Parameters : DataFlash Service */
-/* : <BufferCommand> = command to write buffer1 or buffer2 */
-/* : <*dataBuffer> = data buffer to write */
-/* : <bufferAddress> = address in the internal buffer */
-/* : <SizeToWrite> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned char *dataBuffer,
- unsigned int bufferAddress,
- int SizeToWrite )
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
- return DATAFLASH_BAD_COMMAND;
-
- /* buffer address must be lower than page size */
- if (bufferAddress > pDataFlash->pDevice->pages_size)
- return DATAFLASH_BAD_ADDRESS;
-
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* Send first Write Command */
- pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
- pDataFlash->pDataFlashDesc->command[1] = 0;
- if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[2] = 0;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- cmdsize = 5;
- } else {
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- pDataFlash->pDataFlashDesc->command[4] = 0;
- cmdsize = 4;
- }
-
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
-
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
-
- return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_PageErase */
-/* Object : Erase a page */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PageErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int page)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_BlockErase */
-/* Object : Erase a Block */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_BlockErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int block)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_WriteBufferToMain */
-/* Object : Write buffer to the main memory */
-/* Input Parameters : DataFlash Service */
-/* : <BufferCommand> = command to send to buffer1 or buffer2 */
-/* : <dest> = main memory address */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int dest )
-{
- int cmdsize;
- /* Test if the buffer command is correct */
- if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
- (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
- return DATAFLASH_BAD_COMMAND;
-
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- /* Send the command to the dataflash */
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_PartialPageWrite */
-/* Object : Erase partielly a page */
-/* Input Parameters : <page> = page number */
-/* : <AdrInpage> = adr to begin the fading */
-/* : <length> = Number of bytes to erase */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int size)
-{
- unsigned int page;
- unsigned int AdrInPage;
-
- page = dest / (pDataFlash->pDevice->pages_size);
- AdrInPage = dest % (pDataFlash->pDevice->pages_size);
-
- /* Read the contents of the page in the Sram Buffer */
- AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- /*Update the SRAM buffer */
- AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Erase page if a 128 Mbits device */
- if (pDataFlash->pDevice->pages_number >= 16384) {
- AT91F_PageErase(pDataFlash, page);
- /* Rewrite the modified Sram Buffer in the main memory */
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- }
-
- /* Rewrite the modified Sram Buffer in the main memory */
- return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashWrite */
-/* Object : */
-/* Input Parameters : <*src> = Source buffer */
-/* : <dest> = dataflash adress */
-/* : <size> = data buffer size */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size )
-{
- unsigned int length;
- unsigned int page;
- unsigned int status;
-
- AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
- if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
- return DATAFLASH_MEMORY_OVERFLOW;
-
- /* If destination does not fit a page start address */
- if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
- length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
-
- if (size < length)
- length = size;
-
- if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Update size, source and destination pointers */
- size -= length;
- dest += length;
- src += length;
- }
-
- while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
- /* program dataflash page */
- page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
-
- status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- status = AT91F_PageErase(pDataFlash, page);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- if (!status)
- return DATAFLASH_ERROR;
-
- status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
- if(!status)
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Update size, source and destination pointers */
- size -= pDataFlash->pDevice->pages_size ;
- dest += pDataFlash->pDevice->pages_size ;
- src += pDataFlash->pDevice->pages_size ;
- }
-
- /* If still some bytes to read */
- if ( size > 0 ) {
- /* program dataflash page */
- if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- }
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashRead */
-/* Object : Read a block in dataflash */
-/* Input Parameters : */
-/* Return value : */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
- AT91PS_DataFlash pDataFlash,
- unsigned long addr,
- unsigned long size,
- char *buffer)
-{
- unsigned long SizeToRead;
-
- AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
- if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
- return -1;
-
- while (size) {
- SizeToRead = (size < 0x8000)? size:0x8000;
-
- if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
- return -1;
-
- if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
- return -1;
-
- size -= SizeToRead;
- addr += SizeToRead;
- buffer += SizeToRead;
- }
-
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataflashProbe */
-/* Object : */
-/* Input Parameters : */
-/* Return value : Dataflash status register */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
-{
- AT91F_SpiEnable(cs);
- AT91F_DataFlashGetStatus(pDesc);
- return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
-}
-
-#endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
*/
#include <common.h>
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
+#include <asm/immap.h>
int checkboard (void)
long int initdram (int board_type)
{
- volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
+ volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+ } else {
+ }
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_AMD79C874VC "AMD79C874VC"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ strcpy(info->phy_name,
+ STR_ID_AMD79C874VC);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ printf(STR_ID_AMD79C874VC);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+int mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
#define MACH_TYPE_DAVINCI_EVM 901
+DECLARE_GLOBAL_DATA_PTR;
+
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
tmp[0] &= buf[i];
if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
- sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
setenv("ethaddr", (char *)&tmp[0]);
}
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#define MACH_TYPE_SCHMOOGIE 1255
+DECLARE_GLOBAL_DATA_PTR;
+
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
forceenv("serial#", "FAILED");
} else {
/* CRC OK, set "serial" env variable */
- sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx",
+ sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
forceenv("serial#", (char *)&tmp[0]);
}
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#define MACH_TYPE_SONATA 1254
+DECLARE_GLOBAL_DATA_PTR;
+
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SONATA;
tmp[0] &= buf[i];
if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
- sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
setenv("ethaddr", (char *)&tmp[0]);
}
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
-int testdram (void)
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
+#ifdef CONFIG_LXT971_NO_SLEEP
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
#endif
+}
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ $(CPLD) \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
return 0;
/*
* Setup and enable EEPROM write protection
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
-
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
return (0);
}
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
break;
}
}
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#include <common.h>
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
-#endif
-
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
+#if defined(CFG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
+#endif
#include <fat.h>
#include <part.h>
rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#else
+ rc = -1;
#endif
}
if (rc != 0) {
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETCLE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+ break;
+ case NAND_CTL_CLRCLE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+ break;
+ case NAND_CTL_SETALE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+ break;
+ case NAND_CTL_CLRALE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+ break;
+ case NAND_CTL_SETNCE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+ break;
+ case NAND_CTL_CLRNCE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+ break;
+ }
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+ return 1;
+ return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+ /*
+ * Set NAND-FLASH GPIO signals to defaults
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Initialize nand_chip structure
+ */
+ nand->hwcontrol = esd405ep_nand_hwcontrol;
+ nand->dev_ready = esd405ep_nand_device_ready;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_BIG_DELAY_US;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ return 0;
+}
+#endif
#define DP(x)
#endif
+static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
+ {"PCI0DLL_1 "}, /* 30 */
+ {"PCI0DLL_0 "}, /* 29 */
+ {"PCI1DLL_2 "}, /* 28 */
+ {"PCI1DLL_1 "}, /* 27 */
+ {"PCI1DLL_0 "}, /* 26 */
+ {"BbEP2En "}, /* 25 */
+ {"SDRAMRdDataDel"}, /* 24 */
+ {"SDRAMRdDel "}, /* 23 */
+ {"SDRAMSync "}, /* 22 */
+ {"SDRAMPipeSel_1"}, /* 21 */
+ {"SDRAMPipeSel_0"}, /* 20 */
+ {"SDRAMAddDel "}, /* 19 */
+ {"SDRAMClkSel "}, /* 18 */
+ {"Reserved(1!) "}, /* 17 */
+ {"PCIRty "}, /* 16 */
+ {"BootCSWidth_1 "}, /* 15 */
+ {"BootCSWidth_0 "}, /* 14 */
+ {"PCI1PadsCal "}, /* 13 */
+ {"PCI0PadsCal "}, /* 12 */
+ {"MultiMVId_1 "}, /* 11 */
+ {"MultiMVId_0 "}, /* 10 */
+ {"MultiGTEn "}, /* 09 */
+ {"Int60xArb "}, /* 08 */
+ {"CPUBusConfig_1"}, /* 07 */
+ {"CPUBusConfig_0"}, /* 06 */
+ {"DefIntSpc "}, /* 05 */
+ {0 }, /* 04 */
+ {"SROMAdd_1 "}, /* 03 */
+ {"SROMAdd_0 "}, /* 02 */
+ {"DRAMPadCal "}, /* 01 */
+ {"SInitEn "}, /* 00 */
+ {0 }, /* 31 */
+ {0 }, /* 30 */
+ {0 }, /* 29 */
+ {0 }, /* 28 */
+ {0 }, /* 27 */
+ {0 }, /* 26 */
+ {0 }, /* 25 */
+ {0 }, /* 24 */
+ {0 }, /* 23 */
+ {0 }, /* 22 */
+ {"JTAGCalBy "}, /* 21 */
+ {"GB2Sel "}, /* 20 */
+ {"GB1Sel "}, /* 19 */
+ {"DRAMPLL_MDiv_5"}, /* 18 */
+ {"DRAMPLL_MDiv_4"}, /* 17 */
+ {"DRAMPLL_MDiv_3"}, /* 16 */
+ {"DRAMPLL_MDiv_2"}, /* 15 */
+ {"DRAMPLL_MDiv_1"}, /* 14 */
+ {"DRAMPLL_MDiv_0"}, /* 13 */
+ {"GB0Sel "}, /* 12 */
+ {"DRAMPLLPU "}, /* 11 */
+ {"DRAMPLL_HIKVCO"}, /* 10 */
+ {"DRAMPLLNP "}, /* 09 */
+ {"DRAMPLL_NDiv_7"}, /* 08 */
+ {"DRAMPLL_NDiv_6"}, /* 07 */
+ {"CPUPadCal "}, /* 06 */
+ {"DRAMPLL_NDiv_5"}, /* 05 */
+ {"DRAMPLL_NDiv_4"}, /* 04 */
+ {"DRAMPLL_NDiv_3"}, /* 03 */
+ {"DRAMPLL_NDiv_2"}, /* 02 */
+ {"DRAMPLL_NDiv_1"}, /* 01 */
+ {"DRAMPLL_NDiv_0"}}; /* 00 */
+
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern flash_info_t flash_info[];
dcache_disable ();
}
-
-int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned int reset_sample_low;
unsigned int reset_sample_high;
+ unsigned int l, l1, l2;
GT_REG_READ(0x3c4, &reset_sample_low);
GT_REG_READ(0x3d4, &reset_sample_high);
printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+ l2 = 0;
+ for (l=0; l<63; l++) {
+ if (show_config_tab[l][0] != 0) {
+ printf("%14s:%1x ", show_config_tab[l],
+ ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
+ l2++;
+ if ((l2 % 4) == 0)
+ printf("\n");
+ } else {
+ l1++;
+ }
+ if (l == 32)
+ reset_sample_low = reset_sample_high;
+ }
+ printf("\n");
+
return(0);
}
U_BOOT_CMD(
- show_cfg, 1, 1, do_show_cfg,
- "show_cfg- Show Marvell strapping register\n",
+ show_config, 1, 1, do_show_config,
+ "show_config - Show Marvell strapping register\n",
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
);
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
+ if (devbusfn == -1)
+ devbusfn = pci_find_device (0x1095, 0x3114, 0);
if (devbusfn != -1) {
status = 0;
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Reset touch-screen controller
*/
#endif /* CONFIG_IDE_RESET */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
out32(GPIO0_OR, val);
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* check board type and setup AP power
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
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+ 0x3a,0x1e,0xf6,0xdf,0x14,0x14,0xe7,0x1e,0x2f,0x93,0x31,0x7c,0x68,0x22,0xdf,0xba,
+ 0xeb,0x0d,0x16,0xfe,0xf3,0x37,0xa5,0x91,0x81,0xe2,0x0d,0x63,0x2c,0x1f,0x52,0xa4,
+ 0xc4,0xab,0x27,0x33,0x3e,0x3c,0xb0,0xef,0xdc,0x9f,0x77,0xda,0xb4,0xfe,0xbb,0x73,
+ 0xa3,0xcf,0xe9,0x85,0x39,0x6a,0x7e,0x78,0xf6,0x11,0x8e,0x58,0xf8,0xb6,0xc6,0xbf,
+ 0x8b,0xf5,0x0f,0x3f,0x0a,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0xfa,0xd4,
+ 0x65,0x66,0x07,0xc9,0xb3,0x03,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x7a,
+ 0xb7,0xcc,0xec,0x50,0xe3,0xd9,0x81,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62,
+ 0xbd,0x5b,0x66,0x76,0xf0,0xcc,0xec,0xf0,0xb1,0x53,0x61,0xb1,0x58,0x2c,0x16,0x8b,
+ 0xc5,0x62,0xb1,0x58,0xff,0xa3,0x22,0xfa,0x7d,0x1c,0x3c,0xfb,0x23,0x02,0x4d,0xbf,
+ 0x5a,0xa9,0x46,0xa0,0xde,0xfb,0xf3,0x84,0xf4,0xb5,0x13,0x11,0x6c,0x88,0xe2,0x98,
+ 0x7f,0x7d,0xb9,0x73,0xdd,0x1b,0x3b,0x1c,0x29,0xc2,0xf0,0x33,0x01,0x00,
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#define FPGA_DEBUG
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
int index;
int i;
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
#endif /* CONFIG_IDE_RESET */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
-#ifdef CONFIG_AUTO_UPDATE_SHOW
-void board_auto_update_show(int au_active)
-{
- if (au_active) {
- printf("\n Dies ist die board-funktion: Updating!!!\n");
- } else {
- printf("\n Dies ist die board-funktion: Updating done!!!\n");
- }
-}
-#endif
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
}
}
#endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
/*
* Enable interrupts in exar duart mcr[3]
*/
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
#undef CONFIG_BOOTARGS
#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#if !defined(CONFIG_MPC885ADS)
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
+#endif
/*
* New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CFG_DIRECT_FLASH_TFTP
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB = $(obj)lib$(VENDOR).a
+
+COBJS := sys_eeprom.o \
+ pixis.o \
+ pq-mds-pib.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
#include <common.h>
#include <command.h>
#include <watchdog.h>
-#include <asm/cache.h>
+#ifdef CONFIG_FSL_PIXIS
+#include <asm/cache.h>
#include "pixis.h"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
);
+#endif /* CONFIG_FSL_PIXIS */
--- /dev/null
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Tony Li <tony.li@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_PQ_MDS_PIB
+
+#include "pq-mds-pib.h"
+
+int pib_init(void)
+{
+ u8 val8;
+ u8 orig_i2c_bus;
+
+ /* Switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0;
+#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
+ /* Assign PIB PMC slot to desired PCI bus */
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(CONFIG_MPC832XEMDS)
+ val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
+#else
+ val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
+#endif
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ eieio();
+
+#if defined(CONFIG_MPC832XEMDS)
+ printf("PCI 32bit bus on PMC2 &PMC3\n");
+#else
+ printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
+#endif
+#endif
+
+#if defined(CONFIG_PQ_MDS_PIB_ATM)
+#if defined(CONFIG_MPC8360EMDS)
+ val8 = 0;
+ i2c_write(0x20, 0x6, 1, &val8, 1);
+ i2c_write(0x20, 0x7, 1, &val8, 1);
+
+ val8 = 0xdf;
+ i2c_write(0x20, 0x2, 1, &val8, 1);
+ val8 = 0xf7;
+ i2c_write(0x20, 0x3, 1, &val8, 1);
+
+ eieio();
+
+ printf("QOC3 ATM card on PMC0\n");
+#elif defined(CONFIG_MPC832XEMDS)
+ val = 0;
+ i2c_write(0x26, 0x7, 1, &val, 1);
+ val = 0xf7;
+ i2c_write(0x26, 0x3, 1, &val, 1);
+
+ val = 0;
+ i2c_write(0x21, 0x6, 1, &val, 1);
+ i2c_write(0x21, 0x7, 1, &val, 1);
+
+ val = 0xdf;
+ i2c_write(0x21, 0x2, 1, &val, 1);
+ val = 0xef;
+ i2c_write(0x21, 0x3, 1, &val, 1);
+
+ eieio();
+
+ printf("QOC3 ATM card on PMC1\n");
+#endif
+#endif
+ /* Reset to original I2C bus */
+ i2c_set_bus_num(orig_i2c_bus);
+ return 0;
+}
+#endif /* CONFIG_PQ_MDS_PIB */
--- /dev/null
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+extern int pib_init(void);
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o mii.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+/*TEXT_BASE = 0xFFC00000*/
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
\ No newline at end of file
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M5235 EVB\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ u32 dramsize, i, dramclk;
+
+ /*
+ * When booting from external Flash, the port-size is less than
+ * the port-size of SDRAM. In this case it is necessary to enable
+ * Data[15:0] on Port Address/Data.
+ */
+ gpio->par_ad =
+ GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+ GPIO_PAR_AD_DATAL;
+
+ /* Initialize PAR to enable SDRAM signals */
+ gpio->par_sdram =
+ GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
+ GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
+
+ dramsize = CFG_SDRAM_SIZE * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
+ dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+
+ /* Initialize DRAM Control Register: DCR */
+ sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
+ SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
+
+ /* Initialize DACR0 */
+ sdram->dacr0 =
+ SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
+ SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+
+ /* Initialize DMR0 */
+ sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+
+ /* Set IP (bit 3) in DACR */
+ sdram->dacr0 |= SDRAMC_DARCn_IP;
+
+ /* Wait 30ns to allow banks to precharge */
+ for (i = 0; i < 5; i++) {
+ asm("nop");
+ }
+
+ /* Write to this block to initiate precharge */
+ *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
+
+ /* Set RE (bit 15) in DACR */
+ sdram->dacr0 |= SDRAMC_DARCn_RE;
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ for (i = 0; i < 0x2000; i++) {
+ asm("nop");
+ }
+
+ /* Finish the configuration by issuing the MRS. */
+ sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+
+ /* Write to the SDRAM Mode Register */
+ *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+ }
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+ } else {
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+ }
+
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+#define STR_ID_KS8721BL "KS8721BL"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ strcpy(info->phy_name,
+ STR_ID_KS8721BL);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ printf(STR_ID_KS8721BL);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
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+ .rel.dtors : { *(.rel.dtors) }
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+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf523x/start.o (.text)
+ cpu/mcf523x/cpu_init.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
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+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
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+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
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+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf523x/start.o (.text)
+ cpu/mcf523x/cpu.o (.text)
+ cpu/mcf523x/cpu_init.o (.text)
+ cpu/mcf523x/interrupts.o (.text)
+ cpu/mcf523x/speed.o (.text)
+ lib_m68k/libm68k.a (.text)
+ common/dlmalloc.o (.text)
+ common/cmd_bootm.o (.text)
+ common/cmd_flash.o (.text)
+ common/cmd_elf.o (.text)
+ common/cmd_mem.o (.text)
+ common/console.o (.text)
+ common/main.o (.text)
+ lib_generic/libgeneric.a (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
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+ {
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+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
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+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
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+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
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+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
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+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf523x/start.o (.text)
+ cpu/mcf523x/cpu_init.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/immap.h>
+
+
+/* Prototypes */
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+int checkboard (void) {
+ ulong val;
+ uchar val8;
+
+ puts ("Board: ");
+ puts("Freescale M5249EVB");
+ val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+ printf(" (Switch=%1X)\n", val8);
+
+ /*
+ * Set LED on
+ */
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
+
+ return 0;
+};
+
+
+long int initdram (int board_type) {
+ unsigned long junk = 0xa5a59696;
+
+ /*
+ * Note:
+ * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+ */
+
+#ifdef CFG_FAST_CLK
+ /*
+ * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CFG_PLL_BYPASS
+ /*
+ * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+ /*
+ * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+ /*
+ * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+ * PM=1 (continuous page mode)
+ */
+
+ /* RE=0 (keep auto-refresh disabled while setting up registers) */
+ mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+ /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+ mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+ /** Precharge sequence **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+ *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+ udelay(0x10); /* Allow several Precharge cycles */
+
+ /** Refresh Sequence **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+ udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+ /** Mode Register initialization **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf52x2/start.o (.text)
+ lib_m68k/traps.o (.text)
+ cpu/mcf52x2/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5253 EVBE\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ int i;
+
+ /*
+ * Check to see if the SDRAM has already been initialized
+ * by a run control tool
+ */
+ if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+ u32 RC, dramsize;
+
+ RC = (CFG_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* Initialize DRAM Control Register: DCR */
+ mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+
+ mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+
+ /* Initialize DMR0 */
+ dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
+ mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
+
+ mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+
+ /* Write to this block to initiate precharge */
+ *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+
+ /* Set RE bit in DACR */
+ mbar_writeLong(MCFSIM_DACR0,
+ mbar_readLong(MCFSIM_DACR0) | 0x8000);
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ udelay(500);
+
+ /* Finish the configuration by issuing the MRS */
+ mbar_writeLong(MCFSIM_DACR0,
+ mbar_readLong(MCFSIM_DACR0) | 0x0040);
+
+ *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ }
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+ return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+ volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+ long period;
+ /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
+ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
+ {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
+ {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
+ {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
+ {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
+ };
+
+ if (idereset) {
+ ata->cr = 0; /* control reset */
+ udelay(100);
+ } else {
+ mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+ period = 1000000000 / (CFG_CLK / 2); /* period in ns */
+
+ /*ata->ton = CALC_TIMING (180); */
+ ata->t1 = CALC_TIMING(piotms[2][0]);
+ ata->t2w = CALC_TIMING(piotms[2][1]);
+ ata->t2r = CALC_TIMING(piotms[2][1]);
+ ata->ta = CALC_TIMING(piotms[2][8]);
+ ata->trd = CALC_TIMING(piotms[2][7]);
+ ata->t4 = CALC_TIMING(piotms[2][3]);
+ ata->t9 = CALC_TIMING(piotms[2][6]);
+
+ ata->cr = 0x40; /* IORDY enable */
+ udelay(2000);
+ ata->cr |= 0x01; /* IORDY enable */
+ }
+}
+#endif /* CONFIG_CMD_IDE */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf52x2/start.o (.text)
+ lib_m68k/traps.o (.text)
+ cpu/mcf52x2/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o mii.o nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5329 EVB\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CFG_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ sdram->cs0 = (CFG_SDRAM_BASE | i);
+ sdram->cfg1 = CFG_SDRAM_CFG1;
+ sdram->cfg2 = CFG_SDRAM_CFG2;
+
+ /* Issue PALL */
+ sdram->ctrl = CFG_SDRAM_CTRL | 2;
+
+ /* Issue LEMR */
+ sdram->mode = CFG_SDRAM_EMOD;
+ sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+
+ udelay(500);
+
+ /* Issue PALL */
+ sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+
+ /* Perform two refresh cycles */
+ sdram->ctrl = CFG_SDRAM_CTRL | 4;
+ sdram->ctrl = CFG_SDRAM_CTRL | 4;
+
+ sdram->mode = CFG_SDRAM_MODE;
+
+ sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+ } else {
+ gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+ }
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_DP83848VV:
+ strcpy(info->phy_name,
+ STR_ID_DP83848VV);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_DP83848VV:
+ printf(STR_ID_DP83848VV);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE 0x10
+#define CLR_CLE ~SET_CLE
+#define SET_ALE 0x08
+#define CLR_ALE ~SET_ALE
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+
+ switch (cmd) {
+ case NAND_CTL_SETNCE:
+ case NAND_CTL_CLRNCE:
+ break;
+ case NAND_CTL_SETCLE:
+ nand_baseaddr |= SET_CLE;
+ break;
+ case NAND_CTL_CLRCLE:
+ nand_baseaddr &= CLR_CLE;
+ break;
+ case NAND_CTL_SETALE:
+ nand_baseaddr |= SET_ALE;
+ break;
+ case NAND_CTL_CLRALE:
+ nand_baseaddr |= CLR_ALE;
+ break;
+ case NAND_CTL_SETWP:
+ fbcs->csmr2 |= CSMR_WP;
+ break;
+ case NAND_CTL_CLRWP:
+ fbcs->csmr2 &= ~CSMR_WP;
+ break;
+ }
+ this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
+}
+
+static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ *((volatile u8 *)(this->IO_ADDR_W)) = byte;
+}
+
+static u8 nand_read_byte(struct mtd_info *mtdinfo)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ return (u8) (*((volatile u8 *)this->IO_ADDR_R));
+}
+
+static int nand_dev_ready(struct mtd_info *mtdinfo)
+{
+ return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+
+ /* set up pin configuration */
+ gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
+ gpio->pddr_timer |= 0x08;
+ gpio->ppd_timer |= 0x08;
+ gpio->pclrr_timer = 0;
+ gpio->podr_timer = 0;
+
+ nand->chip_delay = 50;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->hwcontrol = nand_hwcontrol;
+ nand->read_byte = nand_read_byte;
+ nand->write_byte = nand_write_byte;
+ nand->dev_ready = nand_dev_ready;
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf532x/start.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o flash.o mii.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/immap.h>
+
+#ifndef CFG_FLASH_CFI
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE 0x00200020
+#define INTEL_WRSETUP 0x00400040
+#define INTEL_CLEAR 0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS 0x00700070
+#define INTEL_READID 0x00900090
+#define INTEL_CFIQRY 0x00980098
+#define INTEL_SUSERASE 0x00B000B0
+#define INTEL_PROTPROG 0x00C000C0
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_WRBLK 0x00e800e8
+#define INTEL_RESET 0x00FF00FF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK 0x00800080
+#define INTEL_ERASESUS 0x00600060
+#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
+
+/* 28F160C3B CFI Data offset - This could vary */
+#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
+#define INTEL_CFI_PART 0x01 /* Product ID */
+#define INTEL_CFI_LOCK 0x02 /* */
+#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
+#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
+#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
+#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
+#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
+#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
+#define INTEL_CFI_CAP 0x28
+#define INTEL_CFI_WRBUF 0x2A
+#define INTEL_CFI_BANK 0x2C /* Number of Bank */
+#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
+#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
+#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
+#define INTEL_CFI_SZ1B 0x30
+#define INTEL_CFI_BLK2A 0x31
+#define INTEL_CFI_BLK2B 0x32
+#define INTEL_CFI_SZ2A 0x33
+#define INTEL_CFI_SZ2B 0x34
+
+#define FLASH_CYCLE1 0x0555
+#define FLASH_CYCLE2 0x0aaa
+
+#define WR_BLOCK 0x20
+
+/* not in the flash.h yet */
+#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
+#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
+#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
+#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
+#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
+#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
+
+#define SYNC __asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int flash_cmd_rd(volatile u16 * addr, int index);
+int write_data(flash_info_t * info, ulong dest, FPW data);
+int write_data_block(flash_info_t * info, ulong src, ulong dest);
+int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
+void inline spin_wheel(void);
+void flash_sync_real_protect(flash_info_t * info);
+uchar intel_sector_protected(flash_info_t * info, ushort sector);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+ int i;
+ ulong size = 0;
+ ulong fbase = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+ switch (i) {
+ case 0:
+ fbase = (ulong) CFG_FLASH0_BASE;
+ break;
+ case 1:
+ fbase = (ulong) CFG_FLASH1_BASE;
+ break;
+ }
+
+ flash_get_size((FPWV *) fbase, &flash_info[i]);
+ flash_get_offsets((ulong) fbase, &flash_info[i]);
+ fbase += flash_info[i].size;
+ size += flash_info[i].size;
+
+ /* get the h/w and s/w protection status in sync */
+ flash_sync_real_protect(&flash_info[i]);
+ }
+
+ /* Protect monitor and environment sectors */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+ return size;
+}
+
+int flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i, j, k;
+ int sectors, bs, banks;
+ ulong start;
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
+ int sect[] = CFG_ATMEL_SECT;
+ int sectsz[] = CFG_ATMEL_SECTSZ;
+
+ info->start[0] = base;
+ for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
+ for (j = 0; j < sect[i]; j++, k++) {
+ info->start[k + 1] = info->start[k] + sectsz[i];
+ info->protect[k] = 0;
+ }
+ }
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ volatile u16 *addr16 = (volatile u16 *)base;
+
+ *addr16 = (FPW) INTEL_RESET; /* restore read mode */
+ *addr16 = (FPW) INTEL_READID;
+
+ banks = addr16[INTEL_CFI_BANK] & 0xff;
+
+ sectors = 0;
+ info->start[0] = base;
+
+ for (k = 0, i = 0; i < banks; i++) {
+ /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
+ * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
+ * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
+ */
+ bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
+ | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
+ 0x100);
+ sectors =
+ (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
+
+ for (j = 0; j < sectors; j++, k++) {
+ info->start[k + 1] = info->start[k] + bs;
+ }
+ }
+
+ *addr16 = (FPW) INTEL_RESET; /* restore read mode */
+ }
+
+ return ERR_OK;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf("INTEL ");
+ break;
+ case FLASH_MAN_ATM:
+ printf("ATMEL ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AT040:
+ printf("AT49BV040A\n");
+ break;
+ case FLASH_28F128J3A:
+ printf("Intel 28F128J3A\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ return;
+ }
+
+ if (info->size > 0x100000) {
+ int remainder;
+
+ printf(" Size: %ld", info->size >> 20);
+
+ remainder = (info->size % 0x100000);
+ if (remainder) {
+ remainder >>= 10;
+ remainder = (int)((float)
+ (((float)remainder / (float)1024) *
+ 10000));
+ printf(".%d ", remainder);
+ }
+
+ printf("MB in %d Sectors\n", info->sector_count);
+ } else
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+ volatile u16 *addr16 = (volatile u16 *)addr;
+ int intel = 0, banks = 0;
+ u16 value;
+ int i;
+
+ addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
+ addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
+ addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
+
+ switch (addr[0] & 0xff) {
+ case (u8) ATM_MANUFACT:
+ info->flash_id = FLASH_MAN_ATM;
+ value = addr[1];
+ break;
+ case (u8) INTEL_MANUFACT:
+ /* Terminate Atmel ID read */
+ addr[0] = (FPWV) 0x00F000F0;
+ /* Write auto select command: read Manufacturer ID */
+ /* Write auto select command sequence and test FLASH answer */
+ *addr16 = (FPW) INTEL_RESET; /* restore read mode */
+ *addr16 = (FPW) INTEL_READID;
+
+ info->flash_id = FLASH_MAN_INTEL;
+ value = (addr16[INTEL_CFI_MFG] << 8);
+ value |= addr16[INTEL_CFI_PART] & 0xff;
+ intel = 1;
+ break;
+ default:
+ printf("Unknown Flash\n");
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+
+ *addr = (FPW) 0x00F000F0;
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ switch (value) {
+ case (u8) ATM_ID_LV040:
+ info->flash_id += FLASH_AT040;
+ break;
+ case (u16) INTEL_ID_28F128J3:
+ info->flash_id += FLASH_28F128J3A;
+ break;
+ case (u16) INTEL_ID_28F64P30T:
+ info->flash_id += FLASH_28F64P30T;
+ break;
+ case (u16) INTEL_ID_28F64P30B:
+ info->flash_id += FLASH_28F64P30B;
+ break;
+ case (u16) INTEL_ID_28F128P30T:
+ info->flash_id += FLASH_28F128P30T;
+ break;
+ case (u16) INTEL_ID_28F128P30B:
+ info->flash_id += FLASH_28F128P30B;
+ break;
+ case (u16) INTEL_ID_28F256P30T:
+ info->flash_id += FLASH_28F256P30T;
+ break;
+ case (u16) INTEL_ID_28F256P30B:
+ info->flash_id += FLASH_28F256P30B;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (intel) {
+ /* Intel spec. under CFI section */
+ u32 sz;
+ int sectors, bs;
+
+ banks = addr16[INTEL_CFI_BANK] & 0xff;
+
+ sectors = sz = 0;
+ for (i = 0; i < banks; i++) {
+ /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
+ * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
+ * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
+ */
+ bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
+ | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
+ 0x100);
+ sectors +=
+ (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
+ sz += (bs * sectors);
+ }
+
+ info->sector_count = sectors;
+ info->size = sz;
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ } else {
+ int sect[] = CFG_ATMEL_SECT;
+ int sectsz[] = CFG_ATMEL_SECTSZ;
+
+ info->sector_count = 0;
+ info->size = 0;
+ for (i = 0; i < CFG_ATMEL_REGION; i++) {
+ info->sector_count += sect[i];
+ info->size += sect[i] * sectsz[i];
+ }
+
+ /* reset ID mode */
+ addr[0] = (FPWV) 0x00F000F0;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ return (info->size);
+}
+
+int flash_cmd_rd(volatile u16 * addr, int index)
+{
+ return (int)addr[index];
+}
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+void flash_sync_real_protect(flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
+ for (i = 0; i < info->sector_count; ++i) {
+ info->protect[i] = intel_sector_protected(info, i);
+ }
+ break;
+ default:
+ /* no h/w protect support */
+ break;
+ }
+}
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+uchar intel_sector_protected(flash_info_t * info, ushort sector)
+{
+ FPWV *addr;
+ FPWV *lock_conf_addr;
+ ulong start;
+ unsigned char ret;
+
+ /*
+ * first, wait for the WSM to be finished. The rationale for
+ * waiting for the WSM to become idle for at most
+ * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+ * because of: (1) erase, (2) program or (3) lock bit
+ * configuration. So we just wait for the longest timeout of
+ * the (1)-(3), i.e. the erase timeout.
+ */
+
+ /* wait at least 35ns (W12) before issuing Read Status Register */
+ /*udelay(1); */
+ addr = (FPWV *) info->start[sector];
+ *addr = (FPW) INTEL_STATUS;
+
+ start = get_timer(0);
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ printf("WSM busy too long, can't get prot status\n");
+ return 1;
+ }
+ }
+
+ /* issue the Read Identifier Codes command */
+ *addr = (FPW) INTEL_READID;
+
+ /* Intel example code uses offset of 4 for 8-bit flash */
+ lock_conf_addr = (FPWV *) info->start[sector];
+ ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+ /* put flash back in read mode */
+ *addr = (FPW) INTEL_RESET;
+
+ return ret;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, last;
+ int rcode = 0, intel = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+
+ if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
+ if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
+ type = (info->flash_id & FLASH_VENDMASK);
+ printf
+ ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+ }
+
+ if (type == FLASH_MAN_INTEL)
+ intel = 1;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+
+ start = get_timer(0);
+ last = start;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ int min = 0;
+
+ printf(".");
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ if (intel) {
+ *addr = (FPW) INTEL_READID;
+ min = addr[INTEL_CFI_TERB] & 0xff;
+ min = 1 << min; /* ms */
+ min = (min / info->sector_count) * 1000;
+
+ /* start erase block */
+ *addr = (FPW) INTEL_CLEAR; /* clear status register */
+ *addr = (FPW) INTEL_ERASE; /* erase setup */
+ *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+ while ((*addr & (FPW) INTEL_FINISHED) !=
+ (FPW) INTEL_FINISHED) {
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
+ *addr = (FPW) INTEL_RESET; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = (FPW) INTEL_RESET; /* resest to read mode */
+ } else {
+ FPWV *base; /* first address in bank */
+ FPWV *atmeladdr;
+
+ flag = disable_interrupts();
+
+ atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
+ base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
+
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ *atmeladdr = (u8) 0x00300030; /* erase sector */
+
+ if (flag)
+ enable_interrupts();
+
+ while ((*atmeladdr & (u8) 0x00800080) !=
+ (u8) 0x00800080) {
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
+ }
+
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ } /* Atmel or Intel */
+ }
+ }
+ printf(" done\n");
+
+ return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ if (info->flash_id == FLASH_UNKNOWN)
+ return 4;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_ATM:
+ {
+ u16 data = 0;
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof(data), left -=
+ sizeof(data) - bytes) {
+
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits
+ */
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left)
+ data += *((uchar *) addr + i);
+ else
+ data += *src++;
+ }
+
+ data = (data >> 8) | (data << 8);
+ res = write_word_atm(info, (FPWV *) addr, data);
+ }
+ return res;
+ } /* case FLASH_MAN_ATM */
+
+ case FLASH_MAN_INTEL:
+ {
+ ulong cp, wp;
+ u16 data;
+ int count, i, l, rc, port_width;
+
+ /* get lower word aligned address */
+ wp = addr;
+ port_width = sizeof(FPW);
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+
+ for (; cnt == 0 && i < port_width; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ if ((rc = write_data(info, wp, data)) != 0)
+ return (rc);
+
+ wp += port_width;
+ }
+
+ if (cnt > WR_BLOCK) {
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= WR_BLOCK) {
+
+ if ((rc =
+ write_data_block(info,
+ (ulong) src,
+ wp)) != 0)
+ return (rc);
+
+ wp += WR_BLOCK;
+ src += WR_BLOCK;
+ cnt -= WR_BLOCK;
+
+ if (count++ > 0x800) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+ }
+
+ /* handle word aligned part */
+ if (cnt < WR_BLOCK) {
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i)
+ data = (data << 8) | *src++;
+
+ if ((rc =
+ write_data(info,
+ (ulong) ((FPWV *) wp),
+ (FPW) (data))) != 0)
+ return (rc);
+
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+ }
+
+ if (cnt == 0)
+ return ERR_OK;
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0;
+ ++i, ++cp) {
+ data = (data << 8) | (*src++);
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return write_data(info, (ulong) ((FPWV *) wp),
+ (FPW) data);
+
+ } /* case FLASH_MAN_INTEL */
+
+ } /* switch */
+
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_data_block(flash_info_t * info, ulong src, ulong dest)
+{
+ FPWV *srcaddr = (FPWV *) src;
+ FPWV *dstaddr = (FPWV *) dest;
+ ulong start;
+ int flag, i;
+
+ /* Check if Flash is (sufficiently) erased */
+ for (i = 0; i < WR_BLOCK; i++)
+ if ((*dstaddr++ & 0xff) != 0xff) {
+ printf("not erased at %08lx (%lx)\n",
+ (ulong) dstaddr, *dstaddr);
+ return (2);
+ }
+
+ dstaddr = (FPWV *) dest;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
+
+ if (flag)
+ enable_interrupts();
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
+ for (i = 0; i < WR_BLOCK; i++)
+ *dstaddr++ = *srcaddr++;
+
+ dstaddr -= 1;
+ *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_data(flash_info_t * info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf("not erased at %08lx (%lx)\n", (ulong) addr,
+ (ulong) * addr);
+ return (2);
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = (int)disable_interrupts();
+
+ *addr = (FPW) INTEL_CLEAR;
+ *addr = (FPW) INTEL_RESET;
+
+ *addr = (FPW) INTEL_WRSETUP; /* write setup */
+ *addr = data;
+
+ if (flag)
+ enable_interrupts();
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) INTEL_SUSERASE; /* suspend mode */
+ *addr = (FPW) INTEL_CLEAR; /* clear status */
+ *addr = (FPW) INTEL_RESET; /* reset */
+ return (1);
+ }
+ }
+
+ *addr = (FPW) INTEL_CLEAR; /* clear status */
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for ATMEL FLASH
+ * A word is 16 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
+{
+ ulong start;
+ int flag, i;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile u16 *)dest) & data) != data) {
+ return (2);
+ }
+
+ base = (FPWV *) (CFG_ATMEL_BASE);
+
+ for (i = 0; i < sizeof(u16); i++) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ /* data polling for D7 */
+ while (res == 0
+ && (*dest & (u8) 0x00800080) !=
+ (data & (u8) 0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dest = (u8) 0x00F000F0; /* reset bank */
+ res = 1;
+ }
+ }
+
+ *dest++ = (u8) 0x00F000F0; /* reset bank */
+ data >>= 8;
+ }
+
+ return (res);
+}
+
+void inline spin_wheel(void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+ int rcode = 0; /* assume success */
+ FPWV *addr; /* address of sector */
+ FPW value;
+
+ addr = (FPWV *) (info->start[sector]);
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
+ *addr = (FPW) INTEL_RESET; /* make sure in read mode */
+ *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
+
+ if (prot)
+ *addr = (FPW) INTEL_PROTECT; /* lock sector */
+ else
+ *addr = (FPW) INTEL_CONFIRM; /* unlock sector */
+
+ /* now see if it really is locked/unlocked as requested */
+ *addr = (FPW) INTEL_READID;
+
+ /* read sector protection at sector address, (A7 .. A0) = 0x02.
+ * D0 = 1 for each device if protected.
+ * If at least one device is protected the sector is marked
+ * protected, but return failure. Mixed protected and
+ * unprotected devices within a sector should never happen.
+ */
+ value = addr[2] & (FPW) INTEL_PROTECT;
+ if (value == 0)
+ info->protect[sector] = 0;
+ else if (value == (FPW) INTEL_PROTECT)
+ info->protect[sector] = 1;
+ else {
+ /* error, mixed protected and unprotected */
+ rcode = 1;
+ info->protect[sector] = 1;
+ }
+ if (info->protect[sector] != prot)
+ rcode = 1; /* failed to protect/unprotect as requested */
+
+ /* reload all protection bits from hardware for now */
+ flash_sync_real_protect(info);
+ break;
+
+ default:
+ /* no hardware protect that we support */
+ info->protect[sector] = prot;
+ break;
+ }
+
+ return rcode;
+}
+#endif
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M54455 EVB\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
+ volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ u32 dramsize, i;
+
+ dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ gpio->mscr_sdram = 0xAA;
+
+ sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+ sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
+
+ sdram->sdcfg1 = CFG_SDRAM_CFG1;
+ sdram->sdcfg2 = CFG_SDRAM_CFG2;
+
+ /* Issue PALL */
+ sdram->sdcr = CFG_SDRAM_CTRL | 2;
+
+ /* Issue LEMR */
+ sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
+ sdram->sdmr = CFG_SDRAM_MODE | 0x300;
+
+ udelay(500);
+
+ /* Issue PALL */
+ sdram->sdcr = CFG_SDRAM_CTRL | 2;
+
+ /* Perform two refresh cycles */
+ sdram->sdcr = CFG_SDRAM_CTRL | 4;
+ sdram->sdcr = CFG_SDRAM_CTRL | 4;
+
+ sdram->sdmr = CFG_SDRAM_MODE | 0x200;
+
+ sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+ udelay(100);
+
+ return (dramsize << 1);
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#if defined(CONFIG_CMD_IDE)
+#include <ata.h>
+
+int ide_preinit(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
+ gpio->par_feci2c |=
+ (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
+ GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
+ gpio->par_ata |=
+ (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+ GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
+ | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+ GPIO_PAR_ATA_IORDY_IORDY);
+ gpio->par_pci |=
+ (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+
+ return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+ volatile atac_t *ata = (atac_t *) MMAP_ATA;
+ long period;
+ /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
+ int piotms[5][9] = {
+ {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
+ {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
+ {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
+ {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
+ {25, 70, 20, 10, 20, 5, 10, 0, 35}
+ }; /* PIO 4 */
+
+ if (idereset) {
+ ata->cr = 0; /* control reset */
+ udelay(10000);
+ } else {
+#define CALC_TIMING(t) (t + period - 1) / period
+ period = 1000000000 / gd->bus_clk; /* period in ns */
+
+ /*ata->ton = CALC_TIMING (180); */
+ ata->t1 = CALC_TIMING(piotms[2][0]);
+ ata->t2w = CALC_TIMING(piotms[2][1]);
+ ata->t2r = CALC_TIMING(piotms[2][1]);
+ ata->ta = CALC_TIMING(piotms[2][8]);
+ ata->trd = CALC_TIMING(piotms[2][7]);
+ ata->t4 = CALC_TIMING(piotms[2][3]);
+ ata->t9 = CALC_TIMING(piotms[2][6]);
+
+ ata->cr = 0x40; /* IORDY enable */
+ udelay(200000);
+ ata->cr |= 0x01; /* IORDY enable */
+ }
+}
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf5445x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+ pci_mcf5445x_init(&hose);
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+ if (setclear) {
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+ if (info->iobase == CFG_FEC0_IOBASE)
+ gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+ else
+ gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+ } else {
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+ if (info->iobase == CFG_FEC0_IOBASE)
+ gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
+ else
+ gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
+ }
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ struct eth_device *dev;
+ int i, miispd;
+ u16 rst = 0;
+
+ dev = eth_get_dev();
+
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
+ for (i = 0; i < FEC_RESET_DELAY; ++i) {
+ udelay(500);
+ miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
+ if ((rst & PHY_BMCR_RESET) == 0)
+ break;
+ }
+ if (i == FEC_RESET_DELAY)
+ printf("Mii reset timeout %d\n", i);
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_DP83848VV:
+ strcpy(info->phy_name,
+ STR_ID_DP83848VV);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_DP83848VV:
+ printf(STR_ID_DP83848VV);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf5445x/start.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
*/
#include <common.h>
+#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
#include <pci.h>
#include <mpc83xx.h>
mpc83xx_pci_init(1, reg, warmboot);
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
p = ft_get_prop(blob, "/memory/reg", &len);
- if (p) {
+ if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#endif
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
}
#endif
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CFG_8313ERDB_BROKEN_PMC
static void resume_from_sleep(void)
{
- DECLARE_GLOBAL_DATA_PTR;
u32 magic = *(u32 *)0;
typedef void (*func_t)(void);
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
resume_from_sleep();
#endif
- puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return msize;
}
#include <miiphy.h>
#include <command.h>
#include <libfdt.h>
-#include <libfdt_env.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
msize = fixed_sdram();
- puts("\n DDR RAM: ");
-
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
}
#if defined(CONFIG_OF_BOARD_SETUP)
-
-/*
- * Prototypes of functions that we use.
- */
-void ft_cpu_setup(void *blob, bd_t *bd);
-
-#ifdef CONFIG_PCI
-void ft_pci_setup(void *blob, bd_t *bd);
-#endif
-
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
{
- int nodeoffset;
- int tmp[2];
-
- nodeoffset = fdt_find_node_by_path(blob, "/memory");
- if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(bd->bi_memstart);
- tmp[1] = cpu_to_be32(bd->bi_memsize);
- fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
+#if defined(CONFIG_OF_FLAT_TREE)
+ u32 *p;
+ int len;
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
}
-
+#endif
ft_cpu_setup(blob, bd);
-
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
-#endif /* CONFIG_OF_BOARD_SETUP */
+#endif
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
return 0;
}
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+ pib_init();
+#endif
+ return 0;
+}
+
int fixed_sdram(void);
long int initdram(int board_type)
msize = fixed_sdram();
- puts("\n DDR RAM: ");
-
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
return 0;
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#endif
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
}
#endif
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
#endif
#include <asm/fsl_i2c.h>
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
- u8 val8, orig_i2c_bus;
u16 reg16;
u32 val32;
u32 dev;
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
PIWAR_IWS_2G;
- /*
- * Assign PIB PMC slot to desired PCI bus
- */
-
- /* Switch temporarily to I2C bus #2 */
- orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- val8 = 0;
- i2c_write(0x23, 0x6, 1, &val8, 1);
- i2c_write(0x23, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x23, 0x2, 1, &val8, 1);
- i2c_write(0x23, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x26, 0x6, 1, &val8, 1);
- val8 = 0x34;
- i2c_write(0x26, 0x7, 1, &val8, 1);
-
- val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
- i2c_write(0x26, 0x2, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x27, 0x6, 1, &val8, 1);
- i2c_write(0x27, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x27, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x27, 0x3, 1, &val8, 1);
- asm("eieio");
-
- /* Reset to original I2C bus */
- i2c_set_bus_num(orig_i2c_bus);
-
/*
* Release PCI RST Output signal
*/
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
- printf("PCI 32bit bus on PMC2 & PMC3\n");
-
/*
* Hose scan.
*/
}
#endif /* CONFIG_PCISLAVE */
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+ int err;
+ int tmp[2];
+
+ nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ if (nodeoffset >= 0) {
+ tmp[0] = cpu_to_be32(hose[0].first_busno);
+ tmp[1] = cpu_to_be32(hose[0].last_busno);
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
+ }
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
#endif
int fixed_sdram(void);
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- puts(" DDR RAM: ");
+
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- puts("\n SDRAM on Local Bus: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
#else
void sdram_init(void)
{
- puts(" SDRAM on Local Bus is NOT available!\n");
}
#endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#endif
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
}
#endif
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
}
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+ int err;
+ int tmp[2];
+
+ nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ if (nodeoffset >= 0) {
+ tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
+ }
+#ifdef CONFIG_MPC83XX_PCI2
+ nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600");
+ if (nodeoffset >= 0) {
+ tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
+ }
+#endif
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
#endif
#ifndef CONFIG_SPD_EEPROM
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
- im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
+ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
ddr_enable_ecc(msize * 1048576);
#endif
- puts(" DDR RAM: ");
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
return rc;
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#endif
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
}
#endif
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#endif
}
-#endif /* CONFIG_PCI */
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+ int err;
+ int tmp[2];
+
+ nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ if (nodeoffset >= 0) {
+ tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
+ }
+#ifdef CONFIG_MPC83XX_PCI2
+ nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ if (nodeoffset >= 0) {
+ tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
+ }
+#endif
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
#endif
}
#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_PCI */
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
return 0;
}
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+ pib_init();
+#endif
+ return 0;
+}
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
* Initialize SDRAM if it is on local bus.
*/
sdram_init();
- puts(" DDR RAM: ");
+
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
volatile lbus83xx_t *lbc = &immap->lbus;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
- puts("\n SDRAM on Local Bus: ");
- print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
#else
void sdram_init(void)
{
- puts("SDRAM on Local Bus is NOT available!\n");
}
#endif
-#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
- && defined(CONFIG_OF_BOARD_SETUP)
-
-/*
- * Prototypes of functions that we use.
- */
-void ft_cpu_setup(void *blob, bd_t *bd);
-
-#ifdef CONFIG_PCI
-void ft_pci_setup(void *blob, bd_t *bd);
-#endif
-
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_LIBFDT)
- int nodeoffset;
- int tmp[2];
-
- nodeoffset = fdt_find_node_by_path(blob, "/memory");
- if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(bd->bi_memstart);
- tmp[1] = cpu_to_be32(bd->bi_memsize);
- fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
- }
-#else
+#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
-
+ ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
- ft_cpu_setup(blob, bd);
}
-#endif /* CONFIG_OF_x */
+#endif
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
#endif
#include <asm/fsl_i2c.h>
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
- u8 val8, orig_i2c_bus;
u16 reg16;
u32 val32;
u32 dev;
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
PIWAR_IWS_2G;
- /*
- * Assign PIB PMC slot to desired PCI bus
- */
-
- /* Switch temporarily to I2C bus #2 */
- orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- val8 = 0;
- i2c_write(0x23, 0x6, 1, &val8, 1);
- i2c_write(0x23, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x23, 0x2, 1, &val8, 1);
- i2c_write(0x23, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x26, 0x6, 1, &val8, 1);
- val8 = 0x34;
- i2c_write(0x26, 0x7, 1, &val8, 1);
-
- val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */
- i2c_write(0x26, 0x2, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x27, 0x6, 1, &val8, 1);
- i2c_write(0x27, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x27, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x27, 0x3, 1, &val8, 1);
- asm("eieio");
-
- /* Reset to original I2C bus */
- i2c_set_bus_num(orig_i2c_bus);
-
/*
* Release PCI RST Output signal
*/
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
- printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
-
/*
* Hose scan.
*/
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
}
}
#elif defined(CONFIG_OF_FLAT_TREE)
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o \
- ../common/pixis.o
+COBJS := $(BOARD).o
SOBJS := init.o
*/
#define entry_start \
- mflr r1 ; \
- bl 0f ;
+ mflr r1 ; \
+ bl 0f ;
#define entry_end \
0: mflr r0 ; \
.long 0
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
- .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
- /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region */
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+ .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ /* contains both PCIE3 MEM & IO space */
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
- .long (CFG_PCIE3_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+ .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
4:
entry_end
#include <common.h>
#include <command.h>
+#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
#include <spd.h>
#include <miiphy.h>
{
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %x\n",&gur->porpllsr);
}
printf ("Board: MPC8544DS\n");
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
+
return 0;
}
}
#endif
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+int first_free_busno=0;
+
+void
+pci_init_board(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+ devdisr, io_sel, host_agent);
+
+ if (io_sel & 1) {
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ printf (" eTSEC1 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ printf (" eTSEC3 is in sgmii mode.\n");
+ }
+
+#ifdef CONFIG_PCIE3
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie3_hose;
+ int pcie_ep = (host_agent == 3);
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE3 connected to ULI as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE3_MEM_BASE,
+ CFG_PCIE3_MEM_PHYS,
+ CFG_PCIE3_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE3_IO_BASE,
+ CFG_PCIE3_IO_PHYS,
+ CFG_PCIE3_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE3_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE3_MEM_BASE2,
+ CFG_PCIE3_MEM_PHYS2,
+ CFG_PCIE3_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCIE3 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ */
+ in_be32(CFG_PCIE3_MEM_BASE);
+ } else {
+ printf (" PCIE3: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 5);
+ int pcie_configured = io_sel & 6;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE1_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE1_MEM_BASE2,
+ CFG_PCIE1_MEM_PHYS2,
+ CFG_PCIE1_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf(" PCIE1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE1: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie2_hose;
+ int pcie_ep = (host_agent == 3);
+ int pcie_configured = io_sel & 4;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE2_MEM_BASE,
+ CFG_PCIE2_MEM_PHYS,
+ CFG_PCIE2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE2_IO_BASE,
+ CFG_PCIE2_IO_PHYS,
+ CFG_PCIE2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE2_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE2_MEM_BASE2,
+ CFG_PCIE2_MEM_PHYS2,
+ CFG_PCIE2_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf (" PCIE2 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE2: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif
+
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+
+ uint pci_agent = (host_agent == 6);
+ uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
+ uint pci_32 = 1;
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ (uint)pci
+ );
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+#ifdef CFG_PCIE3_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE3_MEM_BASE2,
+ CFG_PCIE3_MEM_PHYS2,
+ CFG_PCIE3_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+}
+
+
int last_stage_init(void)
{
return 0;
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#ifdef CONFIG_PCI1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE3
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
+ debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
}
#endif
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../freescale/common)
-endif
-
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o sys_eeprom.o \
- ../freescale/common/pixis.o
+COBJS := $(BOARD).o
SOBJS := init.o
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif
-#include "../freescale/common/pixis.h"
+#include "../common/pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((unsigned *) CFG_PCI1_MEM_BASE
- + CFG_PCI1_MEM_SIZE - 0x1000000);
+ in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
+ + CFG_PCI1_MEM_SIZE - 0x1000000)));
} else {
puts("PCI-EXPRESS 1: Disabled\n");
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#ifdef CONFIG_PCI1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCI2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+ debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
}
#endif
.text :
{
cpu/mpc86xx/start.o (.text)
- board/mpc8641hpcn/init.o (.bootpg)
+ board/freescale/mpc8641hpcn/init.o (.bootpg)
cpu/mpc86xx/traps.o (.text)
cpu/mpc86xx/interrupts.o (.text)
cpu/mpc86xx/cpu_init.o (.text)
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
}
#endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
*/
#include <common.h>
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
+#include <asm/immap.h>
int checkboard (void) {
puts ("Board: iDMR\n");
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ } else {
+ }
+
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+#define STR_ID_KS8721BL "KS8721BL"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ strcpy(info->phy_name,
+ STR_ID_KS8721BL);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ printf(STR_ID_KS8721BL);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+int mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
+#include <libfdt.h>
#define SDRAM_DDR 0
#if 1
}
#endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
#include <common.h>
#include <clps7111.h>
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* Activate LED flasher */
IO_LEDFLSH = 0x40;
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o sdram.o
+COBJS = $(BOARD).o kbd.o sdram.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <i2c.h>
+#include <command.h>
+#include <post.h>
+#include <serial.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h> /* for strdup */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+/*--------------------- Local macros and constants --------------------*/
+#define _NOT_USED_ 0xFFFFFFFF
+
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define KEYBD_CMD_READ_KEYS 0x01
+#define KEYBD_CMD_READ_VERSION 0x02
+#define KEYBD_CMD_READ_STATUS 0x03
+#define KEYBD_CMD_RESET_ERRORS 0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK 0x3F
+#define KEYBD_STATUS_H_RESET 0x20
+#define KEYBD_STATUS_BROWNOUT 0x10
+#define KEYBD_STATUS_WD_RESET 0x08
+#define KEYBD_STATUS_OVERLOAD 0x04
+#define KEYBD_STATUS_ILLEGAL_WR 0x02
+#define KEYBD_STATUS_ILLEGAL_RD 0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN 2 /* version information */
+
+/*
+ * This is different from the "old" lwmon dsPIC kbd controller
+ * implementation. Now the controller still answers with 9 bytes,
+ * but the last 3 bytes are always "0x06 0x07 0x08". So we just
+ * set the length to compare to 6 instead of 9.
+ */
+#define KEYBD_DATALEN 6 /* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function: int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: This function is the board_postclk_init() method implementation
+Z* for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+ kbd_init();
+
+ return (0);
+}
+
+static void kbd_init (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar tmp_data[KEYBD_DATALEN];
+ uchar val, errcd;
+ int i;
+
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ gd->kbd_status = 0;
+
+ /* Forced by PIC. Delays <= 175us loose */
+ udelay(1000);
+
+ /* Read initial keyboard error code */
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &errcd, 1);
+ /* clear unused bits */
+ errcd &= KEYBD_STATUS_MASK;
+ /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+ errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+ if (errcd) {
+ gd->kbd_status |= errcd << 8;
+ }
+ /* Reset error code and verify */
+ val = KEYBD_CMD_RESET_ERRORS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ udelay(1000); /* delay NEEDED by keyboard PIC !!! */
+
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &val, 1);
+
+ val &= KEYBD_STATUS_MASK; /* clear unused bits */
+ if (val) { /* permanent error, report it */
+ gd->kbd_status |= val;
+ return;
+ }
+
+ /*
+ * Read current keyboard state.
+ *
+ * After the error reset it may take some time before the
+ * keyboard PIC picks up a valid keyboard scan - the total
+ * scan time is approx. 1.6 ms (information by Martin Rajek,
+ * 28 Sep 2002). We read a couple of times for the keyboard
+ * to stabilize, using a big enough delay.
+ * 10 times should be enough. If the data is still changing,
+ * we use what we get :-(
+ */
+
+ memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
+ for (i=0; i<10; ++i) {
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+ /* consistent state, done */
+ break;
+ }
+ /* remeber last state, delay, and retry */
+ memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+ udelay (5000);
+ }
+}
+
+/***********************************************************************
+F* Function: int misc_init_r (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned, even in the case of a keyboard
+P* error.
+ *
+Z* Intention: This function is the misc_init_r() method implementation
+Z* for the lwmon board.
+Z* The keyboard controller is initialized and the result
+Z* of a read copied to the environment variable "keybd".
+Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z* this key, and if found display to the LCD will be enabled.
+Z* The keys in "keybd" are checked against the magic
+Z* keycommands defined in the environment.
+Z* See also key_match().
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r_kbd (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar kbd_init_status = gd->kbd_status >> 8;
+ uchar kbd_status = gd->kbd_status;
+ uchar val;
+ char *str;
+ int i;
+
+ if (kbd_init_status) {
+ printf ("KEYBD: Error %02X\n", kbd_init_status);
+ }
+ if (kbd_status) { /* permanent error, report it */
+ printf ("*** Keyboard error code %02X ***\n", kbd_status);
+ sprintf (keybd_env, "%02X", kbd_status);
+ setenv ("keybd", keybd_env);
+ return 0;
+ }
+
+ /*
+ * Now we know that we have a working keyboard, so disable
+ * all output to the LCD except when a key press is detected.
+ */
+
+ if ((console_assign (stdout, "serial") < 0) ||
+ (console_assign (stderr, "serial") < 0)) {
+ printf ("Can't assign serial port as output device\n");
+ }
+
+ /* Read Version */
+ val = KEYBD_CMD_READ_VERSION;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+ printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+ /* Read current keyboard state */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ }
+ setenv ("keybd", keybd_env);
+
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+ if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
+ if ((console_assign (stdout, "lcd") < 0) ||
+ (console_assign (stderr, "lcd") < 0)) {
+ printf ("Can't assign LCD display as output device\n");
+ }
+ }
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
+ setenv ("preboot", str); /* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+ if (str != NULL) {
+ free (str);
+ }
+ return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+ uchar compare[KEYBD_DATALEN-1];
+ char *nxt;
+ int i;
+
+ /* Don't include modifier byte */
+ memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+ uchar c;
+ int k;
+
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+ if (str == (uchar *)nxt) { /* invalid character */
+ break;
+ }
+
+ /*
+ * Check if this key matches the input.
+ * Set matches to zero, so they match only once
+ * and we can find duplicates or extra keys
+ */
+ for (k = 0; k < sizeof(compare); ++k) {
+ if (compare[k] == '\0') /* only non-zero entries */
+ continue;
+ if (c == compare[k]) { /* found matching key */
+ compare[k] = '\0';
+ break;
+ }
+ }
+ if (k == sizeof(compare)) {
+ return -1; /* unmatched key */
+ }
+ }
+
+ /*
+ * A full match leaves no keys in the `compare' array,
+ */
+ for (i = 0; i < sizeof(compare); ++i) {
+ if (compare[i])
+ {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/***********************************************************************
+F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters: uchar *kbd_data
+P* - The keys to match against our magic definitions
+P*
+P* Returnvalue: uchar *
+P* - != NULL: Pointer to the corresponding command(s)
+P* NULL: No magic is about to happen
+ *
+Z* Intention: Check if pressed key(s) match magic sequence,
+Z* and return the command string associated with that key(s).
+Z*
+Z* If no key press was decoded, NULL is returned.
+Z*
+Z* Note: the first character of the argument will be
+Z* overwritten with the "magic charcter code" of the
+Z* decoded key(s), or '\0'.
+Z*
+Z* Note: the string points to static environment data
+Z* and must be saved before you call any function that
+Z* modifies the environment.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ uchar *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can pe appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ debug ("### Check magic \"%s\"\n", magic);
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+ cmd = getenv (cmd_name);
+ debug ("### Set PREBOOT to $(%s): \"%s\"\n",
+ cmd_name, cmd ? cmd : "<<NULL>>");
+ *kbd_data = *suffix;
+ return ((uchar *)cmd);
+ }
+ }
+ debug ("### Delete PREBOOT\n");
+ *kbd_data = '\0';
+ return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+/***********************************************************************
+F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char *argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: Implement the "kbd" command.
+Z* The keyboard status is read. The result is printed on
+Z* the console and written into the "keybd" environment
+Z* variable.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar val;
+ int i;
+
+#if 0 /* Done in kbd_init */
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ puts ("Keys:");
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ printf (" %02x", kbd_data[i]);
+ }
+ putc ('\n');
+ setenv ("keybd", keybd_env);
+ return 0;
+}
+
+U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "kbd - read keyboard status\n",
+ NULL
+);
+
+/*----------------------------- Utilities -----------------------------*/
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar val;
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
*/
#include <common.h>
+#include <command.h>
#include <ppc440.h>
#include <asm/processor.h>
#include <asm/gpio.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-ulong flash_get_size (ulong base, int banknum);
+ulong flash_get_size(ulong base, int banknum);
+int misc_init_r_kbd(void);
int board_early_init_f(void)
{
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
- mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
- mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
+ mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
+ mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
- mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
+ mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
+ mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
- mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
+ mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
/* Trace Pins are disabled. SDR0_PFC0 Register */
mtsdr(SDR0_PFC0, 0x0);
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
- &flash_info[0]);
+ &flash_info[1]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
+ &flash_info[1]);
/*
* USB suff...
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
- /* Lime memory clock adjusted to 133MHz */
- out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+ /* Lime memory clock adjusted to 100MHz */
+ out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
/* Wait untill time expired. Because of requirements in lime manual */
udelay(300);
/* Write lime controller memory parameters */
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+ /*
+ * Init display controller
+ */
+ /* Setup dot clock (internal PLL, division rate 1/16) */
+ out_be32((void *)0xc1fd0100, 0x00000f00);
+
+ /* Lime L0 init (16 bpp, 640x480) */
+ out_be32((void *)0xc1fd0020, 0x801401df);
+ out_be32((void *)0xc1fd0024, 0x0);
+ out_be32((void *)0xc1fd0028, 0x0);
+ out_be32((void *)0xc1fd002c, 0x0);
+ out_be32((void *)0xc1fd0110, 0x0);
+ out_be32((void *)0xc1fd0114, 0x0);
+ out_be32((void *)0xc1fd0118, 0x01df0280);
+
+ /* Display timing init */
+ out_be32((void *)0xc1fd0004, 0x031f0000);
+ out_be32((void *)0xc1fd0008, 0x027f027f);
+ out_be32((void *)0xc1fd000c, 0x015f028f);
+ out_be32((void *)0xc1fd0010, 0x020c0000);
+ out_be32((void *)0xc1fd0014, 0x01df01ea);
+ out_be32((void *)0xc1fd0018, 0x0);
+ out_be32((void *)0xc1fd001c, 0x01e00280);
+
+#if 1
+ /*
+ * Clear framebuffer using Lime's drawing engine
+ * (draw blue rect. with white border around it)
+ */
+ /* Setup mode and fbbase, xres, fg, bg */
+ out_be32((void *)0xc1ff0420, 0x8300);
+ out_be32((void *)0xc1ff0440, 0x0000);
+ out_be32((void *)0xc1ff0444, 0x0280);
+ out_be32((void *)0xc1ff0480, 0x7fff);
+ out_be32((void *)0xc1ff0484, 0x0000);
+ /* Reset clipping rectangle */
+ out_be32((void *)0xc1ff0454, 0x0000);
+ out_be32((void *)0xc1ff0458, 0x0280);
+ out_be32((void *)0xc1ff045c, 0x0000);
+ out_be32((void *)0xc1ff0460, 0x01e0);
+ /* Draw white rect. */
+ out_be32((void *)0xc1ff04a0, 0x09410000);
+ out_be32((void *)0xc1ff04a0, 0x00000000);
+ out_be32((void *)0xc1ff04a0, 0x01e00280);
+ udelay(2000);
+ /* Draw blue rect. */
+ out_be32((void *)0xc1ff0480, 0x001f);
+ out_be32((void *)0xc1ff04a0, 0x09410000);
+ out_be32((void *)0xc1ff04a0, 0x00010001);
+ out_be32((void *)0xc1ff04a0, 0x01de027e);
+#endif
+ /* Display enable, L0 layer */
+ out_be32((void *)0xc1fd0100, 0x80010f00);
+
+ /* TFT-LCD enable - PWM duty, lamp on */
+ out_be32((void *)0xc4000024, 0x64);
+ out_be32((void *)0xc4000020, 0x701);
+
+ /*
+ * Init matrix keyboard
+ */
+ misc_init_r_kbd();
+
return 0;
}
val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
gpio_write_bit(CFG_GPIO_WATCHDOG, val);
}
+
+int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc < 2) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if ((strcmp(argv[1], "on") == 0)) {
+ gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1);
+ } else if ((strcmp(argv[1], "off") == 0)) {
+ gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0);
+ } else {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ eepromwp, 2, 0, do_eeprom_wp,
+ "eepromwp- eeprom write protect off/on\n",
+ "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n"
+);
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
-#ifdef CONFIG_ADD_RAM_INFO
static u32 is_ecc_enabled(void)
{
u32 val;
val = DDR0_03_CASLAT_DECODE(val);
printf(", CL%d)", val);
}
-#endif
static int wait_for_dlllock(void)
{
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
-#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/*
* Some boards (like lwmon5) need to preserve the memory
* content upon ECC generation (for the log-buffer).
current_address = start_address;
while (current_address < end_address) {
+ /*
+ * TODO: Th following sequence doesn't work correctly.
+ * Just invalidating and flushing the cache doesn't
+ * seem to trigger the re-write of the memory.
+ */
ppcDcbi(current_address);
ppcDcbf(current_address);
current_address += CFG_CACHELINE_SIZE;
}
#endif
-static __inline__ u32 get_mcsr(void)
-{
- u32 val;
-
- asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
- return val;
-}
-
-static __inline__ void set_mcsr(u32 val)
-{
- asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
************************************************************************/
long int initdram (int board_type)
{
- u32 val;
-
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/* CL=3 */
mtsdram(DDR0_02, 0x00000000);
* Perform data eye search if requested.
*/
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- val = get_mcsr();
- set_mcsr(val);
#endif
#ifdef CONFIG_DDR_ECC
program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#endif
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
return (CFG_MBYTES_SDRAM << 20);
}
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o
+COBJS = $(BOARD).o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
*/
#include <common.h>
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
+#include <asm/immap.h>
int checkboard (void) {
puts ("Board: Freescale M5271EVB\n");
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ } else {
+ }
+
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+#define STR_ID_KS8721BL "KS8721BL"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ strcpy(info->phy_name,
+ STR_ID_KS8721BL);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ printf(STR_ID_KS8721BL);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
*/
#include <common.h>
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
+#include <asm/immap.h>
int checkboard (void) {
puts ("Board: ");
- puts("MOTOROLA MCF5272C3 EVB\n");
+ puts ("Freescale MCF5272C3 EVB\n");
return 0;
};
long int initdram (int board_type) {
- volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR);
+ volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+ } else {
+ }
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_AMD79C874VC "AMD79C874VC"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ strcpy(info->phy_name,
+ STR_ID_AMD79C874VC);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ printf(STR_ID_AMD79C874VC);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
# MA 02111-1307 USA
#
-TEXT_BASE = 0x20000
+TEXT_BASE = 0xFFE00000
+++ /dev/null
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define PHYS_FLASH_1 CFG_FLASH_BASE
-#define FLASH_BANK_SIZE 0x200000
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (AMD_MANUFACT & FLASH_VENDMASK):
- printf ("AMD: ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (AMD_ID_PL160CB & FLASH_TYPEMASK):
- printf ("AM29PL160CB (16Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-
- Done:
- return;
-}
-
-
-unsigned long flash_init (void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id =
- (AMD_MANUFACT & FLASH_VENDMASK) |
- (AMD_ID_PL160CB & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
- if (i == 0)
- flashbase = PHYS_FLASH_1;
- else
- panic ("configured to many flash banks!\n");
-
- for (j = 0; j < flash_info[i].sector_count; j++) {
- if (j == 0) {
- /* 1st is 16 KiB */
- flash_info[i].start[j] = flashbase;
- }
- if ((j >= 1) && (j <= 2)) {
- /* 2nd and 3rd are 8 KiB */
- flash_info[i].start[j] =
- flashbase + 0x4000 + 0x2000 * (j - 1);
- }
- if (j == 3) {
- /* 4th is 32 KiB */
- flash_info[i].start[j] = flashbase + 0x8000;
- }
- if ((j >= 4) && (j <= 34)) {
- /* rest is 256 KiB */
- flash_info[i].start[j] =
- flashbase + 0x10000 + 0x10000 * (j -
- 4);
- }
- }
- size += flash_info[i].size;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE + 0xffff, &flash_info[0]);
-
- return size;
-}
-
-
-#define CMD_READ_ARRAY 0x00F0
-#define CMD_UNLOCK1 0x00AA
-#define CMD_UNLOCK2 0x0055
-#define CMD_ERASE_SETUP 0x0080
-#define CMD_ERASE_CONFIRM 0x0030
-#define CMD_PROGRAM 0x00A0
-#define CMD_UNLOCK_BYPASS 0x0020
-
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
-
-#define BIT_ERASE_DONE 0x0080
-#define BIT_RDY_MASK 0x0080
-#define BIT_PROGRAM_ERROR 0x0020
-#define BIT_TIMEOUT 0x80000000 /* our flag */
-
-#define READY 1
-#define ERR 2
-#define TMO 4
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- ulong result;
- int iflag, cflag, prot, sect;
- int rc = ERR_OK;
- int chip1;
-
- /* first look for protection bits */
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (AMD_MANUFACT & FLASH_VENDMASK)) {
- return ERR_UNKNOWN_FLASH_VENDOR;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot)
- return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- cflag = icache_status ();
- icache_disable ();
- iflag = disable_interrupts ();
-
- printf ("\n");
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- set_timer (0);
-
- if (info->protect[sect] == 0) { /* not protected */
- volatile u16 *addr =
- (volatile u16 *) (info->start[sect]);
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- *addr = CMD_ERASE_CONFIRM;
-
- /* wait until flash is ready */
- chip1 = 0;
-
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
- chip1 = TMO;
- break;
- }
-
- if (!chip1
- && (result & 0xFFFF) & BIT_ERASE_DONE)
- chip1 = READY;
-
- } while (!chip1);
-
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
- if (chip1 == ERR) {
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if (chip1 == TMO) {
- rc = ERR_TIMOUT;
- goto outahere;
- }
-
- printf ("ok.\n");
- } else { /* it was protected */
-
- printf ("protected!\n");
- }
- }
-
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- outahere:
- /* allow flash to settle - wait 10 ms */
- udelay (10000);
-
- if (iflag)
- enable_interrupts ();
-
- if (cflag)
- icache_enable ();
-
- return rc;
-}
-
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile u16 *addr = (volatile u16 *) dest;
- ulong result;
- int rc = ERR_OK;
- int cflag, iflag;
- int chip1;
-
- /*
- * Check if Flash is (sufficiently) erased
- */
- result = *addr;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
-
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- cflag = icache_status ();
- icache_disable ();
- iflag = disable_interrupts ();
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_PROGRAM;
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- set_timer (0);
-
- /* wait until flash is ready */
- chip1 = 0;
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
- chip1 = ERR | TMO;
- break;
- }
- if (!chip1 && ((result & 0x80) == (data & 0x80)))
- chip1 = READY;
-
- } while (!chip1);
-
- *addr = CMD_READ_ARRAY;
-
- if (chip1 == ERR || *addr != data)
- rc = ERR_PROG_ERROR;
-
- if (iflag)
- enable_interrupts ();
-
- if (cflag)
- icache_enable ();
-
- return rc;
-}
-
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp, data;
- int rc;
-
- if (addr & 1) {
- printf ("unaligned destination not supported\n");
- return ERR_ALIGN;
- }
-
-#if 0
- if (cnt & 1) {
- printf ("odd transfer sizes not supported\n");
- return ERR_ALIGN;
- }
-#endif
-
- wp = addr;
-
- if (addr & 1) {
- data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
- src);
- if ((rc = write_word (info, wp - 1, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- while (cnt >= 2) {
- data = *((volatile u16 *) src);
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 2;
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 1) {
- data = (*((volatile u8 *) src) << 8) |
- *((volatile u8 *) (wp + 1));
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- return ERR_OK;
-}
*/
#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
- puts ("MOTOROLA M5272EVB Evaluation Board\n");
+ puts ("Board: Freescale M5282EVB Evaluation Board\n");
return 0;
}
long int initdram (int board_type)
{
- return 0x1000000;
+ u32 dramsize, i, dramclk;
+
+ dramsize = CFG_SDRAM_SIZE * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
+ {
+ dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+
+ /* Initialize DRAM Control Register: DCR */
+ MCFSDRAMC_DCR = (0
+ | MCFSDRAMC_DCR_RTIM_6
+ | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
+
+ /* Initialize DACR0 */
+ MCFSDRAMC_DACR0 = (0
+ | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
+ | MCFSDRAMC_DACR_CASL(1)
+ | MCFSDRAMC_DACR_CBM(3)
+ | MCFSDRAMC_DACR_PS_32);
+
+ /* Initialize DMR0 */
+ MCFSDRAMC_DMR0 = (0
+ | ((dramsize - 1) & 0xFFFC0000)
+ | MCFSDRAMC_DMR_V);
+
+ /* Set IP (bit 3) in DACR */
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+
+ /* Wait 30ns to allow banks to precharge */
+ for (i = 0; i < 5; i++) {
+ asm ("nop");
+ }
+
+ /* Write to this block to initiate precharge */
+ *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+
+ /* Set RE (bit 15) in DACR */
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ for (i = 0; i < 2000; i++) {
+ asm(" nop");
+ }
+
+ /* Finish the configuration by issuing the IMRS. */
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+
+ /* Write to the SDRAM Mode Register */
+ *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+ }
}
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ MCFGPIO_PASPAR |= 0x0F00;
+ MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+ } else {
+ MCFGPIO_PASPAR &= 0xF0FF;
+ MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
+ }
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_AMD79C874VC "AMD79C874VC"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ strcpy(info->phy_name,
+ STR_ID_AMD79C874VC);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_AMD79C874VC:
+ printf(STR_ID_AMD79C874VC);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
#include <common.h>
#include <mpc5xxx.h>
#include <miiphy.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
#if defined(CONFIG_STATUS_LED)
#include <status_led.h>
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_STATUS_LED)
#undef DEBUG
+DECLARE_GLOBAL_DATA_PTR;
+
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
void after_reloc (ulong dest_addr)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/*
* Jump to the main U-Boot board init code
*/
#include <asm/processor.h>
#include <tsi108.h>
+DECLARE_GLOBAL_DATA_PTR;
+
extern void mpicInit (int verbose);
/*
int board_early_init_f (void)
{
- DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
{
u32 *p;
int len;
- ulong data;
p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
bcsr[9] &= ~(0x01);
}
+
+void enable_8568mds_qe_mdio()
+{
+ u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[7] |= 0x01;
+}
void enable_8568mds_duart(void);
void enable_8568mds_flash_write(void);
void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
#endif /* __BCSR_H_ */
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 2: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM
+ * TLBe 2: 1G Non-cacheable, guarded
+ * 0x80000000 512M PCI1 MEM
+ * 0xa0000000 512M PCIe MEM
*/
.long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCIe Mem
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 4: Reserved for future usage
- */
-
- /*
- * TLBe 5: 64M Non-cacheable, guarded
+ * TLBe 3: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 8M PCI1 IO
* 0xe280_0000 8M PCIe IO
*/
- .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 6: 64M Cacheable, non-guarded
+ * TLBe 4: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 7: 256K Non-cacheable, guarded
+ * TLBe 5: 256K Non-cacheable, guarded
* 0xf8000000 32K BCSR
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
- .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
* LAW(Local Access Window) configuration:
*
*0) 0x0000_0000 0x7fff_ffff DDR 2G
- *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB
- *2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB
- *5) 0xc000_0000 0xdfff_ffff SRIO 256MB
+ *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
+ *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
*-) 0xe000_0000 0xe00f_ffff CCSR 1M
*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
- *4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M
+ *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
+#include <i2c.h>
+#include <ioports.h>
#include "bcsr.h"
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {4, 10, 1, 0, 2}, /* TxD0 */
+ {4, 9, 1, 0, 2}, /* TxD1 */
+ {4, 8, 1, 0, 2}, /* TxD2 */
+ {4, 7, 1, 0, 2}, /* TxD3 */
+ {4, 23, 1, 0, 2}, /* TxD4 */
+ {4, 22, 1, 0, 2}, /* TxD5 */
+ {4, 21, 1, 0, 2}, /* TxD6 */
+ {4, 20, 1, 0, 2}, /* TxD7 */
+ {4, 15, 2, 0, 2}, /* RxD0 */
+ {4, 14, 2, 0, 2}, /* RxD1 */
+ {4, 13, 2, 0, 2}, /* RxD2 */
+ {4, 12, 2, 0, 2}, /* RxD3 */
+ {4, 29, 2, 0, 2}, /* RxD4 */
+ {4, 28, 2, 0, 2}, /* RxD5 */
+ {4, 27, 2, 0, 2}, /* RxD6 */
+ {4, 26, 2, 0, 2}, /* RxD7 */
+ {4, 11, 1, 0, 2}, /* TX_EN */
+ {4, 24, 1, 0, 2}, /* TX_ER */
+ {4, 16, 2, 0, 2}, /* RX_DV */
+ {4, 30, 2, 0, 2}, /* RX_ER */
+ {4, 17, 2, 0, 2}, /* RX_CLK */
+ {4, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+
+ /* GETH2 */
+ {5, 10, 1, 0, 2}, /* TxD0 */
+ {5, 9, 1, 0, 2}, /* TxD1 */
+ {5, 8, 1, 0, 2}, /* TxD2 */
+ {5, 7, 1, 0, 2}, /* TxD3 */
+ {5, 23, 1, 0, 2}, /* TxD4 */
+ {5, 22, 1, 0, 2}, /* TxD5 */
+ {5, 21, 1, 0, 2}, /* TxD6 */
+ {5, 20, 1, 0, 2}, /* TxD7 */
+ {5, 15, 2, 0, 2}, /* RxD0 */
+ {5, 14, 2, 0, 2}, /* RxD1 */
+ {5, 13, 2, 0, 2}, /* RxD2 */
+ {5, 12, 2, 0, 2}, /* RxD3 */
+ {5, 29, 2, 0, 2}, /* RxD4 */
+ {5, 28, 2, 0, 2}, /* RxD5 */
+ {5, 27, 2, 0, 3}, /* RxD6 */
+ {5, 26, 2, 0, 2}, /* RxD7 */
+ {5, 11, 1, 0, 2}, /* TX_EN */
+ {5, 24, 1, 0, 2}, /* TX_ER */
+ {5, 16, 2, 0, 2}, /* RX_DV */
+ {5, 30, 2, 0, 2}, /* RX_ER */
+ {5, 17, 2, 0, 2}, /* RX_CLK */
+ {5, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+ {4, 6, 3, 0, 2}, /* MDIO */
+ {4, 5, 1, 0, 2}, /* MDC */
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
enable_8568mds_duart();
enable_8568mds_flash_write();
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+ enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CFG_I2C2_OFFSET
+ /* Enable I2C2_SCL and I2C2_SDA */
+ volatile struct par_io *port_c;
+ port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+ port_c->cpdir2 |= 0x0f000000;
+ port_c->cppar2 &= ~0x0f000000;
+ port_c->cppar2 |= 0x0a000000;
+#endif
return 0;
}
#endif
static struct pci_controller hose[] = {
+ {
#ifndef CONFIG_PCI_PNP
- { config_table: pci_mpc8568mds_config_table,},
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
- {},
+ config_table: pci_mpc8568mds_config_table,
#endif
+ }
};
#endif /* CONFIG_PCI */
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+ u8 val8, orig_i2c_bus;
+ /*
+ * Assign PIB PMC2/3 to PCI bus
+ */
+
+ /*switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0x00;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf9;
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ asm("eieio");
+}
+
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
+ pib_init();
+ pci_mpc85xx_init(hose);
#endif
}
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern void print_vcma9_info(void);
extern int vcma9_cantest(int);
extern int vcma9_nandtest(void);
int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (strcmp(argv[1], "info") == 0)
{
print_vcma9_info();
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ *
+ * Modified 6/6/2007
+ * Added isync
+ * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#if CFG_MAX_FLASH_BANKS != 1
+#error "CFG_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+
+ /* Init: no FLASHes known */
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM,
+ &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ /* Setup offsets */
+ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void) flash_protect (FLAG_PROTECT_SET,
+ FLASH_BASE0_PRELIM,
+ FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+ &flash_info[0]);
+ flash_info[0].size = size_b0;
+
+ return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/*
+ * This implementation assumes that the flash chips are uniform sector
+ * devices. This is true for all likely flash devices on a HCUx.
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ unsigned idx;
+ unsigned long sector_size = info->size / info->sector_count;
+
+ for (idx = 0; idx < info->sector_count; idx += 1) {
+ info->start[idx] = base + (idx * sector_size);
+ }
+}
+
+/*-----------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf ("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf ("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf ("SST ");
+ break;
+ case FLASH_MAN_STM:
+ printf ("ST Micro ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ /* (Reduced table of only parts expected in HCUx boards.) */
+ switch (info->flash_id) {
+ case FLASH_MAN_AMD | FLASH_AM040:
+ printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_MAN_STM | FLASH_AM040:
+ printf ("MM29W040W (512 Kbit, uniform sector size)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *) info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------*/
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ asm("isync");
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ asm("isync");
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ asm("isync");
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+ asm("isync");
+
+ value = addr2[0];
+ asm("isync");
+
+ switch (value) {
+ case (FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (FLASH_WORD_SIZE)STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ printf("Unknown flash manufacturer code: 0x%x at %p\n",
+ value, addr);
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ switch (value) {
+ case (FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* Calculate the sector offsets (Use HCUx Optimized code). */
+ flash_get_offsets(base, info);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address,
+ *(A7 .. A0) = 0x02
+ * D0 = 1 if protected
+ */
+ addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (FLASH_WORD_SIZE *) info->start[0];
+ *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr =
+ (FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors not erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+ printf ("Erasing sector %p\n", addr2); /* CLH */
+
+ if ((info->flash_id & FLASH_VENDMASK) ==
+ FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ /* block erase */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00500050;
+ for (i = 0; i < 50; i++) udelay (1000);
+ } else {
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ /* sector erase */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00300030;
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7 (info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+#if 0
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+ wait_for_DQ7 (info, l_sect);
+
+DONE:
+#endif
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 =
+ (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
--- /dev/null
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BSP
+/*
+ * Command nm_bsp: Netstal Maschinen BSP specific command
+ */
+int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__,
+ flag, argc, argv[0]);
+ printf("Netstal Maschinen BSP specific command. None at the moment.\n");
+ return 0;
+}
+
+U_BOOT_CMD(
+ nm_bsp, 1, 1, nm_bsp,
+ "nm_bsp - Netstal Maschinen BSP specific command. \n",
+ "Help for Netstal Maschinen BSP specific command.\n"
+ );
+#endif
--- /dev/null
+#
+# (C) Copyright 2007 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+vpath hcu_flash.c ../common
+
+# NOBJS : Netstal common objects
+NOBJS = hcu_flash.o
+COBJS = $(BOARD).o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+NOBJS := $(addprefix $(obj),$(NOBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+HCU4 Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+0x70000000
+
+Chip-Select 3: CAN Interface
+----------------------------
+0x7800000
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+Our IO-Bus (slow version)
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+Our IO-Bus (fast, but not yet use)
+
+
+Memory Bank 1 -- SDRAM
+-------------------------------------
+
+0x00000000 - 0x1ffffff # Default 32 MB
--- /dev/null
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: HCU4 boards
+#
+
+TEXT_BASE = 0xFFFa0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
--- /dev/null
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm-ppc/u-boot.h>
+#include "../common/nm_bsp.c"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
+
+#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
+
+#define DO_UGLY_SDRAM_WORKAROUND
+
+enum {
+ /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
+ HW_GENERATION_HCU2 = 0x10,
+ HW_GENERATION_HCU3 = 0x10,
+ HW_GENERATION_HCU4 = 0x20,
+ HW_GENERATION_MCU = 0x08,
+ HW_GENERATION_MCU20 = 0x0a,
+ HW_GENERATION_MCU25 = 0x09,
+};
+
+void hcu_led_set(u32 value);
+long int spd_sdram(int(read_spd)(uint addr));
+
+#ifdef CONFIG_SPD_EEPROM
+#define DEBUG
+#endif
+
+#if defined(DEBUG)
+void show_sdram_registers(void);
+#endif
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+#define CPC0_CR0 0xb1 /* Chip control register 0 */
+#define CPC0_CR1 0xb2 /* Chip control register 1 */
+/* Attention: If you want 1 microsecs times from the external oscillator
+ * use 0x00804051. But this causes problems with u-boot and linux!
+ */
+#define CPC0_CR1_VALUE 0x00004051
+#define CPC0_ECR 0xaa /* Edge condition register */
+#define EBC0_CFG 0x23 /* External Peripheral Control Register */
+#define CPC0_EIRR 0xb6 /* External Interrupt Register */
+
+
+int board_early_init_f (void)
+{
+ /*-------------------------------------------------------------------+
+ | Interrupt controller setup for the HCU4 board.
+ | Note: IRQ 0-15 405GP internally generated; high; level sensitive
+ | IRQ 16 405GP internally generated; low; level sensitive
+ | IRQ 17-24 RESERVED/UNUSED
+ | IRQ 31 (EXT IRQ 6) (unused)
+ +-------------------------------------------------------------------*/
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (uicer, 0x00000000); /* disable all ints */
+ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
+ mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
+ mtdcr (uictr, 0x10000000); /* set int trigger levels */
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
+ mtdcr(CPC0_ECR, 0x60606000);
+ mtdcr(CPC0_EIRR, 0x7c000000);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+ return board_early_init_f ();
+}
+#endif
+
+int checkboard (void)
+{
+ unsigned int j;
+ u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
+ u16 generation = *boardVersReg & 0xf0;
+ u16 index = *boardVersReg & 0x0f;
+
+ /* Force /RTS to active. The board it not wired quite
+ correctly to use cts/rtc flow control, so just force the
+ /RST active and forget about it. */
+ writeb (readb (0xef600404) | 0x03, 0xef600404);
+ printf ("\nNetstal Maschinen AG ");
+ if (generation == HW_GENERATION_HCU3)
+ printf ("HCU3: index %d\n\n", index);
+ else if (generation == HW_GENERATION_HCU4)
+ printf ("HCU4: index %d\n\n", index);
+ hcu_led_set(0);
+ for (j = 0; j < 7; j++) {
+ hcu_led_set(1 << j);
+ udelay(50 * 1000);
+ }
+
+ return 0;
+}
+
+u32 hcu_led_get(void)
+{
+ return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
+}
+
+/*---------------------------------------------------------------------------+
+ * hcu_led_set value to be placed into the LEDs (max 6 bit)
+ *---------------------------------------------------------------------------*/
+void hcu_led_set(u32 value)
+{
+ u32 tmp = ~value;
+ u32 *ledReg;
+
+ tmp = (tmp << 23) | 0x7FFFFF;
+ ledReg = (u32 *)GPIO0_OR;
+ *ledReg = tmp;
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram or initdram
+ * used for HCUx
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+#if defined(DEBUG)
+void show_sdram_registers(void)
+{
+ u32 value;
+
+ printf ("SDRAM Controller Registers --\n");
+ mfsdram(mem_mcopt1, value);
+ printf (" SDRAM0_CFG : 0x%08x\n", value);
+ mfsdram(mem_status, value);
+ printf (" SDRAM0_STATUS: 0x%08x\n", value);
+ mfsdram(mem_mb0cf, value);
+ printf (" SDRAM0_B0CR : 0x%08x\n", value);
+ mfsdram(mem_mb1cf, value);
+ printf (" SDRAM0_B1CR : 0x%08x\n", value);
+ mfsdram(mem_sdtr1, value);
+ printf (" SDRAM0_TR : 0x%08x\n", value);
+ mfsdram(mem_rtr, value);
+ printf (" SDRAM0_RTR : 0x%08x\n", value);
+}
+#endif
+
+/*
+ * this is even after checkboard. It returns the size of the SDRAM
+ * that we have installed. This function is called by board_init_f
+ * in lib_ppc/board.c to initialize the memory and return what I
+ * found. These are default value, which will be overridden later.
+ */
+
+long int fixed_hcu4_sdram (int board_type)
+{
+#ifdef DEBUG
+ printf (__FUNCTION__);
+#endif
+ /* disable memory controller */
+ mtdcr (memcfga, mem_mcopt1);
+ mtdcr (memcfgd, 0x00000000);
+
+ udelay (500);
+
+ /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+ mtdcr (memcfga, mem_besra);
+ mtdcr (memcfgd, 0xffffffff);
+
+ /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+ mtdcr (memcfga, mem_besrb);
+ mtdcr (memcfgd, 0xffffffff);
+
+ /* Clear SDRAM0_ECCCFG (disable ECC) */
+ mtdcr (memcfga, mem_ecccf);
+ mtdcr (memcfgd, 0x00000000);
+
+ /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+ mtdcr (memcfga, mem_eccerr);
+ mtdcr (memcfgd, 0xffffffff);
+
+ /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
+ * TODO ngngng
+ */
+ mtdcr (memcfga, mem_sdtr1);
+ mtdcr (memcfgd, 0x008a4015);
+
+ /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
+ * TODO ngngng
+ */
+ mtdcr (memcfga, mem_mb0cf);
+ mtdcr (memcfgd, 0x00062001);
+
+ /* refresh timer = 0x400 */
+ mtdcr (memcfga, mem_rtr);
+ mtdcr (memcfgd, 0x04000000);
+
+ /* Power management idle timer set to the default. */
+ mtdcr (memcfga, mem_pmit);
+ mtdcr (memcfgd, 0x07c00000);
+
+ udelay (500);
+
+ /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
+ mtdcr (memcfga, mem_mcopt1);
+ mtdcr (memcfgd, 0x90800000);
+
+#ifdef DEBUG
+ printf ("%s: done\n", __FUNCTION__);
+#endif
+ return SDRAM_LEN;
+}
+
+/*---------------------------------------------------------------------------+
+ * hcu_serial_number
+ *---------------------------------------------------------------------------*/
+static u32 hcu_serial_number(void)
+{
+ u32 *serial = (u32 *)CFG_FLASH_BASE;
+
+ if (*serial == 0xffffffff)
+ return get_ticks();
+
+ return *serial;
+}
+
+
+/*---------------------------------------------------------------------------+
+ * misc_init_r.
+ *---------------------------------------------------------------------------*/
+
+int misc_init_r(void)
+{
+ char *s = getenv("ethaddr");
+ char *e;
+ int i;
+ u32 serial = hcu_serial_number();
+
+ for (i = 0; i < 6; ++i) {
+ gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+
+ if (gd->bd->bi_enetaddr[3] == 0 &&
+ gd->bd->bi_enetaddr[4] == 0 &&
+ gd->bd->bi_enetaddr[5] == 0) {
+ char ethaddr[22];
+ /* [0..3] Must be in sync with CONFIG_ETHADDR */
+ gd->bd->bi_enetaddr[0] = 0x00;
+ gd->bd->bi_enetaddr[1] = 0x60;
+ gd->bd->bi_enetaddr[2] = 0x13;
+ gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
+ gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
+ gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff;
+ sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
+ gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
+ gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
+ gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
+ printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
+ ethaddr, serial);
+ setenv ("ethaddr", ethaddr);
+ }
+ return 0;
+}
+
+#ifdef DO_UGLY_SDRAM_WORKAROUND
+#include "i2c.h"
+
+void set_spd_default_value(unsigned int spd_addr,uchar def_val)
+{
+ uchar value;
+ int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
+
+ if (res == 0 && value == 0xff) {
+ res = i2c_write(SPD_EEPROM_ADDRESS,
+ spd_addr, 1, &def_val, 1) ;
+#ifdef DEBUG
+ printf("%s: Setting spd offset %3d to %3d res %d\n",
+ __FUNCTION__, spd_addr, def_val, res);
+#endif
+ }
+}
+#endif
+
+long int initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if !defined(CONFIG_SPD_EEPROM)
+ dram_size = fixed_hcu4_sdram();
+#else
+#ifdef DO_UGLY_SDRAM_WORKAROUND
+ /* Workaround if you have no working I2C-EEPROM-SPD-configuration */
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ set_spd_default_value(2, 4); /* SDRAM Type */
+ set_spd_default_value(7, 0); /* module width, high byte */
+ set_spd_default_value(12, 1); /* Refresh or 0x81 */
+
+ /* Only correct for HCU3 with 32 MB RAM*/
+ /* Number of bytes used by module manufacturer */
+ set_spd_default_value( 0, 128);
+ set_spd_default_value( 1, 11 ); /* Total SPD memory size */
+ set_spd_default_value( 2, 4 ); /* Memory type */
+ set_spd_default_value( 3, 12 ); /* Number of row address bits */
+ set_spd_default_value( 4, 9 ); /* Number of column address bits */
+ set_spd_default_value( 5, 1 ); /* Number of module rows */
+ set_spd_default_value( 6, 32 ); /* Module data width, LSB */
+ set_spd_default_value( 7, 0 ); /* Module data width, MSB */
+ set_spd_default_value( 8, 1 ); /* Module interface signal levels */
+ /* SDRAM cycle time for highest CL (Tclk) */
+ set_spd_default_value( 9, 112);
+ /* SDRAM access time from clock for highest CL (Tac) */
+ set_spd_default_value(10, 84 );
+ set_spd_default_value(11, 2 ); /* Module configuration type */
+ set_spd_default_value(12, 128); /* Refresh rate/type */
+ set_spd_default_value(13, 16 ); /* Primary SDRAM width */
+ set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
+ /* SDRAM device attributes, min clock delay for back to back */
+ /*random column addresses (Tccd) */
+ set_spd_default_value(15, 1 );
+ /* SDRAM device attributes, burst lengths supported */
+ set_spd_default_value(16, 143);
+ /* SDRAM device attributes, number of banks on SDRAM device */
+ set_spd_default_value(17, 4 );
+ /* SDRAM device attributes, CAS latency */
+ set_spd_default_value(18, 6 );
+ /* SDRAM device attributes, CS latency */
+ set_spd_default_value(19, 1 );
+ /* SDRAM device attributes, WE latency */
+ set_spd_default_value(20, 1 );
+ set_spd_default_value(21, 0 ); /* SDRAM module attributes */
+ /* SDRAM device attributes, general */
+ set_spd_default_value(22, 14 );
+ /* SDRAM cycle time for 2nd highest CL (Tclk) */
+ set_spd_default_value(23, 117);
+ /* SDRAM access time from clock for2nd highest CL (Tac) */
+ set_spd_default_value(24, 84 );
+ /* SDRAM cycle time for 3rd highest CL (Tclk) */
+ set_spd_default_value(25, 0 );
+ /* SDRAM access time from clock for3rd highest CL (Tac) */
+ set_spd_default_value(26, 0 );
+ set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
+ /* Minimum row active to row active delay (Trrd) */
+ set_spd_default_value(28, 14 );
+ set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
+ set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
+ set_spd_default_value(31, 8 ); /* Module bank density */
+ /* Command and Address signal input setup time */
+ set_spd_default_value(32, 21 );
+ /* Command and Address signal input hold time */
+ set_spd_default_value(33, 8 );
+ set_spd_default_value(34, 21 ); /* Data signal input setup time */
+ set_spd_default_value(35, 8 ); /* Data signal input hold time */
+#endif /* DO_UGLY_SDRAM_WORKAROUND */
+ dram_size = spd_sdram(0);
+#endif
+
+#ifdef DEBUG
+ show_sdram_registers();
+#endif
+
+#if defined(CFG_DRAM_TEST)
+ bcu4_testdram(dram_size);
+ printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));
+#endif
+
+ return dram_size;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text : {
+ /* The start.o file includes the initial jump vector that
+ must be located in the beginning. It is the basic run-
+ time function that calls all other functions. */
+ cpu/ppc4xx/start.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2007 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+vpath hcu_flash.c ../common
+
+# NOBJS : Netstal common objects
+NOBJS = hcu_flash.o
+COBJS = $(BOARD).o sdram.o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+NOBJS := $(addprefix $(obj),$(NOBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+HCU5 configuration details and startup sequence
+
+(C) Copyright 2007 Netstal Maschinen AG
+ Niklaus Giger (Niklaus.Giger@netstal.com)
+
+TODO:
+-----
+- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
+ - Does not occur if both EMAC are connected
+- Fix RTS/CTS problem (HW?)
+ CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
+ Switching to interrupt driven serial input mode
+- Make vxWorks start from u-boot. Possible reasons
+ - Does vxWorks need an entry for the Machine Check interrupt like this
+ tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
+
+Caveats:
+--------
+Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
+see hcu5.c.
+
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xe0010000- 0xe0013fff CFG_OCM_BASE
+The 440EPx includes a 16K on-chip memory that can be placed however
+software chooses.
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC440EPX
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+Not used
+
+Chip-Select 3: CAN Interface
+----------------------------
+0xc800000: 2 Intel 82527 CAN-Controller
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+0xcc00000: Netstal specific IO-Bus
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+0xce00000: Netstal specific IO-Bus (fast, but not yet used)
+
+
+Memory Bank 1 -- DDR2
+-------------------------------------
+
+0x00000000 - 0xfffffff # Default 256 MB
+
+PCI ??
+
+USB ??
+Only USB_STORAGE is enabled to load vxWorks
+from a memory stick.
+
+System-LEDs ??? (Analog zu HCU4 ???)
+
+Startup sequence
+----------------
+
+(cpu/ppc4xx/resetvec.S)
+depending on configs option
+call _start_440 _start_pci oder _start
+
+(cpu/ppc4xx/start.S)
+
+_start_440:
+ initialize register like
+ CCR0
+ debug
+ setup interrupt vectors
+ configure cache regions
+ clear and setup TLB
+ enable internal RAM
+ jump start_ram
+ which in turn will jump to start
+_start:
+ Clear and set up some registers.
+ Debug setup
+ Setup the internal SRAM
+ Setup the stack in internal SRAM
+ setup stack pointer (r1)
+ setup GOT
+ call cpu_init_f /* run low-level CPU init code (from Flash) */
+
+ call cpu_init_f
+ board_init_f: (lib_ppc\board.c)
+ init_sequence defines a list of function to be called
+ board_early_init_f: (board/netstal/hcu5/hcu5.c)
+ We are using Bootstrap-Option A
+ if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
+ Setup the GPIO pins
+ Setup the interrupt controller polarities, triggers, etc.
+ Ethernet, PCI, USB enable
+ setup BOOT FLASH (Chip timing)
+ init_baudrate,
+ serial_init
+ checkcpu
+ misc_init_f #ifdef
+ init_func_i2c #ifdef
+ post_init_f #ifdef
+ init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
+ (EYE function removed!!)
+ test_dram call
+
+ * Reserve memory at end of RAM for (top down in that order):
+ * - kernel log buffer
+ * - protected RAM
+ * - LCD framebuffer
+ * - monitor code
+ * - board info struct
+ Save local variables to board info struct
+ call relocate_code() does not return
+ relocate_code: (cpu/ppc4xx/start.S)
+-------------------------------------------------------
+From now on our copy is in RAM and we will run from there,
+ starting with board_init_r
+-------------------------------------------------------
+ board_init_r: (lib_ppc\board.c)
+ setup bd function pointers
+ trap_init
+ flash_init: (board/netstal/hcu5/flash.c)
+ /* setup for u-boot erase, update */
+ setup bd flash info
+ cpu_init_r: (cpu/ppc4xx/cpu_init.c)
+ peripheral chip select in using defines like
+ CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h
+ mem_malloc_init
+ malloc_bin_reloc
+ spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+ env_relocated
+ misc_init_r(bd): (board/netstal/hcu5.c)
+ ethaddr mit serial number ergänzen
+ Then we will somehow go into the command loop
+
+Most of the HW specific code for the HCU5 may be found in
+include/configs/hcu5.h
+board/netstal/hcu5/*
+cpu/ppc4xx/*
+lib_ppc/*
+include/ppc440.h
+
+Drivers for serial etc are found under drivers/
+
+Don't ask question if you did not look at the README !!
+Most CFG_* and CONFIG_* switches are mentioned/explained there.
--- /dev/null
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: HCU5 boards
+#
+
+TEXT_BASE = 0xFFFa0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
--- /dev/null
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include <asm/mmu.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void hcu_led_set(u32 value);
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#undef BOOTSTRAP_OPTION_A_ACTIVE
+
+#define SDR0_CP440 0x0180
+
+#define SYSTEM_RESET 0x30000000
+#define CHIP_RESET 0x20000000
+
+#define SDR0_ECID0 0x0080
+#define SDR0_ECID1 0x0081
+#define SDR0_ECID2 0x0082
+#define SDR0_ECID3 0x0083
+
+#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
+#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000)
+
+#define DEFAULT_ETH_ADDR "ethaddr"
+/* ethaddr for first or etha1ddr for second ethernet */
+
+enum {
+ /* HW_GENERATION_HCU1 is no longer supported */
+ HW_GENERATION_HCU2 = 0x10,
+ HW_GENERATION_HCU3 = 0x10,
+ HW_GENERATION_HCU4 = 0x20,
+ HW_GENERATION_HCU5 = 0x30,
+ HW_GENERATION_MCU = 0x08,
+ HW_GENERATION_MCU20 = 0x0a,
+ HW_GENERATION_MCU25 = 0x09,
+};
+
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+int board_early_init_f(void)
+{
+ u32 reg;
+
+#ifdef BOOTSTRAP_OPTION_A_ACTIVE
+ /* Booting with Bootstrap Option A
+ * First boot, with CPR0_ICFG_RLI_MASK == 0
+ * no we setup varios boot strapping register,
+ * then we do reset the PPC440 using a chip reset
+ * Unfortunately, we cannot use this option, as Nto1 is not set
+ * with Bootstrap Option A and cannot be changed later on by SW
+ * There are no other possible boostrap options with a 8 bit ROM
+ * See Errata (Version 1.04) CHIP_9
+ */
+
+ u32 cpr0icfg;
+ u32 dbcr;
+
+ mfcpr(CPR0_ICFG, cpr0icfg);
+ if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
+ mtcpr(CPR0_MALD, 0x02000000);
+ mtcpr(CPR0_OPBD, 0x02000000);
+ mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
+ mtcpr(CPR0_PLLC, 0x40000238);
+ mtcpr(CPR0_PLLD, 0x01010414);
+ mtcpr(CPR0_PRIMAD, 0x01000000);
+ mtcpr(CPR0_PRIMBD, 0x01000000);
+ mtcpr(CPR0_SPCID, 0x03000000);
+ mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
+ mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
+ mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
+
+ /*
+ * Initiate system reset in debug control register DBCR
+ */
+ dbcr = mfspr(dbcr0);
+ mtspr(dbcr0, dbcr | CHIP_RESET);
+ }
+ mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
+#endif
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /* test-only: take GPIO init from pcs440ep ???? in config file */
+ out32(GPIO0_OR, 0x00000000);
+ out32(GPIO0_TCR, 0x7C2FF1CF);
+ out32(GPIO0_OSRL, 0x40055000);
+ out32(GPIO0_OSRH, 0x00000000);
+ out32(GPIO0_TSRL, 0x40055000);
+ out32(GPIO0_TSRH, 0x00000400);
+ out32(GPIO0_ISR1L, 0x40000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x00000000);
+ out32(GPIO0_ISR2H, 0x00000000);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
+
+ out32(GPIO1_OR, 0x00000000);
+ out32(GPIO1_TCR, 0xC6007FFF);
+ out32(GPIO1_OSRL, 0x00140000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x00000000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x05415555);
+ out32(GPIO1_ISR1H, 0x40000000);
+ out32(GPIO1_ISR2L, 0x00000000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x00000000);
+ out32(GPIO1_ISR3H, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
+ mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ pci_pre_init(0);
+
+ /* setup BOOT FLASH */
+ mtsdr(SDR0_CUST0, 0xC0082350);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init(void)
+{
+ return board_early_init_f();
+}
+
+#endif
+
+int checkboard(void)
+{
+ unsigned int j;
+ u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
+ u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
+ u16 generation = *boardVersReg & 0xf0;
+ u16 index = *boardVersReg & 0x0f;
+ u32 ecid0, ecid1, ecid2, ecid3;
+
+ printf("Netstal Maschinen AG: ");
+ if (generation == HW_GENERATION_HCU3)
+ printf("HCU3: index %d", index);
+ else if (generation == HW_GENERATION_HCU4)
+ printf("HCU4: index %d", index);
+ else if (generation == HW_GENERATION_HCU5)
+ printf("HCU5: index %d", index);
+ printf(" HW 0x%02x\n", *hwVersReg & 0xff);
+ mfsdr(SDR0_ECID0, ecid0);
+ mfsdr(SDR0_ECID1, ecid1);
+ mfsdr(SDR0_ECID2, ecid2);
+ mfsdr(SDR0_ECID3, ecid3);
+
+ printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
+ for (j = 0;j < 6; j++) {
+ hcu_led_set(1 << j);
+ udelay(200 * 1000);
+ }
+
+ return 0;
+}
+
+u32 hcu_led_get(void)
+{
+ return in16(SYS_IO_ADDRESS) & 0x3f;
+}
+
+/*---------------------------------------------------------------------------+
+ * hcu_led_set value to be placed into the LEDs (max 6 bit)
+ *---------------------------------------------------------------------------*/
+void hcu_led_set(u32 value)
+{
+ out16(SYS_IO_ADDRESS, value);
+}
+
+/*---------------------------------------------------------------------------+
+ * get_serial_number
+ *---------------------------------------------------------------------------*/
+static u32 get_serial_number(void)
+{
+ u32 *serial = (u32 *)CFG_FLASH_BASE;
+
+ if (*serial == 0xffffffff)
+ return 0;
+
+ return *serial;
+}
+
+
+/*---------------------------------------------------------------------------+
+ * hcu_get_slot
+ *---------------------------------------------------------------------------*/
+u32 hcu_get_slot(void)
+{
+ u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
+ return (*slot) & 0x7f;
+}
+
+
+/*---------------------------------------------------------------------------+
+ * misc_init_r.
+ *---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+ char *s = getenv(DEFAULT_ETH_ADDR);
+ char *e;
+ int i;
+ u32 serial = get_serial_number();
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+
+ for (i = 0; i < 6; ++i) {
+ gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+
+ if (gd->bd->bi_enetaddr[3] == 0 &&
+ gd->bd->bi_enetaddr[4] == 0 &&
+ gd->bd->bi_enetaddr[5] == 0) {
+ char ethaddr[22];
+
+ /* Must be in sync with CONFIG_ETHADDR */
+ gd->bd->bi_enetaddr[0] = 0x00;
+ gd->bd->bi_enetaddr[1] = 0x60;
+ gd->bd->bi_enetaddr[2] = 0x13;
+ gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
+ gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
+ gd->bd->bi_enetaddr[5] = hcu_get_slot();
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
+ gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
+ gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
+ gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
+ printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
+ ethaddr, serial);
+ setenv(DEFAULT_ETH_ADDR, ethaddr);
+ }
+
+ /* IP-Adress update */
+ {
+ IPaddr_t ipaddr;
+ char *ipstring;
+
+ ipstring = getenv("ipaddr");
+ if (ipstring == 0)
+ ipaddr = string_to_ip("172.25.1.99");
+ else
+ ipaddr = string_to_ip(ipstring);
+ if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
+ char tmp[22];
+
+ ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
+ ip_to_string (ipaddr, tmp);
+ printf("%s: enforce %s\n", __FUNCTION__, tmp);
+ setenv("ipaddr", tmp);
+ }
+ }
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ /*
+ * USB stuff...
+ */
+
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*clear resets*/
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*-------------------------------------------------------------------+
+ * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
+ * Workaround: Disable write pipelining to DDR SDRAM by setting
+ * PLB0_ACR[WRP] = 0.
+ *-------------------------------------------------------------------*/
+
+ /*-------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
+ mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
+
+ /*-------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
+ mtdcr(plb4_acr, addr); /* Sequoia */
+
+ /*-------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
+
+ /* mtdcr(plb0_acr, addr); */ /* Sequoia */
+ mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) ;
+ /* mtdcr(plb1_acr, addr); */ /* Sequoia */
+ mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
+
+ return 1;
+}
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+void pci_target_init(struct pci_controller *hose)
+{
+ /*-------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *-------------------------------------------------------------*/
+ /*-------------------------------------------------------------+
+ | PowerPC440EPX PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
+ | 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +-------------------------------------------------------------*/
+ /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0MA, 0x00000000);
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM0MA, 0xE0000001);
+
+ /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1MA, 0x00000000);
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM1MA, 0xE0000001);
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*------------------------------------------------------------------+
+ * Set up Configuration registers
+ *------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+}
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*---------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+int is_pci_host(struct pci_controller *hose)
+{
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /* vxWorks needs this entry for the Machine Check interrupt, */
+ /* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
+
+ /*
+ * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for EBC (CFG_CPLD) */
+ /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
+ /* CAN */
+ tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ /* IMC + CPLD */
+ tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ /* IMC-Fast */
+ tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /* TLB for SDRAM will be added by initdram (sdram.c) */
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <ppc440.h>
+
+void hcu_led_set(u32 value);
+void dcbz_area(u32 start_address, u32 num_bytes);
+void dflush(void);
+
+#define DDR_DCR_BASE 0x10
+#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
+#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
+
+#define DDR0_01_INT_MASK_MASK 0x000000FF
+#define DDR0_00_INT_ACK_ALL 0x7F000000
+#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
+
+#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
+#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
+
+#define DDR0_22 0x16
+/* ECC */
+#define DDR0_22_CTRL_RAW_MASK 0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
+#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
+#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+
+#ifdef CFG_ENABLE_SDRAM_CACHE
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
+#else
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
+#endif
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+
+void board_add_ram_info(int use_default)
+{
+ PPC440_SYS_INFO board_cfg;
+ u32 val;
+ mfsdram(DDR0_22, val);
+ val &= DDR0_22_CTRL_RAW_MASK;
+ switch (val) {
+ case DDR0_22_CTRL_RAW_ECC_DISABLE:
+ puts(" (ECC disabled");
+ break;
+ case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
+ puts(" (ECC check only");
+ break;
+ case DDR0_22_CTRL_RAW_NO_ECC_RAM:
+ puts(" (no ECC ram");
+ break;
+ case DDR0_22_CTRL_RAW_ECC_ENABLE:
+ puts(" (ECC enabled");
+ break;
+ }
+
+ get_sys_info(&board_cfg);
+ printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+ mfsdram(DDR0_03, val);
+ val = DDR0_03_CASLAT_DECODE(val);
+ printf(", CL%d)", val);
+}
+
+/*--------------------------------------------------------------------
+ * wait_for_dlllock.
+ *--------------------------------------------------------------------*/
+static int wait_for_dlllock(void)
+{
+ unsigned long val;
+ int wait = 0;
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_17);
+ val = DDR0_17_DLLLOCKREG_UNLOCKED;
+
+ while (wait != 0xffff) {
+ val = mfdcr(ddrcfgd);
+ if ((val & DDR0_17_DLLLOCKREG_MASK) ==
+ DDR0_17_DLLLOCKREG_LOCKED)
+ /* dlllockreg bit on */
+ return 0;
+ else
+ wait++;
+ }
+ debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+ debug("Waiting for dlllockreg bit to raise\n");
+
+ return -1;
+}
+
+/***********************************************************************
+ *
+ * sdram_panic -- Panic if we cannot configure the sdram correctly
+ *
+ ************************************************************************/
+void sdram_panic(const char *reason)
+{
+ printf("\n%s: reason %s", __FUNCTION__, reason);
+ hcu_led_set(0xff);
+ while (1) {
+ }
+ /* Never return */
+}
+
+#ifdef CONFIG_DDR_ECC
+static void blank_string(int size)
+{
+ int i;
+
+ for (i=0; i<size; i++)
+ putc('\b');
+ for (i=0; i<size; i++)
+ putc(' ');
+ for (i=0; i<size; i++)
+ putc('\b');
+}
+/*---------------------------------------------------------------------------+
+ * program_ecc.
+ *---------------------------------------------------------------------------*/
+static void program_ecc(unsigned long start_address, unsigned long num_bytes,
+ unsigned long tlb_word2_i_value)
+{
+ unsigned long current_address= start_address;
+ int loopi = 0;
+ u32 val;
+
+ char str[] = "ECC generation -";
+ char slash[] = "\\|/-\\|/-";
+
+ sync();
+ eieio();
+
+ puts(str);
+
+ if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
+ /* ECC bit set method for non-cached memory */
+ /* This takes various seconds */
+ for(current_address = 0; current_address < num_bytes;
+ current_address += sizeof(u32)) {
+ *(u32 *)current_address = 0;
+ if ((current_address % (2 << 20)) == 0) {
+ putc('\b');
+ putc(slash[loopi++ % 8]);
+ }
+ }
+ } else {
+ /* ECC bit set method for cached memory */
+ /* Fast method, no noticeable delay */
+ dcbz_area(start_address, num_bytes);
+ dflush();
+ }
+ blank_string(strlen(str));
+
+ /* Clear error status */
+ mfsdram(DDR0_00, val);
+ mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+ /*
+ * Clear possible errors
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ mtspr(mcsr, mfspr(mcsr));
+
+ /* Set 'int_mask' parameter to functionnal value */
+ mfsdram(DDR0_01, val);
+ mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
+ DDR0_01_INT_MASK_ALL_OFF));
+
+ return;
+}
+
+#endif
+
+/***********************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+#define HCU_HW_SDRAM_CONFIG_MASK 0x7
+#define INVALID_HW_CONFIG "Invalid HW-Config"
+ u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
+ unsigned int dram_size = 0;
+
+ mtsdram(DDR0_02, 0x00000000);
+
+ /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02030602);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020307);
+ switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
+ case 0:
+ dram_size = 128 * 1024 * 1024 ;
+ mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
+ mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
+ mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
+ break;
+ case 1:
+ dram_size = 256 * 1024 * 1024 ;
+ mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
+ mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
+ mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
+ break;
+ default:
+ sdram_panic(INVALID_HW_CONFIG);
+ break;
+ }
+ mtsdram(DDR0_07, 0x00090100);
+ /*
+ * TCPD=200 cycles of clock input is required to lock the DLL.
+ * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
+ */
+ mtsdram(DDR0_08, 0x02C80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1D000000);
+ mtsdram(DDR0_18, 0x1D1D1D1D);
+ mtsdram(DDR0_19, 0x1D1D1D1D);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+ #define ECC_RAM 0x03267F0B
+ #define NO_ECC_RAM 0x00267F0B
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, ECC_RAM);
+#else
+ mtsdram(DDR0_22, NO_ECC_RAM);
+#endif
+
+ mtsdram(DDR0_23, 0x00000000);
+ mtsdram(DDR0_24, 0x01020001);
+ mtsdram(DDR0_26, 0x2D930517);
+ mtsdram(DDR0_27, 0x00008236);
+ mtsdram(DDR0_28, 0x00000000);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000006);
+ mtsdram(DDR0_44, 0x00000003);
+ mtsdram(DDR0_02, 0x00000001);
+ wait_for_dlllock();
+ mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
+
+ /*
+ * Program tlb entries for this size (dynamic)
+ */
+ remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+ program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
+ /*
+ * Setup 2nd TLB with same physical address but different virtual
+ * address with cache enabled. This is done for fast ECC generation.
+ */
+ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+
+ /* Diminish RAM to initialize */
+ dram_size = dram_size - 32 ;
+#ifdef CONFIG_DDR_ECC
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
+#endif
+
+ return (dram_size);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/sizes.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE SZ_128K
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-# define FLASH_PORT_WIDTH ushort
-# define FLASH_PORT_WIDTHV vu_short
-# define SWAP(x) __swab16(x)
-#else
-# define FLASH_PORT_WIDTH ulong
-# define FLASH_PORT_WIDTHV vu_long
-# define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
- unsigned int sector_number;
- unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
- {4, SZ_32K}, /* 4 * 32kBytes sectors */
- {255, SZ_128K}, /* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-void flash_unlock(flash_info_t * info, int bank);
-int flash_probe(void);
-
-/*-----------------------------------------------------------------------
- */
-
-/* see if flash is ok */
-int flash_probe(void)
-{
- return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0]));
-}
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- /* to reset the lock bit */
- flash_unlock(&flash_info[i],i);
- break;
- case 1:
- flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
- /* to reset the lock bit */
- flash_unlock(&flash_info[i],i);
- break;
-
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
-#endif
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_unlock(flash_info_t * info, int bank)
-{
- int j;
- if (!bank)
- j=2; /* leave 0,1 locked for boot bank */
- else
- j=0; /* get the whole bank for #2 */
-
- for (;j<CFG_MAX_FLASH_SECT;j++) {
- FPWV *addr = (FPWV *) (info->start[j]);
- if (addr == NULL) {
- printf("Warning Flash probe failed\n");
- break;
- }
- flash_unprotect_sectors (addr);
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
- volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- if (i > 254) { /* 255,256,257,258 */
- r=i;
- info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE));
- info->protect[i] = 0;
- } else {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256L18T:
- printf ("FLASH 28F256L18T\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- volatile FPW value;
- /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return(0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
- switch (value) {
-
- case (FPW) (INTEL_ID_28F256L18T): /* 880D */
- info->flash_id += FLASH_28F256L18T;
- info->sector_count = 259; /*0-258*/
- info->size = SZ_32M;
- break; /* => 32 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CFG_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
- info->sector_count = CFG_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return(info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK 0x0080
-
- *addr = (FPW) 0x00500050; /* clear status register */
-
- /* this sends the clear lock bit command */
- *addr = (FPW) 0x00600060;
- *addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type, start, last;
- int rcode = 0;
-#ifdef CONFIG_USE_IRQ
- int iflag;
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-
- start = get_timer (0);
- last = start;
-
-#ifdef CONFIG_USE_IRQ
- /* Disable interrupts which might cause a timeout here */
- iflag = disable_interrupts ();
-#endif
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- flash_unprotect_sectors (addr);
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00200020;/* erase setup */
- *addr = (FPW) 0x00D000D0;/* erase confirm */
-
- while (((status =
- *addr) & (FPW) 0x00800080) !=
- (FPW) 0x00800080) {
- if (get_timer_masked () >
- CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- /* reset to read mode */
- *addr = (FPW) 0x00FF00FF;
- rcode = 1;
- break;
- }
- }
-
- /* clear status register cmd. */
- *addr = (FPW) 0x00500050;
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
- printf (" done\n");
- }
- }
-#ifdef CONFIG_USE_IRQ
- if (iflag)
- enable_interrupts();
-#endif
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return(rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return(rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return(0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return(write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
-#ifdef CONFIG_USE_IRQ
- int iflag;
-#endif
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
- return(2);
- }
- /* Disable interrupts which might cause a timeout here */
-#ifdef CONFIG_USE_IRQ
- iflag = disable_interrupts ();
-#endif
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return(1);
- }
- }
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
-#ifdef CONFIG_USE_IRQ
- if (iflag)
- enable_interrupts();
-#endif
-
- return(0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
#include <spd_sdram.h>
#include <status_led.h>
#include <sha1.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
);
#endif
+#if defined (CONFIG_CMD_IDE)
+/* These addresses need to be shifted one place to the left
+ * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
+ * These values are shifted
+ */
+extern ulong *ide_bus_offset;
+void inline ide_outb(int dev, int port, unsigned char val)
+{
+ debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+ dev, port, val, (ATA_CURR_BASE(dev)+port));
+
+ out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
+}
+unsigned char inline ide_inb(int dev, int port)
+{
+ uchar val;
+ val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
+ debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+ dev, port, (ATA_CURR_BASE(dev)+port), val);
+ return (val);
+}
+#endif
+
#ifdef CONFIG_IDE_PREINIT
int ide_preinit (void)
{
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o
+COBJS = $(BOARD).o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ } else {
+ }
+
+ return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970 0x78100000 /* LXT970 */
+#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
+#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
+#define PHY_ID_QS6612 0x01814400 /* QS6612 */
+#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
+#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
+#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
+#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
+#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
+#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
+
+#define STR_ID_LXT970 "LXT970"
+#define STR_ID_LXT971 "LXT971"
+#define STR_ID_82555 "Intel82555"
+#define STR_ID_QS6612 "QS6612"
+#define STR_ID_AMD79C784 "AMD79C784"
+#define STR_ID_LSI80225 "LSI80225"
+#define STR_ID_LSI80225B "LSI80225/B"
+#define STR_ID_DP83848VV "N83848"
+#define STR_ID_DP83849 "N83849"
+#define STR_ID_KS8721BL "KS8721BL"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *) (info->miibase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ volatile fec_t *ep;
+ uint mii_reply;
+ int j = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ ep = (fec_t *) info->miibase;
+
+ ep->mmfr = mii_cmd; /* command to phy */
+
+ /* wait for mii complete */
+ while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("MII not complete\n");
+ return -1;
+ }
+
+ mii_reply = ep->mmfr; /* result from phy */
+ ep->eir = FEC_EIR_MII; /* clear MII complete */
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+ __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+ return (mii_reply & 0xffff); /* data read from phy */
+}
+#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+ struct fec_info_s *info = dev->priv;
+ int phyaddr, pass;
+ uint phyno, phytype;
+
+ if (info->phyname_init)
+ return info->phy_addr;
+
+ phyaddr = -1; /* didn't find a PHY yet */
+ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+ if (pass > 1) {
+ /* PHY may need more time to recover from reset.
+ * The LXT970 needs 50ms typical, no maximum is
+ * specified, so wait 10ms before try again.
+ * With 11 passes this gives it 100ms to wake up.
+ */
+ udelay(10000); /* wait 10ms */
+ }
+
+ for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+ phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+ if (phytype != 0xffff) {
+ phyaddr = phyno;
+ phytype <<= 16;
+ phytype |=
+ mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ strcpy(info->phy_name,
+ STR_ID_KS8721BL);
+ info->phyname_init = 1;
+ break;
+ default:
+ strcpy(info->phy_name, "unknown");
+ info->phyname_init = 1;
+ break;
+ }
+
+#ifdef ET_DEBUG
+ printf("PHY @ 0x%x pass %d type ", phyno, pass);
+ switch (phytype & 0xffffffff) {
+ case PHY_ID_KS8721BL:
+ printf(STR_ID_KS8721BL);
+ break;
+ default:
+ printf("0x%08x\n", phytype);
+ break;
+ }
+#endif
+ }
+ }
+ }
+ if (phyaddr < 0)
+ printf("No PHY device found.\n");
+
+ return phyaddr;
+}
+#endif /* CFG_DISCOVER_PHY */
+
+int mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+ volatile fec_t *fecp;
+ struct fec_info_s *info;
+ struct eth_device *dev;
+ int miispd = 0, i = 0;
+ u16 autoneg = 0;
+
+ /* retrieve from register structure */
+ dev = eth_get_dev();
+ info = dev->priv;
+
+ fecp = (fec_t *) info->miibase;
+
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set MII speed */
+ miispd = (gd->bus_clk / 1000000) / 5;
+ fecp->mscr = miispd << 1;
+
+ info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+ while (i < MCFFEC_TOUT_LOOP) {
+ autoneg = 0;
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ i++;
+
+ if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ break;
+
+ udelay(500);
+ }
+ if (i >= MCFFEC_TOUT_LOOP) {
+ printf("Auto Negotiation not complete\n");
+ }
+
+ /* adapt to the half/full speed settings */
+ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+ info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ * no PHY connected...
+ * For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ * Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+ rdreg = mii_send(mk_mii_read(addr, reg));
+
+ *value = rdreg;
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", *value);
+#endif
+
+ return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ short rdreg; /* register working value */
+
+#ifdef MII_DEBUG
+ printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+ rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+ printf("0x%04x\n", value);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
#include <linux/mtd/nand.h>
#endif
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
#define FCLK_SPEED 1
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
#if defined(CONFIG_DDR_2T_TIMING)
| SDRAM_CFG_2T_EN
#endif
- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+ | SDRAM_CFG_SDRAM_TYPE_DDR1;
#if defined (CONFIG_DDR_32BIT)
/* for 32-bit mode burst length is 8 */
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Jeff Brown
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# sbc8641 board
+# default CCSRBAR is at 0xff700000
+#
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
--- /dev/null
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman joe.hamman@embeddedspecialties.com
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc86xx.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x0fff_ffff DDR1 256M
+ * 0x1000_0000 0x1fff_ffff DDR2 256M
+ * 0xe000_0000 0xffff_ffff LBC 512M
+ *
+ * Notes:
+ * CCSRBAR doesn't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+# DDR Bank 1
+# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+# DDR Bank 2
+# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
+# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+# LBC
+# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
+# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
+
+/*
+ * LAW (Local Access Window) configuration:
+ *
+ * 0x0000_0000 DDR 256M
+ * 0x1000_0000 DDR2 256M
+ * 0x8000_0000 PCI1 MEM 512M
+ * 0xa000_0000 PCI2 MEM 512M
+ * 0xc000_0000 RapidIO 512M
+ * 0xe200_0000 PCI1 IO 16M
+ * 0xe300_0000 PCI2 IO 16M
+ * 0xf800_0000 CCSRBAR 2M
+ * 0xfe00_0000 FLASH (boot bank) 32M
+ *
+ */
+
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
+
+#define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
+#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
+
+#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
+#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+
+#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ lis r7,CFG_CCSRBAR@h
+ ori r7,r7,CFG_CCSRBAR@l
+
+ addi r4,r7,0
+ addi r5,r7,0
+
+ /* Skip LAWAR0, start at LAWAR1 */
+ lis r6,LAWBAR1@h
+ ori r6,r6,LAWBAR1@l
+ stwu r6, 0xc28(r4)
+
+ lis r6,LAWAR1@h
+ ori r6,r6,LAWAR1@l
+ stwu r6, 0xc30(r5)
+
+ /* LAWBAR2, LAWAR2 */
+ lis r6,LAWBAR2@h
+ ori r6,r6,LAWBAR2@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR2@h
+ ori r6,r6,LAWAR2@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR3, LAWAR3 */
+ lis r6,LAWBAR3@h
+ ori r6,r6,LAWBAR3@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR3@h
+ ori r6,r6,LAWAR3@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR4, LAWAR4 */
+ lis r6,LAWBAR4@h
+ ori r6,r6,LAWBAR4@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR4@h
+ ori r6,r6,LAWAR4@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR5, LAWAR5 */
+ lis r6,LAWBAR5@h
+ ori r6,r6,LAWBAR5@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR5@h
+ ori r6,r6,LAWAR5@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR6, LAWAR6 */
+ lis r6,LAWBAR6@h
+ ori r6,r6,LAWBAR6@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR6@h
+ ori r6,r6,LAWAR6@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR7, LAWAR7 */
+ lis r6,LAWBAR7@h
+ ori r6,r6,LAWBAR7@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR7@h
+ ori r6,r6,LAWAR7@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR8, LAWAR8 */
+ lis r6,LAWBAR8@h
+ ori r6,r6,LAWBAR8@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR8@h
+ ori r6,r6,LAWAR8@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR9, LAWAR9 */
+ lis r6,LAWBAR9@h
+ ori r6,r6,LAWBAR9@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR9@h
+ ori r6,r6,LAWAR9@l
+ stwu r6, 0x20(r5)
+
+ blr
--- /dev/null
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman joe.hamman@embeddedspecialties.com
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup (void *blob, bd_t * bd);
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc (unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init (void);
+long int fixed_sdram (void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ puts ("Board: Wind River SBC8641D\n");
+
+ return 0;
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CFG_RAMBOOT)
+ puts (" DDR: ");
+ return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc (dram_size);
+#endif
+
+ puts (" DDR: ");
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ puts ("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts ("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts ("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int fixed_sdram (void)
+{
+#if !defined(CFG_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs1_bnds = CFG_DDR_CS1_BNDS;
+ ddr->cs2_bnds = CFG_DDR_CS2_BNDS;
+ ddr->cs3_bnds = CFG_DDR_CS3_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->cs1_config = CFG_DDR_CS1_CONFIG;
+ ddr->cs2_config = CFG_DDR_CS2_CONFIG;
+ ddr->cs3_config = CFG_DDR_CS3_CONFIG;
+ ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_cfg_1 = CFG_DDR_CFG_1A;
+ ddr->sdram_cfg_2 = CFG_DDR_CFG_2;
+ ddr->sdram_mode_1 = CFG_DDR_MODE_1;
+ ddr->sdram_mode_2 = CFG_DDR_MODE_2;
+ ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+
+ asm ("sync;isync");
+
+ udelay (500);
+
+ ddr->sdram_cfg_1 = CFG_DDR_CFG_1B;
+ asm ("sync; isync");
+
+ udelay (500);
+ ddr = &immap->im_ddr2;
+
+ ddr->cs0_bnds = CFG_DDR2_CS0_BNDS;
+ ddr->cs1_bnds = CFG_DDR2_CS1_BNDS;
+ ddr->cs2_bnds = CFG_DDR2_CS2_BNDS;
+ ddr->cs3_bnds = CFG_DDR2_CS3_BNDS;
+ ddr->cs0_config = CFG_DDR2_CS0_CONFIG;
+ ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
+ ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
+ ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
+ ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
+ ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
+ ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A;
+ ddr->sdram_cfg_2 = CFG_DDR2_CFG_2;
+ ddr->sdram_mode_1 = CFG_DDR2_MODE_1;
+ ddr->sdram_mode_2 = CFG_DDR2_MODE_2;
+ ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL;
+ ddr->sdram_interval = CFG_DDR2_INTERVAL;
+ ddr->sdram_data_init = CFG_DDR2_DATA_INIT;
+ ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL;
+
+ asm ("sync;isync");
+
+ udelay (500);
+
+ ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B;
+ asm ("sync; isync");
+
+ udelay (500);
+#endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+ {}
+};
+#endif
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc86xxcts_config_table
+#endif
+};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+int first_free_busno = 0;
+
+void pci_init_board(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+#ifdef DEBUG
+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
+#endif
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+ || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+ debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ debug("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ puts("PCI-EXPRESS 1: Disabled\n");
+ }
+}
+#else
+ puts("PCI-EXPRESS1: Disabled\n");
+#endif /* CONFIG_PCI1 */
+
+#ifdef CONFIG_PCI2
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci2_hose;
+
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS,
+ CFG_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+}
+#else
+ puts("PCI-EXPRESS 2: Disabled\n");
+#endif /* CONFIG_PCI2 */
+
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t * bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup (blob, bd);
+
+ p = ft_get_prop (blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32 (bd->bi_memstart);
+ *p = cpu_to_be32 (bd->bi_memsize);
+ }
+}
+#endif
+
+void sbc8641d_reset_board (void)
+{
+ puts ("Resetting board....\n");
+}
+
+/*
+ * get_board_sys_clk
+ * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long get_board_sys_clk (ulong dummy)
+{
+ int i;
+ ulong val = 0;
+
+ i = 5;
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33000000;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66000000;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 134000000;
+ break;
+ case 7:
+ val = 166000000;
+ break;
+ }
+
+ return val;
+}
--- /dev/null
+/*
+ * Copyright 2006, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+
+ /* Read-only sections, merged into text segment: */
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc86xx/start.o (.text)
+ board/sbc8641d/init.o (.bootpg)
+ cpu/mpc86xx/traps.o (.text)
+ cpu/mpc86xx/interrupts.o (.text)
+ cpu/mpc86xx/cpu_init.o (.text)
+ cpu/mpc86xx/cpu.o (.text)
+ cpu/mpc86xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#include <common.h>
#include <clps7111.h>
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* arch number MACH_TYPE_ARMADILLO - not official*/
gd->bd->bi_arch_number = 83;
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#endif
-static struct pci_controller hose = {
+static struct pci_controller hose[] = {
#ifndef CONFIG_PCI_PNP
- config_table: pci_stxgp3_config_table,
+ { config_table: pci_stxgp3_config_table,},
+#else
+ {},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
#endif
};
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif /* CONFIG_PCI */
}
. = ALIGN(256);
__init_end = .;
+ . = .;
__bss_start = .;
.bss :
{
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
#include "mt48lc16m16a2-75.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
int board_early_init_f (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (silent_boot())
gd->flags |= GD_FLG_SILENT;
#endif /* CONFIG_VIDEO_SM501 */
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
/* enable DDR controller */
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR);
+ SDRAM_CFG_SDRAM_TYPE_DDR1);
SYNC;
/* size detection */
/* don't enable DDR controller yet */
im->ddr.sdram_cfg =
SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR;
+ SDRAM_CFG_SDRAM_TYPE_DDR1;
SYNC;
/* Set SDRAM mode */
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := conxs.o eeprom.o
+SOBJS := lowlevel_init.o pxavoltage.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE =0xa1f00000
+# 0xa1700000
+#TEXT_BASE = 0
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void usb_board_init(void)
+{
+ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+ UHCHR |= UHCHR_FSBIR;
+
+ while (UHCHR & UHCHR_FSBIR);
+
+ UHCHR &= ~UHCHR_SSE;
+ UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+ /* Clear any OTG Pin Hold */
+ if (PSSR & PSSR_OTGPH)
+ PSSR |= PSSR_OTGPH;
+
+ UHCRHDA &= ~(RH_A_NPS);
+ UHCRHDA |= RH_A_PSM;
+
+ /* Set port power control mask bits, only 3 ports. */
+ UHCRHDB |= (0x7<<17);
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+ CKEN &= ~CKEN10_USBHOST;
+
+ puts("Called USB STOP\n");
+ return;
+}
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of ConXS Board */
+ gd->bd->bi_arch_number = 776;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa000003c;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ char *console=getenv("boot_console");
+
+ if ((strcmp(console,"serial_btuart") == 0) ||
+ (strcmp(console,"serial_stuart") == 0) ||
+ (strcmp(console,"serial_ffuart") == 0)) {
+ setenv("stdout",console);
+ setenv("stdin", console);
+ setenv("stderr",console);
+ } else {
+ setenv("stdout", "serial");
+ setenv("stdin", "serial");
+ setenv("stderr", "serial");
+ }
+#endif
+ return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+static unsigned char srom[128];
+extern u16 read_srom_word(int);
+extern void write_srom_word(int offset, u16 val);
+
+static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+ int i;
+
+ for (i=0; i < 0x40; i++) {
+ if (!(i % 0x10))
+ printf("\n%08lx:", i);
+ printf(" %04x", read_srom_word(i));
+ }
+ printf ("\n");
+ return (0);
+}
+
+static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+ int offset,value;
+
+ if (argc < 4) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ offset=simple_strtoul(argv[2],NULL,16);
+ value=simple_strtoul(argv[3],NULL,16);
+ if (offset > 0x40) {
+ printf("Wrong offset : 0x%x\n",offset);
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+ write_srom_word(offset, value);
+ return (0);
+}
+
+int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (strcmp (argv[1],"read") == 0) {
+ return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
+ } else if (strcmp (argv[1],"write") == 0) {
+ return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
+ } else {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+}
+
+U_BOOT_CMD(
+ dm9000ee,4,1,do_dm9000_eeprom,
+ "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
+ "\ndm9000ee write <word offset> <value> \n"
+ "\tdm9000ee read \n"
+ "\tword:\t\t00-02 : MAC Address\n"
+ "\t\t\t03-07 : DM9000 Configuration\n"
+ "\t\t\t08-63 : User data\n");
--- /dev/null
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR3
+ ldr r1, =CFG_GPSR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR3
+ ldr r1, =CFG_GPCR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER0
+ ldr r1, =CFG_GRER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER1
+ ldr r1, =CFG_GRER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER2
+ ldr r1, =CFG_GRER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER3
+ ldr r1, =CFG_GRER3_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER0
+ ldr r1, =CFG_GFER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER1
+ ldr r1, =CFG_GFER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER2
+ ldr r1, =CFG_GFER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER3
+ ldr r1, =CFG_GFER3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR3
+ ldr r1, =CFG_GPDR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_L
+ ldr r1, =CFG_GAFR3_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_U
+ ldr r1, =CFG_GAFR3_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+ ldr r2, =CFG_FLYCNFG_VAL
+ str r2, [r1, #FLYCNFG_OFFSET]
+ str r2, [r1, #FLYCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r2, =0xFFF
+ bic r4, r4, r2
+
+ ldr r3, =CFG_MDREFR_VAL
+ and r3, r3, r2
+
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+
+ orr r4, r4, #MDREFR_K0RUN
+ orr r4, r4, #MDREFR_K0DB4
+ orr r4, r4, #MDREFR_K0FREE
+ orr r4, r4, #MDREFR_K0DB2
+ orr r4, r4, #MDREFR_K1DB2
+ bic r4, r4, #MDREFR_K1FREE
+ bic r4, r4, #MDREFR_K2FREE
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ ldr r2, =CFG_SXCNFG_VAL
+ str r2, [r1, #SXCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+ orr r4, r4, #MDREFR_K1RUN
+ bic r4, r4, #MDREFR_K2DB2
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ bic r4, r4, #MDREFR_SLFRSH
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ orr r4, r4, #MDREFR_E1PIN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ nop
+ nop
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ mov r4, r3
+ orr r3, r3, #MDCNFG_DE0
+ str r3, [r1, #MDCNFG_OFFSET]
+ mov r0, r3
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ /* enable APD */
+ ldr r3, [r1, #MDREFR_OFFSET]
+ orr r3, r3, #MDREFR_APD
+ str r3, [r1, #MDREFR_OFFSET]
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+setvoltage:
+
+ mov r10, lr
+ bl initPXAvoltage /* In case the board is rebooting with a */
+ mov lr, r10 /* low voltage raise it up to a good one. */
+
+#if 1
+ b initirqs
+#endif
+
+wakeup:
+ /* Are we waking from sleep? */
+ ldr r0, =RCSR
+ ldr r1, [r0]
+ and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r1, [r0]
+ teq r1, #RCSR_SMR
+
+ bne initirqs
+
+ ldr r0, =PSSR
+ mov r1, #PSSR_PH
+ str r1, [r0]
+
+ /* if so, resume at PSPR */
+ ldr r0, =PSPR
+ ldr r1, [r0]
+ mov pc, r1
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off on-chip peripheral clocks (except for memory) */
+ /* for re-configuration. */
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN
+ str r2, [r1]
+
+ /* ... and write the core clock config register */
+ ldr r2, =CFG_CCCR
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* Turn on turbo mode */
+ mrc p14, 0, r2, c6, c0, 0
+ orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
+ mcr p14, 0, r2, c6, c0, 0
+
+ /* Re-write MDREFR */
+ ldr r1, =MEMC_BASE
+ ldr r2, [r1, #MDREFR_OFFSET]
+ str r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#else
+#error "RTC not defined"
+#endif
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+ /* FIXME */
+
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+ .global initPXAvoltage
+
+initPXAvoltage:
+ mov pc, lr
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o update.o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+#if defined(CONFIG_ZEUS)
+
+u8 buf_zeus_ce[] = {
+/*00 01 02 03 04 05 06 07 */
+ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08 09 0a 0b 0c 0d 0e 0f */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10 11 12 13 14 15 16 17 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18 19 1a 1b 1c 1d 1e 1f */
+ 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
+
+u8 buf_zeus_pe[] = {
+
+/* CPU_CLOCK_DIV 1 = 00
+ CPU_PLB_FREQ_DIV 3 = 10
+ OPB_PLB_FREQ_DIV 2 = 01
+ EBC_PLB_FREQ_DIV 2 = 00
+ MAL_PLB_FREQ_DIV 1 = 00
+ PCI_PLB_FRQ_DIV 3 = 10
+ PLL_PLLOUTA = IS SET
+ PLL_OPERATING = IS NOT SET
+ PLL_FDB_MUL 10 = 1010
+ PLL_FWD_DIV_A 3 = 101
+ PLL_FWD_DIV_B 3 = 101
+ TUNE = 0x2be */
+/*00 01 02 03 04 05 06 07 */
+ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08 09 0a 0b 0c 0d 0e 0f */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10 11 12 13 14 15 16 17 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18 19 1a 1b 1c 1d 1e 1f */
+ 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
+
+static int update_boot_eeprom(void)
+{
+ u32 len = 0x20;
+ u8 chip = CFG_I2C_EEPROM_ADDR;
+ u8 *pbuf;
+ u8 base;
+ int i;
+
+ if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
+ pbuf = buf_zeus_pe;
+ base = 0x40;
+ } else {
+ pbuf = buf_zeus_ce;
+ base = 0x00;
+ }
+
+ for (i = 0; i < len; i++, base++) {
+ if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
+ printf("i2c_write fail\n");
+ return 1;
+ }
+ udelay(11000);
+ }
+
+ return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
+{
+ return update_boot_eeprom();
+}
+
+U_BOOT_CMD (
+ update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+ "update_boot_eeprom - update boot eeprom content\n",
+ NULL
+);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REBOOT_MAGIC 0x07081967
+#define REBOOT_NOP 0x00000000
+#define REBOOT_DO_POST 0x00000001
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern env_t *env_ptr;
+extern uchar default_environment[];
+
+ulong flash_get_size(ulong base, int banknum);
+void env_crc_update(void);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+static u32 start_time;
+
+int board_early_init_f(void)
+{
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000);
+ mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
+ mtdcr(uictr, 0x00000000); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ */
+ mtdcr(cpc0_pci, CPC0_PCI_SPE);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 pbcr;
+ int size_val = 0;
+ u32 post_magic;
+ u32 post_val;
+
+ post_magic = in_be32((void *)CFG_POST_MAGIC);
+ post_val = in_be32((void *)CFG_POST_VAL);
+ if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
+ /*
+ * Set special bootline bootparameter to pass this POST boot
+ * mode to Linux to reset the username/password
+ */
+ setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
+
+ /*
+ * Normally don't run POST tests, only when enabled
+ * via the sw-reset button. So disable further tests
+ * upon next bootup here.
+ */
+ out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
+ } else {
+ /*
+ * Only run POST when initiated via the sw-reset button mechanism
+ */
+ post_word_store(0);
+ }
+
+ /*
+ * Get current time
+ */
+ start_time = get_timer(0);
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ mfebc(pb0cr, pbcr);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(pb0cr, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: Zeus-");
+
+ if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
+ puts("PE");
+ else
+ puts("CE");
+
+ puts(" of BulletEndPoint");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ /* both LED's off */
+ gpio_write_bit(CFG_GPIO_LED_RED, 0);
+ gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
+ udelay(10000);
+ /* and on again */
+ gpio_write_bit(CFG_GPIO_LED_RED, 1);
+ gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
+
+ return (0);
+}
+
+static u32 detect_sdram_size(void)
+{
+ u32 val;
+ u32 size;
+
+ mfsdram(mem_mb0cf, val);
+ size = (4 << 20) << ((val & 0x000e0000) >> 17);
+
+ /*
+ * Check if 2nd bank is enabled too
+ */
+ mfsdram(mem_mb1cf, val);
+ if (val & 1)
+ size += (4 << 20) << ((val & 0x000e0000) >> 17);
+
+ return size;
+}
+
+long int initdram (int board_type)
+{
+ return detect_sdram_size();
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+ unsigned long msr;
+ unsigned long total_kbytes;
+
+ total_kbytes = detect_sdram_size();
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_EE));
+
+ for (k = 0; k < total_kbytes ;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ mtmsr(msr);
+
+ return 0;
+}
+#endif
+
+static int default_env_var(char *buf, char *var)
+{
+ char *ptr;
+ char *val;
+
+ /*
+ * Find env variable
+ */
+ ptr = strstr(buf + 4, var);
+ if (ptr == NULL) {
+ printf("ERROR: %s not found!\n", var);
+ return -1;
+ }
+ ptr += strlen(var) + 1;
+
+ /*
+ * Now the ethaddr needs to be updated in the "normal"
+ * environment storage -> redundant flash.
+ */
+ val = ptr;
+ setenv(var, val);
+ printf("Updated %s from eeprom to %s!\n", var, val);
+
+ return 0;
+}
+
+static int restore_default(void)
+{
+ char *buf;
+ char *buf_save;
+ u32 crc;
+
+ /*
+ * Unprotect and erase environment area
+ */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ flash_sect_erase(CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1);
+
+ /*
+ * Now restore default environment from U-Boot image
+ * -> ipaddr, serverip...
+ */
+ memset(env_ptr, 0, sizeof(env_t));
+ memcpy(env_ptr->data, default_environment, ENV_SIZE);
+#ifdef CFG_REDUNDAND_ENVIRONMENT
+ env_ptr->flags = 0xFF;
+#endif
+ env_crc_update();
+ gd->env_valid = 1;
+
+ /*
+ * Read board specific values from I2C EEPROM
+ * and set env variables accordingly
+ * -> ethaddr, eth1addr, serial#
+ */
+ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+ if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+ (u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
+ puts("\nError reading EEPROM!\n");
+ } else {
+ crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
+ if (crc != *(u32 *)buf) {
+ printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf);
+ return -1;
+ }
+
+ default_env_var(buf, "ethaddr");
+ buf += 8 + 18;
+ default_env_var(buf, "eth1addr");
+ buf += 9 + 18;
+ default_env_var(buf, "serial#");
+ }
+
+ /*
+ * Finally save updated env variables back to flash
+ */
+ saveenv();
+
+ free(buf_save);
+
+ return 0;
+}
+
+int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char *buf;
+ char *buf_save;
+ char str[32];
+ u32 crc;
+ char var[32];
+
+ if (argc < 4) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+ memset(buf, 0, FACTORY_RESET_ENV_SIZE);
+
+ strcpy(var, "ethaddr");
+ printf("Setting %s to %s\n", var, argv[1]);
+ sprintf(str, "%s=%s", var, argv[1]);
+ strcpy(buf + 4, str);
+ buf += strlen(str) + 1;
+
+ strcpy(var, "eth1addr");
+ printf("Setting %s to %s\n", var, argv[2]);
+ sprintf(str, "%s=%s", var, argv[2]);
+ strcpy(buf + 4, str);
+ buf += strlen(str) + 1;
+
+ strcpy(var, "serial#");
+ printf("Setting %s to %s\n", var, argv[3]);
+ sprintf(str, "%s=%s", var, argv[3]);
+ strcpy(buf + 4, str);
+
+ crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
+ *(u32 *)buf_save = crc;
+
+ if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+ (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
+ puts("\nError writing EEPROM!\n");
+ return -1;
+ }
+
+ free(buf_save);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setdef, 4, 1, do_set_default,
+ "setdef - write board-specific values to EEPROM (ethaddr...)\n",
+ "ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
+ );
+
+static inline int sw_reset_pressed(void)
+{
+ return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
+}
+
+int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
+{
+ int delta;
+ int count = 0;
+ int post = 0;
+ int factory_reset = 0;
+
+ if (!sw_reset_pressed()) {
+ printf("SW-Reset already high (Button released)\n");
+ printf("-> No action taken!\n");
+ return 0;
+ }
+
+ printf("Waiting for SW-Reset button to be released.");
+
+ while (1) {
+ delta = get_timer(start_time);
+ if (!sw_reset_pressed())
+ break;
+
+ if ((delta > CFG_TIME_POST) && !post) {
+ printf("\nWhen released now, POST tests will be started.");
+ gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
+ post = 1;
+ }
+
+ if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
+ printf("\nWhen released now, factory default values"
+ " will be restored.");
+ gpio_write_bit(CFG_GPIO_LED_RED, 0);
+ factory_reset = 1;
+ }
+
+ udelay(1000);
+ if (!(count++ % 1000))
+ printf(".");
+ }
+
+
+ printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
+
+ if (delta > CFG_TIME_FACTORY_RESET) {
+ printf("Starting factory reset value restoration...\n");
+
+ /*
+ * Restore default setting
+ */
+ restore_default();
+
+ /*
+ * Reset the board for default to become valid
+ */
+ do_reset(NULL, 0, 0, NULL);
+
+ return 0;
+ }
+
+ if (delta > CFG_TIME_POST) {
+ printf("Starting POST configuration...\n");
+
+ /*
+ * Enable POST upon next bootup
+ */
+ out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
+ out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
+ post_bootmode_init();
+
+ /*
+ * Reset the logbuffer for a clean start
+ */
+ logbuff_reset();
+
+ do_reset(NULL, 0, 0, NULL);
+
+ return 0;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ chkreset, 1, 1, do_chkreset,
+ "chkreset- Check for status of SW-reset button and act accordingly\n",
+ NULL
+);
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ u32 post_magic;
+ u32 post_val;
+
+ post_magic = in_be32((void *)CFG_POST_MAGIC);
+ post_val = in_be32((void *)CFG_POST_VAL);
+
+ if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
+ return 1;
+ else
+ return 0;
+}
+#endif /* CONFIG_POST */
return 0;
}
+#elif defined(CONFIG_M68K) /* M68K */
+static void print_str(const char *, const char *);
+
+int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ bd_t *bd = gd->bd;
+ char buf[32];
+
+ print_num ("memstart", (ulong)bd->bi_memstart);
+ print_num ("memsize", (ulong)bd->bi_memsize);
+ print_num ("flashstart", (ulong)bd->bi_flashstart);
+ print_num ("flashsize", (ulong)bd->bi_flashsize);
+ print_num ("flashoffset", (ulong)bd->bi_flashoffset);
+#if defined(CFG_INIT_RAM_ADDR)
+ print_num ("sramstart", (ulong)bd->bi_sramstart);
+ print_num ("sramsize", (ulong)bd->bi_sramsize);
+#endif
+#if defined(CFG_MBAR)
+ print_num ("mbar", bd->bi_mbar_base);
+#endif
+ print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
+#ifdef CONFIG_PCI
+ print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq));
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+ print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));
+ print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
+ print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq));
+#endif
+#if defined(CONFIG_CMD_NET)
+ puts ("ethaddr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+ }
+
+#if defined(CONFIG_HAS_ETH1)
+ puts ("\neth1addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
+ }
+#endif
+
+#if defined(CONFIG_HAS_ETH2)
+ puts ("\neth2addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
+ }
+#endif
+
+#if defined(CONFIG_HAS_ETH3)
+ puts ("\neth3addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
+ }
+#endif
+
+ puts ("\nip_addr = ");
+ print_IPaddr (bd->bi_ip_addr);
+#endif
+ printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
+
+ return 0;
+}
+
#else /* ! PPC, which leaves MIPS */
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("%-12s= 0x%08lX\n", name, value);
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static void print_str(const char *name, const char *str)
{
printf ("%-12s= %6s MHz\n", name, str);
int i;
/* skip kernel length, initrd length, and terminator */
- of_data = (ulong)(&len_ptr[3]);
+ of_flat_tree = (char *)(&len_ptr[3]);
/* skip any additional image length fields */
for (i=2; len_ptr[i]; ++i)
- of_data += 4;
+ of_flat_tree += 4;
/* add kernel length, and align */
- of_data += ntohl(len_ptr[0]);
+ of_flat_tree += ntohl(len_ptr[0]);
if (tail) {
- of_data += 4 - tail;
+ of_flat_tree += 4 - tail;
}
/* add initrd length, and align */
tail = ntohl(len_ptr[1]) % 4;
- of_data += ntohl(len_ptr[1]);
+ of_flat_tree += ntohl(len_ptr[1]);
if (tail) {
- of_data += 4 - tail;
+ of_flat_tree += 4 - tail;
}
+#ifndef CFG_NO_FLASH
+ /* move the blob if it is in flash (set of_data to !null) */
+ if (addr2info ((ulong)of_flat_tree) != NULL)
+ of_data = (ulong)of_flat_tree;
+#endif
+
+
#if defined(CONFIG_OF_FLAT_TREE)
- if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+ if (*((ulong *)(of_flat_tree)) != OF_DT_HEADER) {
#else
- if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
+ if (fdt_check_header (of_flat_tree) != 0) {
#endif
puts ("ERROR: image is not a fdt - "
"must RESET the board to recover.\n");
}
#if defined(CONFIG_OF_FLAT_TREE)
- if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
+ if (((struct boot_param_header *)of_flat_tree)->totalsize !=
+ ntohl (len_ptr[2])) {
#else
- if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
+ if (be32_to_cpu (fdt_totalsize (of_flat_tree)) !=
+ ntohl(len_ptr[2])) {
#endif
puts ("ERROR: fdt size != image size - "
"must RESET the board to recover.\n");
}
#if defined(CONFIG_OF_LIBFDT)
+
+#ifdef CFG_BOOTMAPSZ
+ /*
+ * The blob must be within CFG_BOOTMAPSZ,
+ * so we flag it to be copied if it is not.
+ */
+ if (of_flat_tree >= (char *)CFG_BOOTMAPSZ)
+ of_data = (ulong)of_flat_tree;
+#endif
+
/* move of_flat_tree if needed */
if (of_data) {
int err;
ulong of_start, of_len;
of_len = be32_to_cpu(fdt_totalsize(of_data));
- /* position on a 4K boundary before the initrd/kbd */
- if (initrd_start)
- of_start = initrd_start - of_len;
- else
- of_start = (ulong)kbd - of_len;
+
+ /* position on a 4K boundary before the kbd */
+ of_start = (ulong)kbd - of_len;
of_start &= ~(4096 - 1); /* align on page */
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
of_data, of_data + of_len - 1, of_len, of_len);
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
+ puts ("OK\n");
}
/*
* Add the chosen node if it doesn't exist, add the env and bd_t
* if the user wants it (the logic is in the subroutines).
*/
- if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
- puts ("ERROR: /chosen node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (of_flat_tree) {
+ if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
+ puts ("ERROR: /chosen node create failed - "
+ "must RESET the board to recover.\n");
+ do_reset (cmdtp, flag, argc, argv);
+ }
#ifdef CONFIG_OF_HAS_UBOOT_ENV
- if (fdt_env(of_flat_tree) < 0) {
- puts ("ERROR: /u-boot-env node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (fdt_env(of_flat_tree) < 0) {
+ puts ("ERROR: /u-boot-env node create failed - "
+ "must RESET the board to recover.\n");
+ do_reset (cmdtp, flag, argc, argv);
+ }
#endif
#ifdef CONFIG_OF_HAS_BD_T
- if (fdt_bd_t(of_flat_tree) < 0) {
- puts ("ERROR: /bd_t node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
+ if (fdt_bd_t(of_flat_tree) < 0) {
+ puts ("ERROR: /bd_t node create failed - "
+ "must RESET the board to recover.\n");
+ do_reset (cmdtp, flag, argc, argv);
+ }
#endif
#ifdef CONFIG_OF_BOARD_SETUP
- /* Call the board-specific fixup routine */
- ft_board_setup(of_flat_tree, gd->bd);
+ /* Call the board-specific fixup routine */
+ ft_board_setup(of_flat_tree, gd->bd);
#endif
+ }
#endif /* CONFIG_OF_LIBFDT */
#if defined(CONFIG_OF_FLAT_TREE)
+#ifdef CFG_BOOTMAPSZ
+ /*
+ * The blob must be within CFG_BOOTMAPSZ,
+ * so we flag it to be copied if it is not.
+ */
+ if (of_flat_tree >= (char *)CFG_BOOTMAPSZ)
+ of_data = (ulong)of_flat_tree;
+#endif
+
/* move of_flat_tree if needed */
if (of_data) {
ulong of_start, of_len;
of_len = ((struct boot_param_header *)of_data)->totalsize;
+
/* provide extra 8k pad */
- if (initrd_start)
- of_start = initrd_start - of_len - 8192;
- else
- of_start = (ulong)kbd - of_len - 8192;
+ of_start = (ulong)kbd - of_len - 8192;
of_start &= ~(4096 - 1); /* align on page */
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
of_data, of_data + of_len - 1, of_len, of_len);
printf (" Loading Device Tree to %08lx, end %08lx ... ",
of_start, of_start + of_len - 1);
memmove ((void *)of_start, (void *)of_data, of_len);
+ puts ("OK\n");
}
/*
* Create the /chosen node and modify the blob with board specific
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
+#if (CONFIG_FPGA & CFG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
dataptr = (unsigned char *)fpgadata;
-#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
+#include <asm/io.h>
#if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA)
# include <pcmcia.h>
};
-#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
-
#ifndef CONFIG_AMIGAONEG3SE
static int ide_bus_ok[CFG_IDE_MAXBUS];
#else
#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-static void __inline__ ide_outb(int dev, int port, unsigned char val);
-static unsigned char __inline__ ide_inb(int dev, int port);
+void inline ide_outb(int dev, int port, unsigned char val);
+unsigned char inline ide_inb(int dev, int port);
static void input_data(int dev, ulong *sect_buf, int words);
static void output_data(int dev, ulong *sect_buf, int words);
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
/* ------------------------------------------------------------------------- */
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
-static void __inline__
-ide_outb(int dev, int port, unsigned char val)
+void inline
+__ide_outb(int dev, int port, unsigned char val)
{
debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
- dev, port, val, (ATA_CURR_BASE(dev)+port));
-
- /* Ensure I/O operations complete */
- EIEIO;
- *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))) = val;
-}
-#else /* ! __PPC__ */
-static void __inline__
-ide_outb(int dev, int port, unsigned char val)
-{
- outb(val, ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port));
+ dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
+ outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
}
-#endif /* __PPC__ */
-
+void inline ide_outb (int dev, int port, unsigned char val)
+ __attribute__((weak, alias("__ide_outb")));
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
-static unsigned char __inline__
-ide_inb(int dev, int port)
+unsigned char inline
+__ide_inb(int dev, int port)
{
uchar val;
- /* Ensure I/O operations complete */
- EIEIO;
- val = *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
+ val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
- dev, port, (ATA_CURR_BASE(dev)+port), val);
- return (val);
+ dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val);
+ return val;
}
-#else /* ! __PPC__ */
-static unsigned char __inline__
-ide_inb(int dev, int port)
-{
- return inb(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port));
-}
-#endif /* __PPC__ */
+unsigned char inline ide_inb(int dev, int port)
+ __attribute__((weak, alias("__ide_inb")));
#ifdef __PPC__
# ifdef CONFIG_AMIGAONEG3SE
int rcode = 0;
char *devname;
-#ifdef CONFIG_8xx
+#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x)
mii_init ();
#endif
ulong addr, off, size;
char *cmd, *s;
nand_info_t *nand;
+#ifdef CFG_NAND_QUIET
+ int quiet = CFG_NAND_QUIET;
+#else
int quiet = 0;
+#endif
const char *quiet_str = getenv("quiet");
/* at least two arguments please */
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2] - addr off|partition size\n"
- "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n"
+ "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"
ulong offset, ulong addr, char *cmd)
{
int r;
- char *ep;
+ char *ep, *s;
ulong cnt;
image_header_t *hdr;
+ int jffs2 = 0;
+
+ s = strchr(cmd, '.');
+ if (s != NULL &&
+ (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")))
+ jffs2 = 1;
printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
cnt = nand->oobblock;
- r = nand_read(nand, offset, &cnt, (u_char *) addr);
+ if (jffs2) {
+ nand_read_options_t opts;
+ memset(&opts, 0, sizeof(opts));
+ opts.buffer = (u_char*) addr;
+ opts.length = cnt;
+ opts.offset = offset;
+ opts.quiet = 1;
+ r = nand_read_opts(nand, &opts);
+ } else {
+ r = nand_read(nand, offset, &cnt, (u_char *) addr);
+ }
+
if (r) {
puts("** Read error\n");
show_boot_progress (-56);
print_image_hdr(hdr);
cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
+ if (jffs2) {
+ nand_read_options_t opts;
+ memset(&opts, 0, sizeof(opts));
+ opts.buffer = (u_char*) addr;
+ opts.length = cnt;
+ opts.offset = offset;
+ opts.quiet = 1;
+ r = nand_read_opts(nand, &opts);
+ } else {
+ r = nand_read(nand, offset, &cnt, (u_char *) addr);
+ }
- r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
puts("** Read error\n");
show_boot_progress (-58);
if (argc > 3)
goto usage;
if (argc == 3)
- addr = simple_strtoul(argv[2], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
else
addr = CFG_LOAD_ADDR;
return nand_load_image(cmdtp, &nand_info[dev->id->num],
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
"nboot - boot from NAND device\n",
- "[partition] | [[[loadAddr] dev] offset]\n");
+ "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n");
#endif
ulong addr1 = (ulong)&(flash_addr->data);
ulong addr2 = (ulong)&(flash_addr_new->data);
-#ifdef CONFIG_OMAP2420H4
- int flash_probe(void);
-
- if(flash_probe() == 0)
- goto bad_flash;
-#endif
-
crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc);
crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
gd->env_valid = 2;
}
-#ifdef CONFIG_OMAP2420H4
-bad_flash:
-#endif
return (0);
}
int env_init(void)
{
-#ifdef CONFIG_OMAP2420H4
- int flash_probe(void);
-
- if(flash_probe() == 0)
- goto bad_flash;
-#endif
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
gd->env_addr = (ulong)&(env_ptr->data);
gd->env_valid = 1;
return(0);
}
-#ifdef CONFIG_OMAP2420H4
-bad_flash:
-#endif
+
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 0;
return (0);
* a seperate section. Note that ENV_CRC is only defined when building
* U-Boot itself.
*/
-#if (defined(CONFIG_CMI) || \
- defined(CONFIG_FADS) || \
- defined(CONFIG_HYMOD) || \
- defined(CONFIG_ICU862) || \
- defined(CONFIG_R360MPI) || \
- defined(CONFIG_TQM8xxL) || \
- defined(CONFIG_RRVISION) || \
- defined(CONFIG_TRAB) || \
- defined(CONFIG_PPCHAMELEONEVB) || \
- defined(CONFIG_M5271EVB) || \
- defined(CONFIG_IDMR) || \
- defined(CONFIG_NAND_U_BOOT)) && \
+#if (defined(CFG_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))
int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
- bd_t *bd = gd->bd;
int nodeoffset;
int err;
u32 tmp; /* used to set 32 bit integer properties */
short s_end = info->sector_count - 1; /* index of last sector */
int i;
- debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n",
- (flag & FLAG_PROTECT_SET) ? "ON" :
- (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???",
- from, to);
-
/* Do nothing if input data is bad. */
if (info->sector_count == 0 || info->size == 0 || to < from) {
return;
}
+ debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n",
+ (flag & FLAG_PROTECT_SET) ? "ON" :
+ (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???",
+ from, to);
+
/* There is nothing to do if we have no data about the flash
* or the protect range and flash range don't overlap.
*/
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
-#ifndef CONFIG_LWMON
+#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
struct serial_device *default_serial_console (void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
}
#endif
-static int serial_register (struct serial_device *dev)
+int serial_register (struct serial_device *dev)
{
dev->init += gd->reloc_off;
dev->setbrg += gd->reloc_off;
serial_register(&eserial4_device);
#endif
#endif /* CFG_NS16550_SERIAL */
+#if defined (CONFIG_FFUART)
+ serial_register(&serial_ffuart_device);
+#endif
+#if defined (CONFIG_BTUART)
+ serial_register(&serial_btuart_device);
+#endif
+#if defined (CONFIG_STUART)
+ serial_register(&serial_stuart_device);
+#endif
serial_assign (default_serial_console ()->name);
}
#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
#include <ioports.h>
#endif
-#ifdef CONFIG_AT91RM9200DK /* need this for the at91rm9200dk */
+#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */
#include <asm/io.h>
#include <asm/arch/hardware.h>
#endif
*/
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
{
+#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
uchar tmpdin = 0;
uchar tmpdout = 0;
int j;
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
#elif defined(CONFIG_LPC2292)
+DECLARE_GLOBAL_DATA_PTR;
+
#include <asm/arch/hardware.h>
void serial_setbrg (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned short divisor = 0;
switch (gd->baudrate) {
LIB = $(obj)lib$(SOC).a
COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
- lxt972.o serial.o usb.o
+ lxt972.o serial.o usb.o spi.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
return TRUE;
}
- if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+ if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
/*set MII for 100BaseTX and Half Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
/* set FDX, SPD, Link, INTR masks */
IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
- DM9161_LINK_MASK | DM9161_INTR_MASK);
+ DM9161_LINK_MASK | DM9161_INTR_MASK);
at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
- /* Set the Auto_negotiation Advertisement Register */
- /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+ /* Set the Auto_negotiation Advertisement Register */
+ /* MII advertising for Next page, 100BaseTxFD and HD, */
+ /* 10BaseTFD and HD, IEEE 802.3 */
PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
- DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+ DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
return FALSE;
--- /dev/null
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
+ the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY 200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0: NPCS0%1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
+
+/*-------------------------------------------------------------------*/
+/* SPI DataFlash Init */
+/*-------------------------------------------------------------------*/
+void AT91F_SpiInit(void)
+{
+ /* Configure PIOs */
+ AT91C_BASE_PIOA->PIO_ASR =
+ AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
+ AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
+ AT91C_PA2_SPCK;
+ AT91C_BASE_PIOA->PIO_PDR =
+ AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
+ AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
+ AT91C_PA2_SPCK;
+ /* Enable CLock */
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+ /* Reset the SPI */
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+ /* Configure SPI in Master Mode with No CS selected !!! */
+ AT91C_BASE_SPI->SPI_MR =
+ AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+ /* Configure CS0 and CS3 */
+ *(AT91C_SPI_CSR + 0) =
+ AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+ *(AT91C_SPI_CSR + 3) =
+ AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+}
+
+void AT91F_SpiEnable(int cs)
+{
+ switch(cs) {
+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI->SPI_MR |=
+ ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) &
+ AT91C_SPI_PCS);
+ break;
+ case 3: /* Configure SPI CS3 for Serial DataFlash Card */
+ /* Set up PIO SDC_TYPE to switch on DataFlash Card */
+ /* and not MMC/SDCard */
+ AT91C_BASE_PIOB->PIO_PER =
+ AT91C_PIO_PB7; /* Set in PIO mode */
+ AT91C_BASE_PIOB->PIO_OER =
+ AT91C_PIO_PB7; /* Configure in output */
+ /* Clear Output */
+ AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+ /* Configure PCS */
+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI->SPI_MR |=
+ ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ break;
+ }
+
+ /* SPI_Enable */
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; }
+
+/*---------------------------------------------------------------------------*/
+/* \fn AT91F_SpiWrite */
+/* \brief Set the PDC registers for a transfert */
+/*---------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+ unsigned int timeout;
+
+ pDesc->state = BUSY;
+
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+ /* Initialize the Transmit and Receive Pointer */
+ AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+ AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+ /* Intialize the Transmit and Receive Counters */
+ AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+ AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+ if ( pDesc->tx_data_size != 0 ) {
+ /* Initialize the Next Transmit and Next Receive Pointer */
+ AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+ AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+ /* Intialize the Next Transmit and Next Receive Counters */
+ AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+ AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+ }
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+ timeout = 0;
+
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+ while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
+ ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ pDesc->state = IDLE;
+
+ if (timeout >= CFG_SPI_WRITE_TOUT){
+ printf("Error Timeout\n\r");
+ return DATAFLASH_ERROR;
+ }
+
+ return DATAFLASH_OK;
+}
+#endif
#include <config.h>
#include <version.h>
-
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+#include <led.h>
+#endif
/*
*************************************************************************
orr r0,r0,#0xd3
msr cpsr,r0
+#if CONFIG_AT91RM9200
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+ bl LED_init
+ bl red_LED_on
+#endif
+
+#ifdef CONFIG_BOOTBINFUNC
+/* code based on entry.S from ATMEL */
+#define AT91C_BASE_CKGR 0xFFFFFC20
+#define CKGR_MOR 0
+ /* Get the CKGR Base Address */
+ ldr r1, =AT91C_BASE_CKGR
+
+/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
+/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
+ ldr r0, =0x0000FF01
+ str r0, [r1, #CKGR_MOR]
+ /* Add loop to compensate Main Oscillator startup time */
+ ldr r0, =0x00000010
+LoopOsc:
+ subs r0, r0, #1
+ bhi LoopOsc
+ /* scratch stack */
+ ldr r1, =0x00204000
+ /* Insure word alignment */
+ bic r1, r1, #3
+ /* Init stack SYS */
+ mov sp, r1
+ /*
+ * This does a lot more than just set up the memory, which
+ * is why it's called lowlevelinit
+ */
+ bl lowlevelinit /* in memsetup.S */
+ bl icache_enable;
+ /* ------------------------------------
+ * Read/modify/write CP15 control register
+ * -------------------------------------
+ * read cp15 control register (cp15 r1) in r0
+ * ------------------------------------
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ /* Reset bit :Little Endian end fast bus mode */
+ ldr r3, =0xC0000080
+ /* Set bit :Asynchronous clock mode, Not Fast Bus */
+ ldr r4, =0xC0000000
+ bic r0, r0, r3
+ orr r0, r0, r4
+ /* write r0 in cp15 control register (cp15 r1) */
+ mcr p15, 0, r0, c1, c0, 0
+#endif /* CONFIG_BOOTBINFUNC */
+ /*
+ * relocate exeception table
+ */
+ ldr r0, =_start
+ ldr r1, =0x0
+ mov r2, #16
+copyex:
+ subs r2, r2, #1
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ bne copyex
+#endif
+
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
bl cpu_init_crit
#endif
+#ifdef CONFIG_AT91RM9200
+#ifdef CONFIG_BOOTBINFUNC
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+#endif /* CONFIG_BOOTBINFUNC */
+#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
+#endif
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+
+#else
bl lowlevel_init
+#endif
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
void serial_setbrg(void)
{
int i;
- DECLARE_GLOBAL_DATA_PTR;
calc_baud();
#include <i2c.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ (\
"%0 = w[%1] (z);\n\t"\
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
- DECLARE_GLOBAL_DATA_PTR; \
if (gd->have_console) \
printf(fmt ,##args); \
} while (0)
#include <asm/io.h>
#include "serial.h"
+DECLARE_GLOBAL_DATA_PTR;
+
unsigned long pll_div_fact;
void calc_baud(void)
void serial_setbrg(void)
{
int i;
- DECLARE_GLOBAL_DATA_PTR;
calc_baud();
#include "serial.h"
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
unsigned long pll_div_fact;
void calc_baud(void)
void serial_setbrg(void)
{
int i;
- DECLARE_GLOBAL_DATA_PTR;
calc_baud();
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB = lib$(CPU).a
+
+START = start.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+PLATFORM_CPPFLAGS += -m5307 -fPIC
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+
+ ccm->rcr = CCM_RCR_SOFTRST;
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ u16 msk;
+ u16 id = 0;
+ u8 ver;
+
+ puts("CPU: ");
+ msk = (ccm->cir >> 6);
+ ver = (ccm->cir & 0x003f);
+ switch (msk) {
+ case 0x31:
+ id = 5235;
+ break;
+ }
+
+ if (id) {
+ printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+ ver);
+ printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
+ (int)(gd->cpu_clk / 1000000),
+ (int)(gd->bus_clk / 1000000));
+ }
+
+ return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+ wdp->sr = 0x5555; /* Count register */
+ asm("nop");
+ wdp->sr = 0xAAAA; /* Count register */
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+ /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+ wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ u32 wdog_module = 0;
+
+ /* set timeout and enable watchdog */
+ wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module |= (wdog_module / 8192);
+ wdp->mr = wdog_module;
+
+ wdp->cr = WTM_WCR_EN;
+ puts("WATCHDOG:enabled\n");
+
+ return (0);
+}
+#endif /* CONFIG_WATCHDOG */
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#include <asm/immap.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+ volatile scm_t *scm = (scm_t *) MMAP_SCM;
+
+ /* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+ wdog->cr = 0;
+#endif
+
+ scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+
+ /* Port configuration */
+ gpio->par_cs = 0;
+
+#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
+ fbcs->csar0 = CFG_CS0_BASE;
+ fbcs->cscr0 = CFG_CS0_CTRL;
+ fbcs->csmr0 = CFG_CS0_MASK;
+#endif
+
+#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS1;
+ fbcs->csar1 = CFG_CS1_BASE;
+ fbcs->cscr1 = CFG_CS1_CTRL;
+ fbcs->csmr1 = CFG_CS1_MASK;
+#endif
+
+#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS2;
+ fbcs->csar2 = CFG_CS2_BASE;
+ fbcs->cscr2 = CFG_CS2_CTRL;
+ fbcs->csmr2 = CFG_CS2_MASK;
+#endif
+
+#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS3;
+ fbcs->csar3 = CFG_CS3_BASE;
+ fbcs->cscr3 = CFG_CS3_CTRL;
+ fbcs->csmr3 = CFG_CS3_MASK;
+#endif
+
+#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS4;
+ fbcs->csar4 = CFG_CS4_BASE;
+ fbcs->cscr4 = CFG_CS4_CTRL;
+ fbcs->csmr4 = CFG_CS4_MASK;
+#endif
+
+#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS5;
+ fbcs->csar5 = CFG_CS5_BASE;
+ fbcs->cscr5 = CFG_CS5_CTRL;
+ fbcs->csmr5 = CFG_CS5_MASK;
+#endif
+
+#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS6;
+ fbcs->csar6 = CFG_CS6_BASE;
+ fbcs->cscr6 = CFG_CS6_CTRL;
+ fbcs->csmr6 = CFG_CS6_MASK;
+#endif
+
+#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS_CS7;
+ fbcs->csar7 = CFG_CS7_BASE;
+ fbcs->cscr7 = CFG_CS7_CTRL;
+ fbcs->csmr7 = CFG_CS7_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
+ gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
+#endif
+
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+ break;
+ case 1:
+ gpio->par_uart =
+ (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+ break;
+ case 2:
+ gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+ break;
+ }
+}
--- /dev/null
+/*
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <asm/immap.h>
+
+int interrupt_init(void)
+{
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+ /* Make sure all interrupts are disabled */
+ intp->imrl0 |= 0x1;
+
+ enable_interrupts();
+ return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+ intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->imrl0 &= ~INTC_IPRL_INT0;
+ intp->imrl0 &= ~CFG_TMRINTR_MASK;
+}
+#endif
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+ pll->syncr = PLL_SYNCR_MFD(1);
+
+ while (!(pll->synsr & PLL_SYNSR_LOCK));
+
+ gd->bus_clk = CFG_CLK;
+ gd->cpu_clk = (gd->bus_clk * 2);
+
+ return (0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "version.h"
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define _START _start
+#define _FAULT _fault
+
+#define SAVE_ALL \
+ move.w #0x2700,%sr; /* disable intrs */ \
+ subl #60,%sp; /* space for 15 regs */ \
+ moveml %d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL \
+ moveml %sp@,%d0-%d7/%a0-%a6; \
+ addl #60,%sp; /* space for 15 regs */ \
+ rte;
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+INITSP: .long 0x00000000 /* Initial SP */
+INITPC: .long _START /* Initial PC */
+vector02: .long _FAULT /* Access Error */
+vector03: .long _FAULT /* Address Error */
+vector04: .long _FAULT /* Illegal Instruction */
+vector05: .long _FAULT /* Reserved */
+vector06: .long _FAULT /* Reserved */
+vector07: .long _FAULT /* Reserved */
+vector08: .long _FAULT /* Privilege Violation */
+vector09: .long _FAULT /* Trace */
+vector0A: .long _FAULT /* Unimplemented A-Line */
+vector0B: .long _FAULT /* Unimplemented F-Line */
+vector0C: .long _FAULT /* Debug Interrupt */
+vector0D: .long _FAULT /* Reserved */
+vector0E: .long _FAULT /* Format Error */
+vector0F: .long _FAULT /* Unitialized Int. */
+
+/* Reserved */
+vector10_17:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18: .long _FAULT /* Spurious Interrupt */
+vector19: .long _FAULT /* Autovector Level 1 */
+vector1A: .long _FAULT /* Autovector Level 2 */
+vector1B: .long _FAULT /* Autovector Level 3 */
+vector1C: .long _FAULT /* Autovector Level 4 */
+vector1D: .long _FAULT /* Autovector Level 5 */
+vector1E: .long _FAULT /* Autovector Level 6 */
+vector1F: .long _FAULT /* Autovector Level 7 */
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector30_3F:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+ .text
+
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr /* Mask off Interrupt */
+
+ /* Set vector base register at the beginning of the Flash */
+ move.l #CFG_FLASH_BASE, %d0
+ movec %d0, %VBR
+
+ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+
+ /* invalidate and disable cache */
+ move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ nop
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
+ /* set stackpointer to end of internal ram to get some stackspace for the
+ first c-code */
+ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ move.l #__got_start, %a5 /* put relocation table address to a5 */
+
+ bsr cpu_init_f /* run low-level CPU init code (from flash) */
+ bsr board_init_f /* run low-level board init code (from flash) */
+
+ /* board_init_f() does not return */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CFG_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ move.l %a0, %d1
+ add.l #(_ebss - CFG_MONITOR_BASE),%d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ move.l %a1,%a5 /* * fix got pointer register a5 */
+
+ move.l %a0, %a2
+ add.l #(__got_end - CFG_MONITOR_BASE),%a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start,%d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+ jsr (%a1)
+
+/*------------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ jmp _fault
+ .globl _exc_handler
+
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*------------------------------------------------------------------------------*/
+/* cache functions */
+ .globl icache_enable
+icache_enable:
+ move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ nop
+ move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
+ movec %d0, %ACR0 /* Enable cache */
+ move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
+ movec %d0, %ACR1 /* Enable cache */
+
+ move.l #0x80400100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ nop
+
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl icache_disable
+icache_disable:
+ move.l #0x00000100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Disable cache */
+ clr.l %d0 /* Setup cache mask */
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ moveq #0, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl icache_status
+icache_status:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l (%a1), %d0
+ rts
+
+ .globl icache_invalid
+icache_invalid:
+ move.l #0x80600100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ nop
+ rts
+
+ .globl dcache_enable
+dcache_enable:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+
+ /* No dcache, just a dummy function */
+ .globl dcache_disable
+dcache_disable:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ moveq #0, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl dcache_status
+dcache_status:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l (%a1), %d0
+ rts
+
+/*------------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
LIB = $(obj)lib$(CPU).a
-START =
-COBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
+START = start.o
+COBJS = interrupts.o cpu.o speed.o cpu_init.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <asm/immap.h>
#ifdef CONFIG_M5271
-#include <asm/immap_5271.h>
-#include <asm/m5271.h>
-#endif
-
-#ifdef CONFIG_M5272
-#include <asm/immap_5272.h>
-#include <asm/m5272.h>
-#endif
-
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
-#endif
-
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#endif
-
-#ifdef CONFIG_M5271
/*
* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
* determine which one we are running on, based on the Chip Identification
* Register (CIR).
*/
-int checkcpu (void)
+int checkcpu(void)
{
char buf[32];
unsigned short cir; /* Chip Identification Register */
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CFG_CLK));
+ cpu_model, prn, strmhz(buf, CFG_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
- " (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CFG_CLK));
+ " (PIN: 0x%x) rev. %hu, at %s MHz\n",
+ pin, prn, strmhz(buf, CFG_CLK));
return 0;
}
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
mbar_writeByte(MCF_RCM_RCR,
- MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
+ MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
return 0;
};
#if defined(CONFIG_WATCHDOG)
-void watchdog_reset (void)
+void watchdog_reset(void)
{
mbar_writeShort(MCF_WTM_WSR, 0x5555);
mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
}
-int watchdog_disable (void)
+int watchdog_disable(void)
{
mbar_writeShort(MCF_WTM_WCR, 0);
return (0);
}
-int watchdog_init (void)
+int watchdog_init(void)
{
mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
return (0);
}
-#endif /* #ifdef CONFIG_WATCHDOG */
+#endif /* #ifdef CONFIG_WATCHDOG */
#endif
#ifdef CONFIG_M5272
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
- volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR);
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdp->wdog_wrrr = 0;
- udelay (1000);
+ udelay(1000);
/* enable watchdog, set timeout to 0 and wait */
wdp->wdog_wrrr = 1;
- while (1);
+ while (1) ;
/* we don't return! */
return 0;
};
-int checkcpu(void) {
- ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR);
+int checkcpu(void)
+{
+ volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
uchar msk;
- char *suf;
+ char *suf;
- puts ("CPU: ");
- msk = (*dirp > 28) & 0xf;
+ puts("CPU: ");
+ msk = (sysctrl->sc_dir > 28) & 0xf;
switch (msk) {
- case 0x2: suf = "1K75N"; break;
- case 0x4: suf = "3K75N"; break;
- default:
- suf = NULL;
- printf ("Freescale MCF5272 (Mask:%01x)\n", msk);
- break;
- }
+ case 0x2:
+ suf = "1K75N";
+ break;
+ case 0x4:
+ suf = "3K75N";
+ break;
+ default:
+ suf = NULL;
+ printf("Freescale MCF5272 (Mask:%01x)\n", msk);
+ break;
+ }
if (suf)
- printf ("Freescale MCF5272 %s\n", suf);
+ printf("Freescale MCF5272 %s\n", suf);
return 0;
};
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
-void watchdog_reset (void)
+void watchdog_reset(void)
{
- volatile immap_t * regp = (volatile immap_t *)CFG_MBAR;
- regp->wdog_reg.wdog_wcr = 0;
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdt->wdog_wcr = 0;
}
-int watchdog_disable (void)
+int watchdog_disable(void)
{
- volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
- regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
- regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */
+ wdt->wdog_wcr = 0; /* reset watchdog counter */
+ wdt->wdog_wirr = 0; /* disable watchdog interrupt */
+ wdt->wdog_wrrr = 0; /* disable watchdog timer */
- puts ("WATCHDOG:disabled\n");
+ puts("WATCHDOG:disabled\n");
return (0);
}
-int watchdog_init (void)
+int watchdog_init(void)
{
- volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
+ wdt->wdog_wirr = 0; /* disable watchdog interrupt */
/* set timeout and enable watchdog */
- regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
- regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
+ wdt->wdog_wrrr =
+ ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ wdt->wdog_wcr = 0; /* reset watchdog counter */
- puts ("WATCHDOG:enabled\n");
+ puts("WATCHDOG:enabled\n");
return (0);
}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
-#endif /* #ifdef CONFIG_M5272 */
+#endif /* #ifdef CONFIG_WATCHDOG */
+#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5282
-int checkcpu (void)
+int checkcpu(void)
{
unsigned char resetsource = MCFRESET_RSR;
- printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
- MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
- printf ("Reset:%s%s%s%s%s%s%s\n",
- (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
- (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
- (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
- (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
- (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
- (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
- (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""
- );
+ printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
+ MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
+ printf("Reset:%s%s%s%s%s%s%s\n",
+ (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
+ (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
+ (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
+ (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
+ (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
+ (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
+ (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
return 0;
}
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
};
#endif
-#ifdef CONFIG_M5249 /* test-only: todo... */
-int checkcpu (void)
+#ifdef CONFIG_M5249
+int checkcpu(void)
{
char buf[32];
- printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK));
+ printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
+ strmhz(buf, CFG_CLK));
return 0;
}
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
- while (1);
+ while (1) ;
+
+ /* we don't return! */
+ return 0;
+};
+#endif
+
+#ifdef CONFIG_M5253
+int checkcpu(void)
+{
+ char buf[32];
+
+ unsigned char resetsource = mbar_readLong(SIM_RSR);
+ printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
+ strmhz(buf, CFG_CLK));
+
+ if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
+ printf("Reset:%s%s\n",
+ (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
+ : "",
+ (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
+ "");
+ }
+ return 0;
+}
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+ /* enable watchdog, set timeout to 0 and wait */
+ mbar_writeByte(SIM_SYPCR, 0xc0);
+ while (1) ;
/* we don't return! */
return 0;
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <common.h>
#include <watchdog.h>
+#include <asm/immap.h>
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-#endif
+#if defined(CONFIG_M5253)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
+ mbar_writeByte(MCFSIM_SYPCR, 0x00);
+ mbar_writeByte(MCFSIM_SWIVR, 0x0f);
+ mbar_writeByte(MCFSIM_SWSR, 0x00);
+ mbar_writeByte(MCFSIM_SWDICR, 0x00);
+ mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
+ mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
+ mbar_writeByte(MCFSIM_I2CICR, 0x00);
+ mbar_writeByte(MCFSIM_UART1ICR, 0x00);
+ mbar_writeByte(MCFSIM_UART2ICR, 0x00);
+ mbar_writeByte(MCFSIM_ICR6, 0x00);
+ mbar_writeByte(MCFSIM_ICR7, 0x00);
+ mbar_writeByte(MCFSIM_ICR8, 0x00);
+ mbar_writeByte(MCFSIM_ICR9, 0x00);
+ mbar_writeByte(MCFSIM_QSPIICR, 0x00);
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
-#endif
+ mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
+ mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
+ mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
-#endif
+ /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#endif
+ /*
+ * Setup chip selects...
+ */
+
+ mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
+ mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
+ mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
+
+ mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
+ mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
+ mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ break;
+ case 1:
+ break;
+ case 2:
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5253) */
#if defined(CONFIG_M5271)
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* Disable the watchdog if we aren't using it */
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
- while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
-
- /* Enable UART pins */
- mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
- MCF_GPIO_PAR_UART_U0RXD |
- MCF_GPIO_PAR_UART_U1RXD_UART1 |
- MCF_GPIO_PAR_UART_U1TXD_UART1);
-
- /* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
+ MCF_GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+ mbar_writeShort(MCF_GPIO_PAR_UART,
+ MCF_GPIO_PAR_UART_U1RXD_UART1 |
+ MCF_GPIO_PAR_UART_U1TXD_UART1);
+ break;
+ case 2:
+ mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
+ break;
+ }
+}
#endif
#if defined(CONFIG_M5272)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile immap_t *regp = (immap_t *)CFG_MBAR;
-
- volatile unsigned char *mbar;
- mbar = (volatile unsigned char *) CFG_MBAR;
+ volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
+ volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+ volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- regp->sysctrl_reg.sc_scr = CFG_SCR;
- regp->sysctrl_reg.sc_spr = CFG_SPR;
+ sysctrl->sc_scr = CFG_SCR;
+ sysctrl->sc_spr = CFG_SPR;
/* Setup Ports: */
- regp->gpio_reg.gpio_pacnt = CFG_PACNT;
- regp->gpio_reg.gpio_paddr = CFG_PADDR;
- regp->gpio_reg.gpio_padat = CFG_PADAT;
- regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
- regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
- regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
- regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
+ gpio->gpio_pacnt = CFG_PACNT;
+ gpio->gpio_paddr = CFG_PADDR;
+ gpio->gpio_padat = CFG_PADAT;
+ gpio->gpio_pbcnt = CFG_PBCNT;
+ gpio->gpio_pbddr = CFG_PBDDR;
+ gpio->gpio_pbdat = CFG_PBDAT;
+ gpio->gpio_pdcnt = CFG_PDCNT;
/* Memory Controller: */
- regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
- regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
+ csctrl->cs_br0 = CFG_BR0_PRELIM;
+ csctrl->cs_or0 = CFG_OR0_PRELIM;
#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
- regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
+ csctrl->cs_br1 = CFG_BR1_PRELIM;
+ csctrl->cs_or1 = CFG_OR1_PRELIM;
#endif
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
- regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
+ csctrl->cs_br2 = CFG_BR2_PRELIM;
+ csctrl->cs_or2 = CFG_OR2_PRELIM;
#endif
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
- regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
+ csctrl->cs_br3 = CFG_BR3_PRELIM;
+ csctrl->cs_or3 = CFG_OR3_PRELIM;
#endif
#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
- regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
+ csctrl->cs_br4 = CFG_BR4_PRELIM;
+ csctrl->cs_or4 = CFG_OR4_PRELIM;
#endif
#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
- regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
+ csctrl->cs_br5 = CFG_BR5_PRELIM;
+ csctrl->cs_or5 = CFG_OR5_PRELIM;
#endif
#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
- regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
+ csctrl->cs_br6 = CFG_BR6_PRELIM;
+ csctrl->cs_or6 = CFG_OR6_PRELIM;
#endif
#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
- regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
+ csctrl->cs_br7 = CFG_BR7_PRELIM;
+ csctrl->cs_or7 = CFG_OR7_PRELIM;
#endif
-#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
/* enable instruction cache now */
icache_enable();
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
-#endif /* #if defined(CONFIG_M5272) */
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-#ifdef CONFIG_M5282
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+ gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+ break;
+ case 1:
+ gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+ gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5272) */
+
+#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
*
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* disable watchdog if we aren't using it */
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
- MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ MCFCLOCK_SYNCR =
+ MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
+
+ MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
#ifdef CFG_PEPAR
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
defined(CFG_CS0_WS)
- MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
-
- #if (CFG_CS0_WIDTH == 8)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS0_WIDTH == 16)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS0_WIDTH == 32)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
- #endif
- MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
- |CFG_CS0_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS0_RO != 0)
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
- |MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
- #endif
+ MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
+
+#if (CFG_CS0_WIDTH == 8)
+#define CFG_CS0_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS0_WIDTH == 16)
+#define CFG_CS0_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS0_WIDTH == 32)
+#define CFG_CS0_PS MCFCSM_CSCR_PS_32
+#else
+#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
+#endif
+ MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
+ | CFG_CS0_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS0_RO != 0)
+ MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
- #waring "Chip Select 0 are not initialized/used"
+ MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
+#endif
+#else
+#waring "Chip Select 0 are not initialized/used"
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
- #if (CFG_CS1_WIDTH == 8)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS1_WIDTH == 16)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS1_WIDTH == 32)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
- #endif
- MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
- |CFG_CS1_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS1_RO != 0)
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
+#if (CFG_CS1_WIDTH == 8)
+#define CFG_CS1_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS1_WIDTH == 16)
+#define CFG_CS1_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS1_WIDTH == 32)
+#define CFG_CS1_PS MCFCSM_CSCR_PS_32
+#else
+#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
+#endif
+ MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
+ | CFG_CS1_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS1_RO != 0)
+ MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
+ | MCFCSM_CSMR_V;
+#endif
#else
- #warning "Chip Select 1 are not initialized/used"
+#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
- #if (CFG_CS2_WIDTH == 8)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS2_WIDTH == 16)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS2_WIDTH == 32)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
- #endif
- MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
- |CFG_CS2_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS2_RO != 0)
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
+#if (CFG_CS2_WIDTH == 8)
+#define CFG_CS2_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS2_WIDTH == 16)
+#define CFG_CS2_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS2_WIDTH == 32)
+#define CFG_CS2_PS MCFCSM_CSCR_PS_32
#else
- #warning "Chip Select 2 are not initialized/used"
+#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
+#endif
+ MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
+ | CFG_CS2_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS2_RO != 0)
+ MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
+ | MCFCSM_CSMR_V;
+#endif
+#else
+#warning "Chip Select 2 are not initialized/used"
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
- #if (CFG_CS3_WIDTH == 8)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS3_WIDTH == 16)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS3_WIDTH == 32)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
- #endif
- MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
- |CFG_CS3_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS3_RO != 0)
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
+#if (CFG_CS3_WIDTH == 8)
+#define CFG_CS3_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS3_WIDTH == 16)
+#define CFG_CS3_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS3_WIDTH == 32)
+#define CFG_CS3_PS MCFCSM_CSCR_PS_32
#else
- #warning "Chip Select 3 are not initialized/used"
+#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
#endif
+ MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
+ | CFG_CS3_PS | MCFCSM_CSCR_AA;
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
+#if (CFG_CS3_RO != 0)
+ MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
+ | MCFCSM_CSMR_V;
+#endif
+#else
+#warning "Chip Select 3 are not initialized/used"
+#endif
+
+#endif /* CONFIG_MONITOR_IS_IN_RAM */
/* defer enabling cache until boot (see do_go) */
/* icache_enable(); */
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ MCFGPIO_PUAPAR &= 0xFc;
+ MCFGPIO_PUAPAR |= 0x03;
+ break;
+ case 1:
+ MCFGPIO_PUAPAR &= 0xF3;
+ MCFGPIO_PUAPAR |= 0x0C;
+ break;
+ case 2:
+ MCFGPIO_PASPAR &= 0xFF0F;
+ MCFGPIO_PASPAR |= 0x00A0;
+ break;
+ }
+}
#endif
#if defined(CONFIG_M5249)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
-#ifndef CFG_PLL_BYPASS
- /*
- * Setup the PLL to run at the specified speed
- *
- */
- volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
- unsigned long pllcr;
-#ifdef CFG_FAST_CLK
- pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
-#else
- pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
-#endif
- cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
- pllcr ^= 0x00000001; /* Set pll bypass to 1 */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
- udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CFG_PLL_BYPASS */
-
/*
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
- * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
- * which is their primary function.
- * ~Jeremy
+ * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
+ * which is their primary function.
+ * ~Jeremy
*/
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
* ~Jeremy
*
*/
- mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
+ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
mbar_writeByte(MCFSIM_SWSR, 0x00);
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
- mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
+ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
/* Setup interrupt priorities for gpio7 */
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
-#endif /* #if defined(CONFIG_M5249) */
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ break;
+ case 1:
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5249) */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/fec.h>
-
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-#endif
-
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
-#endif
-
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
-#endif
-
-#include <net.h>
-#include <command.h>
-
-#ifdef CONFIG_M5272
-#define FEC_ADDR (CFG_MBAR + 0x840)
-#endif
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
-#define FEC_ADDR (CFG_MBAR + 0x1000)
-#endif
-
-#undef ET_DEBUG
-#undef MII_DEBUG
-
-#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
-
-#ifdef CFG_DISCOVER_PHY
-#include <miiphy.h>
-static void mii_discover_phy (void);
-#endif
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH 1520
-
-#define TX_BUF_CNT 2
-
-#define TOUT_LOOP 100
-
-#define PKT_MAXBUF_SIZE 1518
-#define PKT_MINBUF_SIZE 64
-#define PKT_MAXBLR_SIZE 1520
-
-
-static char txbuf[DBUF_LENGTH];
-
-static uint rxIdx; /* index of the current RX buffer */
-static uint txIdx; /* index of the current TX buffer */
-
-/*
- * FEC Ethernet Tx and Rx buffer descriptors allocated at the
- * immr->udata_bd address on Dual-Port RAM
- * Provide for Double Buffering
- */
-
-typedef volatile struct CommonBufferDescriptor {
- cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
- cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
-} RTXBD;
-
-static RTXBD *rtx = NULL;
-
-int eth_send (volatile void *packet, int length)
-{
- int j, rc;
- volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
-
- /* section 16.9.23.3
- * Wait for ready
- */
- j = 0;
- while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
- && (j < TOUT_LOOP)) {
- udelay (1);
- j++;
- }
- if (j >= TOUT_LOOP) {
- printf ("TX not ready\n");
- }
-
- rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
- rtx->txbd[txIdx].cbd_datlen = length;
- rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
-
- /* Activate transmit Buffer Descriptor polling */
- fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
-
- j = 0;
- while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
- && (j < TOUT_LOOP)) {
- udelay (1);
- j++;
- }
- if (j >= TOUT_LOOP) {
- printf ("TX timeout\n");
- }
-#ifdef ET_DEBUG
- printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
- __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
- (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
-#endif
-
- /* return only status bits */ ;
- rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
-
- txIdx = (txIdx + 1) % TX_BUF_CNT;
-
- return rc;
-}
-
-int eth_rx (void)
-{
- int length;
- volatile fec_t *fecp = (fec_t *) FEC_ADDR;
-
- for (;;) {
- /* section 16.9.23.2 */
- if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
-
- length = rtx->rxbd[rxIdx].cbd_datlen;
-
- if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
-#ifdef ET_DEBUG
- printf ("%s[%d] err: %x\n",
- __FUNCTION__, __LINE__,
- rtx->rxbd[rxIdx].cbd_sc);
-#endif
- } else {
- /* Pass the packet up to the protocol layers. */
- NetReceive (NetRxPackets[rxIdx], length - 4);
- }
-
- /* Give the buffer back to the FEC. */
- rtx->rxbd[rxIdx].cbd_datlen = 0;
-
- /* wrap around buffer index when necessary */
- if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
- (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
- rxIdx = 0;
- } else {
- rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
- rxIdx++;
- }
-
- /* Try to fill Buffer Descriptors */
- fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
- }
-
- return length;
-}
-
-/**************************************************************
- *
- * FEC Ethernet Initialization Routine
- *
- *************************************************************/
-#define FEC_ECNTRL_ETHER_EN 0x00000002
-#define FEC_ECNTRL_RESET 0x00000001
-
-#define FEC_RCNTRL_BC_REJ 0x00000010
-#define FEC_RCNTRL_PROM 0x00000008
-#define FEC_RCNTRL_MII_MODE 0x00000004
-#define FEC_RCNTRL_DRT 0x00000002
-#define FEC_RCNTRL_LOOP 0x00000001
-
-#define FEC_TCNTRL_FDEN 0x00000004
-#define FEC_TCNTRL_HBC 0x00000002
-#define FEC_TCNTRL_GTS 0x00000001
-
-#define FEC_RESET_DELAY 50000
-
-int eth_init (bd_t * bd)
-{
-#ifndef CFG_ENET_BD_BASE
- DECLARE_GLOBAL_DATA_PTR;
-#endif
- int i;
- volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
-
- /* Whack a reset.
- * A delay is required between a reset of the FEC block and
- * initialization of other FEC registers because the reset takes
- * some time to complete. If you don't delay, subsequent writes
- * to FEC registers might get killed by the reset routine which is
- * still in progress.
- */
- fecp->fec_ecntrl = FEC_ECNTRL_RESET;
- for (i = 0;
- (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
- ++i) {
- udelay (1);
- }
- if (i == FEC_RESET_DELAY) {
- printf ("FEC_RESET_DELAY timeout\n");
- return 0;
- }
-
- /* We use strictly polling mode only
- */
- fecp->fec_imask = 0;
-
- /* Clear any pending interrupt */
- fecp->fec_ievent = 0xffffffff;
-
- /* Set station address */
-#define ea bd->bi_enetaddr
- fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
- (ea[2] << 8) | (ea[3]);
- fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
-#ifdef ET_DEBUG
- printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
- ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
-#endif
-#undef ea
-
-#ifdef CONFIG_M5271
- /* Clear multicast address hash table
- */
- fecp->fec_ghash_table_high = 0;
- fecp->fec_ghash_table_low = 0;
-
- /* Clear individual address hash table
- */
- fecp->fec_ihash_table_high = 0;
- fecp->fec_ihash_table_low = 0;
-#else
- /* Clear multicast address hash table
- */
-#ifdef CONFIG_M5282
- fecp->fec_ihash_table_high = 0;
- fecp->fec_ihash_table_low = 0;
-#else
- fecp->fec_hash_table_high = 0;
- fecp->fec_hash_table_low = 0;
-#endif
-#endif
-
- /* Set maximum receive buffer size.
- */
- fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
-
- /*
- * Setup Buffers and Buffer Desriptors
- */
- rxIdx = 0;
- txIdx = 0;
-
- if (!rtx) {
-#ifdef CFG_ENET_BD_BASE
- rtx = (RTXBD *) CFG_ENET_BD_BASE;
-#else
- rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
- (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
- +0xFF)
- & ~0xFF)
- );
- debug("set ENET_DB_BASE to %lX\n",(long) rtx);
-#endif
- }
-
- /*
- * Setup Receiver Buffer Descriptors (13.14.24.18)
- * Settings:
- * Empty, Wrap
- */
- for (i = 0; i < PKTBUFSRX; i++) {
- rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx->rxbd[i].cbd_datlen = 0; /* Reset */
- rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
- }
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
- /*
- * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
- * Settings:
- * Last, Tx CRC
- */
- for (i = 0; i < TX_BUF_CNT; i++) {
- rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
- rtx->txbd[i].cbd_datlen = 0; /* Reset */
- rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
- }
- rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
- /* Set receive and transmit descriptor base
- */
- fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
- fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
-
- /* Enable MII mode
- */
-
-#if 0 /* Full duplex mode */
- fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
- fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
-#else /* Half duplex mode */
- fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
- fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl = 0;
-#endif
- /* Set MII speed */
- fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
- fecp->fec_mii_speed *= 2;
-
- /* Configure port B for MII.
- */
- /* port initialization was already made in cpu_init_f() */
-
- /* Now enable the transmit and receive processing
- */
- fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
-
-#ifdef CFG_DISCOVER_PHY
- /* wait for the PHY to wake up after reset */
- mii_discover_phy ();
-#endif
-
- /* And last, try to fill Rx Buffer Descriptors */
- fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
-
- return 1;
-}
-
-void eth_halt (void)
-{
- volatile fec_t *fecp = (fec_t *) FEC_ADDR;
-
- fecp->fec_ecntrl = 0;
-}
-
-
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-
-static int phyaddr = -1; /* didn't find a PHY yet */
-static uint phytype;
-
-/* Make MII read/write commands for the FEC.
-*/
-
-#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
- (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
- (REG & 0x1f) << 18) | \
- (VAL & 0xffff))
-
-/* Interrupt events/masks.
-*/
-#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
-#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
-#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
-#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
-#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
-#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
-#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
-#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
-#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
-#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
-
-/* PHY identification
- */
-#define PHY_ID_LXT970 0x78100000 /* LXT970 */
-#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
-#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
-#define PHY_ID_QS6612 0x01814400 /* QS6612 */
-#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
-#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
-#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
-
-/* send command to phy using mii, wait for result */
-static uint mii_send (uint mii_cmd)
-{
- uint mii_reply;
- volatile fec_t *ep = (fec_t *) (FEC_ADDR);
-
- ep->fec_mii_data = mii_cmd; /* command to phy */
-
- /* wait for mii complete */
- while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
- mii_reply = ep->fec_mii_data; /* result from phy */
- ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
-#ifdef ET_DEBUG
- printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
- __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
- return (mii_reply & 0xffff); /* data read from phy */
-}
-#endif
-
-#if defined(CFG_DISCOVER_PHY)
-static void mii_discover_phy (void)
-{
-#define MAX_PHY_PASSES 11
- uint phyno;
- int pass;
-
- phyaddr = -1; /* didn't find a PHY yet */
- for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
- if (pass > 1) {
- /* PHY may need more time to recover from reset.
- * The LXT970 needs 50ms typical, no maximum is
- * specified, so wait 10ms before try again.
- * With 11 passes this gives it 100ms to wake up.
- */
- udelay (10000); /* wait 10ms */
- }
- for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
- phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
- printf ("PHY type 0x%x pass %d type ", phytype, pass);
-#endif
- if (phytype != 0xffff) {
- phyaddr = phyno;
- phytype <<= 16;
- phytype |= mii_send (mk_mii_read (phyno,
- PHY_PHYIDR2));
-
-#ifdef ET_DEBUG
- printf ("PHY @ 0x%x pass %d type ", phyno,
- pass);
- switch (phytype & 0xfffffff0) {
- case PHY_ID_LXT970:
- printf ("LXT970\n");
- break;
- case PHY_ID_LXT971:
- printf ("LXT971\n");
- break;
- case PHY_ID_82555:
- printf ("82555\n");
- break;
- case PHY_ID_QS6612:
- printf ("QS6612\n");
- break;
- case PHY_ID_AMD79C784:
- printf ("AMD79C784\n");
- break;
- case PHY_ID_LSI80225B:
- printf ("LSI L80225/B\n");
- break;
- default:
- printf ("0x%08x\n", phytype);
- break;
- }
-#endif
- }
- }
- }
- if (phyaddr < 0) {
- printf ("No PHY device found.\n");
- }
-}
-#endif /* CFG_DISCOVER_PHY */
-
-#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII)
-
-static int mii_init_done = 0;
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_init (void)
-{
- volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
-
- int i;
-
- if (mii_init_done != 0) {
- return;
- }
-
- /* Whack a reset.
- * A delay is required between a reset of the FEC block and
- * initialization of other FEC registers because the reset takes
- * some time to complete. If you don't delay, subsequent writes
- * to FEC registers might get killed by the reset routine which is
- * still in progress.
- */
-
- fecp->fec_ecntrl = FEC_ECNTRL_RESET;
- for (i = 0;
- (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
- ++i) {
- udelay (1);
- }
- if (i == FEC_RESET_DELAY) {
- printf ("FEC_RESET_DELAY timeout\n");
- return;
- }
-
- /* We use strictly polling mode only
- */
- fecp->fec_imask = 0;
-
- /* Clear any pending interrupt
- */
- fecp->fec_ievent = 0xffffffff;
-
- /* Set MII speed */
- fecp->fec_mii_speed = 0x0e;
-
- /* Configure port B for MII.
- */
- /* port initialization was already made in cpu_init_f() */
-
- /* Now enable the transmit and receive processing */
- fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
-
- mii_init_done = 1;
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- * no PHY connected...
- * For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- * Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcf52x2_miiphy_read (char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
- rdreg = mii_send (mk_mii_read (addr, reg));
-
- *value = rdreg;
-
-#ifdef MII_DEBUG
- printf ("0x%04x\n", *value);
-#endif
-
- return 0;
-}
-
-int mcf52x2_miiphy_write (char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- short rdreg; /* register working value */
-
-#ifdef MII_DEBUG
- printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
- rdreg = mii_send (mk_mii_write (addr, reg, value));
-
-#ifdef MII_DEBUG
- printf ("0x%04x\n", value);
-#endif
-
- return 0;
-}
-#endif
-#endif
-
-int mcf52x2_miiphy_initialize(bd_t *bis)
-{
-#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
-#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII)
- miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
-#endif
-#endif
- return 0;
-}
/*
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
-
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-#endif
+#include <asm/immap.h>
#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
-#endif
-
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
-#endif
-
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#endif
-
-
-#define NR_IRQS 31
-
-/*
- * Interrupt vector functions.
- */
-struct interrupt_action {
- interrupt_handler_t *handler;
- void *arg;
-};
-
-static struct interrupt_action irq_vecs[NR_IRQS];
-
-static __inline__ unsigned short get_sr (void)
+int interrupt_init(void)
{
- unsigned short sr;
-
- asm volatile ("move.w %%sr,%0":"=r" (sr):);
+ volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
- return sr;
-}
-
-static __inline__ void set_sr (unsigned short sr)
-{
- asm volatile ("move.w %0,%%sr"::"r" (sr));
-}
-
-/************************************************************************/
-/*
- * Install and free an interrupt handler
- */
-void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
-{
-#ifdef CONFIG_M5272
- volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
-#endif
- int vec_base = 0;
-
-#ifdef CONFIG_M5272
- vec_base = intp->int_pivr & 0xe0;
-#endif
-
- if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) {
- printf ("irq_install_handler: wrong interrupt vector %d\n",
- vec);
- return;
- }
-
- irq_vecs[vec - vec_base].handler = handler;
- irq_vecs[vec - vec_base].arg = arg;
-}
-
-void irq_free_handler (int vec)
-{
-#ifdef CONFIG_M5272
- volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
-#endif
- int vec_base = 0;
-
-#ifdef CONFIG_M5272
- vec_base = intp->int_pivr & 0xe0;
-#endif
+ /* disable all external interrupts */
+ intp->int_icr1 = 0x88888888;
+ intp->int_icr2 = 0x88888888;
+ intp->int_icr3 = 0x88888888;
+ intp->int_icr4 = 0x88888888;
+ intp->int_pitr = 0x00000000;
+ /* initialize vector register */
+ intp->int_pivr = 0x40;
- if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) {
- return;
- }
+ enable_interrupts();
- irq_vecs[vec - vec_base].handler = NULL;
- irq_vecs[vec - vec_base].arg = NULL;
+ return 0;
}
-void enable_interrupts (void)
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
{
- unsigned short sr;
+ volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE);
- sr = get_sr ();
- set_sr (sr & ~0x0700);
+ intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
+ intp->int_icr1 |= CFG_TMRINTR_PRI;
}
+#endif /* CONFIG_MCFTMR */
+#endif /* CONFIG_M5272 */
-int disable_interrupts (void)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+int interrupt_init(void)
{
- unsigned short sr;
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
- sr = get_sr ();
- set_sr (sr | 0x0700);
+ /* Make sure all interrupts are disabled */
+ intp->imrl0 |= 0x1;
- return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */
+ enable_interrupts();
+ return 0;
}
-void int_handler (struct pt_regs *fp)
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
{
-#ifdef CONFIG_M5272
- volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
-#endif
- int vec, vec_base = 0;
-
- vec = (fp->vector >> 2) & 0xff;
-#ifdef CONFIG_M5272
- vec_base = intp->int_pivr & 0xe0;
-#endif
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
- if (irq_vecs[vec - vec_base].handler != NULL) {
- irq_vecs[vec -
- vec_base].handler (irq_vecs[vec - vec_base].arg);
- } else {
- printf ("\nBogus External Interrupt Vector %d\n", vec);
- }
+ intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->imrl0 &= ~0xFFFFFFFE;
+ intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
+#endif /* CONFIG_MCFTMR */
+#endif /* CONFIG_M5282 | CONFIG_M5271 */
-
-#ifdef CONFIG_M5272
-int interrupt_init (void)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+int interrupt_init(void)
{
- volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
-
- /* disable all external interrupts */
- intp->int_icr1 = 0x88888888;
- intp->int_icr2 = 0x88888888;
- intp->int_icr3 = 0x88888888;
- intp->int_icr4 = 0x88888888;
- intp->int_pitr = 0x00000000;
- /* initialize vector register */
- intp->int_pivr = 0x40;
+ enable_interrupts();
- enable_interrupts ();
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
-int interrupt_init (void)
-{
return 0;
}
-#endif
-#ifdef CONFIG_M5249
-int interrupt_init (void)
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
{
- enable_interrupts ();
-
- return 0;
+ mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
+ mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
}
-#endif
+#endif /* CONFIG_MCFTMR */
+#endif /* CONFIG_M5249 || CONFIG_M5253 */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <watchdog.h>
-
-#include <asm/mcfuart.h>
-
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#endif
-
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#endif
-
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#endif
-
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5271)
-#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a))
-#else
-#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a))
-#endif
-
-void rs_serial_setbaudrate(int port,int baudrate)
-{
-#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
- volatile unsigned char *uartp;
-# ifndef CONFIG_M5271
- double fraction;
-# endif
- double clock;
-
- if (port == 0)
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
- else
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
-
- clock = DoubleClock(baudrate); /* Set baud above */
-
- uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
- uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
-
-# ifndef CONFIG_M5271
- fraction = ((clock - (int)clock) * 16.0) + 0.5;
- uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
-# endif
-#endif
-
-#if defined(CONFIG_M5282)
- volatile unsigned char *uartp;
- long clock;
-
- switch (port) {
- case 1:
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
- break;
- case 2:
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
- break;
- default:
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
- }
-
- clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */
-
- uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
- uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */
-
-#endif
-};
-
-void rs_serial_init (int port, int baudrate)
-{
- volatile unsigned char *uartp;
-
- /*
- * Reset UART, get it into known state...
- */
- switch (port) {
- case 1:
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
- break;
-#if defined(CONFIG_M5282)
- case 2:
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
- break;
-#endif
- default:
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
- }
-
- uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
- uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
-
- uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */
- uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */
-
- /*
- * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
- */
- uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8;
- uartp[MCFUART_UMR] = MCFUART_MR2_STOP1;
-
- /* Mask UART interrupts */
- uartp[MCFUART_UIMR] = 0;
-
- /* Set clock Select Register: Tx/Rx clock is timer */
- uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
-
- rs_serial_setbaudrate (port, baudrate);
-
- /* Enable Tx/Rx */
- uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
-
- return;
-}
-
-/****************************************************************************/
-/*
- * Output a single character, using UART polled mode.
- * This is used for console output.
- */
-
-void rs_put_char(char ch)
-{
- volatile unsigned char *uartp;
- int i;
-
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-
- for (i = 0; (i < 0x10000); i++) {
- if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY)
- break;
- }
- uartp[MCFUART_UTB] = ch;
- return;
-}
-
-int rs_is_char(void)
-{
- volatile unsigned char *uartp;
-
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
- return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0);
-}
-
-int rs_get_char(void)
-{
- volatile unsigned char *uartp;
-
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
- return(uartp[MCFUART_URB]);
-}
-
-void serial_setbrg(void) {
- rs_serial_setbaudrate(0,gd->bd->bi_baudrate);
-}
-
-int serial_init(void) {
- rs_serial_init(0,gd->baudrate);
- return 0;
-}
-
-
-void serial_putc(const char c) {
- if (c == '\n')
- serial_putc ('\r');
- rs_put_char(c);
-}
-
-void serial_puts (const char *s) {
- while (*s)
- serial_putc(*s++);
-}
-
-int serial_getc(void) {
- while(!rs_is_char())
- WATCHDOG_RESET();
-
- return rs_get_char();
-}
-
-int serial_tstc() {
- return rs_is_char();
-}
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <common.h>
#include <asm/processor.h>
+#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
*/
int get_clocks (void)
{
- gd->cpu_clk = CFG_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+ volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
+ unsigned long pllcr;
+
+#ifndef CFG_PLL_BYPASS
+
#ifdef CONFIG_M5249
+ /* Setup the PLL to run at the specified speed */
+#ifdef CFG_FAST_CLK
+ pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
+#else
+ pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
+#endif
+#endif /* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+ pllcr = CFG_PLLCR;
+#endif /* CONFIG_M5253 */
+
+ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+ mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
+ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
+ pllcr ^= 0x00000001; /* Set pll bypass to 1 */
+ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
+ udelay(0x20); /* Wait for a lock ... */
+#endif /* #ifndef CFG_PLL_BYPASS */
+
+#endif /* CONFIG_M5249 || CONFIG_M5253 */
+
+ gd->cpu_clk = CFG_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
nop
move.w #0x2700,%sr
-#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
+#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
move.l #(CFG_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
-#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
+#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
+ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
movec %d0, %RAMBAR0
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
+ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
movec %d0, %RAMBAR0
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
- #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
- defined(CFG_HALT_BEFOR_RAM_JUMP)
- halt
- #endif
+#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
+ defined(CFG_HALT_BEFOR_RAM_JUMP)
+ halt
+#endif
jsr (%a1)
/*------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------*/
/* cache functions */
+#ifdef CONFIG_M5271
+ .globl icache_enable
+icache_enable:
+ move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
+ movec %d0, %ACR0 /* Enable cache */
+
+ move.l #0x80000200, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ nop
+
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+#endif
+
#ifdef CONFIG_M5272
.globl icache_enable
icache_enable:
rts
#endif
-#ifdef CONFIG_M5249
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
.globl icache_enable
icache_enable:
/*
.globl icache_status
icache_status:
icache_state_access_3:
- move.l icache_state, %d0
+ move.l #(icache_state), %a0
+ move.l (%a0), %d0
rts
.data
icache_state:
.long 0 /* cache is diabled on inirialization */
+ .globl dcache_enable
+dcache_enable:
+ /* dummy function */
+ rts
+
+ .globl dcache_disable
+dcache_disable:
+ /* dummy function */
+ rts
+
+ .globl dcache_status
+dcache_status:
+ /* dummy function */
+ rts
+
/*------------------------------------------------------------------------------*/
.globl version_string
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB = lib$(CPU).a
+
+START =
+COBJS = cpu.o speed.o cpu_init.o interrupts.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+PLATFORM_CPPFLAGS += -m5307 -fPIC
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+ wdp->cr = 0;
+ udelay(1000);
+
+ /* enable watchdog, set timeout to 0 and wait */
+ wdp->cr = WTM_WCR_EN;
+ while (1) ;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ u16 msk;
+ u16 id = 0;
+ u8 ver;
+
+ puts("CPU: ");
+ msk = (ccm->cir >> 6);
+ ver = (ccm->cir & 0x003f);
+ switch (msk) {
+ case 0x54:
+ id = 5329;
+ break;
+ case 0x59:
+ id = 5328;
+ break;
+ case 0x61:
+ id = 5327;
+ break;
+ }
+
+ if (id) {
+ printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+ ver);
+ printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
+ (int)(gd->cpu_clk / 1000000),
+ (int)(gd->bus_clk / 1000000));
+ }
+
+ return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+ wdp->sr = 0x5555; /* Count register */
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+ /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+ wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ u32 wdog_module = 0;
+
+ /* set timeout and enable watchdog */
+ wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module |= (wdog_module / 8192);
+ wdp->mr = wdog_module;
+
+ wdp->cr = WTM_WCR_EN;
+ puts("WATCHDOG:enabled\n");
+
+ return (0);
+}
+#endif /* CONFIG_WATCHDOG */
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#include <asm/immap.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+
+ /* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+ wdog->cr = 0;
+#endif
+
+ scm1->mpr0 = 0x77777777;
+ scm2->pacra = 0;
+ scm2->pacrb = 0;
+ scm2->pacrc = 0;
+ scm2->pacrd = 0;
+ scm2->pacre = 0;
+ scm2->pacrf = 0;
+ scm2->pacrg = 0;
+ scm1->pacrh = 0;
+
+ /* Port configuration */
+ gpio->par_cs = 0;
+
+#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
+ fbcs->csar0 = CFG_CS0_BASE;
+ fbcs->cscr0 = CFG_CS0_CTRL;
+ fbcs->csmr0 = CFG_CS0_MASK;
+#endif
+
+#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+ /* Latch chipselect */
+ gpio->par_cs |= GPIO_PAR_CS1;
+ fbcs->csar1 = CFG_CS1_BASE;
+ fbcs->cscr1 = CFG_CS1_CTRL;
+ fbcs->csmr1 = CFG_CS1_MASK;
+#endif
+
+#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS2;
+ fbcs->csar2 = CFG_CS2_BASE;
+ fbcs->cscr2 = CFG_CS2_CTRL;
+ fbcs->csmr2 = CFG_CS2_MASK;
+#endif
+
+#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS3;
+ fbcs->csar3 = CFG_CS3_BASE;
+ fbcs->cscr3 = CFG_CS3_CTRL;
+ fbcs->csmr3 = CFG_CS3_MASK;
+#endif
+
+#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS4;
+ fbcs->csar4 = CFG_CS4_BASE;
+ fbcs->cscr4 = CFG_CS4_CTRL;
+ fbcs->csmr4 = CFG_CS4_MASK;
+#endif
+
+#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS5;
+ fbcs->csar5 = CFG_CS5_BASE;
+ fbcs->cscr5 = CFG_CS5_CTRL;
+ fbcs->csmr5 = CFG_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+#endif
+
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+ break;
+ case 1:
+ gpio->par_uart =
+ (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+ break;
+ case 2:
+ gpio->par_timer &= 0x0F;
+ gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+ break;
+ }
+}
--- /dev/null
+/*
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <asm/immap.h>
+
+int interrupt_init(void)
+{
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+ /* Make sure all interrupts are disabled */
+ intp->imrh0 |= 0xFFFFFFFF;
+ intp->imrl0 |= 0xFFFFFFFF;
+
+ enable_interrupts();
+ return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+ intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->imrh0 &= ~CFG_TMRINTR_MASK;
+}
+#endif
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PLL min/max specifications */
+#define MAX_FVCO 500000 /* KHz */
+#define MAX_FSYS 80000 /* KHz */
+#define MIN_FSYS 58333 /* KHz */
+#define FREF 16000 /* KHz */
+#define MAX_MFD 135 /* Multiplier */
+#define MIN_MFD 88 /* Multiplier */
+#define BUSDIV 6 /* Divider */
+/*
+ * Low Power Divider specifications
+ */
+#define MIN_LPD (1 << 0) /* Divider (not encoded) */
+#define MAX_LPD (1 << 15) /* Divider (not encoded) */
+#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
+
+/*
+ * Get the value of the current system clock
+ *
+ * Parameters:
+ * none
+ *
+ * Return Value:
+ * The current output system frequency
+ */
+int get_sys_clock(void)
+{
+ volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+ int divider;
+
+ /* Test to see if device is in LIMP mode */
+ if (ccm->misccr & CCM_MISCCR_LIMP) {
+ divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+ return (FREF / (2 << divider));
+ } else {
+ return ((FREF * pll->pfdr) / (BUSDIV * 4));
+ }
+}
+
+/*
+ * Initialize the Low Power Divider circuit
+ *
+ * Parameters:
+ * div Desired system frequency divider
+ *
+ * Return Value:
+ * The resulting output system frequency
+ */
+int clock_limp(int div)
+{
+ volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+ u32 temp;
+
+ /* Check bounds of divider */
+ if (div < MIN_LPD)
+ div = MIN_LPD;
+ if (div > MAX_LPD)
+ div = MAX_LPD;
+
+ /* Save of the current value of the SSIDIV so we don't overwrite the value */
+ temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
+
+ /* Apply the divider to the system clock */
+ ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
+
+ ccm->misccr |= CCM_MISCCR_LIMP;
+
+ return (FREF / (3 * (1 << div)));
+}
+
+/*
+ * Exit low power LIMP mode
+ *
+ * Parameters:
+ * div Desired system frequency divider
+ *
+ * Return Value:
+ * The resulting output system frequency
+ */
+int clock_exit_limp(void)
+{
+ volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+ int fout;
+
+ /* Exit LIMP mode */
+ ccm->misccr &= (~CCM_MISCCR_LIMP);
+
+ /* Wait for PLL to lock */
+ while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
+
+ fout = get_sys_clock();
+
+ return fout;
+}
+
+/* Initialize the PLL
+ *
+ * Parameters:
+ * fref PLL reference clock frequency in KHz
+ * fsys Desired PLL output frequency in KHz
+ * flags Operating parameters
+ *
+ * Return Value:
+ * The resulting output system frequency
+ */
+int clock_pll(int fsys, int flags)
+{
+ volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+ int fref, temp, fout, mfd;
+ u32 i;
+
+ fref = FREF;
+
+ if (fsys == 0) {
+ /* Return current PLL output */
+ mfd = pll->pfdr;
+
+ return (fref * mfd / (BUSDIV * 4));
+ }
+
+ /* Check bounds of requested system clock */
+ if (fsys > MAX_FSYS)
+ fsys = MAX_FSYS;
+
+ if (fsys < MIN_FSYS)
+ fsys = MIN_FSYS;
+
+ /* Multiplying by 100 when calculating the temp value,
+ and then dividing by 100 to calculate the mfd allows
+ for exact values without needing to include floating
+ point libraries. */
+ temp = (100 * fsys) / fref;
+ mfd = (4 * BUSDIV * temp) / 100;
+
+ /* Determine the output frequency for selected values */
+ fout = ((fref * mfd) / (BUSDIV * 4));
+
+ /*
+ * Check to see if the SDRAM has already been initialized.
+ * If it has then the SDRAM needs to be put into self refresh
+ * mode before reprogramming the PLL.
+ */
+
+ /*
+ * Initialize the PLL to generate the new system clock frequency.
+ * The device must be put into LIMP mode to reprogram the PLL.
+ */
+
+ /* Enter LIMP mode */
+ clock_limp(DEFAULT_LPD);
+
+ /* Reprogram PLL for desired fsys */
+ pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
+
+ pll->pfdr = mfd;
+
+ /* Exit LIMP mode */
+ clock_exit_limp();
+
+ /*
+ * Return the SDRAM to normal operation if it is in use.
+ */
+
+ /* software workaround for SDRAM opeartion after exiting LIMP mode errata */
+ *sdram_workaround = CFG_SDRAM_BASE;
+
+ /* wait for DQS logic to relock */
+ for (i = 0; i < 0x200; i++) ;
+
+ return fout;
+}
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+ gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
+ gd->cpu_clk = (gd->bus_clk * 3);
+ return (0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "version.h"
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define _START _start
+#define _FAULT _fault
+
+#define SAVE_ALL \
+ move.w #0x2700,%sr; /* disable intrs */ \
+ subl #60,%sp; /* space for 15 regs */ \
+ moveml %d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL \
+ moveml %sp@,%d0-%d7/%a0-%a6; \
+ addl #60,%sp; /* space for 15 regs */ \
+ rte;
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+INITSP: .long 0x00000000 /* Initial SP */
+INITPC: .long _START /* Initial PC */
+vector02: .long _FAULT /* Access Error */
+vector03: .long _FAULT /* Address Error */
+vector04: .long _FAULT /* Illegal Instruction */
+vector05: .long _FAULT /* Reserved */
+vector06: .long _FAULT /* Reserved */
+vector07: .long _FAULT /* Reserved */
+vector08: .long _FAULT /* Privilege Violation */
+vector09: .long _FAULT /* Trace */
+vector0A: .long _FAULT /* Unimplemented A-Line */
+vector0B: .long _FAULT /* Unimplemented F-Line */
+vector0C: .long _FAULT /* Debug Interrupt */
+vector0D: .long _FAULT /* Reserved */
+vector0E: .long _FAULT /* Format Error */
+vector0F: .long _FAULT /* Unitialized Int. */
+
+/* Reserved */
+vector10_17:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18: .long _FAULT /* Spurious Interrupt */
+vector19: .long _FAULT /* Autovector Level 1 */
+vector1A: .long _FAULT /* Autovector Level 2 */
+vector1B: .long _FAULT /* Autovector Level 3 */
+vector1C: .long _FAULT /* Autovector Level 4 */
+vector1D: .long _FAULT /* Autovector Level 5 */
+vector1E: .long _FAULT /* Autovector Level 6 */
+vector1F: .long _FAULT /* Autovector Level 7 */
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector30_3F:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+ .text
+
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr /* Mask off Interrupt */
+
+ /* Set vector base register at the beginning of the Flash */
+ move.l #CFG_FLASH_BASE, %d0
+ movec %d0, %VBR
+
+ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR0
+
+ /* invalidate and disable cache */
+ move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
+ /* set stackpointer to end of internal ram to get some stackspace for the
+ first c-code */
+ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ move.l #__got_start, %a5 /* put relocation table address to a5 */
+
+ bsr cpu_init_f /* run low-level CPU init code (from flash) */
+ bsr board_init_f /* run low-level board init code (from flash) */
+
+ /* board_init_f() does not return */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CFG_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ move.l %a0, %d1
+ add.l #(_ebss - CFG_MONITOR_BASE),%d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ move.l %a1,%a5 /* * fix got pointer register a5 */
+
+ move.l %a0, %a2
+ add.l #(__got_end - CFG_MONITOR_BASE),%a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start,%d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+ jsr (%a1)
+
+/*------------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ jmp _fault
+ .globl _exc_handler
+
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*------------------------------------------------------------------------------*/
+/* cache functions */
+ .globl icache_enable
+icache_enable:
+ move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0
+ movec %d0, %ACR0 /* Enable cache */
+
+ move.l #0x80000200, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ nop
+
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl icache_disable
+icache_disable:
+ move.l #0x01000000, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Disable cache */
+ clr.l %d0 /* Setup cache mask */
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ moveq #0, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl icache_status
+icache_status:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l (%a1), %d0
+ rts
+
+ .globl icache_invalid
+icache_invalid:
+ move.l #0x81000200, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ rts
+
+ .globl dcache_enable
+dcache_enable:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+
+ /* No dcache, just a dummy function */
+ .globl dcache_disable
+dcache_disable:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ moveq #0, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl dcache_status
+dcache_status:
+ move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l (%a1), %d0
+ rts
+
+/*------------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB = lib$(CPU).a
+
+START = start.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+PLATFORM_CPPFLAGS += -m5407 -fPIC
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+ volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ udelay(1000);
+ rcm->rcr |= RCM_RCR_SOFTRST;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ u16 msk;
+ u16 id = 0;
+ u8 ver;
+
+ puts("CPU: ");
+ msk = (ccm->cir >> 6);
+ ver = (ccm->cir & 0x003f);
+ switch (msk) {
+ case 0x48:
+ id = 54455;
+ break;
+ case 0x49:
+ id = 54454;
+ break;
+ case 0x4a:
+ id = 54453;
+ break;
+ case 0x4b:
+ id = 54452;
+ break;
+ case 0x4d:
+ id = 54451;
+ break;
+ case 0x4f:
+ id = 54450;
+ break;
+ }
+
+ if (id) {
+ printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+ ver);
+ printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
+ (int)(gd->cpu_clk / 1000000),
+ (int)(gd->bus_clk / 1000000),
+ (int)(gd->flb_clk / 1000000));
+#ifdef CONFIG_PCI
+ printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n",
+ (int)(gd->pci_clk / 1000000),
+ (int)(gd->inp_clk / 1000000),
+ (int)(gd->vco_clk / 1000000));
+#else
+ printf(" INP CLK %d Mhz VCO CLK %d Mhz\n",
+ (int)(gd->inp_clk / 1000000),
+ (int)(gd->vco_clk / 1000000));
+#endif
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#include <asm/immap.h>
+#include <asm/rtc.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ scm1->mpr = 0x77777777;
+ scm1->pacra = 0;
+ scm1->pacrb = 0;
+ scm1->pacrc = 0;
+ scm1->pacrd = 0;
+ scm1->pacre = 0;
+ scm1->pacrf = 0;
+ scm1->pacrg = 0;
+
+ /* FlexBus */
+ gpio->par_be =
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
+ GPIO_PAR_BE_BE0_BE0;
+ gpio->par_fbctl =
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
+ GPIO_PAR_FBCTL_TS_TS;
+
+#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
+ fbcs->csar0 = CFG_CS0_BASE;
+ fbcs->cscr0 = CFG_CS0_CTRL;
+ fbcs->csmr0 = CFG_CS0_MASK;
+#endif
+
+#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+ /* Latch chipselect */
+ fbcs->csar1 = CFG_CS1_BASE;
+ fbcs->cscr1 = CFG_CS1_CTRL;
+ fbcs->csmr1 = CFG_CS1_MASK;
+#endif
+
+#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+ fbcs->csar2 = CFG_CS2_BASE;
+ fbcs->cscr2 = CFG_CS2_CTRL;
+ fbcs->csmr2 = CFG_CS2_MASK;
+#endif
+
+#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+ fbcs->csar3 = CFG_CS3_BASE;
+ fbcs->cscr3 = CFG_CS3_CTRL;
+ fbcs->csmr3 = CFG_CS3_MASK;
+#endif
+
+#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+ fbcs->csar4 = CFG_CS4_BASE;
+ fbcs->cscr4 = CFG_CS4_CTRL;
+ fbcs->csmr4 = CFG_CS4_MASK;
+#endif
+
+#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+ fbcs->csar5 = CFG_CS5_BASE;
+ fbcs->cscr5 = CFG_CS5_CTRL;
+ fbcs->csmr5 = CFG_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+#endif
+
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFTMR
+ volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
+ volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+ u32 oscillator = CFG_RTC_OSCILLATOR;
+
+ rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
+ rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
+#endif
+
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart =
+ (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+ break;
+ case 1:
+ gpio->par_uart =
+ (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+ break;
+ }
+}
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <asm/immap.h>
+
+int interrupt_init(void)
+{
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+ /* Make sure all interrupts are disabled */
+ intp->imrh0 |= 0xFFFFFFFF;
+ intp->imrl0 |= 0xFFFFFFFF;
+
+ enable_interrupts();
+ return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+ volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+ intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->imrh0 &= ~CFG_TMRINTR_MASK;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+#if defined(CONFIG_PCI)
+/* System RAM mapped over PCI */
+#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+
+#define cfg_read(val, addr, type, op) *val = op((type)(addr));
+#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
+
+#define PCI_OP(rw, size, type, op, mask) \
+int pci_##rw##_cfg_##size(struct pci_controller *hose, \
+ pci_dev_t dev, int offset, type val) \
+{ \
+ u32 addr = 0; \
+ u16 cfg_type = 0; \
+ addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
+ out_be32(hose->cfg_addr, addr); \
+ __asm__ __volatile__("nop"); \
+ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
+ out_be32(hose->cfg_addr, addr & 0x7fffffff); \
+ __asm__ __volatile__("nop"); \
+ return 0; \
+}
+
+PCI_OP(read, byte, u8 *, in_8, 3)
+PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(write, byte, u8, out_8, 3)
+PCI_OP(write, word, u16, out_le16, 2)
+PCI_OP(write, dword, u32, out_le32, 0)
+
+int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
+ int offset, u32 * val)
+{
+ u32 addr;
+ u32 tmpv;
+ u32 mask = 2; /* word access */
+ /* Read lower 16 bits */
+ addr = ((offset & 0xfc) | (dev) | 0x80000000);
+ out_be32(hose->cfg_addr, addr);
+ __asm__ __volatile__("nop");
+ *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+ out_be32(hose->cfg_addr, addr & 0x7fffffff);
+ __asm__ __volatile__("nop");
+
+ /* Read upper 16 bits */
+ offset += 2;
+ addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
+ out_be32(hose->cfg_addr, addr);
+ __asm__ __volatile__("nop");
+ tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+ out_be32(hose->cfg_addr, addr & 0x7fffffff);
+ __asm__ __volatile__("nop");
+
+ /* combine results into dword value */
+ *val = (tmpv << 16) | *val;
+
+ return 0;
+}
+
+void pci_mcf5445x_init(struct pci_controller *hose)
+{
+ volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
+ volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u32 barEn = 0;
+
+ pciarb->acr = 0x001f001f;
+
+ /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
+ PCIREQ2, PCIGNT2 */
+ gpio->par_pci =
+ GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
+ GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
+ GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
+
+ pci->tcr1 |= PCI_TCR1_P;
+
+ /* Initiator windows */
+ pci->iw0btar = CFG_PCI_MEM_PHYS;
+ pci->iw1btar = CFG_PCI_IO_PHYS;
+ pci->iw2btar = CFG_PCI_CFG_PHYS;
+
+ pci->iwcr =
+ PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+ PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+
+ /* Enable bus master and mem access */
+ pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M;
+
+ /* Cache line size and master latency */
+ pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF);
+ pci->cr2 = 0;
+
+#ifdef CFG_PCI_BAR0
+ pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
+ pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
+ barEn |= PCI_TCR1_B0E;
+#endif
+#ifdef CFG_PCI_BAR1
+ pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
+ pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
+ barEn |= PCI_TCR1_B1E;
+#endif
+#ifdef CFG_PCI_BAR2
+ pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
+ pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
+ barEn |= PCI_TCR1_B2E;
+#endif
+#ifdef CFG_PCI_BAR3
+ pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
+ pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
+ barEn |= PCI_TCR1_B3E;
+#endif
+#ifdef CFG_PCI_BAR4
+ pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
+ pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
+ barEn |= PCI_TCR1_B4E;
+#endif
+#ifdef CFG_PCI_BAR5
+ pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
+ pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
+ barEn |= PCI_TCR1_B5E;
+#endif
+
+ pci->tcr2 = barEn;
+
+ /* Deassert reset bit */
+ pci->gscr &= ~PCI_GSCR_PR;
+ udelay(1000);
+
+ /* Enable PCI bus master support */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
+ CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
+ CFG_PCI_IO_SIZE, PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
+ CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 3;
+
+ hose->cfg_addr = &(pci->car);
+ hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
+
+ pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
+ pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
+ pci_write_cfg_dword);
+
+ /* Hose scan */
+ pci_register_hose(hose);
+ hose->last_busno = pci_hose_scan(hose);
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Low Power Divider specifications
+ */
+#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
+#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
+
+#define CLOCK_PLL_FVCO_MAX 540000000
+#define CLOCK_PLL_FVCO_MIN 300000000
+
+#define CLOCK_PLL_FSYS_MAX 266666666
+#define CLOCK_PLL_FSYS_MIN 100000000
+#define MHZ 1000000
+
+void clock_enter_limp(int lpdiv)
+{
+ volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+ int i, j;
+
+ /* Check bounds of divider */
+ if (lpdiv < CLOCK_LPD_MIN)
+ lpdiv = CLOCK_LPD_MIN;
+ if (lpdiv > CLOCK_LPD_MAX)
+ lpdiv = CLOCK_LPD_MAX;
+
+ /* Round divider down to nearest power of two */
+ for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
+
+ /* Apply the divider to the system clock */
+ ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+
+ /* Enable Limp Mode */
+ ccm->misccr |= CCM_MISCCR_LIMP;
+}
+
+/*
+ * brief Exit Limp mode
+ * warning The PLL should be set and locked prior to exiting Limp mode
+ */
+void clock_exit_limp(void)
+{
+ volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+ volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+
+ /* Exit Limp mode */
+ ccm->misccr &= ~CCM_MISCCR_LIMP;
+
+ /* Wait for the PLL to lock */
+ while (!(pll->psr & PLL_PSR_LOCK)) ;
+}
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+ volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+ volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
+ volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
+ int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
+ int pllmult_pci[] = { 12, 6, 16, 8 };
+ int vco, bPci, temp, fbtemp, pcrvalue;
+ int *pPllmult = NULL;
+ u16 fbpll_mask;
+ u8 cpldmode;
+
+ /* To determine PCI is present or not */
+ if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
+ ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
+ pPllmult = &pllmult_pci[0];
+ fbpll_mask = 3;
+ bPci = 1;
+ } else {
+ pPllmult = &pllmult_nopci[0];
+ fbpll_mask = 7;
+#ifdef CONFIG_PCI
+ gd->pci_clk = 0;
+#endif
+ bPci = 0;
+ }
+
+#ifdef CONFIG_M54455EVB
+ /* Temporary place here, belongs in board/freescale/... */
+ /* Temporary read from CCR- fixed fb issue, must be the same clock
+ as pci or input clock, causing cpld/fpga read inconsistancy */
+ fbtemp = pPllmult[ccm->ccr & fbpll_mask];
+
+ /* Break down into small pieces, code still in flex bus */
+ pcrvalue = pll->pcr & 0xFFFFF0FF;
+ temp = fbtemp - 1;
+ pcrvalue |= PLL_PCR_OUTDIV3(temp);
+
+ pll->pcr = pcrvalue;
+
+ cpldmode = *cpld & 0x03;
+ if (cpldmode == 0) {
+ /* RCON mode */
+ vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
+
+ if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+ /* invaild range, re-set in PCR */
+ int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+ int i, j, bus;
+
+ j = (pll->pcr & 0xFF000000) >> 24;
+ for (i = j; i < 0xFF; i++) {
+ vco = i * CFG_INPUT_CLKSRC;
+ if (vco >= CLOCK_PLL_FVCO_MIN) {
+ bus = vco / temp;
+ if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
+ continue;
+ else
+ break;
+ }
+ }
+ pcrvalue = pll->pcr & 0x00FF00FF;
+ fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
+ pcrvalue |= ((i << 24) | fbtemp);
+
+ pll->pcr = pcrvalue;
+ }
+ gd->vco_clk = vco; /* Vco clock */
+ } else if (cpldmode == 2) {
+ /* Normal mode */
+ vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
+ gd->vco_clk = vco; /* Vco clock */
+ } else if (cpldmode == 3) {
+ /* serial mode */
+ }
+#endif /* CONFIG_M54455EVB */
+
+ if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+ /* Limp mode */
+ } else {
+ gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
+
+ temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+ gd->cpu_clk = vco / temp; /* cpu clock */
+
+ temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+ gd->bus_clk = vco / temp; /* bus clock */
+
+ temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
+ gd->flb_clk = vco / temp; /* FlexBus clock */
+
+#ifdef CONFIG_PCI
+ if (bPci) {
+ temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
+ gd->pci_clk = vco / temp; /* PCI clock */
+ }
+#endif
+ }
+
+ return (0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "version.h"
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+/* last three long word reserved for cache status */
+#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
+#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
+
+#define _START _start
+#define _FAULT _fault
+
+#define SAVE_ALL \
+ move.w #0x2700,%sr; /* disable intrs */ \
+ subl #60,%sp; /* space for 15 regs */ \
+ moveml %d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL \
+ moveml %sp@,%d0-%d7/%a0-%a6; \
+ addl #60,%sp; /* space for 15 regs */ \
+ rte;
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+INITSP: .long 0x00000000 /* Initial SP */
+INITPC: .long _START /* Initial PC */
+vector02: .long _FAULT /* Access Error */
+vector03: .long _FAULT /* Address Error */
+vector04: .long _FAULT /* Illegal Instruction */
+vector05: .long _FAULT /* Reserved */
+vector06: .long _FAULT /* Reserved */
+vector07: .long _FAULT /* Reserved */
+vector08: .long _FAULT /* Privilege Violation */
+vector09: .long _FAULT /* Trace */
+vector0A: .long _FAULT /* Unimplemented A-Line */
+vector0B: .long _FAULT /* Unimplemented F-Line */
+vector0C: .long _FAULT /* Debug Interrupt */
+vector0D: .long _FAULT /* Reserved */
+vector0E: .long _FAULT /* Format Error */
+vector0F: .long _FAULT /* Unitialized Int. */
+
+/* Reserved */
+vector10_17:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18: .long _FAULT /* Spurious Interrupt */
+vector19: .long _FAULT /* Autovector Level 1 */
+vector1A: .long _FAULT /* Autovector Level 2 */
+vector1B: .long _FAULT /* Autovector Level 3 */
+vector1C: .long _FAULT /* Autovector Level 4 */
+vector1D: .long _FAULT /* Autovector Level 5 */
+vector1E: .long _FAULT /* Autovector Level 6 */
+vector1F: .long _FAULT /* Autovector Level 7 */
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector30_3F:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+ .text
+
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr /* Mask off Interrupt */
+
+ /* Set vector base register at the beginning of the Flash */
+ move.l #CFG_FLASH_BASE, %d0
+ movec %d0, %VBR
+
+ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR0
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CACR_STATUS), %a1 /* CACR */
+ move.l #(ICACHE_STATUS), %a2 /* icache */
+ move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+ move.l %d0, (%a3)
+
+ /* invalidate and disable cache */
+ move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+ movec %d0, %ACR2
+ movec %d0, %ACR3
+
+ /* set stackpointer to end of internal ram to get some stackspace for
+ the first c-code */
+ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ move.l #__got_start, %a5 /* put relocation table address to a5 */
+
+ bsr cpu_init_f /* run low-level CPU init code (from flash) */
+ bsr board_init_f /* run low-level board init code (from flash) */
+
+ /* board_init_f() does not return */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CFG_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ move.l %a0, %d1
+ add.l #(_ebss - CFG_MONITOR_BASE),%d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ move.l %a1,%a5 /* * fix got pointer register a5 */
+
+ move.l %a0, %a2
+ add.l #(__got_end - CFG_MONITOR_BASE),%a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start,%d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+ jsr (%a1)
+
+/*------------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ jmp _fault
+ .globl _exc_handler
+
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*------------------------------------------------------------------------------*/
+/* cache functions */
+ .globl icache_enable
+icache_enable:
+ move.l #(CACR_STATUS), %a1 /* read CACR Status */
+ move.l (%a1), %d1
+
+ move.l #0x00040100, %d0 /* Invalidate icache */
+ or.l %d1, %d0
+ movec %d0, %CACR
+
+ move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */
+ movec %d0, %ACR2
+
+ or.l #0x00088400, %d1 /* Enable bcache and icache */
+ movec %d1, %CACR
+
+ move.l #(ICACHE_STATUS), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl icache_disable
+icache_disable:
+ move.l #(CACR_STATUS), %a1 /* read CACR Status */
+ move.l (%a1), %d0
+
+ and.l #0xFFF77BFF, %d0
+ or.l #0x00040100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Invalidate icache */
+ clr.l %d0
+ movec %d0, %ACR2
+ movec %d0, %ACR3
+
+ move.l #(ICACHE_STATUS), %a1
+ moveq #0, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl icache_status
+icache_status:
+ move.l #(ICACHE_STATUS), %a1
+ move.l (%a1), %d0
+ rts
+
+ .globl icache_invalid
+icache_invalid:
+ move.l #(CACR_STATUS), %a1 /* read CACR Status */
+ move.l (%a1), %d0
+
+ or.l #0x00040100, %d0 /* Invalidate icache */
+ movec %d0, %CACR /* Enable and invalidate cache */
+ rts
+
+ .globl dcache_enable
+dcache_enable:
+ move.l #(CACR_STATUS), %a1 /* read CACR Status */
+ move.l (%a1), %d1
+
+ move.l #0x01000000, %d0
+ or.l %d1, %d0
+ movec %d0, %CACR /* Invalidate dcache */
+
+ move.l #(CFG_SDRAM_BASE + 0xc000), %d0
+ movec %d0, %ACR0
+ move.l #0, %d0
+ movec %d0, %ACR1
+
+ or.l #0x80000000, %d1 /* Enable bcache and icache */
+ movec %d1, %CACR
+
+ move.l #(DCACHE_STATUS), %a1
+ moveq #1, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl dcache_disable
+dcache_disable:
+ move.l #(CACR_STATUS), %a1 /* read CACR Status */
+ move.l (%a1), %d0
+
+ and.l #0x7FFFFFFF, %d0
+ or.l #0x01000000, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Disable dcache */
+ clr.l %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ move.l #(DCACHE_STATUS), %a1
+ moveq #0, %d0
+ move.l %d0, (%a1)
+ rts
+
+ .globl dcache_invalid
+dcache_invalid:
+ move.l #(CACR_STATUS), %a1 /* read CACR Status */
+ move.l (%a1), %d0
+
+ or.l #0x01000000, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable and invalidate cache */
+ rts
+
+ .globl dcache_status
+dcache_status:
+ move.l #(DCACHE_STATUS), %a1
+ move.l (%a1), %d0
+ rts
+
+/*------------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e
int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
+static uchar rx_buff[FEC_BUFFER_SIZE];
+static int rx_buff_idx = 0;
+
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
/* Set Opcode/Pause Duration Register */
fec->eth->op_pause = 0x00010020;
- /* Frame length=1518; MII mode */
- fec->eth->r_cntrl = 0x05ee000c;
+ /* Frame length=1522; MII mode */
+ fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
/* Half-duplex, heartbeat disabled */
fec->eth->x_cntrl = 0x00000000;
/* Setup recv fifo start and buff size */
fec->eth->r_fstart = 0x500;
- fec->eth->r_buff_size = 0x5e0;
+ fec->eth->r_buff_size = FEC_BUFFER_SIZE;
/* Setup BD base addresses */
fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
unsigned long ievent;
- int frame_length, len = 0;
- uchar buff[FEC_MAX_PKT_SIZE];
+ int frame_length = 0;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
- if ((pRbd->status & FEC_RBD_LAST) &&
- !(pRbd->status & FEC_RBD_ERR) &&
+ if (!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
/*
* Get buffer size
*/
- frame_length = pRbd->dataLength - 4;
-
+ if (pRbd->status & FEC_RBD_LAST)
+ frame_length = pRbd->dataLength - 4;
+ else
+ frame_length = pRbd->dataLength;
#if (DEBUG & 0x20)
{
int i;
- printf ("recv data hdr:");
+ printf ("recv data length 0x%08x data hdr: ",
+ pRbd->dataLength);
for (i = 0; i < 14; i++)
printf ("%x ", *((uint8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
-
/*
* Fill the buffer and pass it to upper layers
*/
- memcpy (buff, (void*)pRbd->dataPointer, frame_length);
- NetReceive ((uchar*)buff, frame_length);
- len = frame_length;
+ memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
+ frame_length - rx_buff_idx);
+ rx_buff_idx = frame_length;
+
+ if (pRbd->status & FEC_RBD_LAST) {
+ NetReceive ((uchar*)rx_buff, frame_length);
+ rx_buff_idx = 0;
+ }
}
/*
/* Try to fill Buffer Descriptors */
fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
- return len;
+ return frame_length;
}
/********************************************************************/
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
-#define FEC_MAX_PKT_SIZE 1536
+#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
+
+/* Buffer size must be evenly divisible by 16 */
+#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
typedef struct {
- uint8 frame[FEC_MAX_PKT_SIZE];
+ uint8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;
typedef struct {
#include <watchdog.h>
#include <command.h>
#include <mpc5xxx.h>
+#include <asm/io.h>
#include <asm/processor.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_cpu_setup(void *blob, bd_t *bd)
+#ifdef CONFIG_OF_LIBFDT
+static void do_fixup(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create)
{
- u32 *p;
- int len;
-
- /* Core XLB bus frequency */
- p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_busfreq);
-
- /* SOC peripherals use the IPB bus frequency */
- p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_ipbfreq);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
- if (p != NULL)
- memcpy(p, bd->bi_enetaddr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len);
- if (p != NULL)
- memcpy(p, bd->bi_enetaddr, 6);
+#if defined(DEBUG)
+ int i;
+ debug("Updating property '%s/%s' = ", node, prop);
+ for (i = 0; i < len; i++)
+ debug(" %.2x", *(u8*)(val+i));
+ debug("\n");
+#endif
+ int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create);
+ if (rc)
+ printf("Unable to update property %s:%s, err=%s\n",
+ node, prop, fdt_strerror(rc));
+}
+
+static void do_fixup_u32(void *fdt, const char *node, const char *prop,
+ u32 val, int create)
+{
+ val = cpu_to_fdt32(val);
+ do_fixup(fdt, node, prop, &val, sizeof(val), create);
+}
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+ int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
+ char * cpu_path = "/cpus/" OF_CPU;
+ char * eth_path = "/" OF_SOC "/ethernet@3000";
+
+ do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
+ do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
+ do_fixup_u32(blob, "/" OF_SOC, "system-frequency",
+ bd->bi_busfreq*div, 1);
+ do_fixup(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
+ do_fixup(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
}
#endif
/* All sample codes do that... */
*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
+#if defined(CONFIG_UC101)
+ /* Configure and reset host */
+ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG =
+ MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
+ udelay (10);
+ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0;
+#else
/* Configure and reset host */
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
udelay (10);
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
+#endif
/* Disable prefetch on Commbus */
psdma->PtdCntrl |= 1;
#include <mpc5xxx.h>
-int usb_cpu_init()
+int usb_cpu_init(void)
{
/* Set the USB Clock */
*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
return 0;
}
-int usb_cpu_stop()
+int usb_cpu_stop(void)
{
return 0;
}
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
{
return 0;
}
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
-
int checkcpu(void)
{
volatile immap_t *immr;
*/
static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
- /*
- * Fix it up if it exists, don't create it if it doesn't exist.
- */
+ /* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
}
/* second onboard ethernet port */
static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
- /*
- * Fix it up if it exists, don't create it if it doesn't exist.
- */
+ /* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
}
/* third onboard ethernet port */
static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
- /*
- * Fix it up if it exists, don't create it if it doesn't exist.
- */
+ /* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
}
/* fourth onboard ethernet port */
static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
- /*
- * Fix it up if it exists, don't create it if it doesn't exist.
- */
+ /* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
}
static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
- /*
- * Create or update the property.
- */
+ /* Create or update the property */
tmp = cpu_to_be32(bd->bi_busfreq);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
- /*
- * Create or update the property.
- */
+ /* Create or update the property */
tmp = cpu_to_be32(OF_TBCLK);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
+static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
+{
+ u32 tmp;
+ /* Create or update the property */
+ tmp = cpu_to_be32(gd->core_clk);
+ return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+#ifdef CONFIG_QE
+static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
+{
+ u32 tmp;
+ /* Create or update the property */
+ tmp = cpu_to_be32(gd->qe_clk);
+ return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
+{
+ u32 tmp;
+ /* Create or update the property */
+ tmp = cpu_to_be32(gd->brg_clk);
+ return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
+}
+#endif
+
/*
* Fixups to the fdt.
*/
},
{ "/cpus/" OF_CPU,
"clock-frequency",
+ fdt_set_clockfreq
+ },
+ { "/" OF_SOC,
+ "bus-frequency",
fdt_set_busfreq
},
{ "/" OF_SOC "/serial@4500",
fdt_set_eth1
},
#endif
+#ifdef CONFIG_QE
+ { "/" OF_QE,
+ "brg-frequency",
+ fdt_set_qe_brgfreq
+ },
+ { "/" OF_QE,
+ "bus-frequency",
+ fdt_set_qe_busfreq
+ },
#ifdef CONFIG_UEC_ETH1
#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
{ "/" OF_QE "/ucc@2000",
"local-mac-address",
fdt_set_eth1
},
-#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
+#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
{ "/" OF_QE "/ucc@3200",
"mac-address",
fdt_set_eth1
},
#endif
#endif /* CONFIG_UEC_ETH2 */
+#endif /* CONFIG_QE */
};
void
ft_cpu_setup(void *blob, bd_t *bd)
{
- int nodeoffset;
- int err;
- int j;
+ int nodeoffset;
+ int err;
+ int j;
+ int tmp[2];
for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node);
fixup_props[j].prop, bd);
if (err < 0)
debug("Problem setting %s = %s: %s\n",
- fixup_props[j].node,
- fixup_props[j].prop,
- fdt_strerror(err));
+ fixup_props[j].node, fixup_props[j].prop,
+ fdt_strerror(err));
} else {
debug("Couldn't find %s: %s\n",
- fixup_props[j].node,
- fdt_strerror(nodeoffset));
+ fixup_props[j].node, fdt_strerror(nodeoffset));
}
}
+
+ /* update, or add and update /memory node */
+ nodeoffset = fdt_find_node_by_path(blob, "/memory");
+ if (nodeoffset < 0) {
+ nodeoffset = fdt_add_subnode(blob, 0, "memory");
+ if (nodeoffset < 0)
+ debug("failed to add /memory node: %s\n",
+ fdt_strerror(nodeoffset));
+ }
+ if (nodeoffset >= 0) {
+ fdt_setprop(blob, nodeoffset, "device_type",
+ "memory", sizeof("memory"));
+ tmp[0] = cpu_to_be32(bd->bi_memstart);
+ tmp[1] = cpu_to_be32(bd->bi_memsize);
+ fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
+ }
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
#elif defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
}
if (pci_num_buses < 2)
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
+ err = fdt_setprop(blob, nodeoffset, "bus-range",
+ tmp, sizeof(tmp));
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+ tmp, sizeof(tmp[0]));
}
}
#elif CONFIG_OF_FLAT_TREE
#include <asm/mmu.h>
#include <spd_sdram.h>
+void board_add_ram_info(int use_default)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ddr83xx_t *ddr = &immap->ddr;
+
+ printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
+ >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
+
+ if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
+ puts(", 32-bit");
+ else
+ puts(", 64-bit");
+
+ if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+ puts(", ECC on)");
+ else
+ puts(", ECC off)");
+
+#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
+ puts("\nSDRAM: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+#endif
+}
+
#ifdef CONFIG_SPD_EEPROM
DECLARE_GLOBAL_DATA_PTR;
unsigned int n_ranks;
unsigned int odt_rd_cfg, odt_wr_cfg;
unsigned char twr_clk, twtr_clk;
- unsigned char sdram_type;
+ unsigned int sdram_type;
unsigned int memsize;
unsigned int law_size;
unsigned char caslat, caslat_ctrl;
#endif
/* Check the memory type */
if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
- printf("DDR: Module mem type is %02X\n", spd.mem_type);
+ debug("DDR: Module mem type is %02X\n", spd.mem_type);
return 0;
}
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
else
burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
- printf("\n DDR DIMM: data bus width is 32 bit");
+ debug("\n DDR DIMM: data bus width is 32 bit");
} else {
burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
- printf("\n DDR DIMM: data bus width is 64 bit");
+ debug("\n DDR DIMM: data bus width is 64 bit");
}
/* Is this an ECC DDR chip? */
if (spd.config == 0x02)
- printf(" with ECC\n");
+ debug(" with ECC\n");
else
- printf(" without ECC\n");
+ debug(" without ECC\n");
/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
Burst type is sequential
* sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
*/
if (spd.mem_type == SPD_MEMTYPE_DDR)
- sdram_type = 2;
+ sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
else
- sdram_type = 3;
+ sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
sdram_cfg = (0
- | (1 << 31) /* DDR enable */
- | (1 << 30) /* Self refresh */
- | (sdram_type << 24) /* SDRAM type */
+ | SDRAM_CFG_MEM_EN /* DDR enable */
+ | SDRAM_CFG_SREN /* Self refresh */
+ | sdram_type /* SDRAM type */
);
/* sdram_cfg[3] = RD_EN - registered DIMM enable */
if (spd.mod_attr & 0x02)
- sdram_cfg |= 0x10000000;
+ sdram_cfg |= SDRAM_CFG_RD_EN;
/* The DIMM is 32bit width */
if (spd.dataw_lsb == 0x20) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
- sdram_cfg |= 0x000C0000;
+ sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
if (spd.mem_type == SPD_MEMTYPE_DDR2)
- sdram_cfg |= 0x00080000;
+ sdram_cfg |= SDRAM_CFG_32_BE;
}
ddrc_ecc_enable = 0;
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
- printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
+ debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
#if defined(CONFIG_DDR_2T_TIMING)
/*
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
+ gd->pci_clk = pci_sync_in;
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->csb_clk;
return 0;
START = start.o resetvec.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
if (p != NULL)
*p = cpu_to_be32(clock);
-#if defined(CONFIG_TSEC1)
+#if defined(CONFIG_HAS_ETH0)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p)
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
if (p)
memcpy(p, bd->bi_enet2addr, 6);
+
+#ifdef CONFIG_UEC_ETH
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet2addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet2addr, 6);
+
+#endif
#endif
#if defined(CONFIG_HAS_ETH3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
if (p)
memcpy(p, bd->bi_enet3addr, 6);
+
+#ifdef CONFIG_UEC_ETH
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet3addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet3addr, 6);
+
+#endif
#endif
}
/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
*
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+ int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+ u8 port, pin;
+ int dir, open_drain, assign;
+ int i;
+
+ for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+ port = qe_iop_conf_tab[i].port;
+ pin = qe_iop_conf_tab[i].pin;
+ dir = qe_iop_conf_tab[i].dir;
+ open_drain = qe_iop_conf_tab[i].open_drain;
+ assign = qe_iop_conf_tab[i].assign;
+ qe_config_iopin(port, pin, dir, open_drain, assign);
+ }
+}
+#endif
#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
#endif
/* now restrict to preliminary range */
+ /* if cs1 is already set via debugger, leave cs0/cs1 alone */
+ if (! memctl->br1 & 1) {
#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
- memctl->br0 = CFG_BR0_PRELIM;
- memctl->or0 = CFG_OR0_PRELIM;
+ memctl->br0 = CFG_BR0_PRELIM;
+ memctl->or0 = CFG_OR0_PRELIM;
#endif
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- memctl->or1 = CFG_OR1_PRELIM;
- memctl->br1 = CFG_BR1_PRELIM;
+ memctl->or1 = CFG_OR1_PRELIM;
+ memctl->br1 = CFG_BR1_PRELIM;
#endif
+ }
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
memctl->or2 = CFG_OR2_PRELIM;
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
+#ifdef CONFIG_QE
+ /* Config QE ioports */
+ config_qe_ioports();
+#endif
+
}
* The newer 8548, etc, parts have twice as much cache, but
* use the same bit-encoding as the older 8555, etc, parts.
*
- * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
*/
int cpu_init_r(void)
{
+#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#endif
+#ifdef CONFIG_CLEAR_LAW0
+ volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+
+ /* clear alternate boot location LAW (used for sdram, or ddr bank) */
+ ecm->lawar0 = 0;
+#endif
+
#if defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
volatile uint cache_ctl;
uint svr, ver;
+ uint l2srbar;
svr = get_svr();
ver = SVR_VER(svr);
switch (cache_ctl & 0x30000000) {
case 0x20000000:
- if (ver == SVR_8548 || ver == SVR_8548_E) {
+ if (ver == SVR_8548 || ver == SVR_8548_E ||
+ ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
+ /* set L2E=1, L2I=1, & L2SRAM=0 */
+ cache_ctl = 0xc0000000;
} else {
printf ("L2 cache 256KB:");
+ /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
+ cache_ctl = 0xc8000000;
}
break;
- case 0x00000000:
case 0x10000000:
+ printf ("L2 cache 256KB:");
+ if (ver == SVR_8544 || ver == SVR_8544_E) {
+ cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
+ }
+ break;
case 0x30000000:
+ case 0x00000000:
default:
printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
return -1;
}
- asm("msync;isync");
- l2cache->l2ctl = 0x68000000; /* invalidate */
- cache_ctl = l2cache->l2ctl;
- asm("msync;isync");
-
- l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
- cache_ctl = l2cache->l2ctl;
- asm("msync;isync");
-
- printf(" enabled\n");
+ if (l2cache->l2ctl & 0x80000000) {
+ printf(" already enabled.");
+ l2srbar = l2cache->l2srbar0;
+#ifdef CFG_INIT_L2_ADDR
+ if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
+ l2srbar = CFG_INIT_L2_ADDR;
+ l2cache->l2srbar0 = l2srbar;
+ printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
+ }
+#endif /* CFG_INIT_L2_ADDR */
+ puts("\n");
+ } else {
+ asm("msync;isync");
+ l2cache->l2ctl = cache_ctl; /* invalidate & enable */
+ asm("msync;isync");
+ printf(" enabled\n");
+ }
#else
printf("L2 cache: disabled\n");
#endif
+#ifdef CONFIG_QE
+ uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+ qe_init(qe_base);
+ qe_reset();
+#endif
return 0;
}
mtspr(SPRN_TCR, TCR_PIE);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
+
+#ifdef CONFIG_INTERRUPTS
+ volatile ccsr_pic_t *pic = &immr->im_pic;
+
+ pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
+ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
+
+ pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
+ debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2);
+
+ pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
+ debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3);
+
+#ifdef CONFIG_PCI1
+ pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
+ debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8);
+#endif
+#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
+ pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
+ debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9);
+#endif
+#ifdef CONFIG_PCIE1
+ pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
+ debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10);
+#endif
+#ifdef CONFIG_PCIE3
+ pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
+ debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11);
+#endif
+
+ pic->ctpr=0; /* 40080 clear current task priority register */
+#endif
+
return (0);
}
u8 header_type;
pci_hose_read_config_byte(hose,
- PCI_BDF(0,17,0),
+ PCI_BDF(0,BRIDGE_ID,0),
PCI_HEADER_TYPE,
&header_type);
}
--- /dev/null
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_85xx.h"
+
+#if defined(CONFIG_QE)
+#define NUM_OF_PINS 32
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+ u32 pin_2bit_mask;
+ u32 pin_2bit_dir;
+ u32 pin_2bit_assign;
+ u32 pin_1bit_mask;
+ u32 tmp_val;
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile par_io_t *par_io = (volatile par_io_t *)
+ &(im->im_gur.qe_par_io);
+
+ /* Caculate pin location and 2bit mask and dir */
+ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+ pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+
+ /* Setup the direction */
+ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+ in_be32(&par_io[port].cpdir2) :
+ in_be32(&par_io[port].cpdir1);
+
+ if (pin > (NUM_OF_PINS/2) -1) {
+ out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
+ } else {
+ out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
+ }
+
+ /* Calculate pin location for 1bit mask */
+ pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+
+ /* Setup the open drain */
+ tmp_val = in_be32(&par_io[port].cpodr);
+ if (open_drain)
+ out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
+ else
+ out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
+
+ /* Setup the assignment */
+ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
+ in_be32(&par_io[port].cppar2):
+ in_be32(&par_io[port].cppar1);
+ pin_2bit_assign = (u32)(assign
+ << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+
+ /* Clear and set 2 bits mask */
+ if (pin > (NUM_OF_PINS/2) - 1) {
+ out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
+ } else {
+ out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
+ }
+}
+
+#endif /* CONFIG_QE */
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
- volatile ccsr_gur_t *gur = &immap->im_gur;
spd_eeprom_t spd;
unsigned int n_ranks;
unsigned int rank_density;
- unsigned int odt_rd_cfg, odt_wr_cfg;
+ unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
unsigned int odt_cfg, mode_odt_enable;
unsigned int refresh_clk;
#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
unsigned int max_data_rate, effective_data_rate;
unsigned int busfreq;
unsigned sdram_cfg;
- unsigned int memsize;
+ unsigned int memsize = 0;
unsigned char caslat, caslat_ctrl;
unsigned int trfc, trfc_clk, trfc_low, trfc_high;
unsigned int trcd_clk;
unsigned int mode_caslat;
unsigned char sdram_type;
unsigned char d_init;
+ unsigned int bnds;
+
+ /*
+ * Skip configuration if already configured.
+ * memsize is determined from last configured chip select.
+ */
+ if (ddr->cs0_config & 0x80000000) {
+ debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds);
+ bnds = 0xfff & ddr->cs0_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4;
+ }
+ }
+ if (ddr->cs1_config & 0x80000000) {
+ debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds);
+ bnds = 0xfff & ddr->cs1_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4; /* assume ordered bnds */
+ }
+ }
+ if (ddr->cs2_config & 0x80000000) {
+ debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds);
+ bnds = 0xfff & ddr->cs2_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4;
+ }
+ }
+ if (ddr->cs3_config & 0x80000000) {
+ debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds);
+ bnds = 0xfff & ddr->cs3_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4;
+ }
+ }
+
+ if (memsize) {
+ printf(" Reusing current %dMB configuration\n",memsize);
+ memsize = setup_laws_and_tlbs(memsize);
+ return memsize << 20;
+ }
/*
* Read SPD information.
return 0;
}
+#ifdef CONFIG_MPC8548
/*
* Adjust DDR II IO voltage biasing.
* Only 8548 rev 1 needs the fix
if ((SVR_VER(get_svr()) == SVR_8548_E) &&
(SVR_MJREV(get_svr()) == 1) &&
(spd.mem_type == SPD_MEMTYPE_DDR2)) {
+ volatile ccsr_gur_t *gur = &immap->im_gur;
gur->ddrioovcr = (0x80000000 /* Enable */
| 0x10000000);/* VSEL to 1.8V */
}
+#endif
/*
* Determine the size of each Rank in bytes.
#endif
}
+ ba_bits = 0;
+ if (spd.nbanks == 0x8)
+ ba_bits = 1;
+
ddr->cs0_config = ( 1 << 31
| (odt_rd_cfg << 20)
| (odt_wr_cfg << 16)
+ | (ba_bits << 14)
| (spd.nrow_addr - 12) << 8
| (spd.ncol_addr - 8) );
debug("\n");
*/
cpo = 0;
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- if (effective_data_rate == 266 || effective_data_rate == 333) {
+ if (effective_data_rate <= 333) {
cpo = 0x7; /* READ_LAT + 5/4 */
- } else if (effective_data_rate == 400) {
- cpo = 0x9; /* READ_LAT + 7/4 */
} else {
- /* Pure speculation */
- cpo = 0xb;
+ cpo = 0x9; /* READ_LAT + 7/4 */
}
}
if (spd.mem_type == SPD_MEMTYPE_DDR)
clk_adjust = 0x6;
else
+#ifdef CONFIG_MPC8568
+ /* Empirally setting clk_adjust */
+ clk_adjust = 0x6;
+#else
clk_adjust = 0x7;
+#endif
ddr->sdram_clk_cntl = (0
| 0x80000000
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright (C) 2003 Motorola,Inc.
- * Xianghua Xiao<X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
#endif
#undef MSR_KERNEL
-#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
/*
* Set up GOT: Global Offset Table
*
*/
- .section .bootpg,"ax"
- .globl _start_e500
+ .section .bootpg,"ax"
+ .globl _start_e500
_start_e500:
- mfspr r0, PVR
- lis r1, PVR_85xx_REV1@h
- ori r1, r1, PVR_85xx_REV1@l
- cmpw r0, r1
- bne 1f
- /* Semi-bogus errata fixup for Rev 1 */
- li r0,0x2000
- mtspr 977,r0
+/* clear registers/arrays not reset by hardware */
- /*
- * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
- * write it back immediately to fixup a Rev 1 bug (Errata CPU4)
- * for this initial TLB1 entry 0, otherwise the TLB1 entry 0
- * will be invalidated (incorrectly).
- */
- lis r2,0x1000
- mtspr MAS0,r2
- tlbre
- tlbwe
- isync
-
-1:
- /*
- * Clear and set up some registers.
- * Note: Some registers need strict synchronization by
- * sync/mbar/msync/isync when being "mtspr".
- * BookE: isync before PID,tlbivax,tlbwe
- * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
- * E500: msync,isync before L1CSR0
- * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
- * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
- * SPEFCSR
- */
-
- /* invalidate d-cache */
- mfspr r0,L1CSR0
- ori r0,r0,0x0002
- msync
- isync
- mtspr L1CSR0,r0
- isync
-
- /* disable d-cache */
- li r0,0x0
- mtspr L1CSR0,r0
-
- /* invalidate i-cache */
- mfspr r0,L1CSR1
- ori r0,r0,0x0002
- mtspr L1CSR1,r0
- isync
-
- /* disable i-cache */
- li r0,0x0
- mtspr L1CSR1,r0
- isync
-
- /* clear registers */
- li r0,0
- mtspr SRR0,r0
- mtspr SRR1,r0
- mtspr CSRR0,r0
- mtspr CSRR1,r0
- mtspr MCSRR0,r0
- mtspr MCSRR1,r0
-
- mtspr ESR,r0
- mtspr MCSR,r0
- mtspr DEAR,r0
-
- /* not needed and conflicts with some debuggers */
- /* mtspr DBCR0,r0 */
- mtspr DBCR1,r0
- mtspr DBCR2,r0
- /* not needed and conflicts with some debuggers */
- /* mtspr IAC1,r0 */
- /* mtspr IAC2,r0 */
- mtspr DAC1,r0
- mtspr DAC2,r0
+ /* L1 */
+ li r0,2
+ mtspr L1CSR0,r0 /* invalidate d-cache */
+ mtspr L1CSR1,r0 /* invalidate i-cache */
mfspr r1,DBSR
mtspr DBSR,r1 /* Clear all valid bits */
- mtspr PID0,r0
- mtspr PID1,r0
- mtspr PID2,r0
- mtspr TCR,r0
+ /*
+ * Enable L1 Caches early
+ *
+ */
- mtspr BUCSR,r0 /* disable branch prediction */
- mtspr MAS4,r0
- mtspr MAS6,r0
-#if defined(CONFIG_ENABLE_36BIT_PHYS)
- mtspr MAS7,r0
-#endif
+ lis r2,L1CSR0_CPE@H /* enable parity */
+ ori r2,r2,L1CSR0_DCE
+ mtspr L1CSR0,r2 /* enable L1 Dcache */
isync
+ mtspr L1CSR1,r2 /* enable L1 Icache */
+ isync
+ msync
/* Setup interrupt vectors */
lis r1,TEXT_BASE@h
- mtspr IVPR, r1
+ mtspr IVPR,r1
li r1,0x0100
mtspr IVOR0,r1 /* 0: Critical input */
li r1,0x0f00
mtspr IVOR15,r1 /* 15: Debug */
- /*
- * Invalidate MMU L1/L2
- *
- * Note: There is a fixup earlier for Errata CPU4 on
- * Rev 1 parts that must precede this MMU invalidation.
- */
- li r2, 0x001e
- mtspr MMUCSR0, r2
- isync
-
- /*
- * Invalidate all TLB0 entries.
- */
- li r3,4
- li r4,0
- tlbivax r4,r3
- /*
- * To avoid REV1 Errata CPU6 issues, make sure
- * the instruction following tlbivax is not a store.
- */
/*
* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
lwzu r4,0(r5) /* how many TLB1 entries we actually use */
mtctr r4
-0: lwzu r0,4(r5)
- lwzu r1,4(r5)
- lwzu r2,4(r5)
- lwzu r3,4(r5)
- mtspr MAS0,r0
- mtspr MAS1,r1
- mtspr MAS2,r2
- mtspr MAS3,r3
+0: lwzu r6,4(r5)
+ lwzu r7,4(r5)
+ lwzu r8,4(r5)
+ lwzu r9,4(r5)
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
isync
msync
tlbwe
1:
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/* Special sequence needed to update CCSRBAR itself */
- lis r4, CFG_CCSRBAR_DEFAULT@h
- ori r4, r4, CFG_CCSRBAR_DEFAULT@l
+ lis r4,CFG_CCSRBAR_DEFAULT@h
+ ori r4,r4,CFG_CCSRBAR_DEFAULT@l
- lis r5, CFG_CCSRBAR@h
- ori r5, r5, CFG_CCSRBAR@l
+ lis r5,CFG_CCSRBAR@h
+ ori r5,r5,CFG_CCSRBAR@l
srwi r6,r5,12
- stw r6, 0(r4)
+ stw r6,0(r4)
isync
- lis r5, 0xffff
+ lis r5,0xffff
ori r5,r5,0xf000
- lwz r5, 0(r5)
+ lwz r5,0(r5)
isync
- lis r3, CFG_CCSRBAR@h
- lwz r5, CFG_CCSRBAR@l(r3)
+ lis r3,CFG_CCSRBAR@h
+ lwz r5,CFG_CCSRBAR@l(r3)
isync
#endif
lwzu r5,0(r6) /* how many windows we actually use */
mtctr r5
- li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
- li r1,0x0c30
+ li r2,0x0c28 /* the first pair is reserved for */
+ li r1,0x0c30 /* boot-over-rio-or-pci */
0: lwzu r4,4(r6)
lwzu r3,4(r6)
addi r1,r1,0x0020
bdnz 0b
- /* Jump out the last 4K page and continue to 'normal' start */
-1: bl 3f
- b _start
-
-3: li r0,0
- mtspr SRR1,r0 /* Keep things disabled for now */
- mflr r1
- mtspr SRR0,r1
- rfi
-
-/*
- * r3 - 1st arg to board_init(): IMMP pointer
- * r4 - 2nd arg to board_init(): boot flag
- */
- .text
- .long 0x27051956 /* U-BOOT Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
-
- . = EXC_OFF_SYS_RESET
- .globl _start
-_start:
/* Clear and set up some registers. */
li r0,0x0000
lis r1,0xffff
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
- ori r0,r0,0x4000 /* time base is processor clock */
#if defined(CONFIG_ENABLE_36BIT_PHYS)
- ori r0,r0,0x0080 /* enable MAS7 updates */
+ ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
+#else
+ ori r0,r0,HID0_TBEN@l /* enable Timebase */
#endif
mtspr HID0,r0
-#if defined(CONFIG_ADDR_STREAMING)
- li r0,0x3000
-#else
- li r0,0x1000
-#endif
+ li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
/* Enable Branch Prediction */
#endif
/* L1 DCache is used for initial RAM */
- mfspr r2, L1CSR0
- ori r2, r2, 0x0003
- oris r2, r2, 0x0001
- mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
- isync
/* Allocate Initial RAM in data cache.
*/
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
- li r2, 512 /* 512*32=16K */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ li r2,512 /* 512*32=16K */
mtctr r2
- li r0, 0
+ li r0,0
1:
- dcbz r0, r3
- dcbtls 0,r0, r3
- addi r3, r3, 32
+ dcbz r0,r3
+ dcbtls 0,r0,r3
+ addi r3,r3,32
bdnz 1b
-#ifndef CFG_RAMBOOT
+ /* Jump out the last 4K page and continue to 'normal' start */
+#ifdef CFG_RAMBOOT
+ bl 3f
+ b _start_cont
+#else
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
- addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+ lis r3,CFG_MONITOR_BASE@h
+ ori r3,r3,CFG_MONITOR_BASE@l
+ addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3
- blr
+#endif
-in_flash:
-#endif /* CFG_RAMBOOT */
+3: li r0,0
+ mtspr SRR1,r0 /* Keep things disabled for now */
+ mflr r1
+ mtspr SRR0,r1
+ rfi
+ isync
+ .text
+ .globl _start
+_start:
+ .long 0x27051956 /* U-BOOT Magic Number */
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+
+ .align 4
+ .globl _start_cont
+_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
stwu r1,-8(r1) /* Save back chain and move SP */
lis r0,RESET_VECTOR@h /* Address of reset vector */
- ori r0,r0, RESET_VECTOR@l
+ ori r0,r0,RESET_VECTOR@l
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT
bl cpu_init_f
- bl icache_enable
bl board_init_f
isync
-/* --FIXME-- machine check with MCSRRn and rfmci */
-
+ . = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
-#if 0
+
/* Critical input. */
- CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
-#endif
-/* Machine check --FIXME-- Should be MACH_EXCEPTION */
- CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
+ CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
+
+/* Machine check */
+ MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x0300, DataStorage, UnknownException)
STD_EXCEPTION(0x0400, InstStorage, UnknownException)
/* External Interrupt exception. */
- STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
+ STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
/* Alignment exception. */
. = 0x0600
mtlr r6
blrl
.L_Alignment:
- .long AlignmentException - _start + EXC_OFF_SYS_RESET
- .long int_return - _start + EXC_OFF_SYS_RESET
+ .long AlignmentException - _start + _START_OFFSET
+ .long int_return - _start + _START_OFFSET
/* Program check exception */
. = 0x0700
mtlr r6
blrl
.L_ProgramCheck:
- .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
- .long int_return - _start + EXC_OFF_SYS_RESET
+ .long ProgramCheckException - _start + _START_OFFSET
+ .long int_return - _start + _START_OFFSET
/* No FPU on MPC85xx. This exception is not supposed to happen.
*/
* r3-... arguments
*/
SystemCall:
- addis r11,r0,0 /* get functions table addr */
- ori r11,r11,0 /* Note: this code is patched in trap_init */
- addis r12,r0,0 /* get number of functions */
+ addis r11,r0,0 /* get functions table addr */
+ ori r11,r11,0 /* Note: this code is patched in trap_init */
+ addis r12,r0,0 /* get number of functions */
ori r12,r12,0
- cmplw 0, r0, r12
+ cmplw 0,r0,r12
bge 1f
- rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
+ rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
add r11,r11,r0
lwz r11,0(r11)
- li r20,0xd00-4 /* Get stack pointer */
+ li r20,0xd00-4 /* Get stack pointer */
lwz r12,0(r20)
- subi r12,r12,12 /* Adjust stack pointer */
+ subi r12,r12,12 /* Adjust stack pointer */
li r0,0xc00+_end_back-SystemCall
- cmplw 0, r0, r12 /* Check stack overflow */
+ cmplw 0,r0,r12 /* Check stack overflow */
bgt 1f
stw r12,0(r20)
_end_of_vectors:
- . = 0x2100
+ . = . + (0x100 - ( . & 0xff )) /* align for debug */
/*
* This code finishes saving the registers to the exception frame
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
- mtspr 990,r2 /* SRR2 */
- mtspr 991,r0 /* SRR3 */
+ mtspr SPRN_CSRR0,r2
+ mtspr SPRN_CSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfci
+mck_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SPRN_MCSRR0,r2
+ mtspr SPRN_MCSRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfmci
+
/* Cache functions.
*/
invalidate_icache:
mfspr r0,L1CSR1
- ori r0,r0,0x0002
+ ori r0,r0,L1CSR1_ICFI
+ msync
+ isync
mtspr L1CSR1,r0
isync
- blr /* entire I cache */
+ blr /* entire I cache */
invalidate_dcache:
mfspr r0,L1CSR0
- ori r0,r0,0x0002
+ ori r0,r0,L1CSR0_DCFI
msync
isync
mtspr L1CSR0,r0
.globl icache_disable
icache_disable:
mfspr r0,L1CSR1
- lis r1,0xfffffffe@h
- ori r1,r1,0xfffffffe@l
- and r0,r0,r1
+ lis r3,0
+ ori r3,r3,L1CSR1_ICE
+ andc r0,r0,r3
mtspr L1CSR1,r0
isync
blr
.globl icache_status
icache_status:
mfspr r3,L1CSR1
- andi. r3,r3,1
+ andi. r3,r3,L1CSR1_ICE
blr
.globl dcache_enable
.globl dcache_disable
dcache_disable:
- mfspr r0,L1CSR0
- lis r1,0xfffffffe@h
- ori r1,r1,0xfffffffe@l
- and r0,r0,r1
- msync
- isync
+ mfspr r3,L1CSR0
+ lis r4,0
+ ori r4,r4,L1CSR0_DCE
+ andc r3,r3,r4
mtspr L1CSR0,r0
isync
blr
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
- andi. r3,r3,1
+ andi. r3,r3,L1CSR0_DCE
blr
.globl get_pir
get_pir:
- mfspr r3, PIR
+ mfspr r3,PIR
blr
.globl get_pvr
get_pvr:
- mfspr r3, PVR
+ mfspr r3,PVR
blr
.globl get_svr
get_svr:
- mfspr r3, SVR
+ mfspr r3,SVR
blr
.globl wr_tcr
wr_tcr:
- mtspr TCR, r3
+ mtspr TCR,r3
blr
/*------------------------------------------------------------------------------- */
*/
.globl relocate_code
relocate_code:
- mr r1, r3 /* Set new stack pointer */
- mr r9, r4 /* Save copy of Init Data pointer */
- mr r10, r5 /* Save copy of Destination Address */
+ mr r1,r3 /* Set new stack pointer */
+ mr r9,r4 /* Save copy of Init Data pointer */
+ mr r10,r5 /* Save copy of Destination Address */
- mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ mr r3,r5 /* Destination Address */
+ lis r4,CFG_MONITOR_BASE@h /* Source Address */
+ ori r4,r4,CFG_MONITOR_BASE@l
lwz r5,GOT(__init_end)
sub r5,r5,r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* Offset:
*/
- sub r15, r10, r4
+ sub r15,r10,r4
/* First our own GOT */
- add r14, r14, r15
+ add r14,r14,r15
/* the the one used by the C code */
- add r30, r30, r15
+ add r30,r30,r15
/*
* Now relocate code
* initialization, now running from RAM.
*/
- addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ addi r0,r10,in_ram - _start + _START_OFFSET
mtlr r0
blr /* NEVER RETURNS! */
-
+ .globl in_ram
in_ram:
/*
lwz r3,GOT(__bss_start)
lwz r4,GOT(_end)
- cmplw 0, r3, r4
+ cmplw 0,r3,r4
beq 6f
- li r0, 0
+ li r0,0
5:
- stw r0, 0(r3)
- addi r3, r3, 4
- cmplw 0, r3, r4
+ stw r0,0(r3)
+ addi r3,r3,4
+ cmplw 0,r3,r4
bne 5b
6:
- mr r3, r9 /* Init Data pointer */
- mr r4, r10 /* Destination Address */
+ mr r3,r9 /* Init Data pointer */
+ mr r4,r10 /* Destination Address */
bl board_init_r
/*
*/
.globl trap_init
trap_init:
- lwz r7, GOT(_start)
- lwz r8, GOT(_end_of_vectors)
+ lwz r7,GOT(_start_of_vectors)
+ lwz r8,GOT(_end_of_vectors)
- li r9, 0x100 /* reset vector always at 0x100 */
+ li r9,0x100 /* reset vector always at 0x100 */
- cmplw 0, r7, r8
+ cmplw 0,r7,r8
bgelr /* return if r7>=r8 - just in case */
mflr r4 /* save link register */
1:
- lwz r0, 0(r7)
- stw r0, 0(r9)
- addi r7, r7, 4
- addi r9, r9, 4
- cmplw 0, r7, r8
+ lwz r0,0(r7)
+ stw r0,0(r9)
+ addi r7,r7,4
+ addi r9,r9,4
+ cmplw 0,r7,r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
- li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r7,.L_CriticalInput - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET
+ li r7,.L_MachineCheck - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET
+ li r7,.L_DataStorage - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET
+ li r7,.L_InstStorage - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ li r7,.L_ExtInterrupt - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ li r7,.L_Alignment - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r7,.L_ProgramCheck - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET
+ li r7,.L_FPUnavailable - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET
- li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+ li r7,.L_Decrementer - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_IntervalTimer - _start + _START_OFFSET
+ li r8,_end_of_vectors - _start + _START_OFFSET
2:
bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
+ addi r7,r7,0x100 /* next exception vector */
+ cmplw 0,r7,r8
blt 2b
lis r7,0x0
- mtspr IVPR, r7
+ mtspr IVPR,r7
mtlr r4 /* restore link register */
blr
* Function: relocate entries for one exception vector
*/
trap_reloc:
- lwz r0, 0(r7) /* hdlr ... */
- add r0, r0, r3 /* ... += dest_addr */
- stw r0, 0(r7)
+ lwz r0,0(r7) /* hdlr ... */
+ add r0,r0,r3 /* ... += dest_addr */
+ stw r0,0(r7)
- lwz r0, 4(r7) /* int_return ... */
- add r0, r0, r3 /* ... += dest_addr */
- stw r0, 4(r7)
+ lwz r0,4(r7) /* int_return ... */
+ add r0,r0,r3 /* ... += dest_addr */
+ stw r0,4(r7)
blr
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2,512
- mtctr r2
-1: icbi r0, r3
- dcbi r0, r3
- addi r3, r3, 32
+ lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
+ li r4,512
+ mtctr r4
+1: icbi r0,r3
+ dcbi r0,r3
+ addi r3,r3,32
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
/*
* linux/arch/ppc/kernel/traps.c
*
+ * Copyright 2007 Freescale Semiconductor.
* Copyright (C) 2003 Motorola
* Modified by Xianghua Xiao(x.xiao@motorola.com)
*
panic("Critical Input Exception");
}
+int machinecheck_count = 0;
+int machinecheck_error = 0;
void
MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
+ unsigned int mcsr, mcsrr0, mcsrr1, mcar;
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
return;
}
+ mcsrr0 = mfspr(SPRN_MCSRR0);
+ mcsrr1 = mfspr(SPRN_MCSRR1);
+ mcsr = mfspr(SPRN_MCSR);
+ mcar = mfspr(SPRN_MCAR);
+
+ machinecheck_count++;
+ machinecheck_error=1;
+
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Machine check in kernel mode.\n");
- printf("Caused by (from msr): ");
- printf("regs %p ",regs);
- switch( regs->msr & 0x000F0000) {
- case (0x80000000>>12):
- printf("Machine check signal - probably due to mm fault\n"
- "with mmu off\n");
- break;
- case (0x80000000>>13):
- printf("Transfer error ack signal\n");
- break;
- case (0x80000000>>14):
- printf("Data parity signal\n");
- break;
- case (0x80000000>>15):
- printf("Address parity signal\n");
- break;
- default:
- printf("Unknown values in msr\n");
- }
+ printf("Caused by (from mcsr): ");
+ printf("mcsr = 0x%08x\n", mcsr);
+ if (mcsr & 0x80000000)
+ printf("Machine check input pin\n");
+ if (mcsr & 0x40000000)
+ printf("Instruction cache parity error\n");
+ if (mcsr & 0x20000000)
+ printf("Data cache push parity error\n");
+ if (mcsr & 0x10000000)
+ printf("Data cache parity error\n");
+ if (mcsr & 0x00000080)
+ printf("Bus instruction address error\n");
+ if (mcsr & 0x00000040)
+ printf("Bus Read address error\n");
+ if (mcsr & 0x00000020)
+ printf("Bus Write address error\n");
+ if (mcsr & 0x00000010)
+ printf("Bus Instruction data bus error\n");
+ if (mcsr & 0x00000008)
+ printf("Bus Read data bus error\n");
+ if (mcsr & 0x00000004)
+ printf("Bus Write bus error\n");
+ if (mcsr & 0x00000002)
+ printf("Bus Instruction parity error\n");
+ if (mcsr & 0x00000001)
+ printf("Bus Read parity error\n");
+
show_regs(regs);
+ printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n",
+ mcsr, mcsrr0, mcsrr1, mcar);
print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
+ if (machinecheck_count > 10) {
+ panic("machine check count too high\n");
+ }
+
+ if (machinecheck_count > 1) {
+ regs->nip += 4; /* skip offending instruction */
+ printf("Skipping current instr, Returning to 0x%08x\n",
+ regs->nip);
+ } else {
+ printf("Returning back to 0x%08x\n",regs->nip);
+ }
}
void
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
+void
+ExtIntException(struct pt_regs *regs)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_pic_t *pic = &immap->im_pic;
+ uint vect;
+
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx",
+ regs->nip, regs->msr, regs->trap);
+ vect = pic->iack0;
+ printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect);
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ machinecheck_count++;
+#ifdef EXTINT_NOSKIP
+ printf("Returning back to 0x%08x\n",regs->nip);
+#else
+ regs->nip += 4; /* skip offending instruction */
+ printf("Skipping current instr, Returning to 0x%08x\n",regs->nip);
+#endif
+
+}
void
DebugException(struct pt_regs *regs)
#include <common.h>
#include <mpc86xx.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Breathe some life into the CPU...
*
void cpu_init_f(void)
{
- DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
- /* enable SYNCBE | ABE bits in HID1 */
- set_hid1(get_hid1() | 0x00000C00);
+ /* enable EMCP, SYNCBE | ABE bits in HID1 */
+ set_hid1(get_hid1() | 0x80000C00);
}
/*
* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
* Xianghua Xiao (X.Xiao@motorola.com)
*
- * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port)
+ * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
{
int ret;
- /*
- * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
- * implement PEX10 errata. As INT is active high, it
- * will cause core to take 0x500 interrupt.
- *
- * Due to the PIC's default pass through mode, as soon
- * as interrupts are enabled (MSR[EE] = 1), an interrupt
- * will be taken and u-boot will hang. This is due to a
- * hardware change (per an errata fix) on new revisions
- * of the board with Rev 2.x parts.
- *
- * Setting the PIC to mixed mode prevents the hang.
- */
- if ((get_svr() & 0xf0) == 0x20) {
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- immr->im_pic.gcr = MPC86xx_PICGCR_RST;
- while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
- immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
- }
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ immr->im_pic.gcr = MPC86xx_PICGCR_RST;
+ while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
+ immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
/* call cpu specific function from $(CPU)/interrupts.c */
ret = interrupt_init_cpu(&decrementer_count);
get_msr(),
get_dec());
+#ifdef CONFIG_INTERRUPTS
+ volatile ccsr_pic_t *pic = &immr->im_pic;
+
+ pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
+ debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
+
+ pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
+ debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2);
+
+ pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
+ debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3);
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
+ pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
+ debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8);
+#endif
+#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
+ pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
+ debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9);
+#endif
+
+ pic->ctpr = 0; /* 40080 clear current task priority register */
+#endif
+
return 0;
}
timestamp++;
- ppcDcbf((unsigned long)×tamp);
-
/* Restore Decrementer Count */
set_dec(decrementer_count);
#include <mpc86xx.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(sys_info_t *sysInfo)
{
int get_clocks(void)
{
- DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
get_sys_info(&sys_info);
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_IDENT_STRING ""
#endif
-/* We don't want the MMU yet.
-*/
-#undef MSR_KERNEL
-/* Machine Check and Recoverable Interr. */
-#define MSR_KERNEL ( MSR_ME | MSR_RI )
+/*
+ * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
+ */
/*
* Set up GOT: Global Offset Table
bl secondary_cpu_setup
#endif
+1:
+#ifdef CFG_RAMBOOT
/* disable everything */
-1: li r0, 0
+ li r0, 0
mtspr HID0, r0
sync
mtmsr 0
+#endif
+
bl invalidate_bats
sync
#ifdef CFG_L2
/* init the L2 cache */
- addis r3, r0, L2_INIT@h
+ lis r3, L2_INIT@h
ori r3, r3, L2_INIT@l
mtspr l2cr, r3
/* invalidate the L2 cache */
bl setup_ccsrbar
#endif
-
- /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */
-
- /* skip fixups if not Rev 1.0 */
- mfspr r4, SVR
- rlwinm r4,r4,0,24,31
- cmpwi r4,0x10
- bne 1f
-
- lis r3,MCM_ABCR@ha
- lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */
-
- /* set ABCR[A_STRM_CNT] = 0 */
- rlwinm r4,r4,0,0,29
-
- /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */
- addi r0,r0,1
- rlwimi r4,r0,12,18,19
-
- stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */
- sync
-
- /* Set DBCR[ERD_DIS] */
- lis r3,MCM_DBCR@ha
- lwz r4,MCM_DBCR@l(r3)
- oris r4, r4, 0x4000
- stw r4,MCM_DBCR@l(r3)
- sync
-1:
/* setup the law entries */
bl law_entry
sync
-
-
-#if (EMULATOR_RUN == 1)
- /* On the emulator we want to adjust these ASAP */
- /* otherwise things are sloooow */
- /* Setup OR0 (LALE FIX)*/
- lis r3, CFG_CCSRBAR@h
- ori r3, r3, 0x5004
- li r4, 0x0FF3
- stw r4, 0(r3)
- sync
-
- /* Setup LCRR */
- lis r3, CFG_CCSRBAR@h
- ori r3, r3, 0x50D4
- lis r4, 0x8000
- ori r4, r4, 0x0002
- stw r4, 0(r3)
- sync
-#endif
-#if 1
- /* make sure timer enabled in guts register too */
- lis r3, CFG_CCSRBAR@h
- oris r3,r3, 0xE
- ori r3,r3,0x0070
- lwz r4, 0(r3)
- lis r5,0xFFFC
- ori r5,r5,0x5FFF
- and r4,r4,r5
- stw r4,0(r3)
-#endif
/*
* Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS.
#ifdef RUN_DIAG
- /* Sri: Code to run the diagnostic automatically */
-
/* Load PX_AUX register address in r4 */
lis r4, 0xf810
ori r4, r4, 0x6
.globl invalidate_bats
invalidate_bats:
+ li r0, 0
/* invalidate BATs */
mtspr IBAT0U, r0
mtspr IBAT1U, r0
mfmsr r7
li r8,MSR_IP
andc r7,r7,r8
+ ori r7,r7,MSR_ME /* Enable Machine Check */
mtmsr r7
mtlr r4 /* restore link register */
sync
isync
- /*SYNCBE|ABE in HID1*/
+ /* MCP|SYNCBE|ABE in HID1 */
mfspr r4, HID1
+ oris r4, r4, 0x8000
ori r4, r4, 0x0C00
mtspr HID1, r4
sync
#include <command.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
void
print_backtrace(unsigned long *sp)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int cnt = 0;
unsigned long i;
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
printf("regs %p ", regs);
- switch (regs->msr & 0x000F0000) {
- case (0x80000000 >> 12):
+ switch ( regs->msr & 0x001F0000) {
+ case (0x80000000>>11):
+ printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0));
+ break;
+ case (0x80000000>>12):
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif
+ printf("UnknownException regs@%x\n", regs);
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
static struct pci_controller ppc440_hose = {0};
-void pci_440_init (struct pci_controller *hose)
+int pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
- return;
+ return -1;
}
#elif defined(CONFIG_440GP)
unsigned long strap;
if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
- return;
+ return -1;
}
#endif
#endif /* CONFIG_DISABLE_PISE_TEST */
* PCI controller init
*--------------------------------------------------------------------------*/
hose->first_busno = 0;
- hose->last_busno = 0xff;
+ hose->last_busno = 0;
/* PCI I/O space */
pci_set_region(hose->regions + reg_num++,
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
- return;
+ return -1;
}
pci_register_hose( hose );
#endif
hose->last_busno = pci_hose_scan(hose);
}
+ return hose->last_busno;
}
void pci_init_board(void)
{
- pci_440_init (&ppc440_hose);
+ int busno;
+
+ busno = pci_440_init (&ppc440_hose);
#if defined(CONFIG_440SPE)
- pcie_setup_hoses();
+ pcie_setup_hoses(busno + 1);
#endif
}
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
LNKW_X8 = 0x8
};
+static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
+{
+ u8 *base = (u8*)hose->cfg_data;
+
+ /* use local configuration space for the first bus */
+ if (PCI_BUS(devfn) == 0) {
+ if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
+ base = (u8*)CFG_PCIE0_XCFGBASE;
+ if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
+ base = (u8*)CFG_PCIE1_XCFGBASE;
+ if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
+ base = (u8*)CFG_PCIE2_XCFGBASE;
+ }
+
+ return base;
+}
+
+static void pcie_dmer_disable(void)
+{
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
+}
+
+static void pcie_dmer_enable(void)
+{
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
+}
+
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
+ u8 *address;
*val = 0;
+
+ /*
+ * Bus numbers are relative to hose->first_busno
+ */
+ devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
/*
- * 440SPE implements only one function per port
+ * NOTICE: configuration space ranges are currenlty mapped only for
+ * the first 16 buses, so such limit must be imposed. In case more
+ * buses are required the TLB settings in board/amcc/<board>/init.S
+ * need to be altered accordingly (one bus takes 1 MB of memory space).
*/
- if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+ if (PCI_BUS(devfn) >= 16)
return 0;
- devfn = PCI_BDF(0,0,0);
+ /*
+ * Only single device/single function is supported for the primary and
+ * secondary buses of the 440SPe host bridge.
+ */
+ if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+ ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+ return 0;
+
+ address = pcie_get_base(hose, devfn);
offset += devfn << 4;
+ /*
+ * Reading from configuration space of non-existing device can
+ * generate transaction errors. For the read duration we suppress
+ * assertion of machine check exceptions to avoid those.
+ */
+ pcie_dmer_disable ();
+
switch (len) {
case 1:
*val = in_8(hose->cfg_data + offset);
*val = in_le16((u16 *)(hose->cfg_data + offset));
break;
default:
- *val = in_le32((u32 *)(hose->cfg_data + offset));
+ *val = in_le32((u32*)(hose->cfg_data + offset));
break;
}
+
+ pcie_dmer_enable ();
+
return 0;
}
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 val) {
+ u8 *address;
+
+ /*
+ * Bus numbers are relative to hose->first_busno
+ */
+ devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
/*
- * 440SPE implements only one function per port
+ * Same constraints as in pcie_read_config().
*/
- if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+ if (PCI_BUS(devfn) >= 16)
return 0;
- devfn = PCI_BDF(0,0,0);
+ if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+ ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+ return 0;
+
+ address = pcie_get_base(hose, devfn);
offset += devfn << 4;
+ /*
+ * Suppress MCK exceptions, similar to pcie_read_config()
+ */
+ pcie_dmer_disable ();
+
switch (len) {
case 1:
out_8(hose->cfg_data + offset, val);
out_le32((u32 *)(hose->cfg_data + offset), val);
break;
}
+
+ pcie_dmer_enable ();
+
return 0;
}
u32 v;
int rv;
- rv = pcie_read_config(hose, dev, offset, 1, &v);
+ rv = pcie_read_config(hose, dev, offset, 1, &v);
*val = (u8)v;
return rv;
}
volatile void *rmbase = NULL;
pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
switch (port) {
case 0:
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
printf("PCIE:%d successfully set as rootpoint\n",port);
+
+ /* Set Device and Vendor Id */
+ switch (port) {
+ case 0:
+ out_le16(mbase + 0x200, 0xaaa0);
+ out_le16(mbase + 0x202, 0xbed0);
+ break;
+ case 1:
+ out_le16(mbase + 0x200, 0xaaa1);
+ out_le16(mbase + 0x202, 0xbed1);
+ break;
+ case 2:
+ out_le16(mbase + 0x200, 0xaaa2);
+ out_le16(mbase + 0x202, 0xbed2);
+ break;
+ default:
+ out_le16(mbase + 0x200, 0xaaa3);
+ out_le16(mbase + 0x202, 0xbed3);
+ }
+
+ /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
+ out_le32(mbase + 0x208, 0x06040001);
+
}
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
attempts = 10;
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
+#define DCRN_PEGPL_CFG(base) (base + 0x16)
/*
* System DCRs (SDRs)
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
-#define PECFG_PIM1LAL 0x348
-#define PECFG_PIM1LAH 0x34c
+#define PECFG_PIM1LAL 0x348
+#define PECFG_PIM1LAH 0x34c
#define PECFG_PIM01SAL 0x350
#define PECFG_PIM01SAH 0x354
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
+#define GPL_DMER_MASK_DISA 0x02000000
+
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);
void yucca_setup_pcie_fpga_rootpoint(int port);
typedef struct bank_param BANKPARMS;
#ifdef CFG_SIMULATE_SPD_EEPROM
-extern unsigned char cfg_simulate_spd_eeprom[128];
+extern const unsigned char cfg_simulate_spd_eeprom[128];
#endif
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static unsigned char spd_read(uchar chip, uint addr);
static void get_spd_info(unsigned long *dimm_populated,
/* Defines for the Read Cycle Delay test */
#define NUMMEMTESTS 8
#define NUMMEMWORDS 8
-#define NUMLOOPS 256 /* memory test loops */
+#define NUMLOOPS 64 /* memory test loops */
#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+/*
+ * To provide an interface for board specific config values in this common
+ * DDR setup code, we implement he "weak" default functions here. They return
+ * the default value back to the caller.
+ *
+ * Please see include/configs/yucca.h for an example fora board specific
+ * implementation.
+ */
+u32 __ddr_wrdtr(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
+
+u32 __ddr_clktr(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
+
/* Private Structure Definitions */
* Prototypes
*-----------------------------------------------------------------------------*/
static unsigned long sdram_memsize(void);
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static void get_spd_info(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
#else
static void DQS_calibration_process(void);
#endif
-#if defined(DEBUG)
static void ppc440sp_sdram_register_dump(void);
-#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
*-----------------------------------------------------------------*/
mfsdram(SDRAM_WRDTR, val);
mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
- (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
+ ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
/*------------------------------------------------------------------
* Set the SDRAM Clock Timing Register
*-----------------------------------------------------------------*/
mfsdram(SDRAM_CLKTR, val);
-#ifdef CFG_44x_DDR2_CKTR_180
- mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
-#else
- mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
-#endif
+ mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
+ ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
/*------------------------------------------------------------------
* Program the BxCF registers.
dram_size = sdram_memsize();
/* and program tlb entries for this size (dynamic) */
- program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
+ /*
+ * Program TLB entries with caches enabled, for best performace
+ * while auto-calibrating and ECC generation
+ */
+ program_tlb(0, 0, dram_size, 0);
/*------------------------------------------------------------------
* DQS calibration.
/*------------------------------------------------------------------
* If ecc is enabled, initialize the parity bits.
*-----------------------------------------------------------------*/
- program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
+ program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
#endif
-#ifdef DEBUG
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(0, dram_size);
+ program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
ppc440sp_sdram_register_dump();
-#endif
return dram_size;
}
}
}
-#ifdef CONFIG_ADD_RAM_INFO
void board_add_ram_info(int use_default)
{
PPC440_SYS_INFO board_cfg;
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
-#endif
/*------------------------------------------------------------------
* For the memory DIMMs installed, this routine verifies that they
printf("\nERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
+ ppc440sp_sdram_register_dump();
spd_ddr_init_hang ();
}
dcr_data = mfdcr(SDRAM_R3BAS);
printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
}
+#else
+static void ppc440sp_sdram_register_dump(void)
+{
+}
#endif
#endif /* CONFIG_SPD_EEPROM */
#define BI_PHYMODE_MII 7
#endif
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
int ethgroup = -1;
#endif
#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long mfr;
#endif
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
/* set speed */
if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
|| (loop_count >= NUM_RX_BUFF))
break;
+
loop_count++;
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
handled++;
data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
if (data_len) {
if (NUM_RX_BUFF == hw_p->rx_i_index)
hw_p->rx_i_index = 0;
+ hw_p->rx_slot++;
+ if (NUM_RX_BUFF == hw_p->rx_slot)
+ hw_p->rx_slot = 0;
+
/* AS.HARNOIS
* free receive buffer only when
* buffer has been handled (eth_rx)
out32(GPIO0_TCR, reg);
}
+#ifdef GPIO1
if (gpio_core == GPIO1) {
/*
* Setup output value
* 0 -> low level
* else -> don't touch
*/
- reg = in32(GPIO0_OR);
+ reg = in32(GPIO1_OR);
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
reg |= (0x80000000 >> (i));
else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
reg &= ~(0x80000000 >> (i));
- out32(GPIO0_OR, reg);
+ out32(GPIO1_OR, reg);
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
out32(GPIO1_TCR, reg);
}
+#endif /* GPIO1 */
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
/*
* Disable memory controller.
*/
- mtsdram0(mem_mcopt1, 0x00000000);
+ mtsdram(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
- mtsdram0(mem_mb0cf, mb0cf[i].reg);
- mtsdram0(mem_sdtr1, sdtr1);
- mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
+ mtsdram(mem_mb0cf, mb0cf[i].reg);
+ mtsdram(mem_sdtr1, sdtr1);
+ mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
- mtsdram0(mem_mcopt1, 0x80800000);
+ mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
/*
- * OK, size detected -> all done
+ * OK, size detected. Enable second bank if
+ * defined (assumes same type as bank 0)
*/
+#ifdef CONFIG_SDRAM_BANK1
+ u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
+
+ mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+ mtsdram(mem_mcopt1, 0x80800000);
+ udelay(10000);
+
+ /*
+ * Check if 2nd bank is really available.
+ * If the size not equal to the size of the first
+ * bank, then disable the 2nd bank completely.
+ */
+ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
+ mb0cf[i].size) {
+ mtsdram(mem_mb1cf, 0);
+ mtsdram(mem_mcopt1, 0);
+ }
+#endif
return;
}
}
#include <config.h>
-#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-
#define ONE_BILLION 1000000000
struct sdram_conf_s {
unsigned long i;
unsigned long est; /* current estimate */
unsigned long plloutb;
+ unsigned long cpr_pllc;
u32 reg;
+ /* check the pll feedback source */
+ mfcpr(cprpllc, cpr_pllc);
+
get_sys_info(&sysinfo);
- plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
- / sysinfo.pllFwdDivB);
+ plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
+ sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) /
+ sysinfo.pllFwdDivB);
udiv = 256; /* Assume lowest possible serial clk */
div = plloutb / (16 * baudrate); /* total divisor */
umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
void get_sys_info (PPC405_SYS_INFO * sysInfo)
{
unsigned long cpr_plld;
+ unsigned long cpr_pllc;
unsigned long cpr_primad;
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
unsigned long primad_cpudv;
* Read PLL Mode registers
*/
mfcpr(cprplld, cpr_plld);
+ mfcpr(cprpllc, cpr_pllc);
/*
* Determine forward divider A
sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
/*
- * Determine forward divider B (should be equal to A)
+ * Determine forward divider B
*/
sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
- if (sysInfo->pllFwdDivB == 0) {
+ if (sysInfo->pllFwdDivB == 0)
sysInfo->pllFwdDivB = 8;
- }
/*
* Determine FBK_DIV.
*/
sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
- if (sysInfo->pllFbkDiv == 0) {
+ if (sysInfo->pllFbkDiv == 0)
sysInfo->pllFbkDiv = 256;
- }
/*
* Read CPR_PRIMAD register
* Determine PLB_DIV.
*/
sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
- if (sysInfo->pllPlbDiv == 0) {
+ if (sysInfo->pllPlbDiv == 0)
sysInfo->pllPlbDiv = 16;
- }
/*
* Determine EXTBUS_DIV.
*/
sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
- if (sysInfo->pllExtBusDiv == 0) {
+ if (sysInfo->pllExtBusDiv == 0)
sysInfo->pllExtBusDiv = 16;
- }
/*
* Determine OPB_DIV.
*/
sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
- if (sysInfo->pllOpbDiv == 0) {
+ if (sysInfo->pllOpbDiv == 0)
sysInfo->pllOpbDiv = 16;
- }
/*
* Determine the M factor
*/
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
+ if (cpr_pllc & PLLC_SRC_MASK)
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
+ else
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
/*
* Determine VCO clock frequency
* Determine CPU clock frequency
*/
primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
- if (primad_cpudv == 0) {
+ if (primad_cpudv == 0)
primad_cpudv = 16;
- }
- sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
+ sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) /
+ sysInfo->pllFwdDiv / primad_cpudv;
/*
* Determine PLB clock frequency
*/
- sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
+ sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
+ sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
}
/********************************************
mtdcr ebccfgd,r3
#endif
-#ifndef CFG_CPC0_PCI
- li r3,CPC0_PCI_HOST_CFG_EN
-#ifdef CONFIG_BUBINGA
- /*
- !-----------------------------------------------------------------------
- ! Check FPGA for PCI internal/external arbitration
- ! If board is set to internal arbitration, update cpc0_pci
- !-----------------------------------------------------------------------
- */
- addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
- ori r5,r5,FPGA_REG1@l
- lbz r5,0x0(r5) /* read to get PCI arb selection */
- andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
- beq ..pci_cfg_set /* if not set, then bypass reg write*/
-#endif
- ori r3,r3,CPC0_PCI_ARBIT_EN
-#else /* CFG_CPC0_PCI */
- li r3,CFG_CPC0_PCI
-#endif /* CFG_CPC0_PCI */
-..pci_cfg_set:
- mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
-
/*
!-----------------------------------------------------------------------
! Check to see if chip is in bypass mode.
..no_pllset:
#endif /* CONFIG_BUBINGA */
+#ifdef CONFIG_TAIHU
+ mfdcr r4, CPC0_BOOT
+ andi. r5, r4, CPC0_BOOT_SEP@l
+ bne strap_1 /* serial eeprom present */
+ addis r5,0,CPLD_REG0_ADDR@h
+ ori r5,r5,CPLD_REG0_ADDR@l
+ andi. r5, r5, 0x10
+ bne _pci_66mhz
+#endif /* CONFIG_TAIHU */
+
+#if defined(CONFIG_ZEUS)
+ mfdcr r4, CPC0_BOOT
+ andi. r5, r4, CPC0_BOOT_SEP@l
+ bne strap_1 /* serial eeprom present */
+ lis r3,0x0000
+ addi r3,r3,0x3030
+ lis r4,0x8042
+ addi r4,r4,0x223e
+ b 1f
+strap_1:
+ mfdcr r3, CPC0_PLLMR0
+ mfdcr r4, CPC0_PLLMR1
+ b 1f
+#endif
+
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
ori r4,r4,PLLMR1_DEFAULT@l /* */
+#ifdef CONFIG_TAIHU
+ b 1f
+_pci_66mhz:
+ addis r3,0,PLLMR0_DEFAULT_PCI66@h
+ ori r3,r3,PLLMR0_DEFAULT_PCI66@l
+ addis r4,0,PLLMR1_DEFAULT_PCI66@h
+ ori r4,r4,PLLMR1_DEFAULT_PCI66@l
+ b 1f
+strap_1:
+ mfdcr r3, CPC0_PLLMR0
+ mfdcr r4, CPC0_PLLMR1
+#endif /* CONFIG_TAIHU */
+
+1:
b pll_write /* Write the CPC0_PLLMR with new value */
pll_done:
#if defined(CONFIG_440)
-#include <ppc4xx.h>
#include <ppc440.h>
#include <asm/io.h>
#include <asm/mmu.h>
unsigned long tlb_word2_i_value;
} region_t;
+void remove_tlb(u32 vaddr, u32 size)
+{
+ int i;
+ u32 tlb_word0_value;
+ u32 tlb_vaddr;
+ u32 tlb_size = 0;
+
+ /* First, find the index of a TLB entry not being used */
+ for (i=0; i<PPC4XX_TLB_SIZE; i++) {
+ tlb_word0_value = mftlb1(i);
+ tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
+ if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
+ (tlb_vaddr >= vaddr)) {
+ /*
+ * TLB is enabled and start address is lower or equal
+ * than the area we are looking for. Now we only have
+ * to check the size/end address for a match.
+ */
+ switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
+ case TLB_WORD0_SIZE_1KB:
+ tlb_size = 1 << 10;
+ break;
+ case TLB_WORD0_SIZE_4KB:
+ tlb_size = 4 << 10;
+ break;
+ case TLB_WORD0_SIZE_16KB:
+ tlb_size = 16 << 10;
+ break;
+ case TLB_WORD0_SIZE_64KB:
+ tlb_size = 64 << 10;
+ break;
+ case TLB_WORD0_SIZE_256KB:
+ tlb_size = 256 << 10;
+ break;
+ case TLB_WORD0_SIZE_1MB:
+ tlb_size = 1 << 20;
+ break;
+ case TLB_WORD0_SIZE_16MB:
+ tlb_size = 16 << 20;
+ break;
+ case TLB_WORD0_SIZE_256MB:
+ tlb_size = 256 << 20;
+ break;
+ }
+
+ /*
+ * Now check the end-address if it's in the range
+ */
+ if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
+ /*
+ * Found a TLB in the range.
+ * Disable it by writing 0 to tlb0 word.
+ */
+ mttlb1(i, 0);
+ }
+ }
+
+ /* Execute an ISYNC instruction so that the new TLB entry takes effect */
+ asm("isync");
+}
+
static int add_tlb_entry(unsigned long phys_addr,
unsigned long virt_addr,
unsigned long tlb_word0_size_value,
unsigned long fixup, val;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
u32 value2;
+ int corr_ecc = 0;
+ int uncorr_ecc = 0;
#endif
- /* Probing PCI using config cycles cause this exception
- * when a device is not present. Catch it and return to
- * the PCI exception handler.
- */
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
+ val = mfspr(MCSR);
+ /* Clear MCSR */
+ mtspr(SPRN_MCSR, val);
return;
}
printf("DDR0: At least one interrupt active\n");
if (val & 0x40)
printf("DDR0: DRAM initialization complete.\n");
- if (val & 0x20)
+ if (val & 0x20) {
printf("DDR0: Multiple uncorrectable ECC events.\n");
- if (val & 0x10)
+ uncorr_ecc = 1;
+ }
+ if (val & 0x10) {
printf("DDR0: Single uncorrectable ECC event.\n");
- if (val & 0x08)
+ uncorr_ecc = 1;
+ }
+ if (val & 0x08) {
printf("DDR0: Multiple correctable ECC events.\n");
- if (val & 0x04)
+ corr_ecc = 1;
+ }
+ if (val & 0x04) {
printf("DDR0: Single correctable ECC event.\n");
+ corr_ecc = 1;
+ }
if (val & 0x02)
printf("Multiple accesses outside the defined"
" physical memory space detected\n");
printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
}
mfsdram(DDR0_23, val);
- if ( (val >> 16) & 0xff)
+ if (((val >> 16) & 0xff) && corr_ecc)
printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
(val >> 16) & 0xff);
mfsdram(DDR0_23, val);
- if ( (val >> 8) & 0xff)
+ if (((val >> 8) & 0xff) && uncorr_ecc)
printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
(val >> 8) & 0xff);
mfsdram(DDR0_33, val);
printf("DDR0: Address of command that caused an "
"Out-of-Range interrupt %p\n", val);
mfsdram(DDR0_34, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_35, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_36, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_37, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_38, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_39, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_40, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
mfsdram(DDR0_41, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
#endif /* CONFIG_440EPX */
#endif /* CONFIG_440 */
#include "usbdev.h"
-int usb_cpu_init()
+int usb_cpu_init(void)
{
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
return 0;
}
-int usb_cpu_stop()
+int usb_cpu_stop(void)
{
return 0;
}
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
{
return 0;
}
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+#define FFUART 0
+#define BTUART 1
+#define STUART 2
+
+#ifndef CONFIG_SERIAL_MULTI
+#if defined (CONFIG_FFUART)
+#define UART_INDEX FFUART
+#elif defined (CONFIG_BTUART)
+#define UART_INDEX BTUART
+#elif defined (CONFIG_STUART)
+#define UART_INDEX STUART
+#else
+#error "Bad: you didn't configure serial ..."
+#endif
+#endif
+
+void pxa_setbrg_dev (unsigned int uart_index)
{
unsigned int quot = 0;
else
hang ();
-#ifdef CONFIG_FFUART
+ switch (uart_index) {
+ case FFUART:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_22_FFUART;
+ CKENA |= CKENA_22_FFUART;
#else
- CKEN |= CKEN6_FFUART;
+ CKEN |= CKEN6_FFUART;
#endif /* CONFIG_CPU_MONAHANS */
- FFIER = 0; /* Disable for now */
- FFFCR = 0; /* No fifos enabled */
+ FFIER = 0; /* Disable for now */
+ FFFCR = 0; /* No fifos enabled */
- /* set baud rate */
- FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
- FFDLL = quot & 0xff;
- FFDLH = quot >> 8;
- FFLCR = LCR_WLS0 | LCR_WLS1;
+ /* set baud rate */
+ FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
+ FFDLL = quot & 0xff;
+ FFDLH = quot >> 8;
+ FFLCR = LCR_WLS0 | LCR_WLS1;
- FFIER = IER_UUE; /* Enable FFUART */
+ FFIER = IER_UUE; /* Enable FFUART */
+ break;
-#elif defined(CONFIG_BTUART)
+ case BTUART:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_21_BTUART;
+ CKENA |= CKENA_21_BTUART;
#else
- CKEN |= CKEN7_BTUART;
+ CKEN |= CKEN7_BTUART;
#endif /* CONFIG_CPU_MONAHANS */
- BTIER = 0;
- BTFCR = 0;
+ BTIER = 0;
+ BTFCR = 0;
- /* set baud rate */
- BTLCR = LCR_DLAB;
- BTDLL = quot & 0xff;
- BTDLH = quot >> 8;
- BTLCR = LCR_WLS0 | LCR_WLS1;
+ /* set baud rate */
+ BTLCR = LCR_DLAB;
+ BTDLL = quot & 0xff;
+ BTDLH = quot >> 8;
+ BTLCR = LCR_WLS0 | LCR_WLS1;
- BTIER = IER_UUE; /* Enable BFUART */
+ BTIER = IER_UUE; /* Enable BFUART */
-#elif defined(CONFIG_STUART)
+ break;
+
+ case STUART:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_23_STUART;
+ CKENA |= CKENA_23_STUART;
#else
- CKEN |= CKEN5_STUART;
+ CKEN |= CKEN5_STUART;
#endif /* CONFIG_CPU_MONAHANS */
- STIER = 0;
- STFCR = 0;
+ STIER = 0;
+ STFCR = 0;
- /* set baud rate */
- STLCR = LCR_DLAB;
- STDLL = quot & 0xff;
- STDLH = quot >> 8;
- STLCR = LCR_WLS0 | LCR_WLS1;
+ /* set baud rate */
+ STLCR = LCR_DLAB;
+ STDLL = quot & 0xff;
+ STDLH = quot >> 8;
+ STLCR = LCR_WLS0 | LCR_WLS1;
- STIER = IER_UUE; /* Enable STUART */
+ STIER = IER_UUE; /* Enable STUART */
+ break;
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
+ default:
+ hang();
+ }
}
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+int pxa_init_dev (unsigned int uart_index)
{
- serial_setbrg ();
+ pxa_setbrg_dev (uart_index);
return (0);
}
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
-{
-#ifdef CONFIG_FFUART
- /* wait for room in the tx FIFO on FFUART */
- while ((FFLSR & LSR_TEMT) == 0)
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- FFTHR = c;
-#elif defined(CONFIG_BTUART)
- while ((BTLSR & LSR_TEMT ) == 0 )
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- BTTHR = c;
-#elif defined(CONFIG_STUART)
- while ((STLSR & LSR_TEMT ) == 0 )
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- STTHR = c;
-#endif
+void pxa_putc_dev (unsigned int uart_index,const char c)
+{
+ switch (uart_index) {
+ case FFUART:
+ /* wait for room in the tx FIFO on FFUART */
+ while ((FFLSR & LSR_TEMT) == 0)
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ FFTHR = c;
+ break;
+
+ case BTUART:
+ while ((BTLSR & LSR_TEMT ) == 0 )
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ BTTHR = c;
+ break;
+
+ case STUART:
+ while ((STLSR & LSR_TEMT ) == 0 )
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ STTHR = c;
+ break;
+ }
/* If \n, also do \r */
if (c == '\n')
- serial_putc ('\r');
+ pxa_putc_dev (uart_index,'\r');
}
/*
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
-{
-#ifdef CONFIG_FFUART
- return FFLSR & LSR_DR;
-#elif defined(CONFIG_BTUART)
- return BTLSR & LSR_DR;
-#elif defined(CONFIG_STUART)
- return STLSR & LSR_DR;
-#endif
+int pxa_tstc_dev (unsigned int uart_index)
+{
+ switch (uart_index) {
+ case FFUART:
+ return FFLSR & LSR_DR;
+ case BTUART:
+ return BTLSR & LSR_DR;
+ case STUART:
+ return STLSR & LSR_DR;
+ }
+ return -1;
}
/*
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
-{
-#ifdef CONFIG_FFUART
- while (!(FFLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) FFRBR & 0xff;
-#elif defined(CONFIG_BTUART)
- while (!(BTLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) BTRBR & 0xff;
-#elif defined(CONFIG_STUART)
- while (!(STLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) STRBR & 0xff;
-#endif
+int pxa_getc_dev (unsigned int uart_index)
+{
+ switch (uart_index) {
+ case FFUART:
+ while (!(FFLSR & LSR_DR))
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ return (char) FFRBR & 0xff;
+
+ case BTUART:
+ while (!(BTLSR & LSR_DR))
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ return (char) BTRBR & 0xff;
+ case STUART:
+ while (!(STLSR & LSR_DR))
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+ return (char) STRBR & 0xff;
+ }
+ return -1;
}
void
-serial_puts (const char *s)
+pxa_puts_dev (unsigned int uart_index,const char *s)
{
while (*s) {
- serial_putc (*s++);
+ pxa_putc_dev (uart_index,*s++);
}
}
+
+#if defined (CONFIG_FFUART)
+static int ffuart_init(void)
+{
+ return pxa_init_dev(FFUART);
+}
+
+static void ffuart_setbrg(void)
+{
+ return pxa_setbrg_dev(FFUART);
+}
+
+static void ffuart_putc(const char c)
+{
+ return pxa_putc_dev(FFUART,c);
+}
+
+static void ffuart_puts(const char *s)
+{
+ return pxa_puts_dev(FFUART,s);
+}
+
+static int ffuart_getc(void)
+{
+ return pxa_getc_dev(FFUART);
+}
+
+static int ffuart_tstc(void)
+{
+ return pxa_tstc_dev(FFUART);
+}
+
+struct serial_device serial_ffuart_device =
+{
+ "serial_ffuart",
+ "PXA",
+ ffuart_init,
+ ffuart_setbrg,
+ ffuart_getc,
+ ffuart_tstc,
+ ffuart_putc,
+ ffuart_puts,
+};
+#endif
+
+#if defined (CONFIG_BTUART)
+static int btuart_init(void)
+{
+ return pxa_init_dev(BTUART);
+}
+
+static void btuart_setbrg(void)
+{
+ return pxa_setbrg_dev(BTUART);
+}
+
+static void btuart_putc(const char c)
+{
+ return pxa_putc_dev(BTUART,c);
+}
+
+static void btuart_puts(const char *s)
+{
+ return pxa_puts_dev(BTUART,s);
+}
+
+static int btuart_getc(void)
+{
+ return pxa_getc_dev(BTUART);
+}
+
+static int btuart_tstc(void)
+{
+ return pxa_tstc_dev(BTUART);
+}
+
+struct serial_device serial_btuart_device =
+{
+ "serial_btuart",
+ "PXA",
+ btuart_init,
+ btuart_setbrg,
+ btuart_getc,
+ btuart_tstc,
+ btuart_putc,
+ btuart_puts,
+};
+#endif
+
+#if defined (CONFIG_STUART)
+static int stuart_init(void)
+{
+ return pxa_init_dev(STUART);
+}
+
+static void stuart_setbrg(void)
+{
+ return pxa_setbrg_dev(STUART);
+}
+
+static void stuart_putc(const char c)
+{
+ return pxa_putc_dev(STUART,c);
+}
+
+static void stuart_puts(const char *s)
+{
+ return pxa_puts_dev(STUART,s);
+}
+
+static int stuart_getc(void)
+{
+ return pxa_getc_dev(STUART);
+}
+
+static int stuart_tstc(void)
+{
+ return pxa_tstc_dev(STUART);
+}
+
+struct serial_device serial_stuart_device =
+{
+ "serial_stuart",
+ "PXA",
+ stuart_init,
+ stuart_setbrg,
+ stuart_getc,
+ stuart_tstc,
+ stuart_putc,
+ stuart_puts,
+};
+#endif
+
+
+#ifndef CONFIG_SERIAL_MULTI
+inline int serial_init(void) {
+ return (pxa_init_dev(UART_INDEX));
+}
+void serial_setbrg(void) {
+ pxa_setbrg_dev(UART_INDEX);
+}
+int serial_getc(void) {
+ return(pxa_getc_dev(UART_INDEX));
+}
+int serial_tstc(void) {
+ return(pxa_tstc_dev(UART_INDEX));
+}
+void serial_putc(const char c) {
+ pxa_putc_dev(UART_INDEX,c);
+}
+void serial_puts(const char *s) {
+ pxa_puts_dev(UART_INDEX,s);
+}
+#endif /* CONFIG_SERIAL_MULTI */
+The 2 important dipswitches are configured as shown below:
+
+SW1 (for 33MHz SysClk)
+----------------------
+S1 S2 S3 S4 S5 S6 S7 S8
+OFF OFF OFF OFF OFF OFF OFF ON
+
+SW7 (for Op-Code Flash and Boot Option H)
+-----------------------------------------
+S1 S2 S3 S4 S5 S6 S7 S8
+OFF OFF OFF ON OFF OFF OFF OFF
+
+The EEPROM at location 0x52 is loaded with these 16 bytes:
+C47042A6 05D7A190 40082350 0d050000
+
+SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
+SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
+SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
+SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
+SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
+SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
+SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
+SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
+SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
+SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
+SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
+SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
+SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
+SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
+SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
+SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
+SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
+SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
+SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
+SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
+SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
+SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
+SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
+SDR0_SDSTP0[NE]: 0 : NDFC: disabled
+SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
+SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
+SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
+SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
+SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
+SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
+SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
+SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
+SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
+SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
+SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
+
+PPC440EP Clocking Configuration
+
+SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
+OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
+
+The above information is reported by Eugene O'Brien
+<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
+
+2007-08-06, Stefan Roese <sr@denx.de>
+---------------------------------------------------------------------
+
The configuration for the AMCC 440EP eval board "Bamboo" was changed
to only use 384 kbytes of FLASH for the U-Boot image. This way the
redundant environment can be saved in the remaining 2 sectors of the
CFG_OHCI_BE_CONTROLLER
-needs to be defined.
+needs to be defined.
PCI Controllers
should to define:
CFG_OHCI_SWAP_REG_ACCESS
-
-
-
--- /dev/null
+Freescale Amadeus Plus M5253EVBE board
+======================================
+
+Hayden Fraser(Hayden.Fraser@freescale.com)
+Created 06/05/2007
+===========================================
+
+
+1. SWITCH SETTINGS
+==================
+1.1 N/A
+
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ SDR: 0x00000000-0x00ffffff
+ SRAM0: 0x20010000-0x20017fff
+ SRAM1: 0x20000000-0x2000ffff
+ MBAR1: 0x10000000-0x4fffffff
+ MBAR2: 0x80000000-0xCfffffff
+ Flash: 0xffe00000-0xffffffff
+
+3. DEFINITIONS AND COMPILATION
+==============================
+3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
+ CONFIG_MCF52x2 Processor family
+ CONFIG_MCF5253 MCF5253 specific
+ CONFIG_M5253EVBE Amadeus Plus board specific
+ CFG_CLK Define Amadeus Plus CPU Clock
+ CFG_MBAR MBAR base address
+ CFG_MBAR2 MBAR2 base address
+
+3.2 Compilation
+ export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
+ cd u-boot-1-2-x
+ make distclean
+ make M5253EVBE_config
+ make
+
+
+4. SCREEN DUMP
+==============
+4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
+
+CPU: Freescale Coldfire MCF5253 at 62 MHz
+Board: Freescale MCF5253 EVBE
+DRAM: 16 MB
+FLASH: 2 MB
+In: serial
+Out: serial
+Err: serial
+=> flinfo
+
+Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors
+ AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
+ Erase timeout: 16384 ms, write timeout: 1 ms
+
+ Sector Start Addresses:
+ FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO
+ FFE20000 FFE30000 FFE40000 FFE50000 FFE60000
+ FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000
+ FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000
+ FFF10000 FFF20000 FFF30000 FFF40000 FFF50000
+ FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000
+ FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000
+
+=> bdinfo
+boot_params = 0x00F62F90
+memstart = 0x00000000
+memsize = 0x01000000
+flashstart = 0xFFE00000
+flashsize = 0x00200000
+flashoffset = 0x00000000
+baudrate = 19200 bps
+
+=> printenv
+bootdelay=5
+baudrate=19200
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 134/8188 bytes
+=> saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+. done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+5. COMPILER
+-----------
+To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
+compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
+You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
+codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
--- /dev/null
+Freescale MCF54455EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 4/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
+- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
+- board/freescale/m54455evb/Makefile Makefile
+- board/freescale/m54455evb/config.mk config make
+- board/freescale/m54455evb/u-boot.lds Linker description
+
+- common/cmd_bdinfo.c Clock frequencies output
+- common/cmd_mii.c mii support
+
+- cpu/mcf5445x/cpu.c cpu specific code
+- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- cpu/mcf5445x/interrupts.c cpu specific interrupt support
+- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
+- cpu/mcf5445x/Makefile Makefile
+- cpu/mcf5445x/config.mk config make
+- cpu/mcf5445x/start.S start up assembly code
+
+- doc/README.m54455evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5445x.h mcf5445x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m5445x.h mcf5445x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M54455EVB.h Board specific configuration file
+
+- lib_m68k/board.c board init function
+- lib_m68k/cache.c
+- lib_m68k/interrupts Coldfire common interrupt functions
+- lib_m68k/m68k_linux.c
+- lib_m68k/time.c Timer functions (Dma timer and PIT)
+- lib_m68k/traps.c Exception init code
+
+- rtc/mcfrtc.c Realtime clock Driver
+
+1 MCF5445x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54455EVB Development Board
+CONFIG_MCF5445x -- define for all MCF5445x CPUs
+CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
+CONFIG_M54455EVB -- define for M54455EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CFG_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CFG_MCFRTC_BASE -- provide base address for RTC in immap.h
+CFG_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_NET_MULTI -- define to use multi FEC in u-boot
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CFG_DISCOVER_PHY -- enable PHY discovery
+CFG_RX_ETH_BUFFER -- Set FEC Receive buffer
+CFG_FAULT_ECHO_LINK_DOWN--
+CFG_FEC0_PINMUX -- Set FEC0 Pin configuration
+CFG_FEC1_PINMUX -- Set FEC1 Pin configuration
+CFG_FEC0_MIIBASE -- Set FEC0 MII base register
+CFG_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_ISO_PARTITION -- enable ISO read/write
+CONFIG_DOS_PARTITION -- enable DOS read/write
+CONFIG_IDE_RESET -- define ide_reset()
+CONFIG_IDE_PREINIT -- define ide_preinit()
+CONFIG_ATAPI -- define ATAPI support
+CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
+CFG_IDE_MAXBUS -- define max channel
+CFG_IDE_MAXDEVICE -- define max devices per channel
+CFG_ATA_BASE_ADDR -- define ATA base address
+CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset
+CFG_ATA_DATA_OFFSET -- define ATA data IO
+CFG_ATA_REG_OFFSET -- define for normal register accesses
+CFG_ATA_ALT_OFFSET -- define for alternate registers
+CFG_ATA_STRIDE -- define for Interval between registers
+_IO_BASE -- define for IO base address
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CFG_I2C_SPEED -- define for I2C speed
+CFG_I2C_SLAVE -- define for I2C slave address
+CFG_I2C_OFFSET -- define for I2C base address offset
+CFG_IMMR -- define for MBAR offset
+
+CONFIG_PCI -- define for PCI support
+CONFIG_PCI_PNP -- define for Plug n play support
+CFG_PCI_MEM_BUS -- PCI memory logical offset
+CFG_PCI_MEM_PHYS -- PCI memory physical offset
+CFG_PCI_MEM_SIZE -- PCI memory size
+CFG_PCI_IO_BUS -- PCI IO logical offset
+CFG_PCI_IO_PHYS -- PCI IO physical offset
+CFG_PCI_IO_SIZE -- PCI IO size
+CFG_PCI_CFG_BUS -- PCI Configuration logical offset
+CFG_PCI_CFG_PHYS -- PCI Configuration physical offset
+CFG_PCI_CFG_SIZE -- PCI Configuration size
+
+CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
+
+CFG_MBAR -- define MBAR offset
+
+CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
+
+CFG_CSn_BASE -- defines the Chip Select Base register
+CFG_CSn_MASK -- defines the Chip Select Mask register
+CFG_CSn_CTRL -- defines the Chip Select Control register
+
+CFG_ATMEL_BASE -- defines the Atmel Flash base
+CFG_INTEL_BASE -- defines the Intel Flash base
+
+CFG_SDRAM_BASE -- defines the DRAM Base
+CFG_SDRAM_BASE1 -- defines the DRAM Base 1
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ ATA: 0x90000000-0x9FFFFFFF (256MB)
+ PCI: 0xA0000000-0xBFFFFFFF (512MB)
+ FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Atmel boot:
+ Flash0: 0x00000000-0x0007FFFF (512KB)
+ Flash1: 0x04000000-0x05FFFFFF (32MB)
+ Intel boot:
+ Flash0: 0x00000000-0x01FFFFFF (32MB)
+ Flash1: 0x04000000-0x0407FFFF (512KB)
+
+ CPLD: 0x08000000-0x08FFFFFF (16MB)
+ FPGA: 0x09000000-0x09FFFFFF (16MB)
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. SWITCH SETTINGS
+==================
+3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+ SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
+ SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
+ 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
+ SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
+ SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+
+4. COMPILATION
+==============
+4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+4.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M54455EVB_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
+ make M54455EVB_intel_config, or - default to intel 33Mhz input clock
+ make M54455EVB_i33_config, or - default to intel 33Mhz input clock
+ make M54455EVB_i66_config, or - default to intel 66Mhz input clock
+ make
+
+5. SCREEN DUMP
+==============
+5.1 M54455EVB Development board
+ Boot from Atmel (NOTE: May not show exactly the same)
+
+U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
+
+CPU: Freescale MCF54455 (Mask:48 Version:1)
+ CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
+ PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
+Board: Freescale M54455 EVB
+I2C: ready
+DRAM: 256 MB
+FLASH: 16.5 MB
+In: serial
+Out: serial
+Err: serial
+Net: FEC0, FEC1
+IDE: Bus 0: not available
+-> print
+bootargs=root=/dev/ram rw
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+hostname=M54455EVB
+netdev=eth0
+inpclk=33333333
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+mtdids=nor0=M54455EVB-1
+mtdparts=M54455EVB-1:16m(user)
+u-boot=u-boot54455.bin
+filesize=292b4
+fileaddr=40010000
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 563/8188 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x10000000
+flashstart = 0x00000000
+flashsize = 0x01080000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 133.333 MHz
+pcifreq = 33.333 MHz
+flbfreq = 66.666 MHz
+inpfreq = 33.333 MHz
+vcofreq = 533.333 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+eth1addr = 00:E0:0C:BC:E5:61
+ip_addr = 192.168.1.3
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+autoscr - run script from memory
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+diskboot- boot from IDE device
+echo - echo args to console
+erase - erase FLASH memory
+ext2load- load binary file from a Ext2 filesystem
+ext2ls - list files in a directory (default /)
+fatinfo - print information about filesystem
+fatload - load binary file from a dos filesystem
+fatls - list files in a directory (default /)
+flinfo - print FLASH memory information
+fsinfo - print information about filesystems
+fsload - load binary file from a filesystem image
+go - start application at address 'addr'
+help - print online help
+icache - enable or disable instruction cache
+icrc32 - checksum calculation
+ide - IDE sub-system
+iloop - infinite loop on address range
+imd - i2c memory display
+iminfo - print header information for application image
+imls - list all images found in flash
+imm - i2c memory modify (auto-incrementing)
+imw - memory write (fill)
+inm - memory modify (constant address)
+iprobe - probe to discover valid I2C chip addresses
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+pci - list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+->bootm 4000000
+
+## Booting image at 04000000 ...
+ Image Name: Linux Kernel Image
+ Created: 2007-08-14 15:13:00 UTC
+ Image Type: M68K Linux Kernel Image (uncompressed)
+ Data Size: 2301952 Bytes = 2.2 MB
+ Load Address: 40020000
+ Entry Point: 40020000
+ Verifying Checksum ... OK
+OK
+Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
+erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
+starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
+Built 1 zonelists. Total pages: 32624
+Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
+ysmap-flash.0:5M(kernel)ro,-(jffs2)
+PID hash table entries: 1024 (order: 10, 4096 bytes)
+Console: colour dummy device 80x25
+Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
+Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
+Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
+Mount-cache hash table entries: 1024
+NET: Registered protocol family 16
+SCSI subsystem initialized
+NET: Registered protocol family 2
+IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
+TCP established hash table entries: 8192 (order: 2, 32768 bytes)
+TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
+TCP: Hash tables configured (established 8192 bind 4096)
+TCP reno registered
+JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler anticipatory registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00
+ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
+RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
+loop: loaded (max 8 devices)
+FEC ENET Version 0.2
+fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
+eth0: ethernet 00:08:ee:00:e4:19
+physmap platform flash device: 01000000 at 04000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+2 cmdlinepart partitions found on MTD device physmap-flash.0
+Creating 2 MTD partitions on "physmap-flash.0":
+0x00000000-0x00500000 : "kernel"
+mtd: Giving out device 0 to kernel
+0x00500000-0x01000000 : "jffs2"
+mtd: Giving out device 1 to jffs2
+mice: PS/2 mouse device common for all mice
+i2c /dev entries driver
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+NET: Registered protocol family 15
+VFS: Mounted root (jffs2 filesystem).
+Setting the hostname to freescale
+Mounting filesystems
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
+Starting syslogd and klogd
+Setting up networking on loopback device:
+Setting up networking on eth0:
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+Adding static route for default gateway to 172.27.255.254:
+Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
+Starting inetd:
+/ #
--- /dev/null
+Overview
+--------
+The MPC8544DS system is similar to the 85xx CDS systems such
+as the MPC8548CDS due to the similar E500 core. However, it
+is placed on the same board as the 8641 HPCN system.
+
+
+Flash Banks
+-----------
+Like the 85xx CDS systems, the 8544 DS board has two flash banks.
+They are both present on boot, but there locations can be swapped
+using the dip-switch SW10, bit 2.
+
+However, unlike the CDS systems, but similar to the 8641 HPCN
+board, a runtime reset through the FPGA can also affect a swap
+on the flash bank mappings for the next reset cycle.
+
+Irrespective of the switch SW10[2], booting is always from the
+boot bank at 0xfff8_0000.
+
+
+Memory Map
+----------
+
+0xff80_0000 - 0xffbf_ffff Alernate bank 4MB
+0xffc0_0000 - 0xffff_ffff Boot bank 4MB
+
+0xffb8_0000 Alternate image start 512KB
+0xfff8_0000 Boot image start 512KB
+
+
+Flashing Images
+---------------
+
+For example, to place a new image in the alternate flash bank
+and then reset with that new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin.8544ds
+ erase ffb80000 ffbfffff
+ cp.b 1000000 ffb80000 80000
+ pixis_reset altbank
+
+
+To overwrite the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin.8544ds
+ protect off all
+ erase fff80000 ffffffff
+ cp.b 1000000 fff80000 80000
+
+Other example U-Boot image and flash manipulations examples
+can be found in the README.mpc85xxcds file as well.
+
+
+The pixis_reset command
+-----------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
+
+After placing the DTB file in your TFTP disk area,
+you can download that dtb file using a command like:
+
+ tftp 900000 mpc8544ds.dtb
+
+Burn it to flash if you want.
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area too.
+
+ tftp 1000000 uImage.8544
+ tftp 900000 mpc8544ds.dtb
+ bootm 1000000 - 900000
+
+Watch your ethact, netdev and bootargs U-Boot environment variables.
+You may want to do something like this too:
+
+ setenv ethact eTSEC3
+ setenv netdev eth1
--- /dev/null
+Wind River SBC8641D reference board
+===========================
+
+Created 06/14/2007 Joe Hamman
+Copyright 2007, Embedded Specialties, Inc.
+Copyright 2007 Wind River Systemes, Inc.
+-----------------------------
+
+1. Building U-Boot
+------------------
+The SBC8641D code is known to build using ELDK 4.1.
+
+ $ make sbc8641d_config
+ Configuring for sbc8641d board...
+
+ $ make
+
+
+2. Switch and Jumper Settings
+-----------------------------
+All Jumpers & Switches are in their default positions. Please refer to
+the board documentation for details. Some settings control CPU voltages
+and settings may change with board revisions.
+
+3. Known limitations
+--------------------
+PCI:
+ The PCI command may hang if no boards are present in either slot.
--- /dev/null
+
+Storage of the board specific values (ethaddr...)
+-------------------------------------------------
+
+The board specific environment variables that should be unique
+for each individual board, can be stored in the I2C EEPROM. This
+will be done from offset 0x80 with the length of 0x80 bytes. The
+following command can be used to store the values here:
+
+=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
+
+ ethaddr eth1addr serial#
+
+Now those 3 values are stored into the I2C EEPROM. A CRC is added
+to make sure that the values get not corrupted.
+
+
+SW-Reset Pushbutton handling:
+-----------------------------
+
+The SW-reset push button is connected to a GPIO input too. This
+way U-Boot can "see" how long the SW-reset was pressed, and a
+specific action can be taken. Two different actions are supported:
+
+a) Release after more than 5 seconds and less then 10 seconds:
+ -> Run POST
+
+ Please note, that the POST test will take a while (approx. 1 min
+ on the 128MByte board). This is mainly due to the system memory
+ test.
+
+b) Release after more than 10 seconds:
+ -> Restore factory default settings
+
+ The factory default values are restored. The default environment
+ variables are restored (ipaddr, serverip...) and the board
+ specific values (ethaddr, eth1addr and serial#) are restored
+ to the environment from the I2C EEPROM. Also a bootline parameter
+ is added to the Linux bootline to signal the Linux kernel upon
+ the next startup, that the factory defaults should be restored.
+
+The command to check this sw-reset status and act accordingly is
+
+=> chkreset
+
+This command is added to the default "bootcmd", so that it is called
+automatically upon startup.
+
+Also, the 2 LED's are used to indicate the current status of this
+command (time passed since pushing the button). When the POST test
+will be run, the green LED will be switched off, and when the
+factory restore will be initiated, the reg LED will be switched off.
+
+
+Loggin of POST results:
+-----------------------
+
+The results of the POST tests are logged in a logbuffer located at the end
+of the onboard memory. It can be accessed with the U-Boot command "log":
+
+=> log show
+<4>POST memory PASSED
+<4>POST cache PASSED
+<4>POST cpu PASSED
+<4>POST uart PASSED
+<4>POST ethernet PASSED
+
+The DENX Linux kernel tree has support for this log buffer included. Exactly
+this buffer is used for logging of all kernel messages too. By enabling the
+compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
+can access the U-Boot log messages from Linux too.
+
+2007-08-10, Stefan Roese <sr@denx.de>
LIB = $(obj)libdrivers.a
-COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
+COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o enc28j60.o \
sed13806.o sed156x.o \
serial.o serial_max3100.o \
serial_pl010.o serial_pl011.o serial_xuartlite.o \
- sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
+ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o systemace.o ahci.o \
ti_pci1410a.o tigon3.o tsec.o \
tsi108_eth.o tsi108_i2c.o tsi108_pci.o \
memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
- probe_ent = malloc(sizeof(probe_ent));
- memset(probe_ent, 0, sizeof(probe_ent));
+ probe_ent = malloc(sizeof(struct ahci_probe_ent));
+ memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
--- /dev/null
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+/*
+ * spi.c API
+ */
+extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc);
+extern void AT91F_SpiEnable(int cs);
+
+#define AT91C_TIMEOUT_WRDY 200000
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashSendCommand */
+/* \brief Generic function to send a command to the dataflash */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress)
+{
+ unsigned int adr;
+
+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* process the address to obtain page address and byte address */
+ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) <<
+ pDataFlash->pDevice->page_offset) + (DataflashAddress %
+ (pDataFlash->pDevice->pages_size));
+
+ /* fill the command buffer */
+ pDataFlash->pDataFlashDesc->command[0] = OpCode;
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ pDataFlash->pDataFlashDesc->command[1] =
+ (unsigned char)((adr & 0x0F000000) >> 24);
+ pDataFlash->pDataFlashDesc->command[2] =
+ (unsigned char)((adr & 0x00FF0000) >> 16);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)((adr & 0x0000FF00) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] =
+ (unsigned char)(adr & 0x000000FF);
+ } else {
+ pDataFlash->pDataFlashDesc->command[1] =
+ (unsigned char)((adr & 0x00FF0000) >> 16);
+ pDataFlash->pDataFlashDesc->command[2] =
+ (unsigned char)((adr & 0x0000FF00) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)(adr & 0x000000FF);
+ pDataFlash->pDataFlashDesc->command[4] = 0;
+ }
+ pDataFlash->pDataFlashDesc->command[5] = 0;
+ pDataFlash->pDataFlashDesc->command[6] = 0;
+ pDataFlash->pDataFlashDesc->command[7] = 0;
+
+ /* Initialize the SpiData structure for the spi write fuction */
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
+
+ /* send the command and read the data */
+ return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); }
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashGetStatus */
+/* \brief Read the status register of the dataflash */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+ AT91S_DataFlashStatus status;
+
+ /* if a transfert is in progress ==> return 0 */
+ if( (pDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* first send the read status command (D7H) */
+ pDesc->command[0] = DB_STATUS;
+ pDesc->command[1] = 0;
+
+ pDesc->DataFlash_state = GET_STATUS;
+ pDesc->tx_data_size = 0; /* Transmit the command */
+ /* and receive response */
+ pDesc->tx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_size = 2;
+ pDesc->tx_cmd_size = 2;
+ status = AT91F_SpiWrite (pDesc);
+
+ pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+ return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashWaitReady */
+/* \brief wait for dataflash ready (bit7 of the status register == 1) */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
+pDataFlashDesc, unsigned int timeout)
+{
+ pDataFlashDesc->DataFlash_state = IDLE;
+
+ do {
+ AT91F_DataFlashGetStatus(pDataFlashDesc);
+ timeout--;
+ } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
+ (timeout > 0) );
+
+ if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+ return DATAFLASH_ERROR;
+
+ return DATAFLASH_OK;
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashContinuousRead */
+/* Object : Continuous stream Read */
+/* Input Parameters : DataFlash Service */
+/* : <src> = dataflash address */
+/* : <*dataBuffer> = data buffer pointer */
+/* : <sizeToRead> = data buffer size */
+/* Return value : State of the dataflash */
+/*--------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead )
+{
+ AT91S_DataFlashStatus status;
+ /* Test the size to read in the device */
+ if ( (src + sizeToRead) >
+ (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
+ return DATAFLASH_MEMORY_OVERFLOW;
+
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+ status = AT91F_DataFlashSendCommand
+ (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+ /* Send the command to the dataflash */
+ return(status);
+}
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashPagePgmBuf */
+/* Object : Main memory page program thru buffer 1 or buffer 2 */
+/* Input Parameters : DataFlash Service */
+/* : <*src> = Source buffer */
+/* : <dest> = dataflash destination address */
+/* : <SizeToWrite> = data buffer size */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite)
+{
+ int cmdsize;
+ pDataFlash->pDataFlashDesc->tx_data_pt = src;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->rx_data_pt = src;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+ cmdsize = 4;
+ /* Send the command to the dataflash */
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1,
+cmdsize, dest)); }
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_MainMemoryToBufferTransfert */
+/* Object : Read a page in the SRAM Buffer 1 or 2 */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int page)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF)
+ && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+ return DATAFLASH_BAD_COMMAND;
+
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
+page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*-------------------------------------------------------------------------- */
+/* Function Name : AT91F_DataFlashWriteBuffer */
+/* Object : Write data to the internal sram buffer 1 or 2 */
+/* Input Parameters : DataFlash Service */
+/* : <BufferCommand> = command to write buffer1 or 2 */
+/* : <*dataBuffer> = data buffer to write */
+/* : <bufferAddress> = address in the internal buffer */
+/* : <SizeToWrite> = data buffer size */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite )
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ if ((BufferCommand != DB_BUF1_WRITE)
+ && (BufferCommand != DB_BUF2_WRITE))
+ return DATAFLASH_BAD_COMMAND;
+
+ /* buffer address must be lower than page size */
+ if (bufferAddress > pDataFlash->pDevice->pages_size)
+ return DATAFLASH_BAD_ADDRESS;
+
+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* Send first Write Command */
+ pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+ pDataFlash->pDataFlashDesc->command[1] = 0;
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ pDataFlash->pDataFlashDesc->command[2] = 0;
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)(((unsigned int)(bufferAddress &
+ pDataFlash->pDevice->byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ cmdsize = 5;
+ } else {
+ pDataFlash->pDataFlashDesc->command[2] =
+ (unsigned char)(((unsigned int)(bufferAddress &
+ pDataFlash->pDevice->byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ pDataFlash->pDataFlashDesc->command[4] = 0;
+ cmdsize = 4;
+ }
+
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize;
+
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
+
+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_PageErase */
+/* Object : Erase a page */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize,
+page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_BlockErase */
+/* Object : Erase a Block */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize,
+block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_WriteBufferToMain */
+/* Object : Write buffer to the main memory */
+/* Input Parameters : DataFlash Service */
+/* : <BufferCommand> = command to send to buffer1 or buffer2 */
+/* : <dest> = main memory address */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest )
+{
+ int cmdsize;
+ /* Test if the buffer command is correct */
+ if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+ return DATAFLASH_BAD_COMMAND;
+
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ /* Send the command to the dataflash */
+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
+ dest)); }
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_PartialPageWrite */
+/* Object : Erase partielly a page */
+/* Input Parameters : <page> = page number */
+/* : <AdrInpage> = adr to begin the fading */
+/* : <length> = Number of bytes to erase */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size)
+{
+ unsigned int page;
+ unsigned int AdrInPage;
+
+ page = dest / (pDataFlash->pDevice->pages_size);
+ AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+ /* Read the contents of the page in the Sram Buffer */
+ AT91F_MainMemoryToBufferTransfert(pDataFlash,
+ DB_PAGE_2_BUF1_TRF, page);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ /*Update the SRAM buffer */
+ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
+ AdrInPage, size);
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ /* Erase page if a 128 Mbits device */
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ AT91F_PageErase(pDataFlash, page);
+ /* Rewrite the modified Sram Buffer in the main memory */
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ }
+
+ /* Rewrite the modified Sram Buffer in the main memory */
+ return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
+ (page*pDataFlash->pDevice->pages_size)));
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashWrite */
+/* Object : */
+/* Input Parameters : <*src> = Source buffer */
+/* : <dest> = dataflash adress */
+/* : <size> = data buffer size */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest,
+ int size )
+{
+ unsigned int length;
+ unsigned int page;
+ unsigned int status;
+
+ AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+ if ( (dest + size) > (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
+ return DATAFLASH_MEMORY_OVERFLOW;
+
+ /* If destination does not fit a page start address */
+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 )
+ {
+ length = pDataFlash->pDevice->pages_size -
+ (dest %
+ ((unsigned int)
+ (pDataFlash->pDevice->pages_size)));
+
+ if (size < length)
+ length = size;
+
+ if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ /* Update size, source and destination pointers */
+ size -= length;
+ dest += length;
+ src += length;
+ }
+
+ while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+ /* program dataflash page */
+ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+ status = AT91F_DataFlashWriteBuffer(pDataFlash,
+ DB_BUF1_WRITE, src, 0,
+ pDataFlash->pDevice->pages_size);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ status = AT91F_PageErase(pDataFlash, page);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ if (!status)
+ return DATAFLASH_ERROR;
+
+ status = AT91F_WriteBufferToMain (pDataFlash,
+ DB_BUF1_PAGE_PGM, dest);
+ if(!status)
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ /* Update size, source and destination pointers */
+ size -= pDataFlash->pDevice->pages_size;
+ dest += pDataFlash->pDevice->pages_size;
+ src += pDataFlash->pDevice->pages_size;
+ }
+
+ /* If still some bytes to read */
+ if ( size > 0 ) {
+ /* program dataflash page */
+ if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ }
+ return DATAFLASH_OK;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashRead */
+/* Object : Read a block in dataflash */
+/* Input Parameters : */
+/* Return value : */
+/*---------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+ AT91PS_DataFlash pDataFlash,
+ unsigned long addr,
+ unsigned long size,
+ char *buffer)
+{
+ unsigned long SizeToRead;
+
+ AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+ if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ return -1;
+
+ while (size) {
+ SizeToRead = (size < 0x8000)? size:0x8000;
+
+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ return -1;
+
+ if (AT91F_DataFlashContinuousRead (pDataFlash, addr,
+ (uchar *) buffer, SizeToRead) != DATAFLASH_OK)
+ return -1;
+
+ size -= SizeToRead;
+ addr += SizeToRead;
+ buffer += SizeToRead;
+ }
+
+ return DATAFLASH_OK;
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataflashProbe */
+/* Object : */
+/* Input Parameters : */
+/* Return value : Dataflash status register */
+/*---------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) {
+ AT91F_SpiEnable(cs);
+ AT91F_DataFlashGetStatus(pDesc);
+ return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+#endif
#include <pci.h>
#include <malloc.h>
-
/*
* PCI Registers and definitions.
*/
#define BCM570X_MBAR 0x80100000
#define BCM570X_ILINE 1
-
#define SECOND_USEC 1000000
#define MAX_PACKET_SIZE 1600
#define MAX_UNITS 4
/* Globals to this module */
int initialized = 0;
unsigned int ioBase = 0;
-volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */
-volatile PUM_DEVICE_BLOCK pUmDevice = NULL;
+volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */
+volatile PUM_DEVICE_BLOCK pUmDevice = NULL;
/* Used to pass the full-duplex flag, etc. */
-int line_speed[MAX_UNITS] = {0,0,0,0};
-static int full_duplex[MAX_UNITS] = {1,1,1,1};
-static int rx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int auto_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_checksum[MAX_UNITS] = {1,1,1,1};
-static int rx_checksum[MAX_UNITS] = {1,1,1,1};
-static int auto_speed[MAX_UNITS] = {1,1,1,1};
+int line_speed[MAX_UNITS] = { 0, 0, 0, 0 };
+static int full_duplex[MAX_UNITS] = { 1, 1, 1, 1 };
+static int rx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int tx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int auto_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int tx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
+static int rx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
+static int auto_speed[MAX_UNITS] = { 1, 1, 1, 1 };
#if JUMBO_FRAMES
/* Jumbo MTU for interfaces. */
-static int mtu[MAX_UNITS] = {0,0,0,0};
+static int mtu[MAX_UNITS] = { 0, 0, 0, 0 };
#endif
/* Turn on Wake-on lan for a device unit */
-static int enable_wol[MAX_UNITS] = {0,0,0,0};
+static int enable_wol[MAX_UNITS] = { 0, 0, 0, 0 };
#define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =
- {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT};
+ { TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT };
#define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
static unsigned int rx_std_desc_cnt[MAX_UNITS] =
- {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT};
+ { RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT };
-static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1};
+static unsigned int rx_adaptive_coalesce[MAX_UNITS] = { 1, 1, 1, 1 };
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
#define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =
- {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT};
+ { JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT };
#endif
#define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
static unsigned int rx_coalesce_ticks[MAX_UNITS] =
- {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK};
+ { RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK };
#define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
static unsigned int rx_max_coalesce_frames[MAX_UNITS] =
- {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM};
+ { RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM };
#define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
static unsigned int tx_coalesce_ticks[MAX_UNITS] =
- {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK};
+ { TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK };
#define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
static unsigned int tx_max_coalesce_frames[MAX_UNITS] =
- {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM};
+ { TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM };
#define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
static unsigned int stats_coalesce_ticks[MAX_UNITS] =
- {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK};
-
+ { ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK };
/*
* Legitimate values for BCM570x device types
/* Chip-Rev names for each device-type */
static struct {
- char* name;
+ char *name;
} chip_rev[] = {
- {"BCM5700VIGIL"},
- {"BCM5700A6"},
- {"BCM5700T6"},
- {"BCM5700A9"},
- {"BCM5700T9"},
- {"BCM5700"},
- {"BCM5701A5"},
- {"BCM5701T1"},
- {"BCM5701T8"},
- {"BCM5701A7"},
- {"BCM5701A10"},
- {"BCM5701A12"},
- {"BCM5701"},
- {"BCM5702"},
- {"BCM5703"},
- {"BCM5703A31"},
- {"TC996T"},
- {"TC996ST"},
- {"TC996SSX"},
- {"TC996SX"},
- {"TC996BT"},
- {"TC997T"},
- {"TC997SX"},
- {"TC1000T"},
- {"TC940BR01"},
- {"TC942BR01"},
- {"NC6770"},
- {"NC7760"},
- {"NC7770"},
- {"NC7780"},
- {0}
+ {
+ "BCM5700VIGIL"}, {
+ "BCM5700A6"}, {
+ "BCM5700T6"}, {
+ "BCM5700A9"}, {
+ "BCM5700T9"}, {
+ "BCM5700"}, {
+ "BCM5701A5"}, {
+ "BCM5701T1"}, {
+ "BCM5701T8"}, {
+ "BCM5701A7"}, {
+ "BCM5701A10"}, {
+ "BCM5701A12"}, {
+ "BCM5701"}, {
+ "BCM5702"}, {
+ "BCM5703"}, {
+ "BCM5703A31"}, {
+ "TC996T"}, {
+ "TC996ST"}, {
+ "TC996SSX"}, {
+ "TC996SX"}, {
+ "TC996BT"}, {
+ "TC997T"}, {
+ "TC997SX"}, {
+ "TC1000T"}, {
+ "TC940BR01"}, {
+ "TC942BR01"}, {
+ "NC6770"}, {
+ "NC7760"}, {
+ "NC7770"}, {
+ "NC7780"}, {
+ 0}
};
-
/* indexed by board_t, above */
static struct {
- char *name;
+ char *name;
} board_info[] = {
- { "Broadcom Vigil B5700 1000Base-T" },
- { "Broadcom BCM5700 1000Base-T" },
- { "Broadcom BCM5700 1000Base-SX" },
- { "Broadcom BCM5700 1000Base-SX" },
- { "Broadcom BCM5700 1000Base-T" },
- { "Broadcom BCM5700" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-SX" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701" },
- { "Broadcom BCM5702 1000Base-T" },
- { "Broadcom BCM5703 1000Base-T" },
- { "Broadcom BCM5703 1000Base-SX" },
- { "3Com 3C996 10/100/1000 Server NIC" },
- { "3Com 3C996 10/100/1000 Server NIC" },
- { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
- { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
- { "3Com 3C996B Gigabit Server NIC" },
- { "3Com 3C997 Gigabit Server NIC" },
- { "3Com 3C997 Gigabit Fiber-SX Server NIC" },
- { "3Com 3C1000 Gigabit NIC" },
- { "3Com 3C940 Gigabit LOM (21X21)" },
- { "3Com 3C942 Gigabit LOM (31X31)" },
- { "Compaq NC6770 Gigabit Server Adapter" },
- { "Compaq NC7760 Gigabit Server Adapter" },
- { "Compaq NC7770 Gigabit Server Adapter" },
- { "Compaq NC7780 Gigabit Server Adapter" },
- { 0 },
-};
+ {
+ "Broadcom Vigil B5700 1000Base-T"}, {
+ "Broadcom BCM5700 1000Base-T"}, {
+ "Broadcom BCM5700 1000Base-SX"}, {
+ "Broadcom BCM5700 1000Base-SX"}, {
+ "Broadcom BCM5700 1000Base-T"}, {
+ "Broadcom BCM5700"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-SX"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701"}, {
+ "Broadcom BCM5702 1000Base-T"}, {
+ "Broadcom BCM5703 1000Base-T"}, {
+ "Broadcom BCM5703 1000Base-SX"}, {
+ "3Com 3C996 10/100/1000 Server NIC"}, {
+ "3Com 3C996 10/100/1000 Server NIC"}, {
+ "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
+ "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
+ "3Com 3C996B Gigabit Server NIC"}, {
+ "3Com 3C997 Gigabit Server NIC"}, {
+ "3Com 3C997 Gigabit Fiber-SX Server NIC"}, {
+ "3Com 3C1000 Gigabit NIC"}, {
+ "3Com 3C940 Gigabit LOM (21X21)"}, {
+ "3Com 3C942 Gigabit LOM (31X31)"}, {
+ "Compaq NC6770 Gigabit Server Adapter"}, {
+ "Compaq NC7760 Gigabit Server Adapter"}, {
+ "Compaq NC7770 Gigabit Server Adapter"}, {
+ "Compaq NC7780 Gigabit Server Adapter"}, {
+0},};
/* PCI Devices which use the 570x chipset */
struct pci_device_table {
- unsigned short vendor_id, device_id; /* Vendor/DeviceID */
- unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
- unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
- unsigned long board_id; /* Data private to the driver */
- int io_size, min_latency;
+ unsigned short vendor_id, device_id; /* Vendor/DeviceID */
+ unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
+ unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
+ unsigned long board_id; /* Data private to the driver */
+ int io_size, min_latency;
} bcm570xDevices[] = {
- {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32},
- {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32},
- {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32},
- {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32},
- {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32},
- {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32},
- {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32},
- {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
- {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
- {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
- {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
- {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
- {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
- {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}
+ {
+ 0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01, 128, 32}, {
+ 0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12, 128, 32}, {
+ 0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770, 128, 32}, {
+ 0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770, 128, 32}, {
+ 0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780, 128, 32}, {
+ 0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01, 128, 32}, {
+ 0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701, 128, 32}, {
+ 0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
+ 0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
+ 0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
+ 0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
+ 0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
+ 0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
+ 0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}
};
#define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
-
/*
* Allocate a packet buffer from the bcm570x packet pool.
*/
-void *
-bcm570xPktAlloc(int u, int pksize)
+void *bcm570xPktAlloc (int u, int pksize)
{
- return malloc(pksize);
+ return malloc (pksize);
}
/*
* Free a packet previously allocated from the bcm570x packet
* buffer pool.
*/
-void
-bcm570xPktFree(int u, void *p)
+void bcm570xPktFree (int u, void *p)
{
- free(p);
+ free (p);
}
-int
-bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice)
+int bcm570xReplenishRxBuffers (PUM_DEVICE_BLOCK pUmDevice)
{
- PLM_PACKET pPacket;
- PUM_PACKET pUmPacket;
- void *skb;
- int queue_rx = 0;
- int ret = 0;
-
- while ((pUmPacket = (PUM_PACKET)
- QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
-
- pPacket = (PLM_PACKET) pUmPacket;
-
- /* reuse an old skb */
- if (pUmPacket->skbuff) {
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- queue_rx = 1;
- continue;
- }
- if ( ( skb = bcm570xPktAlloc(pUmDevice->index,
- pPacket->u.Rx.RxBufferSize + 2)) == 0) {
- QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket);
- printf("NOTICE: Out of RX memory.\n");
- ret = 1;
- break;
- }
+ PLM_PACKET pPacket;
+ PUM_PACKET pUmPacket;
+ void *skb;
+ int queue_rx = 0;
+ int ret = 0;
+
+ while ((pUmPacket = (PUM_PACKET)
+ QQ_PopHead (&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
+
+ pPacket = (PLM_PACKET) pUmPacket;
+
+ /* reuse an old skb */
+ if (pUmPacket->skbuff) {
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+ pPacket);
+ queue_rx = 1;
+ continue;
+ }
+ if ((skb = bcm570xPktAlloc (pUmDevice->index,
+ pPacket->u.Rx.RxBufferSize + 2)) ==
+ 0) {
+ QQ_PushHead (&pUmDevice->rx_out_of_buf_q.Container,
+ pPacket);
+ printf ("NOTICE: Out of RX memory.\n");
+ ret = 1;
+ break;
+ }
- pUmPacket->skbuff = skb;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- queue_rx = 1;
- }
+ pUmPacket->skbuff = skb;
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+ queue_rx = 1;
+ }
- if (queue_rx) {
- LM_QueueRxPackets(pDevice);
- }
+ if (queue_rx) {
+ LM_QueueRxPackets (pDevice);
+ }
- return ret;
+ return ret;
}
/*
* Probe, Map, and Init 570x device.
*/
-int eth_init(bd_t *bis)
+int eth_init (bd_t * bis)
{
- int i, rv, devFound = FALSE;
- pci_dev_t devbusfn;
- unsigned short status;
-
- /* Find PCI device, if it exists, configure ... */
- for( i = 0; i < n570xDevices; i++){
- devbusfn = pci_find_device(bcm570xDevices[i].vendor_id,
- bcm570xDevices[i].device_id, 0);
- if(devbusfn == -1) {
- continue; /* No device of that vendor/device ID */
+ int i, rv, devFound = FALSE;
+ pci_dev_t devbusfn;
+ unsigned short status;
+
+ /* Find PCI device, if it exists, configure ... */
+ for (i = 0; i < n570xDevices; i++) {
+ devbusfn = pci_find_device (bcm570xDevices[i].vendor_id,
+ bcm570xDevices[i].device_id, 0);
+ if (devbusfn == -1) {
+ continue; /* No device of that vendor/device ID */
+ } else {
+
+ /* Set ILINE */
+ pci_write_config_byte (devbusfn,
+ PCI_INTERRUPT_LINE,
+ BCM570X_ILINE);
+
+ /*
+ * 0x10 - 0x14 define one 64-bit MBAR.
+ * 0x14 is the higher-order address bits of the BAR.
+ */
+ pci_write_config_dword (devbusfn,
+ PCI_BASE_ADDRESS_1, 0);
+
+ ioBase = BCM570X_MBAR;
+
+ pci_write_config_dword (devbusfn,
+ PCI_BASE_ADDRESS_0, ioBase);
+
+ /*
+ * Enable PCI memory, IO, and Master -- don't
+ * reset any status bits in doing so.
+ */
+ pci_read_config_word (devbusfn, PCI_COMMAND, &status);
+
+ status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+
+ pci_write_config_word (devbusfn, PCI_COMMAND, status);
+
+ printf
+ ("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
+ board_info[bcm570xDevices[i].board_id].name,
+ PCI_BUS (devbusfn), PCI_DEV (devbusfn),
+ PCI_FUNC (devbusfn), ioBase);
+
+ /* Allocate once, but always clear on init */
+ if (!pDevice) {
+ pDevice = malloc (sizeof (UM_DEVICE_BLOCK));
+ pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ memset (pDevice, 0x0, sizeof (UM_DEVICE_BLOCK));
+ }
+
+ /* Configure pci dev structure */
+ pUmDevice->pdev = devbusfn;
+ pUmDevice->index = 0;
+ pUmDevice->tx_pkt = 0;
+ pUmDevice->rx_pkt = 0;
+ devFound = TRUE;
+ break;
+ }
+ }
+
+ if (!devFound) {
+ printf
+ ("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
+ return -1;
+ }
+
+ /* Setup defaults for chip */
+ pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+
+ if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
+ pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
} else {
- /* Set ILINE */
- pci_write_config_byte(devbusfn,
- PCI_INTERRUPT_LINE, BCM570X_ILINE);
-
- /*
- * 0x10 - 0x14 define one 64-bit MBAR.
- * 0x14 is the higher-order address bits of the BAR.
- */
- pci_write_config_dword(devbusfn,
- PCI_BASE_ADDRESS_1, 0);
-
- ioBase = BCM570X_MBAR;
-
- pci_write_config_dword(devbusfn,
- PCI_BASE_ADDRESS_0, ioBase);
-
- /*
- * Enable PCI memory, IO, and Master -- don't
- * reset any status bits in doing so.
- */
- pci_read_config_word(devbusfn,
- PCI_COMMAND, &status);
-
- status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
-
- pci_write_config_word(devbusfn,
- PCI_COMMAND, status);
-
- printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
- board_info[bcm570xDevices[i].board_id].name,
- PCI_BUS(devbusfn),
- PCI_DEV(devbusfn),
- PCI_FUNC(devbusfn),
- ioBase);
-
- /* Allocate once, but always clear on init */
- if (!pDevice) {
- pDevice = malloc(sizeof(UM_DEVICE_BLOCK));
- pUmDevice = (PUM_DEVICE_BLOCK)pDevice;
- memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK));
- }
-
- /* Configure pci dev structure */
- pUmDevice->pdev = devbusfn;
- pUmDevice->index = 0;
- pUmDevice->tx_pkt = 0;
- pUmDevice->rx_pkt = 0;
- devFound = TRUE;
- break;
+ if (rx_checksum[i]) {
+ pDevice->TaskToOffload |=
+ LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
+ LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
+ }
+
+ if (tx_checksum[i]) {
+ pDevice->TaskToOffload |=
+ LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
+ LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
+ pDevice->NoTxPseudoHdrChksum = TRUE;
+ }
+ }
+
+ /* Set Device PCI Memory base address */
+ pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
+
+ /* Pull down adapter info */
+ if ((rv = LM_GetAdapterInfo (pDevice)) != LM_STATUS_SUCCESS) {
+ printf ("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv);
+ return -2;
}
- }
- if(!devFound){
- printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
- return -1;
- }
+ /* Lock not needed */
+ pUmDevice->do_global_lock = 0;
- /* Setup defaults for chip */
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+ if (T3_ASIC_REV (pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
+ /* The 5700 chip works best without interleaved register */
+ /* accesses on certain machines. */
+ pUmDevice->do_global_lock = 1;
+ }
- if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
- } else {
+ /* Setup timer delays */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ pDevice->UseTaggedStatus = TRUE;
+ pUmDevice->timer_interval = CFG_HZ;
+ } else {
+ pUmDevice->timer_interval = CFG_HZ / 50;
+ }
- if (rx_checksum[i]) {
- pDevice->TaskToOffload |=
- LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
+ /* Grab name .... */
+ pUmDevice->name =
+ (char *)malloc (strlen (board_info[bcm570xDevices[i].board_id].name)
+ + 1);
+ strcpy (pUmDevice->name, board_info[bcm570xDevices[i].board_id].name);
+
+ memcpy (pDevice->NodeAddress, bis->bi_enetaddr, 6);
+ LM_SetMacAddress (pDevice, bis->bi_enetaddr);
+ /* Init queues .. */
+ QQ_InitQueue (&pUmDevice->rx_out_of_buf_q.Container,
+ MAX_RX_PACKET_DESC_COUNT);
+ pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
+
+ /* delay for 4 seconds */
+ pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval;
+
+ pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval;
+
+ /* Sometimes we get spurious ints. after reset when link is down. */
+ /* This field tells the isr to service the int. even if there is */
+ /* no status block update. */
+ pUmDevice->adapter_just_inited =
+ (3 * CFG_HZ) / pUmDevice->timer_interval;
+
+ /* Initialize 570x */
+ if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) {
+ printf ("ERROR: Adapter initialization failed.\n");
+ return ERROR;
}
- if (tx_checksum[i]) {
- pDevice->TaskToOffload |=
- LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
- pDevice->NoTxPseudoHdrChksum = TRUE;
+ /* Enable chip ISR */
+ LM_EnableInterrupt (pDevice);
+
+ /* Clear MC table */
+ LM_MulticastClear (pDevice);
+
+ /* Enable Multicast */
+ LM_SetReceiveMask (pDevice,
+ pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
+
+ pUmDevice->opened = 1;
+ pUmDevice->tx_full = 0;
+ pUmDevice->tx_pkt = 0;
+ pUmDevice->rx_pkt = 0;
+ printf ("eth%d: %s @0x%lx,",
+ pDevice->index, pUmDevice->name, (unsigned long)ioBase);
+ printf ("node addr ");
+ for (i = 0; i < 6; i++) {
+ printf ("%2.2x", pDevice->NodeAddress[i]);
}
- }
-
- /* Set Device PCI Memory base address */
- pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
-
- /* Pull down adapter info */
- if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) {
- printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv );
- return -2;
- }
-
- /* Lock not needed */
- pUmDevice->do_global_lock = 0;
-
- if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
- /* The 5700 chip works best without interleaved register */
- /* accesses on certain machines. */
- pUmDevice->do_global_lock = 1;
- }
-
- /* Setup timer delays */
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- pDevice->UseTaggedStatus = TRUE;
- pUmDevice->timer_interval = CFG_HZ;
- }
- else {
- pUmDevice->timer_interval = CFG_HZ / 50;
- }
-
- /* Grab name .... */
- pUmDevice->name =
- (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1);
- strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name);
-
- memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6);
- LM_SetMacAddress(pDevice, bis->bi_enetaddr);
- /* Init queues .. */
- QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container,
- MAX_RX_PACKET_DESC_COUNT);
- pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
-
- /* delay for 4 seconds */
- pUmDevice->delayed_link_ind =
- (4 * CFG_HZ) / pUmDevice->timer_interval;
-
- pUmDevice->adaptive_expiry =
- CFG_HZ / pUmDevice->timer_interval;
-
- /* Sometimes we get spurious ints. after reset when link is down. */
- /* This field tells the isr to service the int. even if there is */
- /* no status block update. */
- pUmDevice->adapter_just_inited =
- (3 * CFG_HZ) / pUmDevice->timer_interval;
-
- /* Initialize 570x */
- if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) {
- printf("ERROR: Adapter initialization failed.\n");
- return ERROR;
- }
-
- /* Enable chip ISR */
- LM_EnableInterrupt(pDevice);
-
- /* Clear MC table */
- LM_MulticastClear(pDevice);
-
- /* Enable Multicast */
- LM_SetReceiveMask(pDevice,
- pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
-
- pUmDevice->opened = 1;
- pUmDevice->tx_full = 0;
- pUmDevice->tx_pkt = 0;
- pUmDevice->rx_pkt = 0;
- printf("eth%d: %s @0x%lx,",
- pDevice->index, pUmDevice->name, (unsigned long)ioBase);
- printf( "node addr ");
- for (i = 0; i < 6; i++) {
- printf("%2.2x", pDevice->NodeAddress[i]);
- }
- printf("\n");
-
- printf("eth%d: ", pDevice->index);
- printf("%s with ",
- chip_rev[bcm570xDevices[i].board_id].name);
-
- if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
- printf("Broadcom BCM5400 Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
- printf("Broadcom BCM5401 Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
- printf("Broadcom BCM5411 Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
- printf("Broadcom BCM5701 Integrated Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
- printf("Broadcom BCM5703 Integrated Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
- printf("Broadcom BCM8002 SerDes ");
- else if (pDevice->EnableTbi)
- printf("Agilent HDMP-1636 SerDes ");
- else
- printf("Unknown ");
- printf("transceiver found\n");
-
- printf("eth%d: %s, MTU: %d,",
- pDevice->index, pDevice->BusSpeedStr, 1500);
-
- if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) &&
- rx_checksum[i])
- printf("Rx Checksum ON\n");
- else
- printf("Rx Checksum OFF\n");
- initialized++;
-
- return 0;
+ printf ("\n");
+
+ printf ("eth%d: ", pDevice->index);
+ printf ("%s with ", chip_rev[bcm570xDevices[i].board_id].name);
+
+ if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
+ printf ("Broadcom BCM5400 Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
+ printf ("Broadcom BCM5401 Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
+ printf ("Broadcom BCM5411 Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
+ printf ("Broadcom BCM5701 Integrated Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
+ printf ("Broadcom BCM5703 Integrated Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
+ printf ("Broadcom BCM8002 SerDes ");
+ else if (pDevice->EnableTbi)
+ printf ("Agilent HDMP-1636 SerDes ");
+ else
+ printf ("Unknown ");
+ printf ("transceiver found\n");
+
+ printf ("eth%d: %s, MTU: %d,",
+ pDevice->index, pDevice->BusSpeedStr, 1500);
+
+ if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && rx_checksum[i])
+ printf ("Rx Checksum ON\n");
+ else
+ printf ("Rx Checksum OFF\n");
+ initialized++;
+
+ return 0;
}
/* Ethernet Interrupt service routine */
-void
-eth_isr(void)
+void eth_isr (void)
{
- LM_UINT32 oldtag, newtag;
- int i;
-
- pUmDevice->interrupt = 1;
-
- if (pDevice->UseTaggedStatus) {
- if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
- pUmDevice->adapter_just_inited) {
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
- oldtag = pDevice->pStatusBlkVirt->StatusTag;
-
- for (i = 0; ; i++) {
- pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
- LM_ServiceInterrupts(pDevice);
- newtag = pDevice->pStatusBlkVirt->StatusTag;
- if ((newtag == oldtag) || (i > 50)) {
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24);
- if (pDevice->UndiFix) {
- REG_WR(pDevice, Grc.LocalCtrl,
- pDevice->GrcLocalCtrl | 0x2);
- }
- break;
- }
- oldtag = newtag;
- }
+ LM_UINT32 oldtag, newtag;
+ int i;
+
+ pUmDevice->interrupt = 1;
+
+ if (pDevice->UseTaggedStatus) {
+ if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
+ pUmDevice->adapter_just_inited) {
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
+ oldtag = pDevice->pStatusBlkVirt->StatusTag;
+
+ for (i = 0;; i++) {
+ pDevice->pStatusBlkVirt->Status &=
+ ~STATUS_BLOCK_UPDATED;
+ LM_ServiceInterrupts (pDevice);
+ newtag = pDevice->pStatusBlkVirt->StatusTag;
+ if ((newtag == oldtag) || (i > 50)) {
+ MB_REG_WR (pDevice,
+ Mailbox.Interrupt[0].Low,
+ newtag << 24);
+ if (pDevice->UndiFix) {
+ REG_WR (pDevice, Grc.LocalCtrl,
+ pDevice->
+ GrcLocalCtrl | 0x2);
+ }
+ break;
+ }
+ oldtag = newtag;
+ }
+ }
+ } else {
+ while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
+ unsigned int dummy;
+
+ pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
+ pDevice->pStatusBlkVirt->Status &=
+ ~STATUS_BLOCK_UPDATED;
+ LM_ServiceInterrupts (pDevice);
+ pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
+ dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
+ }
+ }
+
+ /* Allocate new RX buffers */
+ if (QQ_GetEntryCnt (&pUmDevice->rx_out_of_buf_q.Container)) {
+ bcm570xReplenishRxBuffers (pUmDevice);
}
- }
- else {
- while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
- unsigned int dummy;
-
- pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
- pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
- LM_ServiceInterrupts(pDevice);
- pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
- dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
+
+ /* Queue packets */
+ if (QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container)) {
+ LM_QueueRxPackets (pDevice);
+ }
+
+ if (pUmDevice->tx_queued) {
+ pUmDevice->tx_queued = 0;
}
- }
-
- /* Allocate new RX buffers */
- if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) {
- bcm570xReplenishRxBuffers(pUmDevice);
- }
-
- /* Queue packets */
- if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) {
- LM_QueueRxPackets(pDevice);
- }
-
- if (pUmDevice->tx_queued) {
- pUmDevice->tx_queued = 0;
- }
-
- if(pUmDevice->tx_full){
- if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){
- printf("NOTICE: tx was previously blocked, restarting MUX\n");
- pUmDevice->tx_full = 0;
+
+ if (pUmDevice->tx_full) {
+ if (pDevice->LinkStatus != LM_STATUS_LINK_DOWN) {
+ printf
+ ("NOTICE: tx was previously blocked, restarting MUX\n");
+ pUmDevice->tx_full = 0;
+ }
}
- }
- pUmDevice->interrupt = 0;
+ pUmDevice->interrupt = 0;
}
-int
-eth_send(volatile void *packet, int length)
+int eth_send (volatile void *packet, int length)
{
- int status = 0;
+ int status = 0;
#if ET_DEBUG
- unsigned char* ptr = (unsigned char*)packet;
+ unsigned char *ptr = (unsigned char *)packet;
#endif
- PLM_PACKET pPacket;
- PUM_PACKET pUmPacket;
+ PLM_PACKET pPacket;
+ PUM_PACKET pUmPacket;
- /* Link down, return */
- while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
+ /* Link down, return */
+ while (pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
#if 0
- printf("eth%d: link down - check cable or link partner.\n",
- pUmDevice->index);
+ printf ("eth%d: link down - check cable or link partner.\n",
+ pUmDevice->index);
#endif
- eth_isr();
+ eth_isr ();
+
+ /* Wait to see link for one-half a second before sending ... */
+ udelay (1500000);
- /* Wait to see link for one-half a second before sending ... */
- udelay(1500000);
+ }
- }
+ /* Clear sent flag */
+ pUmDevice->tx_pkt = 0;
- /* Clear sent flag */
- pUmDevice->tx_pkt = 0;
+ /* Previously blocked */
+ if (pUmDevice->tx_full) {
+ printf ("eth%d: tx blocked.\n", pUmDevice->index);
+ return 0;
+ }
- /* Previously blocked */
- if(pUmDevice->tx_full){
- printf("eth%d: tx blocked.\n", pUmDevice->index);
- return 0;
- }
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->TxPacketFreeQ.Container);
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->TxPacketFreeQ.Container);
+ if (pPacket == 0) {
+ pUmDevice->tx_full = 1;
+ printf ("bcm570xEndSend: TX full!\n");
+ return 0;
+ }
- if (pPacket == 0) {
- pUmDevice->tx_full = 1;
- printf("bcm570xEndSend: TX full!\n");
- return 0;
- }
+ if (pDevice->SendBdLeft.counter == 0) {
+ pUmDevice->tx_full = 1;
+ printf ("bcm570xEndSend: no more TX descriptors!\n");
+ QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
+ return 0;
+ }
- if (pDevice->SendBdLeft.counter == 0) {
- pUmDevice->tx_full = 1;
- printf("bcm570xEndSend: no more TX descriptors!\n");
- QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
- return 0;
- }
-
- if (length <= 0){
- printf("eth: bad packet size: %d\n", length);
- goto out;
- }
-
- /* Get packet buffers and fragment list */
- pUmPacket = (PUM_PACKET) pPacket;
- /* Single DMA Descriptor transmit.
- * Fragments may be provided, but one DMA descriptor max is
- * used to send the packet.
- */
- if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
- if (pUmPacket->skbuff == NULL){
- /* Packet was discarded */
- printf("TX: failed (1)\n");
- status = 1;
- } else{
- printf("TX: failed (2)\n");
- status = 2;
+ if (length <= 0) {
+ printf ("eth: bad packet size: %d\n", length);
+ goto out;
}
- QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
- return status;
- }
-
- /* Copy packet to DMA buffer */
- memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
- memcpy((void*)pUmPacket->skbuff, (void*)packet, length);
- pPacket->PacketSize = length;
- pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW;
- pPacket->u.Tx.FragCount = 1;
- /* We've already provided a frame ready for transmission */
- pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
-
- if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){
- /*
- * A lower level send failure will push the packet descriptor back
- * in the free queue, so just deal with the VxWorks clusters.
+
+ /* Get packet buffers and fragment list */
+ pUmPacket = (PUM_PACKET) pPacket;
+ /* Single DMA Descriptor transmit.
+ * Fragments may be provided, but one DMA descriptor max is
+ * used to send the packet.
*/
- if (pUmPacket->skbuff == NULL){
- printf("TX failed (1)!\n");
- /* Packet was discarded */
- status = 3;
- } else {
- /* A resource problem ... */
- printf("TX failed (2)!\n");
- status = 4;
+ if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
+ if (pUmPacket->skbuff == NULL) {
+ /* Packet was discarded */
+ printf ("TX: failed (1)\n");
+ status = 1;
+ } else {
+ printf ("TX: failed (2)\n");
+ status = 2;
+ }
+ QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
+ return status;
}
- if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) {
- printf("TX: emptyQ!\n");
- pUmDevice->tx_full = 1;
+ /* Copy packet to DMA buffer */
+ memset (pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
+ memcpy ((void *)pUmPacket->skbuff, (void *)packet, length);
+ pPacket->PacketSize = length;
+ pPacket->Flags |= SND_BD_FLAG_END | SND_BD_FLAG_COAL_NOW;
+ pPacket->u.Tx.FragCount = 1;
+ /* We've already provided a frame ready for transmission */
+ pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
+
+ if (LM_SendPacket (pDevice, pPacket) == LM_STATUS_FAILURE) {
+ /*
+ * A lower level send failure will push the packet descriptor back
+ * in the free queue, so just deal with the VxWorks clusters.
+ */
+ if (pUmPacket->skbuff == NULL) {
+ printf ("TX failed (1)!\n");
+ /* Packet was discarded */
+ status = 3;
+ } else {
+ /* A resource problem ... */
+ printf ("TX failed (2)!\n");
+ status = 4;
+ }
+
+ if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) == 0) {
+ printf ("TX: emptyQ!\n");
+ pUmDevice->tx_full = 1;
+ }
}
- }
- while(pUmDevice->tx_pkt == 0){
- /* Service TX */
- eth_isr();
- }
+ while (pUmDevice->tx_pkt == 0) {
+ /* Service TX */
+ eth_isr ();
+ }
#if ET_DEBUG
- printf("eth_send: 0x%x, %d bytes\n"
- "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
- (int)pPacket, length,
- ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5],
- ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12],
- ptr[13],ptr[14],ptr[15]);
+ printf ("eth_send: 0x%x, %d bytes\n"
+ "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
+ (int)pPacket, length,
+ ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5],
+ ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12],
+ ptr[13], ptr[14], ptr[15]);
#endif
- pUmDevice->tx_pkt = 0;
- QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
+ pUmDevice->tx_pkt = 0;
+ QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
- /* Done with send */
- out:
- return status;
+ /* Done with send */
+ out:
+ return status;
}
-
/* Ethernet receive */
-int
-eth_rx(void)
+int eth_rx (void)
{
- PLM_PACKET pPacket = NULL;
- PUM_PACKET pUmPacket = NULL;
- void *skb;
- int size=0;
+ PLM_PACKET pPacket = NULL;
+ PUM_PACKET pUmPacket = NULL;
+ void *skb;
+ int size = 0;
- while(TRUE) {
+ while (TRUE) {
- bcm570x_service_isr:
- /* Pull down packet if it is there */
- eth_isr();
+ bcm570x_service_isr:
+ /* Pull down packet if it is there */
+ eth_isr ();
- /* Indicate RX packets called */
- if(pUmDevice->rx_pkt){
- /* printf("eth_rx: got a packet...\n"); */
- pUmDevice->rx_pkt = 0;
- } else {
- /* printf("eth_rx: waiting for packet...\n"); */
- goto bcm570x_service_isr;
- }
+ /* Indicate RX packets called */
+ if (pUmDevice->rx_pkt) {
+ /* printf("eth_rx: got a packet...\n"); */
+ pUmDevice->rx_pkt = 0;
+ } else {
+ /* printf("eth_rx: waiting for packet...\n"); */
+ goto bcm570x_service_isr;
+ }
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->RxPacketReceivedQ.Container);
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->RxPacketReceivedQ.Container);
- if (pPacket == 0){
- printf("eth_rx: empty packet!\n");
- goto bcm570x_service_isr;
- }
+ if (pPacket == 0) {
+ printf ("eth_rx: empty packet!\n");
+ goto bcm570x_service_isr;
+ }
- pUmPacket = (PUM_PACKET) pPacket;
+ pUmPacket = (PUM_PACKET) pPacket;
#if ET_DEBUG
- printf("eth_rx: packet @0x%x\n",
- (int)pPacket);
+ printf ("eth_rx: packet @0x%x\n", (int)pPacket);
#endif
- /* If the packet generated an error, reuse buffer */
- if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
- ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
-
- /* reuse skb */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- printf("eth_rx: error in packet dma!\n");
- goto bcm570x_service_isr;
- }
+ /* If the packet generated an error, reuse buffer */
+ if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
+ ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
+
+ /* reuse skb */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+ pPacket);
+ printf ("eth_rx: error in packet dma!\n");
+ goto bcm570x_service_isr;
+ }
- /* Set size and address */
- skb = pUmPacket->skbuff;
- size = pPacket->PacketSize;
+ /* Set size and address */
+ skb = pUmPacket->skbuff;
+ size = pPacket->PacketSize;
- /* Pass the packet up to the protocol
- * layers.
- */
- NetReceive(skb, size);
+ /* Pass the packet up to the protocol
+ * layers.
+ */
+ NetReceive (skb, size);
- /* Free packet buffer */
- bcm570xPktFree (pUmDevice->index, skb);
- pUmPacket->skbuff = NULL;
+ /* Free packet buffer */
+ bcm570xPktFree (pUmDevice->index, skb);
+ pUmPacket->skbuff = NULL;
- /* Reuse SKB */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ /* Reuse SKB */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- return 0; /* Got a packet, bail ... */
- }
- return size;
+ return 0; /* Got a packet, bail ... */
+ }
+ return size;
}
-
/* Shut down device */
-void
-eth_halt(void)
+void eth_halt (void)
{
- int i;
- if ( initialized)
- if (pDevice && pUmDevice && pUmDevice->opened){
- printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name);
- printf("HALT,");
- /* stop device */
- LM_Halt(pDevice);
- printf("POWER DOWN,");
- LM_SetPowerState(pDevice, LM_POWER_STATE_D3);
-
- /* Free the memory allocated by the device in tigon3 */
- for (i = 0; i < pUmDevice->mem_list_num; i++) {
- if (pUmDevice->mem_list[i]) {
- /* sanity check */
- if (pUmDevice->dma_list[i]) { /* cache-safe memory */
- free(pUmDevice->mem_list[i]);
- } else {
- free(pUmDevice->mem_list[i]); /* normal memory */
+ int i;
+ if (initialized)
+ if (pDevice && pUmDevice && pUmDevice->opened) {
+ printf ("\neth%d:%s,", pUmDevice->index,
+ pUmDevice->name);
+ printf ("HALT,");
+ /* stop device */
+ LM_Halt (pDevice);
+ printf ("POWER DOWN,");
+ LM_SetPowerState (pDevice, LM_POWER_STATE_D3);
+
+ /* Free the memory allocated by the device in tigon3 */
+ for (i = 0; i < pUmDevice->mem_list_num; i++) {
+ if (pUmDevice->mem_list[i]) {
+ /* sanity check */
+ if (pUmDevice->dma_list[i]) { /* cache-safe memory */
+ free (pUmDevice->mem_list[i]);
+ } else {
+ free (pUmDevice->mem_list[i]); /* normal memory */
+ }
+ }
+ }
+ pUmDevice->opened = 0;
+ free (pDevice);
+ pDevice = NULL;
+ pUmDevice = NULL;
+ initialized = 0;
+ printf ("done - offline.\n");
}
- }
- }
- pUmDevice->opened = 0;
- free(pDevice);
- pDevice = NULL;
- pUmDevice = NULL;
- initialized = 0;
- printf("done - offline.\n");
- }
}
-
/*
*
* Middle Module: Interface between the HW driver (tigon3 modules) and
*/
/* Middle module dependency - size of a packet descriptor */
-int MM_Packet_Desc_Size = sizeof(UM_PACKET);
-
+int MM_Packet_Desc_Size = sizeof (UM_PACKET);
LM_STATUS
-MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 *pValue32)
+MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 Offset, LM_UINT32 * pValue32)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_read_config_dword(pUmDevice->pdev,
- Offset, (u32 *) pValue32);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_read_config_dword (pUmDevice->pdev, Offset, (u32 *) pValue32);
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 Value32)
+MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 Value32)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_write_config_dword(pUmDevice->pdev,
- Offset, Value32);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_write_config_dword (pUmDevice->pdev, Offset, Value32);
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT16 *pValue16)
+MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 Offset, LM_UINT16 * pValue16)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_read_config_word(pUmDevice->pdev,
- Offset, (u16*) pValue16);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_read_config_word (pUmDevice->pdev, Offset, (u16 *) pValue16);
+ return LM_STATUS_SUCCESS;
}
LM_STATUS
-MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT16 Value16)
+MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT16 Value16)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_write_config_word(pUmDevice->pdev,
- Offset, Value16);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_write_config_word (pUmDevice->pdev, Offset, Value16);
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt,
- PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
- LM_BOOL Cached)
+MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt,
+ PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, LM_BOOL Cached)
{
- PLM_VOID pvirt;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- dma_addr_t mapping;
+ PLM_VOID pvirt;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ dma_addr_t mapping;
- pvirt = malloc(BlockSize);
- mapping = (dma_addr_t)(pvirt);
- if (!pvirt)
- return LM_STATUS_FAILURE;
+ pvirt = malloc (BlockSize);
+ mapping = (dma_addr_t) (pvirt);
+ if (!pvirt)
+ return LM_STATUS_FAILURE;
- pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
- pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
- pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
- memset(pvirt, 0, BlockSize);
+ pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
+ pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
+ pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
+ memset (pvirt, 0, BlockSize);
- *pMemoryBlockVirt = (PLM_VOID) pvirt;
- MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
+ *pMemoryBlockVirt = (PLM_VOID) pvirt;
+ MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt)
+MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt)
{
- PLM_VOID pvirt;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PLM_VOID pvirt;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- pvirt = malloc(BlockSize);
+ pvirt = malloc (BlockSize);
- if (!pvirt)
- return LM_STATUS_FAILURE;
+ if (!pvirt)
+ return LM_STATUS_FAILURE;
- pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
- pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
- pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
- memset(pvirt, 0, BlockSize);
- *pMemoryBlockVirt = pvirt;
+ pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
+ pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
+ pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
+ memset (pvirt, 0, BlockSize);
+ *pMemoryBlockVirt = pvirt;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_MapMemBase(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice)
{
- printf("BCM570x PCI Memory base address @0x%x\n",
- (unsigned int)pDevice->pMappedMemBase);
- return LM_STATUS_SUCCESS;
+ printf ("BCM570x PCI Memory base address @0x%x\n",
+ (unsigned int)pDevice->pMappedMemBase);
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice)
{
- int i;
- void* skb;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- PUM_PACKET pUmPacket = NULL;
- PLM_PACKET pPacket = NULL;
-
- for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
- pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- pUmPacket = (PUM_PACKET) pPacket;
+ int i;
+ void *skb;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PUM_PACKET pUmPacket = NULL;
+ PLM_PACKET pPacket = NULL;
+
+ for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
+ pPacket = QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ pUmPacket = (PUM_PACKET) pPacket;
+
+ if (pPacket == 0) {
+ printf ("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
+ }
- if (pPacket == 0) {
- printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
- }
+ skb = bcm570xPktAlloc (pUmDevice->index,
+ pPacket->u.Rx.RxBufferSize + 2);
- skb = bcm570xPktAlloc(pUmDevice->index,
- pPacket->u.Rx.RxBufferSize + 2);
+ if (skb == 0) {
+ pUmPacket->skbuff = 0;
+ QQ_PushTail (&pUmDevice->rx_out_of_buf_q.Container,
+ pPacket);
+ printf ("MM_InitializeUmPackets: out of buffer.\n");
+ continue;
+ }
- if (skb == 0) {
- pUmPacket->skbuff = 0;
- QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket);
- printf("MM_InitializeUmPackets: out of buffer.\n");
- continue;
+ pUmPacket->skbuff = skb;
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
}
- pUmPacket->skbuff = skb;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- }
-
- pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
+ pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_GetConfig(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- int index = pDevice->index;
-
- if (auto_speed[index] == 0)
- pDevice->DisableAutoNeg = TRUE;
- else
- pDevice->DisableAutoNeg = FALSE;
-
- if (line_speed[index] == 0) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->DisableAutoNeg = FALSE;
- }
- else {
- if (line_speed[index] == 1000) {
- if (pDevice->EnableTbi) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
- }
- else if (full_duplex[index]) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
- }
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
- }
- if (!pDevice->EnableTbi)
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ int index = pDevice->index;
+
+ if (auto_speed[index] == 0)
+ pDevice->DisableAutoNeg = TRUE;
+ else
pDevice->DisableAutoNeg = FALSE;
+
+ if (line_speed[index] == 0) {
+ pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
+ pDevice->DisableAutoNeg = FALSE;
+ } else {
+ if (line_speed[index] == 1000) {
+ if (pDevice->EnableTbi) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
+ } else if (full_duplex[index]) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
+ }
+ if (!pDevice->EnableTbi)
+ pDevice->DisableAutoNeg = FALSE;
+ } else if (line_speed[index] == 100) {
+ if (full_duplex[index]) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
+ }
+ } else if (line_speed[index] == 10) {
+ if (full_duplex[index]) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
+ }
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_AUTO;
+ pDevice->DisableAutoNeg = FALSE;
+ }
+
}
- else if (line_speed[index] == 100) {
- if (full_duplex[index]) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
- }
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
- }
- }
- else if (line_speed[index] == 10) {
- if (full_duplex[index]) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
- }
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
- }
+ pDevice->FlowControlCap = 0;
+ if (rx_flow_control[index] != 0) {
+ pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
}
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->DisableAutoNeg = FALSE;
+ if (tx_flow_control[index] != 0) {
+ pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
}
-
- }
- pDevice->FlowControlCap = 0;
- if (rx_flow_control[index] != 0) {
- pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- if (tx_flow_control[index] != 0) {
- pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- }
- if ((auto_flow_control[index] != 0) &&
- (pDevice->DisableAutoNeg == FALSE)) {
-
- pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
- if ((tx_flow_control[index] == 0) &&
- (rx_flow_control[index] == 0)) {
- pDevice->FlowControlCap |=
- LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ if ((auto_flow_control[index] != 0) &&
+ (pDevice->DisableAutoNeg == FALSE)) {
+
+ pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
+ if ((tx_flow_control[index] == 0) &&
+ (rx_flow_control[index] == 0)) {
+ pDevice->FlowControlCap |=
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+ LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ }
}
- }
- /* Default MTU for now */
- pUmDevice->mtu = 1500;
+ /* Default MTU for now */
+ pUmDevice->mtu = 1500;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if (pUmDevice->mtu > 1500) {
- pDevice->RxMtu = pUmDevice->mtu;
- pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
- }
- else {
- pDevice->RxJumboDescCnt = 0;
- }
- pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
+ if (pUmDevice->mtu > 1500) {
+ pDevice->RxMtu = pUmDevice->mtu;
+ pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
+ } else {
+ pDevice->RxJumboDescCnt = 0;
+ }
+ pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
#else
- pDevice->RxMtu = pUmDevice->mtu;
+ pDevice->RxMtu = pUmDevice->mtu;
#endif
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- pDevice->UseTaggedStatus = TRUE;
- pUmDevice->timer_interval = CFG_HZ;
- }
- else {
- pUmDevice->timer_interval = CFG_HZ/50;
- }
-
- pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
- pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
- /* Note: adaptive coalescence really isn't adaptive in this driver */
- pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
- if (!pUmDevice->rx_adaptive_coalesce) {
- pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
- if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
- pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
- pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks;
-
- pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
- if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES)
- pDevice->RxMaxCoalescedFrames =
- MAX_RX_MAX_COALESCED_FRAMES;
- pUmDevice->rx_curr_coalesce_frames =
- pDevice->RxMaxCoalescedFrames;
- pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
- if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS)
- pDevice->StatsCoalescingTicks=
- MAX_STATS_COALESCING_TICKS;
- }
- else {
- pUmDevice->rx_curr_coalesce_frames =
- DEFAULT_RX_MAX_COALESCED_FRAMES;
- pUmDevice->rx_curr_coalesce_ticks =
- DEFAULT_RX_COALESCING_TICKS;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ pDevice->UseTaggedStatus = TRUE;
+ pUmDevice->timer_interval = CFG_HZ;
+ } else {
+ pUmDevice->timer_interval = CFG_HZ / 50;
}
- pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
- if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
- pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
- pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
- if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
- pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
- if (enable_wol[index]) {
- pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
- pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
- }
- pDevice->NicSendBd = TRUE;
+ pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
+ pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
+ /* Note: adaptive coalescence really isn't adaptive in this driver */
+ pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
+ if (!pUmDevice->rx_adaptive_coalesce) {
+ pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
+ if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
+ pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
+ pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks;
+
+ pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
+ if (pDevice->RxMaxCoalescedFrames > MAX_RX_MAX_COALESCED_FRAMES)
+ pDevice->RxMaxCoalescedFrames =
+ MAX_RX_MAX_COALESCED_FRAMES;
+ pUmDevice->rx_curr_coalesce_frames =
+ pDevice->RxMaxCoalescedFrames;
+ pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
+ if (pDevice->StatsCoalescingTicks > MAX_STATS_COALESCING_TICKS)
+ pDevice->StatsCoalescingTicks =
+ MAX_STATS_COALESCING_TICKS;
+ } else {
+ pUmDevice->rx_curr_coalesce_frames =
+ DEFAULT_RX_MAX_COALESCED_FRAMES;
+ pUmDevice->rx_curr_coalesce_ticks = DEFAULT_RX_COALESCING_TICKS;
+ }
+ pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
+ if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
+ pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
+ pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
+ if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
+ pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
+
+ if (enable_wol[index]) {
+ pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
+ pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
+ }
+ pDevice->NicSendBd = TRUE;
- /* Don't update status blocks during interrupt */
- pDevice->RxCoalescingTicksDuringInt = 0;
- pDevice->TxCoalescingTicksDuringInt = 0;
+ /* Don't update status blocks during interrupt */
+ pDevice->RxCoalescingTicksDuringInt = 0;
+ pDevice->TxCoalescingTicksDuringInt = 0;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
-LM_STATUS
-MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- printf("Start TX DMA: dev=%d packet @0x%x\n",
- (int)pUmDevice->index, (unsigned int)pPacket);
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ printf ("Start TX DMA: dev=%d packet @0x%x\n",
+ (int)pUmDevice->index, (unsigned int)pPacket);
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- printf("Complete TX DMA: dev=%d packet @0x%x\n",
- (int)pUmDevice->index, (unsigned int)pPacket);
- return LM_STATUS_SUCCESS;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ printf ("Complete TX DMA: dev=%d packet @0x%x\n",
+ (int)pUmDevice->index, (unsigned int)pPacket);
+ return LM_STATUS_SUCCESS;
}
-
-LM_STATUS
-MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
+LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
{
- char buf[128];
- char lcd[4];
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- LM_FLOW_CONTROL flow_control;
-
- pUmDevice->delayed_link_ind = 0;
- memset(lcd, 0x0, 4);
-
- if (Status == LM_STATUS_LINK_DOWN) {
- sprintf(buf,"eth%d: %s: NIC Link is down\n",
- pUmDevice->index,pUmDevice->name);
- lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?';
- } else if (Status == LM_STATUS_LINK_ACTIVE) {
- sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name);
-
- if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){
- strcat(buf,"1000 Mbps ");
- lcd[0] = '1';lcd[1]='G';lcd[2]='B';
- } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){
- strcat(buf,"100 Mbps ");
- lcd[0] = '1';lcd[1]='0';lcd[2]='0';
- } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){
- strcat(buf,"10 Mbps ");
- lcd[0] = '1';lcd[1]='0';lcd[2]=' ';
- }
- if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){
- strcat(buf, "full duplex");
- lcd[3] = 'F';
- } else {
- strcat(buf, "half duplex");
- lcd[3] = 'H';
- }
- strcat(buf, " link up");
-
- flow_control = pDevice->FlowControl &
- (LM_FLOW_CONTROL_RECEIVE_PAUSE |
- LM_FLOW_CONTROL_TRANSMIT_PAUSE);
-
- if (flow_control) {
- if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
- strcat(buf,", receive ");
- if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
- strcat(buf," & transmit ");
- }
- else {
- strcat(buf,", transmit ");
- }
- strcat(buf,"flow control ON");
- } else {
- strcat(buf, ", flow control OFF");
+ char buf[128];
+ char lcd[4];
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ LM_FLOW_CONTROL flow_control;
+
+ pUmDevice->delayed_link_ind = 0;
+ memset (lcd, 0x0, 4);
+
+ if (Status == LM_STATUS_LINK_DOWN) {
+ sprintf (buf, "eth%d: %s: NIC Link is down\n",
+ pUmDevice->index, pUmDevice->name);
+ lcd[0] = 'L';
+ lcd[1] = 'N';
+ lcd[2] = 'K';
+ lcd[3] = '?';
+ } else if (Status == LM_STATUS_LINK_ACTIVE) {
+ sprintf (buf, "eth%d:%s: ", pUmDevice->index, pUmDevice->name);
+
+ if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) {
+ strcat (buf, "1000 Mbps ");
+ lcd[0] = '1';
+ lcd[1] = 'G';
+ lcd[2] = 'B';
+ } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) {
+ strcat (buf, "100 Mbps ");
+ lcd[0] = '1';
+ lcd[1] = '0';
+ lcd[2] = '0';
+ } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
+ strcat (buf, "10 Mbps ");
+ lcd[0] = '1';
+ lcd[1] = '0';
+ lcd[2] = ' ';
+ }
+ if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
+ strcat (buf, "full duplex");
+ lcd[3] = 'F';
+ } else {
+ strcat (buf, "half duplex");
+ lcd[3] = 'H';
+ }
+ strcat (buf, " link up");
+
+ flow_control = pDevice->FlowControl &
+ (LM_FLOW_CONTROL_RECEIVE_PAUSE |
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE);
+
+ if (flow_control) {
+ if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
+ strcat (buf, ", receive ");
+ if (flow_control &
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE)
+ strcat (buf, " & transmit ");
+ } else {
+ strcat (buf, ", transmit ");
+ }
+ strcat (buf, "flow control ON");
+ } else {
+ strcat (buf, ", flow control OFF");
+ }
+ strcat (buf, "\n");
+ printf ("%s", buf);
}
- strcat(buf,"\n");
- printf("%s",buf);
- }
#if 0
- sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]);
+ sysLedDsply (lcd[0], lcd[1], lcd[2], lcd[3]);
#endif
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- PUM_PACKET pUmPacket;
- void *skb;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PUM_PACKET pUmPacket;
+ void *skb;
- pUmPacket = (PUM_PACKET) pPacket;
+ pUmPacket = (PUM_PACKET) pPacket;
- if ((skb = pUmPacket->skbuff))
- bcm570xPktFree(pUmDevice->index, skb);
+ if ((skb = pUmPacket->skbuff))
+ bcm570xPktFree (pUmDevice->index, skb);
- pUmPacket->skbuff = 0;
+ pUmPacket->skbuff = 0;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-unsigned long
-MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
+unsigned long MM_AnGetCurrentTime_us (PAN_STATE_INFO pAnInfo)
{
- return get_timer(0);
+ return get_timer (0);
}
/*
* non-fatal. The incoming cluster chain is not freed, giving
* the caller the choice of whether to try a retransmit later.
*/
-LM_STATUS
-MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- void *skbnew;
- int len = 0;
-
- if (len == 0)
- return (LM_STATUS_SUCCESS);
-
- if (len > MAX_PACKET_SIZE){
- printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
- pUmDevice->index, len);
- return (LM_STATUS_FAILURE);
- }
+ PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ void *skbnew;
+ int len = 0;
+
+ if (len == 0)
+ return (LM_STATUS_SUCCESS);
+
+ if (len > MAX_PACKET_SIZE) {
+ printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
+ pUmDevice->index, len);
+ return (LM_STATUS_FAILURE);
+ }
- skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE);
+ skbnew = bcm570xPktAlloc (pUmDevice->index, MAX_PACKET_SIZE);
- if (skbnew == NULL) {
- pUmDevice->tx_full = 1;
- printf ("eth%d: out of transmit buffers", pUmDevice->index);
- return (LM_STATUS_FAILURE);
- }
+ if (skbnew == NULL) {
+ pUmDevice->tx_full = 1;
+ printf ("eth%d: out of transmit buffers", pUmDevice->index);
+ return (LM_STATUS_FAILURE);
+ }
- /* New packet values */
- pUmPacket->skbuff = skbnew;
- pUmPacket->lm_packet.u.Tx.FragCount = 1;
+ /* New packet values */
+ pUmPacket->skbuff = skbnew;
+ pUmPacket->lm_packet.u.Tx.FragCount = 1;
- return (LM_STATUS_SUCCESS);
+ return (LM_STATUS_SUCCESS);
}
-
-LM_STATUS
-MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- pUmDevice->rx_pkt = 1;
- return LM_STATUS_SUCCESS;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ pUmDevice->rx_pkt = 1;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- PLM_PACKET pPacket;
- PUM_PACKET pUmPacket;
- void *skb;
- while ( TRUE ) {
-
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->TxPacketXmittedQ.Container);
-
- if (pPacket == 0)
- break;
-
- pUmPacket = (PUM_PACKET) pPacket;
- skb = (void*)pUmPacket->skbuff;
-
- /*
- * Free MBLK if we transmitted a fragmented packet or a
- * non-fragmented packet straight from the VxWorks
- * buffer pool. If packet was copied to a local transmit
- * buffer, then there's no MBUF to free, just free
- * the transmit buffer back to the cluster pool.
- */
-
- if (skb)
- bcm570xPktFree (pUmDevice->index, skb);
-
- pUmPacket->skbuff = 0;
- QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
- pUmDevice->tx_pkt = 1;
- }
- if (pUmDevice->tx_full) {
- if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >=
- (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1))
- pUmDevice->tx_full = 0;
- }
- return LM_STATUS_SUCCESS;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PLM_PACKET pPacket;
+ PUM_PACKET pUmPacket;
+ void *skb;
+ while (TRUE) {
+
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->TxPacketXmittedQ.Container);
+
+ if (pPacket == 0)
+ break;
+
+ pUmPacket = (PUM_PACKET) pPacket;
+ skb = (void *)pUmPacket->skbuff;
+
+ /*
+ * Free MBLK if we transmitted a fragmented packet or a
+ * non-fragmented packet straight from the VxWorks
+ * buffer pool. If packet was copied to a local transmit
+ * buffer, then there's no MBUF to free, just free
+ * the transmit buffer back to the cluster pool.
+ */
+
+ if (skb)
+ bcm570xPktFree (pUmDevice->index, skb);
+
+ pUmPacket->skbuff = 0;
+ QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
+ pUmDevice->tx_pkt = 1;
+ }
+ if (pUmDevice->tx_full) {
+ if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) >=
+ (QQ_GetSize (&pDevice->TxPacketFreeQ.Container) >> 1))
+ pUmDevice->tx_full = 0;
+ }
+ return LM_STATUS_SUCCESS;
}
/*
* Return its length and physical address.
*/
void MM_MapTxDma
- (
- PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR *paddr,
- LM_UINT32 *len,
- int frag)
-{
- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
- *len = pPacket->PacketSize;
- MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
+ (PLM_DEVICE_BLOCK pDevice,
+ struct _LM_PACKET *pPacket,
+ T3_64BIT_HOST_ADDR * paddr, LM_UINT32 * len, int frag) {
+ PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+ *len = pPacket->PacketSize;
+ MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
}
/*
* to a physical address as seen from a PCI device. Store the
* result at paddr.
*/
-void MM_MapRxDma(
- PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR *paddr)
+void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
+ struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr)
{
- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
- MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
+ PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+ MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
}
-void
-MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr)
+void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr)
{
#if (BITS_PER_LONG == 64)
- paddr->High = ((unsigned long) addr) >> 32;
- paddr->Low = ((unsigned long) addr) & 0xffffffff;
+ paddr->High = ((unsigned long)addr) >> 32;
+ paddr->Low = ((unsigned long)addr) & 0xffffffff;
#else
paddr->High = 0;
- paddr->Low = (unsigned long) addr;
+ paddr->Low = (unsigned long)addr;
#endif
}
-void
-MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
+void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr)
{
- unsigned long baddr = (unsigned long) addr;
+ unsigned long baddr = (unsigned long)addr;
#if (BITS_PER_LONG == 64)
- set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32);
+ set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32);
#else
- set_64bit_addr(paddr, baddr, 0);
+ set_64bit_addr (paddr, baddr, 0);
#endif
}
* If any uses of the function remain, they will refer to the single copy
* in the library.
*/
-void
-atomic_set(atomic_t* entry, int val)
+void atomic_set (atomic_t * entry, int val)
{
- entry->counter = val;
+ entry->counter = val;
}
-int
-atomic_read(atomic_t* entry)
+
+int atomic_read (atomic_t * entry)
{
- return entry->counter;
+ return entry->counter;
}
-void
-atomic_inc(atomic_t* entry)
+
+void atomic_inc (atomic_t * entry)
{
- if(entry)
- entry->counter++;
+ if (entry)
+ entry->counter++;
}
-void
-atomic_dec(atomic_t* entry)
+void atomic_dec (atomic_t * entry)
{
- if(entry)
- entry->counter--;
+ if (entry)
+ entry->counter--;
}
-void
-atomic_sub(int a, atomic_t* entry)
+void atomic_sub (int a, atomic_t * entry)
{
- if(entry)
- entry->counter -= a;
+ if (entry)
+ entry->counter -= a;
}
-void
-atomic_add(int a, atomic_t* entry)
+void atomic_add (int a, atomic_t * entry)
{
- if(entry)
- entry->counter += a;
+ if (entry)
+ entry->counter += a;
}
/******************************************************************************/
/* */
/* Return: */
/******************************************************************************/
-void
-QQ_InitQueue(
-PQQ_CONTAINER pQueue,
-unsigned int QueueSize) {
- pQueue->Head = 0;
- pQueue->Tail = 0;
- pQueue->Size = QueueSize+1;
- atomic_set(&pQueue->EntryCnt, 0);
-} /* QQ_InitQueue */
-
+void QQ_InitQueue (PQQ_CONTAINER pQueue, unsigned int QueueSize)
+{
+ pQueue->Head = 0;
+ pQueue->Tail = 0;
+ pQueue->Size = QueueSize + 1;
+ atomic_set (&pQueue->EntryCnt, 0);
+} /* QQ_InitQueue */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-char
-QQ_Full(
-PQQ_CONTAINER pQueue) {
- unsigned int NewHead;
-
- NewHead = (pQueue->Head + 1) % pQueue->Size;
+char QQ_Full (PQQ_CONTAINER pQueue)
+{
+ unsigned int NewHead;
- return(NewHead == pQueue->Tail);
-} /* QQ_Full */
+ NewHead = (pQueue->Head + 1) % pQueue->Size;
+ return (NewHead == pQueue->Tail);
+} /* QQ_Full */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-char
-QQ_Empty(
-PQQ_CONTAINER pQueue) {
- return(pQueue->Head == pQueue->Tail);
-} /* QQ_Empty */
-
+char QQ_Empty (PQQ_CONTAINER pQueue)
+{
+ return (pQueue->Head == pQueue->Tail);
+} /* QQ_Empty */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-unsigned int
-QQ_GetSize(
-PQQ_CONTAINER pQueue) {
- return pQueue->Size;
-} /* QQ_GetSize */
-
+unsigned int QQ_GetSize (PQQ_CONTAINER pQueue)
+{
+ return pQueue->Size;
+} /* QQ_GetSize */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-unsigned int
-QQ_GetEntryCnt(
-PQQ_CONTAINER pQueue) {
- return atomic_read(&pQueue->EntryCnt);
-} /* QQ_GetEntryCnt */
-
+unsigned int QQ_GetEntryCnt (PQQ_CONTAINER pQueue)
+{
+ return atomic_read (&pQueue->EntryCnt);
+} /* QQ_GetEntryCnt */
/******************************************************************************/
/* Description: */
/* TRUE entry was added successfully. */
/* FALSE queue is full. */
/******************************************************************************/
-char
-QQ_PushHead(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
- unsigned int Head;
+char QQ_PushHead (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
+{
+ unsigned int Head;
- Head = (pQueue->Head + 1) % pQueue->Size;
+ Head = (pQueue->Head + 1) % pQueue->Size;
#if !defined(QQ_NO_OVERFLOW_CHECK)
- if(Head == pQueue->Tail) {
- return 0;
- } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
+ if (Head == pQueue->Tail) {
+ return 0;
+ } /* if */
+#endif /* QQ_NO_OVERFLOW_CHECK */
- pQueue->Array[pQueue->Head] = pEntry;
- wmb();
- pQueue->Head = Head;
- atomic_inc(&pQueue->EntryCnt);
-
- return -1;
-} /* QQ_PushHead */
+ pQueue->Array[pQueue->Head] = pEntry;
+ wmb ();
+ pQueue->Head = Head;
+ atomic_inc (&pQueue->EntryCnt);
+ return -1;
+} /* QQ_PushHead */
/******************************************************************************/
/* Description: */
/* TRUE entry was added successfully. */
/* FALSE queue is full. */
/******************************************************************************/
-char
-QQ_PushTail(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
- unsigned int Tail;
-
- Tail = pQueue->Tail;
- if(Tail == 0) {
- Tail = pQueue->Size;
- } /* if */
- Tail--;
+char QQ_PushTail (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
+{
+ unsigned int Tail;
-#if !defined(QQ_NO_OVERFLOW_CHECK)
- if(Tail == pQueue->Head) {
- return 0;
- } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
+ Tail = pQueue->Tail;
+ if (Tail == 0) {
+ Tail = pQueue->Size;
+ } /* if */
+ Tail--;
- pQueue->Array[Tail] = pEntry;
- wmb();
- pQueue->Tail = Tail;
- atomic_inc(&pQueue->EntryCnt);
+#if !defined(QQ_NO_OVERFLOW_CHECK)
+ if (Tail == pQueue->Head) {
+ return 0;
+ } /* if */
+#endif /* QQ_NO_OVERFLOW_CHECK */
- return -1;
-} /* QQ_PushTail */
+ pQueue->Array[Tail] = pEntry;
+ wmb ();
+ pQueue->Tail = Tail;
+ atomic_inc (&pQueue->EntryCnt);
+ return -1;
+} /* QQ_PushTail */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_PopHead(
-PQQ_CONTAINER pQueue) {
- unsigned int Head;
- PQQ_ENTRY Entry;
+PQQ_ENTRY QQ_PopHead (PQQ_CONTAINER pQueue)
+{
+ unsigned int Head;
+ PQQ_ENTRY Entry;
- Head = pQueue->Head;
+ Head = pQueue->Head;
#if !defined(QQ_NO_UNDERFLOW_CHECK)
- if(Head == pQueue->Tail) {
- return (PQQ_ENTRY) 0;
- } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
- if(Head == 0) {
- Head = pQueue->Size;
- } /* if */
- Head--;
+ if (Head == pQueue->Tail) {
+ return (PQQ_ENTRY) 0;
+ } /* if */
+#endif /* QQ_NO_UNDERFLOW_CHECK */
- Entry = pQueue->Array[Head];
- membar();
+ if (Head == 0) {
+ Head = pQueue->Size;
+ } /* if */
+ Head--;
- pQueue->Head = Head;
- atomic_dec(&pQueue->EntryCnt);
+ Entry = pQueue->Array[Head];
+ membar ();
- return Entry;
-} /* QQ_PopHead */
+ pQueue->Head = Head;
+ atomic_dec (&pQueue->EntryCnt);
+ return Entry;
+} /* QQ_PopHead */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_PopTail(
-PQQ_CONTAINER pQueue) {
- unsigned int Tail;
- PQQ_ENTRY Entry;
+PQQ_ENTRY QQ_PopTail (PQQ_CONTAINER pQueue)
+{
+ unsigned int Tail;
+ PQQ_ENTRY Entry;
- Tail = pQueue->Tail;
+ Tail = pQueue->Tail;
#if !defined(QQ_NO_UNDERFLOW_CHECK)
- if(Tail == pQueue->Head) {
- return (PQQ_ENTRY) 0;
- } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
- Entry = pQueue->Array[Tail];
- membar();
- pQueue->Tail = (Tail + 1) % pQueue->Size;
- atomic_dec(&pQueue->EntryCnt);
+ if (Tail == pQueue->Head) {
+ return (PQQ_ENTRY) 0;
+ } /* if */
+#endif /* QQ_NO_UNDERFLOW_CHECK */
- return Entry;
-} /* QQ_PopTail */
+ Entry = pQueue->Array[Tail];
+ membar ();
+ pQueue->Tail = (Tail + 1) % pQueue->Size;
+ atomic_dec (&pQueue->EntryCnt);
+ return Entry;
+} /* QQ_PopTail */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_GetHead(
- PQQ_CONTAINER pQueue,
- unsigned int Idx)
+PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQueue, unsigned int Idx)
{
- if(Idx >= atomic_read(&pQueue->EntryCnt))
- {
- return (PQQ_ENTRY) 0;
- }
-
- if(pQueue->Head > Idx)
- {
- Idx = pQueue->Head - Idx;
- }
- else
- {
- Idx = pQueue->Size - (Idx - pQueue->Head);
- }
- Idx--;
-
- return pQueue->Array[Idx];
-}
+ if (Idx >= atomic_read (&pQueue->EntryCnt)) {
+ return (PQQ_ENTRY) 0;
+ }
+
+ if (pQueue->Head > Idx) {
+ Idx = pQueue->Head - Idx;
+ } else {
+ Idx = pQueue->Size - (Idx - pQueue->Head);
+ }
+ Idx--;
+ return pQueue->Array[Idx];
+}
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_GetTail(
- PQQ_CONTAINER pQueue,
- unsigned int Idx)
+PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx)
{
- if(Idx >= atomic_read(&pQueue->EntryCnt))
- {
- return (PQQ_ENTRY) 0;
- }
-
- Idx += pQueue->Tail;
- if(Idx >= pQueue->Size)
- {
- Idx = Idx - pQueue->Size;
- }
-
- return pQueue->Array[Idx];
+ if (Idx >= atomic_read (&pQueue->EntryCnt)) {
+ return (PQQ_ENTRY) 0;
+ }
+
+ Idx += pQueue->Tail;
+ if (Idx >= pQueue->Size) {
+ Idx = Idx - pQueue->Size;
+ }
+
+ return pQueue->Array[Idx];
}
#endif
#include "bcm570x_queue.h"
#include "bcm570x_bits.h"
-
/******************************************************************************/
/* Basic types. */
/******************************************************************************/
-typedef char LM_CHAR, *PLM_CHAR;
-typedef unsigned int LM_UINT, *PLM_UINT;
-typedef unsigned char LM_UINT8, *PLM_UINT8;
-typedef unsigned short LM_UINT16, *PLM_UINT16;
-typedef unsigned int LM_UINT32, *PLM_UINT32;
-typedef unsigned int LM_COUNTER, *PLM_COUNTER;
-typedef void LM_VOID, *PLM_VOID;
-typedef char LM_BOOL, *PLM_BOOL;
+typedef char LM_CHAR, *PLM_CHAR;
+typedef unsigned int LM_UINT, *PLM_UINT;
+typedef unsigned char LM_UINT8, *PLM_UINT8;
+typedef unsigned short LM_UINT16, *PLM_UINT16;
+typedef unsigned int LM_UINT32, *PLM_UINT32;
+typedef unsigned int LM_COUNTER, *PLM_COUNTER;
+typedef void LM_VOID, *PLM_VOID;
+typedef char LM_BOOL, *PLM_BOOL;
/* 64bit value. */
typedef struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT32 High;
- LM_UINT32 Low;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT32 Low;
- LM_UINT32 High;
-#endif /* !BIG_ENDIAN_HOST */
+ LM_UINT32 High;
+ LM_UINT32 Low;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT32 Low;
+ LM_UINT32 High;
+#endif /* !BIG_ENDIAN_HOST */
} LM_UINT64, *PLM_UINT64;
typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
} \
}
-
#ifndef NULL
#define NULL ((void *) 0)
-#endif /* NULL */
+#endif /* NULL */
#ifndef OFFSETOF
#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m)))
-#endif /* OFFSETOF */
-
+#endif /* OFFSETOF */
/******************************************************************************/
/* Simple macros. */
((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \
((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
-
/******************************************************************************/
/* Constants. */
/******************************************************************************/
#define ETHERNET_ADDRESS_SIZE 6
#define ETHERNET_PACKET_HEADER_SIZE 14
-#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */
-#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */
+#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */
+#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */
#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60
#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514
-#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */
+#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */
#ifndef LM_MAX_MC_TABLE_SIZE
#define LM_MAX_MC_TABLE_SIZE 32
-#endif /* LM_MAX_MC_TABLE_SIZE */
+#endif /* LM_MAX_MC_TABLE_SIZE */
#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1)
#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1)
-
/* Receive filter masks. */
#define LM_ACCEPT_UNICAST 0x0001
#define LM_ACCEPT_MULTICAST 0x0002
#define LM_PROMISCUOUS_MODE 0x10000
-
/******************************************************************************/
/* PCI registers. */
/******************************************************************************/
/******************************************************************************/
typedef struct {
- LM_UINT32 FragSize;
- LM_PHYSICAL_ADDRESS FragBuf;
+ LM_UINT32 FragSize;
+ LM_PHYSICAL_ADDRESS FragBuf;
} LM_FRAG, *PLM_FRAG;
typedef struct {
- /* FragCount is initialized for the caller to the maximum array size, on */
- /* return FragCount is the number of the actual fragments in the array. */
- LM_UINT32 FragCount;
+ /* FragCount is initialized for the caller to the maximum array size, on */
+ /* return FragCount is the number of the actual fragments in the array. */
+ LM_UINT32 FragCount;
- /* Total buffer size. */
- LM_UINT32 TotalSize;
+ /* Total buffer size. */
+ LM_UINT32 TotalSize;
- /* Fragment array buffer. */
- LM_FRAG Fragments[1];
+ /* Fragment array buffer. */
+ LM_FRAG Fragments[1];
} LM_FRAG_LIST, *PLM_FRAG_LIST;
#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \
LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \
} _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
-
/******************************************************************************/
/* Status codes. */
/******************************************************************************/
typedef LM_UINT LM_STATUS, *PLM_STATUS;
-
/******************************************************************************/
/* Requested media type. */
/******************************************************************************/
typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
-
/******************************************************************************/
/* Media type. */
/******************************************************************************/
typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
-
/******************************************************************************/
/* Line speed. */
/******************************************************************************/
typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
-
/******************************************************************************/
/* Duplex mode. */
/******************************************************************************/
typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
-
/******************************************************************************/
/* Power state. */
/******************************************************************************/
typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
-
/******************************************************************************/
/* Task offloading. */
/******************************************************************************/
typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
-
/******************************************************************************/
/* Flow control. */
/******************************************************************************/
typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
-
/******************************************************************************/
/* Wake up mode. */
/******************************************************************************/
typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
-
/******************************************************************************/
/* Counters. */
/******************************************************************************/
typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
-
/******************************************************************************/
/* Forward definition. */
/******************************************************************************/
typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
typedef struct _LM_PACKET *PLM_PACKET;
-
/******************************************************************************/
/* Function prototypes. */
/******************************************************************************/
-LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
-LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
-LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
-
-LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice);
-
-LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
- LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
-LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
- LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
-LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel);
-
-LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
- PLM_UINT32 pData32);
-LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
- LM_UINT32 Data32);
-
-LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
-LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice);
-int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
-
+LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
+LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
+LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
+LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
+LM_STATUS LM_LoopbackAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
+
+LM_UINT32 LM_GetCrcCounter (PLM_DEVICE_BLOCK pDevice);
+
+LM_WAKE_UP_MODE LM_PMCapabilities (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_NwufAdd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
+ LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
+LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
+ LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice,
+ LM_POWER_STATE PowerLevel);
+
+LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
+ PLM_UINT32 pData32);
+LM_VOID LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
+ LM_UINT32 Data32);
+
+LM_STATUS LM_ControlLoopBack (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
+LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice);
+int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
/******************************************************************************/
/* These are the OS specific functions called by LMAC. */
/******************************************************************************/
-LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT16 *pValue16);
-LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT16 Value16);
-LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT32 *pValue32);
-LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT32 Value32);
-LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt);
-LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
- LM_BOOL Cached);
-LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
-LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
+LM_STATUS MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT16 * pValue16);
+LM_STATUS MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT16 Value16);
+LM_STATUS MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT32 * pValue32);
+LM_STATUS MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT32 Value32);
+LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_MapIoBase (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt);
+LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt,
+ PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
+ LM_BOOL Cached);
+LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
+LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS LM_MbufWorkAround (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetLinkSpeed (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
#if INCLUDE_5703_A0_FIX
-LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice);
#endif
-
-#endif /* LM_H */
+#endif /* LM_H */
#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size
-DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1);
+DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1);
#define MAX_MEM 16
int mtu;
int index;
int opened;
- int delayed_link_ind; /* Delay link status during initial load */
- int adapter_just_inited; /* the first few seconds after init. */
- int spurious_int; /* new -- unsupported */
+ int delayed_link_ind; /* Delay link status during initial load */
+ int adapter_just_inited; /* the first few seconds after init. */
+ int spurious_int; /* new -- unsupported */
int timer_interval;
int adaptive_expiry;
- int crc_counter_expiry; /* new -- unsupported */
- int poll_tib_expiry; /* new -- unsupported */
+ int crc_counter_expiry; /* new -- unsupported */
+ int poll_tib_expiry; /* new -- unsupported */
int tx_full;
int tx_queued;
int line_speed; /* in Mbps, 0 if link is down */
UM_RX_PACKET_Q rx_out_of_buf_q;
int rx_out_of_buf;
- int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */
+ int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */
int rx_buf_repl_panic_thresh;
- int rx_buf_align; /* new -- unsupported */
+ int rx_buf_align; /* new -- unsupported */
int do_global_lock;
mutex_t global_lock;
mutex_t undi_lock;
long undi_flags;
volatile int interrupt;
int tasklet_pending;
- int tasklet_busy; /* new -- unsupported */
+ int tasklet_busy; /* new -- unsupported */
int rx_pkt;
int tx_pkt;
-#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */
- void (*nice_rx)(void*, void* );
- void* nice_ctx;
-#endif /* NICE_SUPPORT */
+#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */
+ void (*nice_rx) (void *, void *);
+ void *nice_ctx;
+#endif /* NICE_SUPPORT */
int rx_adaptive_coalesce;
unsigned int rx_last_cnt;
unsigned int tx_last_cnt;
unsigned int rx_curr_coalesce_frames;
unsigned int rx_curr_coalesce_ticks;
- unsigned int tx_curr_coalesce_frames; /* new -- unsupported */
-#if TIGON3_DEBUG /* new -- unsupported */
+ unsigned int tx_curr_coalesce_frames; /* new -- unsupported */
+#if TIGON3_DEBUG /* new -- unsupported */
uint tx_zc_count;
uint tx_chksum_count;
uint tx_himem_count;
uint rx_good_chksum_count;
#endif
- unsigned int rx_bad_chksum_count; /* new -- unsupported */
- unsigned int rx_misc_errors; /* new -- unsupported */
+ unsigned int rx_bad_chksum_count; /* new -- unsupported */
+ unsigned int rx_misc_errors; /* new -- unsupported */
} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
-
/* Physical/PCI DMA address */
typedef union {
dma_addr_t dma_map;
/* Packet */
typedef struct
-_UM_PACKET {
- LM_PACKET lm_packet;
- void* skbuff; /* Address of packet buffer */
+ _UM_PACKET {
+ LM_PACKET lm_packet;
+ void *skbuff; /* Address of packet buffer */
} UM_PACKET, *PUM_PACKET;
#define MM_ACQUIRE_UNDI_LOCK(_pDevice)
#define MEM_TO_PCI_PHYS(addr) (addr)
-extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr);
-extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr);
+extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr);
+extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr);
extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr,
- LM_UINT32 *len, int frag);
-extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR *paddr);
-
+ struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr,
+ LM_UINT32 * len, int frag);
+extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
+ struct _LM_PACKET *pPacket,
+ T3_64BIT_HOST_ADDR * paddr);
/* BSP needs to provide sysUsecDelay and sysSerialPrintString */
extern void sysSerialPrintString (char *s);
#if 0
#define cpu_to_le32(val) LONGSWAP(val)
#endif
-#endif /* MM_H */
+#endif /* MM_H */
LIB := $(obj)libatibiosemu.a
-X86DIR = ./x86emu
+X86DIR = x86emu
-OBJS = atibios.o biosemu.o besys.o bios.o \
+$(shell mkdir -p $(obj)$(X86DIR))
+
+COBJS = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/decode.o \
$(X86DIR)/ops2.o \
$(X86DIR)/ops.o \
$(X86DIR)/sys.o \
$(X86DIR)/debug.o
-CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
-D__PPC__ -D__BIG_ENDIAN__
+CFLAGS += $(EXTRA_CFLAGS)
+HOST_CFLAGS += $(EXTRA_CFLAGS)
+
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
*
****************************************************************************/
-#include "biosemui.h"
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+
+#include "biosemui.h"
+
/*------------------------- Global Variables ------------------------------*/
#ifndef __i386__
*
****************************************************************************/
-#include "biosemui.h"
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+
+#include "biosemui.h"
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
*
****************************************************************************/
-#include "biosemui.h"
#include <malloc.h>
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+#include "biosemui.h"
+
BE_sysEnv _BE_env = {{0}};
static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = {
BE_rdb,
*
****************************************************************************/
-#include "x86emu/x86emui.h"
#include <stdarg.h>
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+#include "x86emu/x86emui.h"
+
/*----------------------------- Implementation ----------------------------*/
#ifdef DEBUG
* instruction decoding and accessess of immediate data via IP. etc.
*
****************************************************************************/
-
-#include "x86emu/x86emui.h"
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+#include "x86emu/x86emui.h"
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
*
****************************************************************************/
-#include "x86emu/x86emui.h"
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+#include "x86emu/x86emui.h"
+
/*----------------------------- Implementation ----------------------------*/
/* constant arrays to do several instructions in just one function */
*
****************************************************************************/
-#include "x86emu/x86emui.h"
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+#include "x86emu/x86emui.h"
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
*
****************************************************************************/
+#include <common.h>
+
#define PRIM_OPS_NO_REDEFINE_ASM
-#include "x86emu/x86emui.h"
#if defined(CONFIG_BIOSEMU)
+#include "x86emu/x86emui.h"
+
/*------------------------- Global Variables ------------------------------*/
static u32 x86emu_parity_tab[8] =
*
****************************************************************************/
-#include "x86emu/x86emui.h"
+#include <common.h>
#if defined(CONFIG_BIOSEMU)
+#include "x86emu/x86emui.h"
+
/*------------------------- Global Variables ------------------------------*/
X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
static AT91S_DataFlash DataFlashInst;
+#ifdef CONFIG_AT91SAM9260EK
+int cs[][CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+#elif defined(CONFIG_AT91SAM9263EK)
+int cs[][CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */
+};
+#else
int cs[][CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
+#endif
/*define the area offsets*/
+#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AT91SAM9263EK)
+#if defined(CONFIG_NEW_PARTITION)
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment */
+ {0x00008400, 0x0003DDFF, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */
+ {0x0003DE00, 0x00041FFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "MON"}, /* Room for alternative boot monitor */
+ {0x00042000, 0x0018BFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */
+ {0x0018C000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0, 0x3fff, FLAG_PROTECT_SET}, /* ROM code */
+ {0x4000, 0x7fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */
+ {0x8000, 0x37fff, FLAG_PROTECT_SET}, /* u-boot code */
+ {0x38000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */
+};
+#endif
+#elif defined(CONFIG_NEW_PARTITION)
+/*define the area offsets*/
+/* Invalid partitions should be defined with start > end */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = {
+ {0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */
+ {0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */
+ {0x00021000, 0x000293ff, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment 8Kb */
+ {0x00029400, 0x00041fff, FLAG_PROTECT_INVALID, 0, "<Unused>"}, /* Rest of Sector 1 */
+ {0x00042000, 0x0018Bfff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */
+ {0x0018C000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */
+
+ {0x00000000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "Data"}, /* data area */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+};
+#else
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */
{0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */
{0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */
{0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */
};
+#endif
extern void AT91F_SpiInit (void);
extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc);
unsigned long addr,
unsigned long size, char *buffer);
extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size );
+ unsigned char *src,
+ int dest,
+ int size );
int AT91F_DataflashInit (void)
{
int i, j;
int dfcode;
+ int part = 0;
+ int last_part;
+ int found[CFG_MAX_DATAFLASH_BANKS];
+ unsigned char protected;
AT91F_SpiInit ();
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
+ found[i] = 0;
dataflash_info[i].Desc.state = IDLE;
dataflash_info[i].id = 0;
dataflash_info[i].Device.pages_number = 0;
- dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc);
+ dfcode = AT91F_DataflashProbe (cs[i][1],
+ &dataflash_info[i].Desc);
switch (dfcode) {
case AT45DB161:
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
case AT45DB321:
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
case AT45DB642:
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
+
case AT45DB128:
dataflash_info[i].Device.pages_number = 16384;
dataflash_info[i].Device.pages_size = 1056;
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
default:
+ dfcode = 0;
break;
}
/* set the last area end to the dataflash size*/
(dataflash_info[i].Device.pages_number *
dataflash_info[i].Device.pages_size)-1;
+ last_part=0;
/* set the area addresses */
for(j = 0; j<NB_DATAFLASH_AREA; j++) {
- dataflash_info[i].Device.area_list[j].start = area_list[j].start + dataflash_info[i].logical_address;
- dataflash_info[i].Device.area_list[j].end = area_list[j].end + dataflash_info[i].logical_address;
- dataflash_info[i].Device.area_list[j].protected = area_list[j].protected;
+ if(found[i]!=0) {
+ dataflash_info[i].Device.area_list[j].start =
+ area_list[part].start +
+ dataflash_info[i].logical_address;
+ if(area_list[part].end == 0xffffffff) {
+ dataflash_info[i].Device.area_list[j].end =
+ dataflash_info[i].end_address +
+ dataflash_info [i].logical_address;
+ last_part = 1;
+ } else {
+ dataflash_info[i].Device.area_list[j].end =
+ area_list[part].end +
+ dataflash_info[i].logical_address;
+ }
+ protected = area_list[part].protected;
+ /* Set the environment according to the label...*/
+ if(protected == FLAG_PROTECT_INVALID) {
+ dataflash_info[i].Device.area_list[j].protected =
+ FLAG_PROTECT_INVALID;
+ } else {
+ dataflash_info[i].Device.area_list[j].protected =
+ protected;
+ }
+ strcpy((char*)(dataflash_info[i].Device.area_list[j].label),
+ (const char *)area_list[part].label);
+ }
+ part++;
}
}
- return (1);
+ return found[0];
}
+#ifdef CONFIG_NEW_DF_PARTITION
+int AT91F_DataflashSetEnv (void)
+{
+ int i, j;
+ int part;
+ unsigned char env;
+ unsigned char s[32]; /* Will fit a long int in hex */
+ unsigned long start;
+ for (i = 0, part= 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
+ for(j = 0; j<NB_DATAFLASH_AREA; j++) {
+ env = area_list[part].setenv;
+ /* Set the environment according to the label...*/
+ if((env & FLAG_SETENV) == FLAG_SETENV) {
+ start =
+ dataflash_info[i].Device.area_list[j].start;
+ sprintf(s,"%X",start);
+ setenv(area_list[part].label,s);
+ }
+ part++;
+ }
+ }
+}
+#endif
void dataflash_print_info (void)
{
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
if (dataflash_info[i].id != 0) {
- printf ("DataFlash:");
+ printf("DataFlash:");
switch (dataflash_info[i].id) {
case AT45DB161:
- printf ("AT45DB161\n");
+ printf("AT45DB161\n");
break;
case AT45DB321:
- printf ("AT45DB321\n");
+ printf("AT45DB321\n");
break;
case AT45DB642:
- printf ("AT45DB642\n");
+ printf("AT45DB642\n");
break;
case AT45DB128:
- printf ("AT45DB128\n");
+ printf("AT45DB128\n");
break;
}
- printf ("Nb pages: %6d\n"
+ printf("Nb pages: %6d\n"
"Page Size: %6d\n"
"Size=%8d bytes\n"
"Logical address: 0x%08X\n",
dataflash_info[i].Device.pages_size,
(unsigned int) dataflash_info[i].logical_address);
for (j=0; j< NB_DATAFLASH_AREA; j++) {
- printf ("Area %i:\t%08lX to %08lX %s\n", j,
- dataflash_info[i].Device.area_list[j].start,
- dataflash_info[i].Device.area_list[j].end,
- (dataflash_info[i].Device.area_list[j].protected ==
- FLAG_PROTECT_SET) ? "(RO)" : "");
+ switch(dataflash_info[i].Device.area_list[j].protected) {
+ case FLAG_PROTECT_SET:
+ case FLAG_PROTECT_CLEAR:
+ printf("Area %i:\t%08lX to %08lX %s", j,
+ dataflash_info[i].Device.area_list[j].start,
+ dataflash_info[i].Device.area_list[j].end,
+ (dataflash_info[i].Device.area_list[j].protected==FLAG_PROTECT_SET) ? "(RO)" : " ");
+#ifdef CONFIG_NEW_DF_PARTITION
+ printf(" %s\n", dataflash_info[i].Device.area_list[j].label);
+#else
+ printf("\n");
+#endif
+ break;
+#ifdef CONFIG_NEW_DF_PARTITION
+ case FLAG_PROTECT_INVALID:
+ break;
+#endif
+ }
}
}
}
}
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataflashSelect */
-/* Object : Select the correct device */
-/*------------------------------------------------------------------------------*/
-AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, unsigned long *addr)
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataflashSelect */
+/* Object : Select the correct device */
+/*---------------------------------------------------------------------------*/
+AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash,
+ unsigned long *addr)
{
char addr_valid = 0;
int i;
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++)
- if ((*addr & 0xFF000000) == dataflash_info[i].logical_address) {
+ if ( dataflash_info[i].id
+ && ((((int) addr) & 0xFF000000) ==
+ dataflash_info[i].logical_address)) {
addr_valid = 1;
break;
}
return (pFlash);
}
-/*------------------------------------------------------------------------------*/
-/* Function Name : addr_dataflash */
-/* Object : Test if address is valid */
-/*------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : addr_dataflash */
+/* Object : Test if address is valid */
+/*---------------------------------------------------------------------------*/
int addr_dataflash (unsigned long addr)
{
int addr_valid = 0;
return addr_valid;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : size_dataflash */
-/* Object : Test if address is valid regarding the size */
-/*-----------------------------------------------------------------------------*/
-int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size)
+/*---------------------------------------------------------------------------*/
+/* Function Name : size_dataflash */
+/* Object : Test if address is valid regarding the size */
+/*---------------------------------------------------------------------------*/
+int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr,
+ unsigned long size)
{
/* is outside the dataflash */
if (((int)addr & 0x0FFFFFFF) > (pdataFlash->pDevice->pages_size *
pdataFlash->pDevice->pages_number)) return 0;
/* is too large for the dataflash */
if (size > ((pdataFlash->pDevice->pages_size *
- pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0;
+ pdataFlash->pDevice->pages_number) -
+ ((int)addr & 0x0FFFFFFF))) return 0;
return 1;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : prot_dataflash */
-/* Object : Test if destination area is protected */
-/*-----------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : prot_dataflash */
+/* Object : Test if destination area is protected */
+/*---------------------------------------------------------------------------*/
int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr)
{
int area;
(addr < pdataFlash->pDevice->area_list[area].end))
break;
}
- if (area == NB_DATAFLASH_AREA) return -1;
+ if (area == NB_DATAFLASH_AREA)
+ return -1;
+
/*test protection value*/
- if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0;
+ if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET)
+ return 0;
+ if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID)
+ return 0;
return 1;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : dataflash_real_protect */
-/* Object : protect/unprotect area */
-/*-----------------------------------------------------------------------------*/
-int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr)
+/*--------------------------------------------------------------------------*/
+/* Function Name : dataflash_real_protect */
+/* Object : protect/unprotect area */
+/*--------------------------------------------------------------------------*/
+int dataflash_real_protect (int flag, unsigned long start_addr,
+ unsigned long end_addr)
{
int i,j, area1, area2, addr_valid = 0;
/* find dataflash */
}
/* find start area */
for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) {
- if (start_addr == dataflash_info[i].Device.area_list[area1].start) break;
+ if (start_addr == dataflash_info[i].Device.area_list[area1].start)
+ break;
}
if (area1 == NB_DATAFLASH_AREA) return -1;
/* find end area */
for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) {
- if (end_addr == dataflash_info[i].Device.area_list[area2].end) break;
+ if (end_addr == dataflash_info[i].Device.area_list[area2].end)
+ break;
}
- if (area2 == NB_DATAFLASH_AREA) return -1;
+ if (area2 == NB_DATAFLASH_AREA)
+ return -1;
/*set protection value*/
for(j = area1; j < area2+1 ; j++)
- if (flag == 0) dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR;
- else dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET;
+ if(dataflash_info[i].Device.area_list[j].protected
+ != FLAG_PROTECT_INVALID) {
+ if (flag == 0) {
+ dataflash_info[i].Device.area_list[j].protected
+ = FLAG_PROTECT_CLEAR;
+ } else {
+ dataflash_info[i].Device.area_list[j].protected
+ = FLAG_PROTECT_SET;
+ }
+ }
return (area2-area1+1);
}
-/*------------------------------------------------------------------------------*/
-/* Function Name : read_dataflash */
-/* Object : dataflash memory read */
-/*------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : read_dataflash */
+/* Object : dataflash memory read */
+/*---------------------------------------------------------------------------*/
int read_dataflash (unsigned long addr, unsigned long size, char *result)
{
unsigned long AddrToRead = addr;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : write_dataflash */
-/* Object : write a block in dataflash */
-/*-----------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : write_dataflash */
+/* Object : write a block in dataflash */
+/*---------------------------------------------------------------------------*/
int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
- unsigned long size)
+ unsigned long size)
{
unsigned long AddrToWrite = addr_dest;
AT91PS_DataFlash pFlash = &DataFlashInst;
if (AddrToWrite == -1)
return -1;
- return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size);
+ return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src,
+ AddrToWrite, size);
}
case ERR_OK:
break;
case ERR_TIMOUT:
- printf ("Timeout writing to DataFlash\n");
+ printf("Timeout writing to DataFlash\n");
break;
case ERR_PROTECTED:
- printf ("Can't write to protected DataFlash sectors\n");
+ printf("Can't write to protected/invalid DataFlash sectors\n");
break;
case ERR_INVAL:
- printf ("Outside available DataFlash\n");
+ printf("Outside available DataFlash\n");
break;
case ERR_UNKNOWN_FLASH_TYPE:
- printf ("Unknown Type of DataFlash\n");
+ printf("Unknown Type of DataFlash\n");
break;
case ERR_PROG_ERROR:
- printf ("General DataFlash Programming Error\n");
+ printf("General DataFlash Programming Error\n");
break;
default:
- printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
+ printf("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
break;
}
}
static int dm9000_probe(void);
static u16 phy_read(int);
static void phy_write(int, u16);
-static u16 read_srom_word(int);
+u16 read_srom_word(int);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);
/* Set Node address */
for (i = 0; i < 6; i++)
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
+
+ if (is_zero_ether_addr(bd->bi_enetaddr) ||
+ is_multicast_ether_addr(bd->bi_enetaddr)) {
+ /* try reading from environment */
+ u8 i;
+ char *s, *e;
+ s = getenv ("ethaddr");
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enetaddr[i] = s ?
+ simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+ }
+
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
/*
Read a word data from SROM
*/
-static u16
+u16
read_srom_word(int offset)
{
DM9000_iow(DM9000_EPAR, offset);
DM9000_iow(DM9000_EPCR, 0x4);
- udelay(200);
+ udelay(8000);
DM9000_iow(DM9000_EPCR, 0x0);
return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
}
+void
+write_srom_word(int offset, u16 val)
+{
+ DM9000_iow(DM9000_EPAR, offset);
+ DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
+ DM9000_iow(DM9000_EPDRL, (val & 0xff));
+ DM9000_iow(DM9000_EPCR, 0x12);
+ udelay(8000);
+ DM9000_iow(DM9000_EPCR, 0);
+}
+
+
/*
Read a byte from I/O port
*/
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#define DEBUG
+
#include <common.h>
#ifdef CONFIG_FSL_PCI_INIT
hose->current_busno = hose->first_busno;
pci->pedr = 0xffffffff; /* Clear any errors */
- pci->peer = 0xffffffff; /* Enable Error Interupts */
+ pci->peer = ~0x20140; /* Enable All Error Interupts except
+ * - Master abort (pci)
+ * - Master PERR (pci)
+ * - ICCA (PCIe)
+ */
pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
if (!enabled) {
debug("....PCIE link error. Skipping scan."
- "LTSSM=0x%02x\n", temp16);
+ "LTSSM=0x%02x\n", ltssm);
hose->last_busno = hose->first_busno;
return;
}
#ifdef DEBUG
pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
neg_link_w = (temp16 & 0x3f0 ) >> 4;
- debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
+ printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
ltssm, neg_link_w);
#endif
hose->current_busno++; /* Start scan with secondary */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- } else {
-#if 0
-/* done in pci_hose_config_device() */
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
- temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16);
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-#endif
}
- /* Call setup to allocate PCSRBAR window */
- pciauto_setup_device(hose, dev, 1, hose->pci_mem,
+ /* Use generic setup_device to initialize standard pci regs,
+ * but do not allocate any windows since any BAR found (such
+ * as PCSRBAR) is not in this cpu's memory space.
+ */
+
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
+#ifndef CONFIG_PCI_NOSCAN
printf (" Scanning PCI bus %02x\n", hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
if ( bridge ) { /* update limit regs and subordinate busno */
pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
}
+#else
+ hose->last_busno = hose->current_busno;
+#endif
/* Clear all error indications */
- if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) {
- debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n",
- &pci->pme_msg_det, pci->pme_msg_det);
- pci->pme_msg_det = 0xffffffff;
- }
-
- if (pci->pedr) {
- debug("pci_fsl_init: pedr@%x=%x. Clearing\n",
- &pci->pedr, pci->pedr);
- pci->pedr = 0xffffffff;
- }
+ pci->pme_msg_det = 0xffffffff;
+ pci->pedr = 0xffffffff;
pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
if (temp16) {
- debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n",
- PCI_DSR, temp16);
pci_hose_write_config_word(hose, dev,
- PCI_DSR, 0xffff);
+ PCI_DSR, 0xffff);
}
pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
if (temp16) {
- debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n",
- PCI_SEC_STATUS, temp16);
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
{NAND_MFR_NATIONAL, "National"},
{NAND_MFR_RENESAS, "Renesas"},
{NAND_MFR_STMICRO, "ST Micro"},
+ {NAND_MFR_MICRON, "Micron"},
{0x0, "Unknown"}
};
#endif
}
if (!opts->quiet) {
- unsigned long long n =(unsigned long long)
- (erase.addr+meminfo->erasesize-opts->offset)
- * 100;
- int percent = (int)do_div(n, erase_length);
+ unsigned long long n =(unsigned long long)
+ (erase.addr + meminfo->erasesize - opts->offset)
+ * 100;
+ int percent;
+
+ do_div(n, erase_length);
+ percent = (int)n;
/* output progress message only at whole percent
* steps to reduce the number of messages printed
imglen -= readlen;
if (!opts->quiet) {
- unsigned long long n = (unsigned long long)
- (opts->length-imglen) * 100;
- int percent = (int)do_div(n, opts->length);
+ unsigned long long n = (unsigned long long)
+ (opts->length-imglen) * 100;
+ int percent;
+
+ do_div(n, opts->length);
+ percent = (int)n;
+
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
}
if (!opts->quiet) {
- unsigned long long n = (unsigned long long)
- (opts->length-imglen) * 100;
- int percent = (int)do_div(n ,opts->length);
+ unsigned long long n = (unsigned long long)
+ (opts->length-imglen) * 100;
+ int percent;
+
+ do_div(n, opts->length);
+ percent = (int)n;
+
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libnet.a
+
+COBJS := mcffec.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+
+#ifdef CONFIG_MCFFEC
+
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <command.h>
+#include <net.h>
+#include <miiphy.h>
+
+#undef ET_DEBUG
+#undef MII_DEBUG
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH 1520
+#define TX_BUF_CNT 2
+#define PKT_MAXBUF_SIZE 1518
+#define PKT_MINBUF_SIZE 64
+#define PKT_MAXBLR_SIZE 1520
+#define LAST_PKTBUFSRX PKTBUFSRX - 1
+#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
+#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+
+struct fec_info_s fec_info[] = {
+#ifdef CFG_FEC0_IOBASE
+ {
+ 0, /* index */
+ CFG_FEC0_IOBASE, /* io base */
+ CFG_FEC0_PINMUX, /* gpio pin muxing */
+ CFG_FEC0_MIIBASE, /* mii base */
+ -1, /* phy_addr */
+ 0, /* duplex and speed */
+ 0, /* phy name */
+ 0, /* phyname init */
+ 0, /* RX BD */
+ 0, /* TX BD */
+ 0, /* rx Index */
+ 0, /* tx Index */
+ 0, /* tx buffer */
+ 0, /* initialized flag */
+ },
+#endif
+#ifdef CFG_FEC1_IOBASE
+ {
+ 1, /* index */
+ CFG_FEC1_IOBASE, /* io base */
+ CFG_FEC1_PINMUX, /* gpio pin muxing */
+ CFG_FEC1_MIIBASE, /* mii base */
+ -1, /* phy_addr */
+ 0, /* duplex and speed */
+ 0, /* phy name */
+ 0, /* phy name init */
+ 0, /* RX BD */
+ 0, /* TX BD */
+ 0, /* rx Index */
+ 0, /* tx Index */
+ 0, /* tx buffer */
+ 0, /* initialized flag */
+ }
+#endif
+};
+
+int fec_send(struct eth_device *dev, volatile void *packet, int length);
+int fec_recv(struct eth_device *dev);
+int fec_init(struct eth_device *dev, bd_t * bd);
+void fec_halt(struct eth_device *dev);
+void fec_reset(struct eth_device *dev);
+
+extern int fecpin_setclear(struct eth_device *dev, int setclear);
+
+#ifdef CFG_DISCOVER_PHY
+extern void __mii_init(void);
+extern uint mii_send(uint mii_cmd);
+extern int mii_discover_phy(struct eth_device *dev);
+extern int mcffec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+extern int mcffec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+#endif
+
+void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
+{
+ if ((dup_spd >> 16) == FULL) {
+ /* Set maximum frame length */
+ fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
+ FEC_RCR_PROM | 0x100;
+ fecp->tcr = FEC_TCR_FDEN;
+ } else {
+ /* Half duplex mode */
+ fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
+ FEC_RCR_MII_MODE | FEC_RCR_DRT;
+ fecp->tcr &= ~FEC_TCR_FDEN;
+ }
+
+ if ((dup_spd & 0xFFFF) == _100BASET) {
+#ifdef MII_DEBUG
+ printf("100Mbps\n");
+#endif
+ bd->bi_ethspeed = 100;
+ } else {
+#ifdef MII_DEBUG
+ printf("10Mbps\n");
+#endif
+ bd->bi_ethspeed = 10;
+ }
+}
+
+int fec_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ struct fec_info_s *info = dev->priv;
+ volatile fec_t *fecp = (fec_t *) (info->iobase);
+ int j, rc;
+ u16 phyStatus;
+
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+
+ /* section 16.9.23.3
+ * Wait for ready
+ */
+ j = 0;
+ while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
+ (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("TX not ready\n");
+ }
+
+ info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
+ info->txbd[info->txIdx].cbd_datlen = length;
+ info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
+
+ /* Activate transmit Buffer Descriptor polling */
+ fecp->tdar = 0x01000000; /* Descriptor polling active */
+
+#ifdef CFG_UNIFY_CACHE
+ icache_invalid();
+#endif
+ j = 0;
+ while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
+ (j < MCFFEC_TOUT_LOOP)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= MCFFEC_TOUT_LOOP) {
+ printf("TX timeout\n");
+ }
+
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
+ __FILE__, __LINE__, __FUNCTION__, j,
+ info->txbd[info->txIdx].cbd_sc,
+ (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
+#endif
+
+ /* return only status bits */
+ rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
+ info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
+
+ return rc;
+}
+
+int fec_recv(struct eth_device *dev)
+{
+ struct fec_info_s *info = dev->priv;
+ volatile fec_t *fecp = (fec_t *) (info->iobase);
+ int length;
+
+ for (;;) {
+#ifdef CFG_UNIFY_CACHE
+ icache_invalid();
+#endif
+ /* section 16.9.23.2 */
+ if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+ length = -1;
+ break; /* nothing received - leave for() loop */
+ }
+
+ length = info->rxbd[info->rxIdx].cbd_datlen;
+
+ if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
+ printf("%s[%d] err: %x\n",
+ __FUNCTION__, __LINE__,
+ info->rxbd[info->rxIdx].cbd_sc);
+#ifdef ET_DEBUG
+ printf("%s[%d] err: %x\n",
+ __FUNCTION__, __LINE__,
+ info->rxbd[info->rxIdx].cbd_sc);
+#endif
+ } else {
+
+ length -= 4;
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[info->rxIdx], length);
+
+ fecp->eir |= FEC_EIR_RXF;
+ }
+
+ /* Give the buffer back to the FEC. */
+ info->rxbd[info->rxIdx].cbd_datlen = 0;
+
+ /* wrap around buffer index when necessary */
+ if (info->rxIdx == LAST_PKTBUFSRX) {
+ info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
+ info->rxIdx = 0;
+ } else {
+ info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ info->rxIdx++;
+ }
+
+ /* Try to fill Buffer Descriptors */
+ fecp->rdar = 0x01000000; /* Descriptor polling active */
+ }
+
+ return length;
+}
+
+#ifdef ET_DEBUG
+void dbgFecRegs(struct eth_device *dev)
+{
+ struct fec_info_s *info = dev->priv;
+ volatile fec_t *fecp = (fec_t *) (info->iobase);
+
+ printf("=====\n");
+ printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
+ printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
+ printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
+ printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
+ printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
+ printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
+ printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
+ printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
+ printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
+ printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
+ printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
+ printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
+ printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
+ printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
+ printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
+ printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
+ printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
+ printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
+ printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
+ printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
+ printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
+ printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
+ printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
+
+ printf("\n");
+ printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
+ fecp->rmon_t_drop);
+ printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
+ fecp->rmon_t_packets);
+ printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
+ fecp->rmon_t_bc_pkt);
+ printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
+ fecp->rmon_t_mc_pkt);
+ printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
+ fecp->rmon_t_crc_align);
+ printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
+ fecp->rmon_t_undersize);
+ printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
+ fecp->rmon_t_oversize);
+ printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
+ fecp->rmon_t_frag);
+ printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
+ fecp->rmon_t_jab);
+ printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
+ fecp->rmon_t_col);
+ printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
+ fecp->rmon_t_p64);
+ printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
+ fecp->rmon_t_p65to127);
+ printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
+ fecp->rmon_t_p128to255);
+ printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
+ fecp->rmon_t_p256to511);
+ printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
+ fecp->rmon_t_p512to1023);
+ printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
+ fecp->rmon_t_p1024to2047);
+ printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
+ fecp->rmon_t_p_gte2048);
+ printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
+ fecp->rmon_t_octets);
+
+ printf("\n");
+ printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
+ fecp->ieee_t_drop);
+ printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
+ fecp->ieee_t_frame_ok);
+ printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
+ fecp->ieee_t_1col);
+ printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
+ fecp->ieee_t_mcol);
+ printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
+ fecp->ieee_t_def);
+ printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
+ fecp->ieee_t_lcol);
+ printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
+ fecp->ieee_t_excol);
+ printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
+ fecp->ieee_t_macerr);
+ printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
+ fecp->ieee_t_cserr);
+ printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
+ fecp->ieee_t_sqe);
+ printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
+ fecp->ieee_t_fdxfc);
+ printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
+ fecp->ieee_t_octets_ok);
+
+ printf("\n");
+ printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
+ fecp->rmon_r_drop);
+ printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
+ fecp->rmon_r_packets);
+ printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
+ fecp->rmon_r_bc_pkt);
+ printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
+ fecp->rmon_r_mc_pkt);
+ printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
+ fecp->rmon_r_crc_align);
+ printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
+ fecp->rmon_r_undersize);
+ printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
+ fecp->rmon_r_oversize);
+ printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
+ fecp->rmon_r_frag);
+ printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
+ fecp->rmon_r_jab);
+ printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
+ fecp->rmon_r_p64);
+ printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
+ fecp->rmon_r_p65to127);
+ printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
+ fecp->rmon_r_p128to255);
+ printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
+ fecp->rmon_r_p256to511);
+ printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
+ fecp->rmon_r_p512to1023);
+ printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
+ fecp->rmon_r_p1024to2047);
+ printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
+ fecp->rmon_r_p_gte2048);
+ printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
+ fecp->rmon_r_octets);
+
+ printf("\n");
+ printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
+ fecp->ieee_r_drop);
+ printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
+ fecp->ieee_r_frame_ok);
+ printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
+ fecp->ieee_r_crc);
+ printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
+ fecp->ieee_r_align);
+ printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
+ fecp->ieee_r_macerr);
+ printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
+ fecp->ieee_r_fdxfc);
+ printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
+ fecp->ieee_r_octets_ok);
+
+ printf("\n\n\n");
+}
+#endif
+
+int fec_init(struct eth_device *dev, bd_t * bd)
+{
+ struct fec_info_s *info = dev->priv;
+ volatile fec_t *fecp = (fec_t *) (info->iobase);
+ int i;
+ u8 *ea = NULL;
+
+ fecpin_setclear(dev, 1);
+
+ fec_reset(dev);
+
+#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
+ defined (CFG_DISCOVER_PHY)
+
+ mii_init();
+
+ setFecDuplexSpeed(fecp, bd, info->dup_spd);
+#else
+#ifndef CFG_DISCOVER_PHY
+ setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
+#endif /* ifndef CFG_DISCOVER_PHY */
+#endif /* CONFIG_CMD_MII || CONFIG_MII */
+
+ /* We use strictly polling mode only */
+ fecp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ fecp->eir = 0xffffffff;
+
+ /* Set station address */
+ if ((u32) fecp == CFG_FEC0_IOBASE) {
+#ifdef CFG_FEC1_IOBASE
+ volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE);
+ ea = &bd->bi_enet1addr[0];
+ fecp1->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
+#endif
+ ea = &bd->bi_enetaddr[0];
+ fecp->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp->paur = (ea[4] << 24) | (ea[5] << 16);
+ } else {
+#ifdef CFG_FEC0_IOBASE
+ volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE);
+ ea = &bd->bi_enetaddr[0];
+ fecp0->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
+#endif
+#ifdef CFG_FEC1_IOBASE
+ ea = &bd->bi_enet1addr[0];
+ fecp->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp->paur = (ea[4] << 24) | (ea[5] << 16);
+#endif
+ }
+
+ /* Clear unicast address hash table */
+ fecp->iaur = 0;
+ fecp->ialr = 0;
+
+ /* Clear multicast address hash table */
+ fecp->gaur = 0;
+ fecp->galr = 0;
+
+ /* Set maximum receive buffer size. */
+ fecp->emrbr = PKT_MAXBLR_SIZE;
+
+ /*
+ * Setup Buffers and Buffer Desriptors
+ */
+ info->rxIdx = 0;
+ info->txIdx = 0;
+
+ /*
+ * Setup Receiver Buffer Descriptors (13.14.24.18)
+ * Settings:
+ * Empty, Wrap
+ */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+ info->rxbd[i].cbd_datlen = 0; /* Reset */
+ info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+ }
+ info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+ /*
+ * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
+ * Settings:
+ * Last, Tx CRC
+ */
+ for (i = 0; i < TX_BUF_CNT; i++) {
+ info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
+ info->txbd[i].cbd_datlen = 0; /* Reset */
+ info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
+ }
+ info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+ /* Set receive and transmit descriptor base */
+ fecp->erdsr = (unsigned int)(&info->rxbd[0]);
+ fecp->etdsr = (unsigned int)(&info->txbd[0]);
+
+ /* Now enable the transmit and receive processing */
+ fecp->ecr |= FEC_ECR_ETHER_EN;
+
+ /* And last, try to fill Rx Buffer Descriptors */
+ fecp->rdar = 0x01000000; /* Descriptor polling active */
+
+ return 1;
+}
+
+void fec_reset(struct eth_device *dev)
+{
+ struct fec_info_s *info = dev->priv;
+ volatile fec_t *fecp = (fec_t *) (info->iobase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ udelay(1);
+ }
+ if (i == FEC_RESET_DELAY) {
+ printf("FEC_RESET_DELAY timeout\n");
+ }
+}
+
+void fec_halt(struct eth_device *dev)
+{
+ struct fec_info_s *info = dev->priv;
+
+ fec_reset(dev);
+
+ fecpin_setclear(dev, 0);
+
+ info->rxIdx = info->txIdx = 0;
+ memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
+ memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
+ memset(info->txbuf, 0, DBUF_LENGTH);
+}
+
+int mcffec_initialize(bd_t * bis)
+{
+ struct eth_device *dev;
+ int i;
+
+ for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
+
+ dev =
+ (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
+ sizeof *dev);
+ if (dev == NULL)
+ hang();
+
+ memset(dev, 0, sizeof(*dev));
+
+ sprintf(dev->name, "FEC%d", fec_info[i].index);
+
+ dev->priv = &fec_info[i];
+ dev->init = fec_init;
+ dev->halt = fec_halt;
+ dev->send = fec_send;
+ dev->recv = fec_recv;
+
+ /* setup Receive and Transmit buffer descriptor */
+ fec_info[i].rxbd =
+ (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+ (PKTBUFSRX * sizeof(cbd_t)));
+ fec_info[i].txbd =
+ (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+ (TX_BUF_CNT * sizeof(cbd_t)));
+ fec_info[i].txbuf =
+ (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+#ifdef ET_DEBUG
+ printf("rxbd %x txbd %x\n",
+ (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
+#endif
+
+ fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
+
+ eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name,
+ mcffec_miiphy_read, mcffec_miiphy_write);
+#endif
+ }
+
+ /* default speed */
+ bis->bi_ethspeed = 10;
+
+ return 1;
+}
+
+#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
+#endif /* CONFIG_MCFFEC */
{ \
u32 val32; \
\
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
+ if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
+ *val = -1; \
return -1; \
+ } \
\
*val = (val32 >> ((offset & (int)off_mask) * 8)); \
\
#define PCIAUTO_IDE_MODE_MASK 0x05
+/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_PCI_CACHE_LINE_SIZE
+#define CFG_PCI_CACHE_LINE_SIZE 8
+#endif
+
/*
*
*/
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
- for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
+ for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
/* Tickle the BAR and get the response */
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
}
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
+ CFG_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
+DECLARE_GLOBAL_DATA_PTR;
+
void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
{
u32 cecr;
uint qe_muram_alloc(uint size, uint align)
{
- DECLARE_GLOBAL_DATA_PTR;
-
uint retloc;
uint align_mask, off;
uint savebase;
void qe_init(uint qe_base)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* Init the QE IMMR base */
qe_immr = (qe_map_t *)qe_base;
int qe_set_brg(uint brg, uint rate)
{
- DECLARE_GLOBAL_DATA_PTR;
volatile uint *bp;
u32 divisor;
int div16 = 0;
return 0;
}
-static int init_mii_management_configuration(uec_t *uec_regs)
+static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
{
uint timeout = 0x1000;
u32 miimcfg = 0;
- miimcfg = in_be32(&uec_regs->miimcfg);
+ miimcfg = in_be32(&uec_mii_regs->miimcfg);
miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
- out_be32(&uec_regs->miimcfg, miimcfg);
+ out_be32(&uec_mii_regs->miimcfg, miimcfg);
/* Wait until the bus is free */
- while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
+ while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
if (timeout <= 0) {
printf("%s: The MII Bus is stuck!", __FUNCTION__);
return -ETIMEDOUT;
static int init_phy(struct eth_device *dev)
{
uec_private_t *uec;
- uec_t *uec_regs;
+ uec_mii_t *umii_regs;
struct uec_mii_info *mii_info;
struct phy_info *curphy;
int err;
uec = (uec_private_t *)dev->priv;
- uec_regs = uec->uec_regs;
+ umii_regs = uec->uec_mii_regs;
uec->oldlink = 0;
uec->oldspeed = 0;
mii_info->mii_id = uec->uec_info->phy_address;
mii_info->dev = dev;
- mii_info->mdio_read = &read_phy_reg;
- mii_info->mdio_write = &write_phy_reg;
+ mii_info->mdio_read = &uec_read_phy_reg;
+ mii_info->mdio_write = &uec_write_phy_reg;
uec->mii_info = mii_info;
- if (init_mii_management_configuration(uec_regs)) {
+ if (init_mii_management_configuration(umii_regs)) {
printf("%s: The MII Bus is stuck!", dev->name);
err = -1;
goto bus_fail;
}
/* get info for this PHY */
- curphy = get_phy_info(uec->mii_info);
+ curphy = uec_get_phy_info(uec->mii_info);
if (!curphy) {
printf("%s: No PHY found", dev->name);
err = -1;
/* Setup MAC interface mode */
uec_set_mac_if_mode(uec, uec_info->enet_interface);
+ /* Setup MII management base */
+#ifndef CONFIG_eTSEC_MDIO_BUS
+ uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
+#else
+ uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
+#endif
+
/* Setup MII master clock source */
qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n",
__FUNCTION__);
- return -EINVAL;
+ return 0;
}
uec_set_mac_address(uec, dev->enetaddr);
uec->the_first_run = 1;
err = uec_open(uec, COMM_DIR_RX_AND_TX);
if (err) {
printf("%s: cannot enable UEC device\n", dev->name);
- return err;
+ return 0;
}
- return 0;
+ return uec->mii_info->link;
}
static void uec_halt(struct eth_device* dev)
ucc_fast_private_t *uccf;
struct eth_device *dev;
uec_t *uec_regs;
+ uec_mii_t *uec_mii_regs;
/* enet init command parameter */
uec_init_cmd_pram_t *p_init_enet_param;
u32 init_enet_param_offset;
/* Write value to the PHY for this device to the register at regnum, */
/* waiting until the write is done before it returns. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
- uec_t *ug_regs;
+ uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
- ug_regs = ugeth->uec_regs;
+ ug_regs = ugeth->uec_mii_regs;
/* Stop the MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
/* Reads from register regnum in the PHY for device dev, */
/* returning the value. Clears miimcom first. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
- uec_t *ug_regs;
+ uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
u16 value;
- ug_regs = ugeth->uec_regs;
+ ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
/* Use the PHY ID registers to determine what type of PHY is attached
* to device dev. return a struct phy_info structure describing that PHY
*/
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
{
u16 phy_reg;
u32 phy_ID;
void (*close) (struct uec_mii_info * mii_info);
};
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
int value);
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts);
static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
+#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
+static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
+{
+ return (0);
+}
+#endif
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
+#ifdef CONFIG_MCAST_TFTP
+ dev->mcast = rtl_bcast_addr;
+#endif
eth_register (dev);
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libserial.a
+
+COBJS := mcfuart.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Minimal serial functions needed to use one of the uart ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_MCFUART
+
+#include <asm/immap.h>
+#include <asm/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void uart_port_conf(void);
+
+int serial_init(void)
+{
+ volatile uart_t *uart;
+ u32 counter;
+
+ uart = (volatile uart_t *)(CFG_UART_BASE);
+
+ uart_port_conf();
+
+ /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+ uart->ucr = UART_UCR_RESET_RX;
+ uart->ucr = UART_UCR_RESET_TX;
+ uart->ucr = UART_UCR_RESET_ERROR;
+ uart->ucr = UART_UCR_RESET_MR;
+ __asm__("nop");
+
+ uart->uimr = 0;
+
+ /* write to CSR: RX/TX baud rate from timers */
+ uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
+
+ uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
+ uart->umr = UART_UMR_SB_STOP_BITS_1;
+
+ /* Setting up BaudRate */
+ counter = (u32) (gd->bus_clk / (gd->baudrate));
+ counter >>= 5;
+
+ /* write to CTUR: divide counter upper byte */
+ uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
+ /* write to CTLR: divide counter lower byte */
+ uart->ubg2 = (u8) (counter & 0x00ff);
+
+ uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
+
+ return (0);
+}
+
+void serial_putc(const char c)
+{
+ volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+
+ if (c == '\n')
+ serial_putc('\r');
+
+ /* Wait for last character to go. */
+ while (!(uart->usr & UART_USR_TXRDY)) ;
+
+ uart->utb = c;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+int serial_getc(void)
+{
+ volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+
+ /* Wait for a character to arrive. */
+ while (!(uart->usr & UART_USR_RXRDY)) ;
+ return uart->urb;
+}
+
+int serial_tstc(void)
+{
+ volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+
+ return (uart->usr & UART_USR_RXRDY);
+}
+
+void serial_setbrg(void)
+{
+ volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+ u32 counter;
+
+ counter = ((gd->bus_clk / gd->baudrate)) >> 5;
+ counter++;
+
+ /* write to CTUR: divide counter upper byte */
+ uart->ubg1 = ((counter & 0xff00) >> 8);
+ /* write to CTLR: divide counter lower byte */
+ uart->ubg2 = (counter & 0x00ff);
+
+ uart->ucr = UART_UCR_RESET_RX;
+ uart->ucr = UART_UCR_RESET_TX;
+
+ uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
+}
+#endif /* CONFIG_MCFUART */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* sil680.c - ide support functions for the Sil0680A controller */
+
+/*
+ * The following parameters must be defined in the configuration file
+ * of the target board:
+ *
+ * #define CFG_IDE_SIL680
+ *
+ * #define CONFIG_PCI_PNP
+ * NOTE it may also be necessary to define this if the default of 8 is
+ * incorrect for the target board (e.g. the sequoia board requires 0).
+ * #define CFG_PCI_CACHE_LINE_SIZE 0
+ *
+ * #define CONFIG_CMD_IDE
+ * #undef CONFIG_IDE_8xx_DIRECT
+ * #undef CONFIG_IDE_LED
+ * #undef CONFIG_IDE_RESET
+ * #define CONFIG_IDE_PREINIT
+ * #define CFG_IDE_MAXBUS 2 - modify to suit
+ * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit
+ * #define CFG_ATA_BASE_ADDR 0
+ * #define CFG_ATA_IDE0_OFFSET 0
+ * #define CFG_ATA_IDE1_OFFSET 0
+ * #define CFG_ATA_DATA_OFFSET 0
+ * #define CFG_ATA_REG_OFFSET 0
+ * #define CFG_ATA_ALT_OFFSET 0x0004
+ *
+ * The mapping for PCI IO-space.
+ * NOTE this is the value for the sequoia board. Modify to suit.
+ * #define CFG_PCI0_IO_SPACE 0xE8000000
+ */
+
+#include <common.h>
+#if defined(CFG_IDE_SIL680)
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+
+int ide_preinit (void)
+{
+ int status;
+ pci_dev_t devbusfn;
+ int l;
+
+ status = 1;
+ for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+ ide_bus_offset[l] = -ATA_STATUS;
+ }
+ devbusfn = pci_find_device (0x1095, 0x0680, 0);
+ if (devbusfn != -1) {
+ status = 0;
+
+ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+ (u32 *) &ide_bus_offset[0]);
+ ide_bus_offset[0] &= 0xfffffff8;
+ ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
+ (u32 *) &ide_bus_offset[1]);
+ ide_bus_offset[1] &= 0xfffffff8;
+ ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+ /* init various things - taken from the Linux driver */
+ /* set PIO mode */
+ pci_write_config_byte(devbusfn, 0x80, 0x00);
+ pci_write_config_byte(devbusfn, 0x84, 0x00);
+ /* IDE0 */
+ pci_write_config_byte(devbusfn, 0xA1, 0x02);
+ pci_write_config_word(devbusfn, 0xA2, 0x328A);
+ pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
+ pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
+ pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
+ /* IDE1 */
+ pci_write_config_byte(devbusfn, 0xB1, 0x02);
+ pci_write_config_word(devbusfn, 0xB2, 0x328A);
+ pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
+ pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
+ pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
+ }
+ return (status);
+}
+
+void ide_set_reset (int flag) {
+ return;
+}
+
+#endif /* CFG_IDE_SIL680 */
/* Local functions. */
/******************************************************************************/
-LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_TranslateRequestedMediaType(
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
- PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed,
- PLM_DUPLEX_MODE pDuplexMode);
-
-static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
-
-__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
-__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
+
+static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE
+ RequestedMediaType,
+ PLM_MEDIA_TYPE pMediaType,
+ PLM_LINE_SPEED pLineSpeed,
+ PLM_DUPLEX_MODE pDuplexMode);
+
+static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice);
+
+__inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice);
+__inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice);
+
+static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE
+ RequestedMediaType);
+static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
+static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 LocalPhyAd,
+ LM_UINT32 RemotePhyAd);
#if INCLUDE_TBI_SUPPORT
-STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice);
#endif
-STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
-STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
-STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
- LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
-STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number);
-STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
- PT3_SND_BD pSendBd);
+STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice);
+STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid,
+ LM_UINT16 Ssid);
+STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
+ LM_PHYSICAL_ADDRESS BufferPhy,
+ LM_UINT32 BufferSize);
+STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number);
+STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice,
+ PLM_PACKET pPacket, PT3_SND_BD pSendBd);
/******************************************************************************/
/* External functions. */
/******************************************************************************/
-LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
-
+LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice);
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_UINT32
-LM_RegRdInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Register) {
- LM_UINT32 Value32;
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
+{
+ LM_UINT32 Value32;
#if PCIX_TARGET_WORKAROUND
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#endif
- MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
- MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
+ MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32);
#if PCIX_TARGET_WORKAROUND
- MM_RELEASE_UNDI_LOCK(pDevice);
+ MM_RELEASE_UNDI_LOCK (pDevice);
#endif
- return Value32;
-} /* LM_RegRdInd */
-
+ return Value32;
+} /* LM_RegRdInd */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
LM_VOID
-LM_RegWrInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Register,
-LM_UINT32 Value32) {
+LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32)
+{
#if PCIX_TARGET_WORKAROUND
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#endif
- MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
- MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
+ MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32);
#if PCIX_TARGET_WORKAROUND
- MM_RELEASE_UNDI_LOCK(pDevice);
+ MM_RELEASE_UNDI_LOCK (pDevice);
#endif
-} /* LM_RegWrInd */
-
+} /* LM_RegWrInd */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_UINT32
-LM_MemRdInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 MemAddr) {
- LM_UINT32 Value32;
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr)
+{
+ LM_UINT32 Value32;
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#ifdef BIG_ENDIAN_HOST
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- Value32 = REG_RD(pDevice, PciCfg.MemWindowData);
- /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+ Value32 = REG_RD (pDevice, PciCfg.MemWindowData);
+ /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
#else
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+ MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
#endif
- MM_RELEASE_UNDI_LOCK(pDevice);
-
- return Value32;
-} /* LM_MemRdInd */
+ MM_RELEASE_UNDI_LOCK (pDevice);
+ return Value32;
+} /* LM_MemRdInd */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
LM_VOID
-LM_MemWrInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 MemAddr,
-LM_UINT32 Value32) {
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32)
+{
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#ifdef BIG_ENDIAN_HOST
- REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr);
- REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32);
+ REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr);
+ REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32);
#else
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
#endif
- MM_RELEASE_UNDI_LOCK(pDevice);
-} /* LM_MemWrInd */
-
+ MM_RELEASE_UNDI_LOCK (pDevice);
+} /* LM_MemWrInd */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_QueueRxPackets(
-PLM_DEVICE_BLOCK pDevice) {
- LM_STATUS Lmstatus;
- PLM_PACKET pPacket;
- PT3_RCV_BD pRcvBd;
- LM_UINT32 StdBdAdded = 0;
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice)
+{
+ LM_STATUS Lmstatus;
+ PLM_PACKET pPacket;
+ PT3_RCV_BD pRcvBd;
+ LM_UINT32 StdBdAdded = 0;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- LM_UINT32 JumboBdAdded = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ LM_UINT32 JumboBdAdded = 0;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- Lmstatus = LM_STATUS_SUCCESS;
+ Lmstatus = LM_STATUS_SUCCESS;
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- while(pPacket) {
- switch(pPacket->u.Rx.RcvProdRing) {
+ pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ while (pPacket) {
+ switch (pPacket->u.Rx.RcvProdRing) {
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
- /* Initialize the buffer descriptor. */
- pRcvBd =
- &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
- pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
- pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
-
- /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new */
- pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
- pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
+ case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
+ /* Initialize the buffer descriptor. */
+ pRcvBd =
+ &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
+ pRcvBd->Flags =
+ RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
+ pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
+
+ /* Initialize the receive buffer pointer */
+#if 0 /* Jimmy, deleted in new */
+ pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
+ pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
#endif
- MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
+ MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
- /* The opaque field may point to an offset from a fix addr. */
- pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
- MM_UINT_PTR(pDevice->pPacketDescBase));
+ /* The opaque field may point to an offset from a fix addr. */
+ pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
+ MM_UINT_PTR (pDevice->
+ pPacketDescBase));
- /* Update the producer index. */
- pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) &
- T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
+ /* Update the producer index. */
+ pDevice->RxJumboProdIdx =
+ (pDevice->RxJumboProdIdx +
+ 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
- JumboBdAdded++;
- break;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
- /* Initialize the buffer descriptor. */
- pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
- pRcvBd->Flags = RCV_BD_FLAG_END;
- pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
-
- /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */
- pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
- pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
+ JumboBdAdded++;
+ break;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
+ /* Initialize the buffer descriptor. */
+ pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
+ pRcvBd->Flags = RCV_BD_FLAG_END;
+ pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
+
+ /* Initialize the receive buffer pointer */
+#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */
+ pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
+ pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
#endif
- MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
+ MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
- /* The opaque field may point to an offset from a fix addr. */
- pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
- MM_UINT_PTR(pDevice->pPacketDescBase));
+ /* The opaque field may point to an offset from a fix addr. */
+ pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
+ MM_UINT_PTR (pDevice->
+ pPacketDescBase));
- /* Update the producer index. */
- pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
- T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
+ /* Update the producer index. */
+ pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
+ T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
- StdBdAdded++;
- break;
+ StdBdAdded++;
+ break;
- case T3_UNKNOWN_RCV_PROD_RING:
- default:
- Lmstatus = LM_STATUS_FAILURE;
- break;
- } /* switch */
+ case T3_UNKNOWN_RCV_PROD_RING:
+ default:
+ Lmstatus = LM_STATUS_FAILURE;
+ break;
+ } /* switch */
- /* Bail out if there is any error. */
- if(Lmstatus != LM_STATUS_SUCCESS)
- {
- break;
- }
+ /* Bail out if there is any error. */
+ if (Lmstatus != LM_STATUS_SUCCESS) {
+ break;
+ }
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- } /* while */
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ } /* while */
- wmb();
- /* Update the procedure index. */
- if(StdBdAdded)
- {
- MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx);
- }
+ wmb ();
+ /* Update the procedure index. */
+ if (StdBdAdded) {
+ MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low,
+ pDevice->RxStdProdIdx);
+ }
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if(JumboBdAdded)
- {
- MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
- pDevice->RxJumboProdIdx);
- }
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- return Lmstatus;
-} /* LM_QueueRxPackets */
+ if (JumboBdAdded) {
+ MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low,
+ pDevice->RxJumboProdIdx);
+ }
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ return Lmstatus;
+} /* LM_QueueRxPackets */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-STATIC LM_VOID
-LM_NvramInit(
- PLM_DEVICE_BLOCK pDevice)
+STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- /* Intialize clock period and state machine. */
- Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
- SEEPROM_ADDR_FSM_RESET;
- REG_WR(pDevice, Grc.EepromAddr, Value32);
-
- for(j = 0; j < 100; j++)
- {
- MM_Wait(10);
- }
-
- /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
- Value32 = REG_RD(pDevice, Grc.LocalCtrl);
- REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
-
- /* Set the 5701 compatibility mode if we are using EEPROM. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
- {
- Value32 = REG_RD(pDevice, Nvram.Config1);
- if((Value32 & FLASH_INTERFACE_ENABLE) == 0)
- {
- /* Use the new interface to read EEPROM. */
- Value32 &= ~FLASH_COMPAT_BYPASS;
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- REG_WR(pDevice, Nvram.Config1, Value32);
+ /* Intialize clock period and state machine. */
+ Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) |
+ SEEPROM_ADDR_FSM_RESET;
+ REG_WR (pDevice, Grc.EepromAddr, Value32);
+
+ for (j = 0; j < 100; j++) {
+ MM_Wait (10);
}
- }
-} /* LM_NvRamInit */
+ /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
+ Value32 = REG_RD (pDevice, Grc.LocalCtrl);
+ REG_WR (pDevice, Grc.LocalCtrl,
+ Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
+
+ /* Set the 5701 compatibility mode if we are using EEPROM. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+ Value32 = REG_RD (pDevice, Nvram.Config1);
+ if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) {
+ /* Use the new interface to read EEPROM. */
+ Value32 &= ~FLASH_COMPAT_BYPASS;
+
+ REG_WR (pDevice, Nvram.Config1, Value32);
+ }
+ }
+} /* LM_NvRamInit */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
STATIC LM_STATUS
-LM_EepromRead(
- PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 *pData)
+LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
{
- LM_UINT32 Value32;
- LM_UINT32 Addr;
- LM_UINT32 Dev;
- LM_UINT32 j;
+ LM_UINT32 Value32;
+ LM_UINT32 Addr;
+ LM_UINT32 Dev;
+ LM_UINT32 j;
- if(Offset > SEEPROM_CHIP_SIZE)
- {
- return LM_STATUS_FAILURE;
- }
+ if (Offset > SEEPROM_CHIP_SIZE) {
+ return LM_STATUS_FAILURE;
+ }
- Dev = Offset / SEEPROM_CHIP_SIZE;
- Addr = Offset % SEEPROM_CHIP_SIZE;
+ Dev = Offset / SEEPROM_CHIP_SIZE;
+ Addr = Offset % SEEPROM_CHIP_SIZE;
- Value32 = REG_RD(pDevice, Grc.EepromAddr);
- Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
- SEEPROM_ADDR_RW_MASK);
- REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) |
- SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ);
+ Value32 = REG_RD (pDevice, Grc.EepromAddr);
+ Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
+ SEEPROM_ADDR_RW_MASK);
+ REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) |
+ SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START |
+ SEEPROM_ADDR_READ);
- for(j = 0; j < 1000; j++)
- {
- Value32 = REG_RD(pDevice, Grc.EepromAddr);
- if(Value32 & SEEPROM_ADDR_COMPLETE)
- {
- break;
+ for (j = 0; j < 1000; j++) {
+ Value32 = REG_RD (pDevice, Grc.EepromAddr);
+ if (Value32 & SEEPROM_ADDR_COMPLETE) {
+ break;
+ }
+ MM_Wait (10);
}
- MM_Wait(10);
- }
-
- if(Value32 & SEEPROM_ADDR_COMPLETE)
- {
- Value32 = REG_RD(pDevice, Grc.EepromData);
- *pData = Value32;
- return LM_STATUS_SUCCESS;
- }
+ if (Value32 & SEEPROM_ADDR_COMPLETE) {
+ Value32 = REG_RD (pDevice, Grc.EepromData);
+ *pData = Value32;
- return LM_STATUS_FAILURE;
-} /* LM_EepromRead */
+ return LM_STATUS_SUCCESS;
+ }
+ return LM_STATUS_FAILURE;
+} /* LM_EepromRead */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
STATIC LM_STATUS
-LM_NvramRead(
- PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 *pData)
+LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
{
- LM_UINT32 Value32;
- LM_STATUS Status;
- LM_UINT32 j;
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Status = LM_EepromRead(pDevice, Offset, pData);
- }
- else
- {
- /* Determine if we have flash or EEPROM. */
- Value32 = REG_RD(pDevice, Nvram.Config1);
- if(Value32 & FLASH_INTERFACE_ENABLE)
- {
- if(Value32 & FLASH_SSRAM_BUFFERRED_MODE)
- {
- Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) <<
- BUFFERED_FLASH_PAGE_POS) +
- (Offset % BUFFERED_FLASH_PAGE_SIZE);
- }
- }
+ LM_UINT32 Value32;
+ LM_STATUS Status;
+ LM_UINT32 j;
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Status = LM_EepromRead (pDevice, Offset, pData);
+ } else {
+ /* Determine if we have flash or EEPROM. */
+ Value32 = REG_RD (pDevice, Nvram.Config1);
+ if (Value32 & FLASH_INTERFACE_ENABLE) {
+ if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) {
+ Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) <<
+ BUFFERED_FLASH_PAGE_POS) +
+ (Offset % BUFFERED_FLASH_PAGE_SIZE);
+ }
+ }
- REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
- for (j = 0; j < 1000; j++)
- {
- if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1)
- {
- break;
- }
- MM_Wait(20);
- }
- if (j == 1000)
- {
- return LM_STATUS_FAILURE;
- }
+ REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
+ for (j = 0; j < 1000; j++) {
+ if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) {
+ break;
+ }
+ MM_Wait (20);
+ }
+ if (j == 1000) {
+ return LM_STATUS_FAILURE;
+ }
- /* Read from flash or EEPROM with the new 5703/02 interface. */
- REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
+ /* Read from flash or EEPROM with the new 5703/02 interface. */
+ REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
- REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
- NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
+ REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
+ NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
- /* Wait for the done bit to clear. */
- for(j = 0; j < 500; j++)
- {
- MM_Wait(10);
+ /* Wait for the done bit to clear. */
+ for (j = 0; j < 500; j++) {
+ MM_Wait (10);
- Value32 = REG_RD(pDevice, Nvram.Cmd);
- if(!(Value32 & NVRAM_CMD_DONE))
- {
- break;
- }
- }
+ Value32 = REG_RD (pDevice, Nvram.Cmd);
+ if (!(Value32 & NVRAM_CMD_DONE)) {
+ break;
+ }
+ }
- /* Wait for the done bit. */
- if(!(Value32 & NVRAM_CMD_DONE))
- {
- for(j = 0; j < 500; j++)
- {
- MM_Wait(10);
+ /* Wait for the done bit. */
+ if (!(Value32 & NVRAM_CMD_DONE)) {
+ for (j = 0; j < 500; j++) {
+ MM_Wait (10);
- Value32 = REG_RD(pDevice, Nvram.Cmd);
- if(Value32 & NVRAM_CMD_DONE)
- {
- MM_Wait(10);
+ Value32 = REG_RD (pDevice, Nvram.Cmd);
+ if (Value32 & NVRAM_CMD_DONE) {
+ MM_Wait (10);
- *pData = REG_RD(pDevice, Nvram.ReadData);
+ *pData =
+ REG_RD (pDevice, Nvram.ReadData);
- /* Change the endianess. */
- *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)|
- ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff);
+ /* Change the endianess. */
+ *pData =
+ ((*pData & 0xff) << 24) |
+ ((*pData & 0xff00) << 8) |
+ ((*pData & 0xff0000) >> 8) |
+ ((*pData >> 24) & 0xff);
- break;
+ break;
+ }
+ }
}
- }
- }
- REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
- if(Value32 & NVRAM_CMD_DONE)
- {
- Status = LM_STATUS_SUCCESS;
- }
- else
- {
- Status = LM_STATUS_FAILURE;
+ REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
+ if (Value32 & NVRAM_CMD_DONE) {
+ Status = LM_STATUS_SUCCESS;
+ } else {
+ Status = LM_STATUS_FAILURE;
+ }
}
- }
-
- return Status;
-} /* LM_NvramRead */
+ return Status;
+} /* LM_NvramRead */
-STATIC void
-LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Vpd_arr[256/4];
- LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
- LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
- LM_UINT32 Value32;
- unsigned int j;
-
- /* Read PN from VPD */
- for (j = 0; j < 256; j += 4, Vpd_dptr++ )
- {
- if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
- printf("BCM570x: LM_ReadVPD: VPD read failed"
- " (no EEPROM onboard)\n");
- return;
- }
- *Vpd_dptr = cpu_to_le32(Value32);
- }
- for (j = 0; j < 256; )
- {
- unsigned int Vpd_r_len;
- unsigned int Vpd_r_end;
-
- if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
- {
- j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
- }
- else if (Vpd[j] == 0x90)
- {
- Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
- j += 3;
- Vpd_r_end = Vpd_r_len + j;
- while (j < Vpd_r_end)
- {
- if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
- {
- unsigned int len = Vpd[j + 2];
-
- if (len <= 24)
- {
- memcpy(pDevice->PartNo, &Vpd[j + 3], len);
- }
- break;
+ LM_UINT32 Vpd_arr[256 / 4];
+ LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0];
+ LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
+ LM_UINT32 Value32;
+ unsigned int j;
+
+ /* Read PN from VPD */
+ for (j = 0; j < 256; j += 4, Vpd_dptr++) {
+ if (LM_NvramRead (pDevice, 0x100 + j, &Value32) !=
+ LM_STATUS_SUCCESS) {
+ printf ("BCM570x: LM_ReadVPD: VPD read failed"
+ " (no EEPROM onboard)\n");
+ return;
}
- else
- {
- if (Vpd[j + 2] == 0)
- {
+ *Vpd_dptr = cpu_to_le32 (Value32);
+ }
+ for (j = 0; j < 256;) {
+ unsigned int Vpd_r_len;
+ unsigned int Vpd_r_end;
+
+ if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) {
+ j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
+ } else if (Vpd[j] == 0x90) {
+ Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
+ j += 3;
+ Vpd_r_end = Vpd_r_len + j;
+ while (j < Vpd_r_end) {
+ if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) {
+ unsigned int len = Vpd[j + 2];
+
+ if (len <= 24) {
+ memcpy (pDevice->PartNo,
+ &Vpd[j + 3], len);
+ }
+ break;
+ } else {
+ if (Vpd[j + 2] == 0) {
+ break;
+ }
+ j = j + Vpd[j + 2];
+ }
+ }
+ break;
+ } else {
break;
- }
- j = j + Vpd[j + 2];
}
- }
- break;
}
- else {
- break;
- }
- }
}
-STATIC void
-LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32, offset, ver_offset;
- int i;
-
- if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
- return;
- if (Value32 != 0xaa559966)
- return;
- if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
- return;
-
- offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)|
- ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
- if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
- return;
- if ((Value32 == 0x0300000e) &&
- (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
- (Value32 == 0)) {
-
- if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
- return;
- ver_offset = ((ver_offset & 0xff0000) >> 8) |
- ((ver_offset >> 24) & 0xff);
- for (i = 0; i < 16; i += 4) {
- if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) !=
- LM_STATUS_SUCCESS)
- {
+ LM_UINT32 Value32, offset, ver_offset;
+ int i;
+
+ if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
return;
- }
- *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32);
- }
- }
- else {
- char c;
+ if (Value32 != 0xaa559966)
+ return;
+ if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
+ return;
+
+ offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) |
+ ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
+ if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
+ return;
+ if ((Value32 == 0x0300000e) &&
+ (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS)
+ && (Value32 == 0)) {
+
+ if (LM_NvramRead (pDevice, offset + 8, &ver_offset) !=
+ LM_STATUS_SUCCESS)
+ return;
+ ver_offset = ((ver_offset & 0xff0000) >> 8) |
+ ((ver_offset >> 24) & 0xff);
+ for (i = 0; i < 16; i += 4) {
+ if (LM_NvramRead
+ (pDevice, offset + ver_offset + i,
+ &Value32) != LM_STATUS_SUCCESS) {
+ return;
+ }
+ *((LM_UINT32 *) & pDevice->BootCodeVer[i]) =
+ cpu_to_le32 (Value32);
+ }
+ } else {
+ char c;
- if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
- return;
+ if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
+ return;
- i = 0;
- c = ((Value32 & 0xff0000) >> 16);
+ i = 0;
+ c = ((Value32 & 0xff0000) >> 16);
- if (c < 10) {
- pDevice->BootCodeVer[i++] = c + '0';
- }
- else {
- pDevice->BootCodeVer[i++] = (c / 10) + '0';
- pDevice->BootCodeVer[i++] = (c % 10) + '0';
- }
- pDevice->BootCodeVer[i++] = '.';
- c = (Value32 & 0xff000000) >> 24;
- if (c < 10) {
- pDevice->BootCodeVer[i++] = c + '0';
- }
- else {
- pDevice->BootCodeVer[i++] = (c / 10) + '0';
- pDevice->BootCodeVer[i++] = (c % 10) + '0';
+ if (c < 10) {
+ pDevice->BootCodeVer[i++] = c + '0';
+ } else {
+ pDevice->BootCodeVer[i++] = (c / 10) + '0';
+ pDevice->BootCodeVer[i++] = (c % 10) + '0';
+ }
+ pDevice->BootCodeVer[i++] = '.';
+ c = (Value32 & 0xff000000) >> 24;
+ if (c < 10) {
+ pDevice->BootCodeVer[i++] = c + '0';
+ } else {
+ pDevice->BootCodeVer[i++] = (c / 10) + '0';
+ pDevice->BootCodeVer[i++] = (c % 10) + '0';
+ }
+ pDevice->BootCodeVer[i] = 0;
}
- pDevice->BootCodeVer[i] = 0;
- }
}
-STATIC void
-LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 PciState = pDevice->PciState;
- LM_UINT32 ClockCtrl;
- char *SpeedStr = "";
-
- if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
- {
- strcpy(pDevice->BusSpeedStr, "32-bit ");
- }
- else
- {
- strcpy(pDevice->BusSpeedStr, "64-bit ");
- }
- if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
- {
- strcat(pDevice->BusSpeedStr, "PCI ");
- if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
- {
- SpeedStr = "66MHz";
- }
- else
- {
- SpeedStr = "33MHz";
- }
- }
- else
- {
- strcat(pDevice->BusSpeedStr, "PCIX ");
- if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)
- {
- SpeedStr = "133MHz";
- }
- else
- {
- ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
- switch (ClockCtrl)
- {
- case 0:
- SpeedStr = "33MHz";
- break;
-
- case 2:
- SpeedStr = "50MHz";
- break;
-
- case 4:
- SpeedStr = "66MHz";
- break;
-
- case 6:
- SpeedStr = "100MHz";
- break;
-
- case 7:
- SpeedStr = "133MHz";
- break;
- }
+ LM_UINT32 PciState = pDevice->PciState;
+ LM_UINT32 ClockCtrl;
+ char *SpeedStr = "";
+
+ if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) {
+ strcpy (pDevice->BusSpeedStr, "32-bit ");
+ } else {
+ strcpy (pDevice->BusSpeedStr, "64-bit ");
+ }
+ if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) {
+ strcat (pDevice->BusSpeedStr, "PCI ");
+ if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) {
+ SpeedStr = "66MHz";
+ } else {
+ SpeedStr = "33MHz";
+ }
+ } else {
+ strcat (pDevice->BusSpeedStr, "PCIX ");
+ if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) {
+ SpeedStr = "133MHz";
+ } else {
+ ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f;
+ switch (ClockCtrl) {
+ case 0:
+ SpeedStr = "33MHz";
+ break;
+
+ case 2:
+ SpeedStr = "50MHz";
+ break;
+
+ case 4:
+ SpeedStr = "66MHz";
+ break;
+
+ case 6:
+ SpeedStr = "100MHz";
+ break;
+
+ case 7:
+ SpeedStr = "133MHz";
+ break;
+ }
+ }
}
- }
- strcat(pDevice->BusSpeedStr, SpeedStr);
+ strcat (pDevice->BusSpeedStr, SpeedStr);
}
/******************************************************************************/
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_GetAdapterInfo(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice)
{
- PLM_ADAPTER_INFO pAdapterInfo;
- LM_UINT32 Value32;
- LM_STATUS Status;
- LM_UINT32 j;
- LM_UINT32 EeSigFound;
- LM_UINT32 EePhyTypeSerdes = 0;
- LM_UINT32 EePhyLedMode = 0;
- LM_UINT32 EePhyId = 0;
-
- /* Get Device Id and Vendor Id */
- Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->PciVendorId = (LM_UINT16) Value32;
- pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
-
- /* If we are not getting the write adapter, exit. */
- if((Value32 != T3_PCI_ID_BCM5700) &&
- (Value32 != T3_PCI_ID_BCM5701) &&
- (Value32 != T3_PCI_ID_BCM5702) &&
- (Value32 != T3_PCI_ID_BCM5702x) &&
- (Value32 != T3_PCI_ID_BCM5702FE) &&
- (Value32 != T3_PCI_ID_BCM5703) &&
- (Value32 != T3_PCI_ID_BCM5703x) &&
- (Value32 != T3_PCI_ID_BCM5704))
- {
- return LM_STATUS_FAILURE;
- }
+ PLM_ADAPTER_INFO pAdapterInfo;
+ LM_UINT32 Value32;
+ LM_STATUS Status;
+ LM_UINT32 j;
+ LM_UINT32 EeSigFound;
+ LM_UINT32 EePhyTypeSerdes = 0;
+ LM_UINT32 EePhyLedMode = 0;
+ LM_UINT32 EePhyId = 0;
+
+ /* Get Device Id and Vendor Id */
+ Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->PciVendorId = (LM_UINT16) Value32;
+ pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
+
+ /* If we are not getting the write adapter, exit. */
+ if ((Value32 != T3_PCI_ID_BCM5700) &&
+ (Value32 != T3_PCI_ID_BCM5701) &&
+ (Value32 != T3_PCI_ID_BCM5702) &&
+ (Value32 != T3_PCI_ID_BCM5702x) &&
+ (Value32 != T3_PCI_ID_BCM5702FE) &&
+ (Value32 != T3_PCI_ID_BCM5703) &&
+ (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) {
+ return LM_STATUS_FAILURE;
+ }
- Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->PciRevId = (LM_UINT8) Value32;
+ Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->PciRevId = (LM_UINT8) Value32;
- /* Get IRQ. */
- Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->Irq = (LM_UINT8) Value32;
+ /* Get IRQ. */
+ Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->Irq = (LM_UINT8) Value32;
- /* Get interrupt pin. */
- pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
+ /* Get interrupt pin. */
+ pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
- /* Get chip revision id. */
- Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
- pDevice->ChipRevId = Value32 >> 16;
+ /* Get chip revision id. */
+ Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
+ pDevice->ChipRevId = Value32 >> 16;
- /* Get subsystem vendor. */
- Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->SubsystemVendorId = (LM_UINT16) Value32;
+ /* Get subsystem vendor. */
+ Status =
+ MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->SubsystemVendorId = (LM_UINT16) Value32;
- /* Get PCI subsystem id. */
- pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
+ /* Get PCI subsystem id. */
+ pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
- /* Get the cache line size. */
- MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
- pDevice->CacheLineSize = (LM_UINT8) Value32;
- pDevice->SavedCacheLineReg = Value32;
+ /* Get the cache line size. */
+ MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
+ pDevice->CacheLineSize = (LM_UINT8) Value32;
+ pDevice->SavedCacheLineReg = Value32;
- if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
- pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
- pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
- {
- pDevice->UndiFix = FALSE;
- }
+ if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
+ pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
+ pDevice->ChipRevId != T3_CHIP_ID_5704_A0) {
+ pDevice->UndiFix = FALSE;
+ }
#if !PCIX_TARGET_WORKAROUND
- pDevice->UndiFix = FALSE;
+ pDevice->UndiFix = FALSE;
#endif
- /* Map the memory base to system address space. */
- if (!pDevice->UndiFix)
- {
- Status = MM_MapMemBase(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
+ /* Map the memory base to system address space. */
+ if (!pDevice->UndiFix) {
+ Status = MM_MapMemBase (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ /* Initialize the memory view pointer. */
+ pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
}
- /* Initialize the memory view pointer. */
- pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
- }
-
#if PCIX_TARGET_WORKAROUND
- /* store whether we are in PCI are PCI-X mode */
- pDevice->EnablePciXFix = FALSE;
-
- MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
- if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
- {
- /* Enable PCI-X workaround only if we are running on 5700 BX. */
- if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
- {
- pDevice->EnablePciXFix = TRUE;
+ /* store whether we are in PCI are PCI-X mode */
+ pDevice->EnablePciXFix = FALSE;
+
+ MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
+ if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) {
+ /* Enable PCI-X workaround only if we are running on 5700 BX. */
+ if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+ pDevice->EnablePciXFix = TRUE;
+ }
+ }
+ if (pDevice->UndiFix) {
+ pDevice->EnablePciXFix = TRUE;
}
- }
- if (pDevice->UndiFix)
- {
- pDevice->EnablePciXFix = TRUE;
- }
#endif
- /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
- /* management register may be clobbered which may cause the */
- /* BCM5700 to go into D3 state. While in this state, we will */
- /* not have memory mapped register access. As a workaround, we */
- /* need to restore the device to D0 state. */
- MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
- Value32 |= T3_PM_PME_ASSERTED;
- Value32 &= ~T3_PM_POWER_STATE_MASK;
- Value32 |= T3_PM_POWER_STATE_D0;
- MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
-
- /* read the current PCI command word */
- MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
-
- /* Make sure bus-mastering is enabled. */
- Value32 |= PCI_BUSMASTER_ENABLE;
+ /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
+ /* management register may be clobbered which may cause the */
+ /* BCM5700 to go into D3 state. While in this state, we will */
+ /* not have memory mapped register access. As a workaround, we */
+ /* need to restore the device to D0 state. */
+ MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
+ Value32 |= T3_PM_PME_ASSERTED;
+ Value32 &= ~T3_PM_POWER_STATE_MASK;
+ Value32 |= T3_PM_POWER_STATE_D0;
+ MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
+
+ /* read the current PCI command word */
+ MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32);
+
+ /* Make sure bus-mastering is enabled. */
+ Value32 |= PCI_BUSMASTER_ENABLE;
#if PCIX_TARGET_WORKAROUND
- /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
- are enabled */
- if (pDevice->EnablePciXFix == TRUE) {
- Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
- PCI_PARITY_ERROR_ENABLE);
- }
- if (pDevice->UndiFix)
- {
- Value32 &= ~PCI_MEM_SPACE_ENABLE;
- }
-
+ /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
+ are enabled */
+ if (pDevice->EnablePciXFix == TRUE) {
+ Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
+ PCI_PARITY_ERROR_ENABLE);
+ }
+ if (pDevice->UndiFix) {
+ Value32 &= ~PCI_MEM_SPACE_ENABLE;
+ }
#endif
- if(pDevice->EnableMWI)
- {
- Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
- }
- else {
- Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
- }
-
- /* Error out if mem-mapping is NOT enabled for PCI systems */
- if (!(Value32 | PCI_MEM_SPACE_ENABLE))
- {
- return LM_STATUS_FAILURE;
- }
+ if (pDevice->EnableMWI) {
+ Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
+ } else {
+ Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
+ }
+
+ /* Error out if mem-mapping is NOT enabled for PCI systems */
+ if (!(Value32 | PCI_MEM_SPACE_ENABLE)) {
+ return LM_STATUS_FAILURE;
+ }
- /* save the value we are going to write into the PCI command word */
- pDevice->PciCommandStatusWords = Value32;
+ /* save the value we are going to write into the PCI command word */
+ pDevice->PciCommandStatusWords = Value32;
- Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
+ Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
- /* Set power state to D0. */
- LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
+ /* Set power state to D0. */
+ LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
#ifdef BIG_ENDIAN_PCI
- pDevice->MiscHostCtrl =
- MISC_HOST_CTRL_MASK_PCI_INT |
- MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
- MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
- MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#else /* No CPU Swap modes for PCI IO */
-
- /* Setup the mode registers. */
- pDevice->MiscHostCtrl =
- MISC_HOST_CTRL_MASK_PCI_INT |
- MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
+ pDevice->MiscHostCtrl =
+ MISC_HOST_CTRL_MASK_PCI_INT |
+ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
+ MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
+ MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
+#else /* No CPU Swap modes for PCI IO */
+
+ /* Setup the mode registers. */
+ pDevice->MiscHostCtrl =
+ MISC_HOST_CTRL_MASK_PCI_INT |
+ MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
#ifdef BIG_ENDIAN_HOST
- MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
-#endif /* BIG_ENDIAN_HOST */
- MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
- MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#endif /* !BIG_ENDIAN_PCI */
+ MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
+#endif /* BIG_ENDIAN_HOST */
+ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
+ MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
+#endif /* !BIG_ENDIAN_PCI */
- /* write to PCI misc host ctr first in order to enable indirect accesses */
- MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
+ /* write to PCI misc host ctr first in order to enable indirect accesses */
+ MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+ pDevice->MiscHostCtrl);
- REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
#ifdef BIG_ENDIAN_PCI
- Value32 = GRC_MODE_WORD_SWAP_DATA|
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+ Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
/* No CPU Swap modes for PCI IO */
#ifdef BIG_ENDIAN_HOST
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
#endif
-#endif /* !BIG_ENDIAN_PCI */
-
- REG_WR(pDevice, Grc.Mode, Value32);
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1);
- }
- MM_Wait(40);
-
- /* Enable indirect memory access */
- REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-
- if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK)
- {
- REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK);
- REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK);
- MM_Wait(40); /* required delay is 27usec */
- }
- REG_WR(pDevice, PciCfg.ClockCtrl, 0);
- REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
+#endif /* !BIG_ENDIAN_PCI */
+
+ REG_WR (pDevice, Grc.Mode, Value32);
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ REG_WR (pDevice, Grc.LocalCtrl,
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1);
+ }
+ MM_Wait (40);
+
+ /* Enable indirect memory access */
+ REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
+
+ if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) {
+ REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK);
+ REG_WR (pDevice, PciCfg.ClockCtrl,
+ T3_PCI_SELECT_ALTERNATE_CLOCK);
+ MM_Wait (40); /* required delay is 27usec */
+ }
+ REG_WR (pDevice, PciCfg.ClockCtrl, 0);
+ REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
#if PCIX_TARGET_WORKAROUND
- MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
- if ((pDevice->EnablePciXFix == FALSE) &&
- ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
- {
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
- {
- __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300]));
- __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
- __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
- if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
- {
- pDevice->EnablePciXFix = TRUE;
- }
+ MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
+ if ((pDevice->EnablePciXFix == FALSE) &&
+ ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) {
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B5) {
+ __raw_writel (0,
+ &(pDevice->pMemView->uIntMem.
+ MemBlock32K[0x300]));
+ __raw_writel (0,
+ &(pDevice->pMemView->uIntMem.
+ MemBlock32K[0x301]));
+ __raw_writel (0xffffffff,
+ &(pDevice->pMemView->uIntMem.
+ MemBlock32K[0x301]));
+ if (__raw_readl
+ (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
+ {
+ pDevice->EnablePciXFix = TRUE;
+ }
+ }
}
- }
#endif
#if 1
- /*
- * This code was at the beginning of else block below, but that's
- * a bug if node address in shared memory.
- */
- MM_Wait(50);
- LM_NvramInit(pDevice);
+ /*
+ * This code was at the beginning of else block below, but that's
+ * a bug if node address in shared memory.
+ */
+ MM_Wait (50);
+ LM_NvramInit (pDevice);
#endif
- /* Get the node address. First try to get in from the shared memory. */
- /* If the signature is not present, then get it from the NVRAM. */
- Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
- if((Value32 >> 16) == 0x484b)
- {
-
- pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[1] = (LM_UINT8) Value32;
-
- Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
-
- pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
- pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[5] = (LM_UINT8) Value32;
-
- Status = LM_STATUS_SUCCESS;
- }
- else
- {
- Status = LM_NvramRead(pDevice, 0x7c, &Value32);
- if(Status == LM_STATUS_SUCCESS)
- {
- pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
-
- Status = LM_NvramRead(pDevice, 0x80, &Value32);
-
- pDevice->NodeAddress[2] = (LM_UINT8) Value32;
- pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
+ /* Get the node address. First try to get in from the shared memory. */
+ /* If the signature is not present, then get it from the NVRAM. */
+ Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
+ if ((Value32 >> 16) == 0x484b) {
+
+ pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
+ pDevice->NodeAddress[1] = (LM_UINT8) Value32;
+
+ Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX);
+
+ pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
+ pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
+ pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
+ pDevice->NodeAddress[5] = (LM_UINT8) Value32;
+
+ Status = LM_STATUS_SUCCESS;
+ } else {
+ Status = LM_NvramRead (pDevice, 0x7c, &Value32);
+ if (Status == LM_STATUS_SUCCESS) {
+ pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
+ pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
+
+ Status = LM_NvramRead (pDevice, 0x80, &Value32);
+
+ pDevice->NodeAddress[2] = (LM_UINT8) Value32;
+ pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
+ pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
+ pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
+ }
}
- }
- /* Assign a default address. */
- if(Status != LM_STATUS_SUCCESS)
- {
+ /* Assign a default address. */
+ if (Status != LM_STATUS_SUCCESS) {
#ifndef EMBEDDED
- printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n");
-#endif
- pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10;
- pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68;
- pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76;
- }
-
- pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
- pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
- pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
- pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
- pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
- pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
-
- /* Initialize the default values. */
- pDevice->NoTxPseudoHdrChksum = FALSE;
- pDevice->NoRxPseudoHdrChksum = FALSE;
- pDevice->NicSendBd = FALSE;
- pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
- pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
- pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
- pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
- pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
- pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
- pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
- pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
- pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
- pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
- pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
- pDevice->EnableMWI = FALSE;
- pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- pDevice->DisableAutoNeg = FALSE;
- pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
- pDevice->LedMode = LED_MODE_AUTO;
- pDevice->ResetPhyOnInit = TRUE;
- pDevice->DelayPciGrant = TRUE;
- pDevice->UseTaggedStatus = FALSE;
- pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
-
- pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
- pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
- pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
-
- pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
- pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
- pDevice->EnableTbi = FALSE;
-#if INCLUDE_TBI_SUPPORT
- pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
+ printk (KERN_ERR
+ "Cannot get MAC addr from NVRAM. Using default.\n");
#endif
+ pDevice->NodeAddress[0] = 0x00;
+ pDevice->NodeAddress[1] = 0x10;
+ pDevice->NodeAddress[2] = 0x18;
+ pDevice->NodeAddress[3] = 0x68;
+ pDevice->NodeAddress[4] = 0x61;
+ pDevice->NodeAddress[5] = 0x76;
+ }
+
+ pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
+ pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
+ pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
+ pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
+ pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
+ pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
+
+ /* Initialize the default values. */
+ pDevice->NoTxPseudoHdrChksum = FALSE;
+ pDevice->NoRxPseudoHdrChksum = FALSE;
+ pDevice->NicSendBd = FALSE;
+ pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
+ pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
+ pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
+ pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
+ pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
+ pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
+ pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
+ pDevice->EnableMWI = FALSE;
+ pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+ pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+ pDevice->DisableAutoNeg = FALSE;
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
+ pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
+ pDevice->LedMode = LED_MODE_AUTO;
+ pDevice->ResetPhyOnInit = TRUE;
+ pDevice->DelayPciGrant = TRUE;
+ pDevice->UseTaggedStatus = FALSE;
+ pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
- switch (T3_ASIC_REV(pDevice->ChipRevId))
- {
- case T3_ASIC_REV_5704:
- pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
- pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
- break;
- default:
- pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
- pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
- break;
- }
-
- pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
- pDevice->QueueRxPackets = TRUE;
-
- pDevice->EnableWireSpeed = TRUE;
+ pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
+ pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
+ pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Make this is a known adapter. */
- pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId,
- pDevice->SubsystemId);
-
- pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
- if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
- pDevice->BondId != GRC_MISC_BD_ID_5701 &&
- pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
- pDevice->BondId != GRC_MISC_BD_ID_5703 &&
- pDevice->BondId != GRC_MISC_BD_ID_5703S &&
- pDevice->BondId != GRC_MISC_BD_ID_5704 &&
- pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE)
- {
- return LM_STATUS_UNKNOWN_ADAPTER;
- }
-
- pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
- if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
- (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE))
- {
- pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
- pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
- }
-
- /* Get Eeprom info. */
- Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
- if (Value32 == T3_NIC_DATA_SIG)
- {
- EeSigFound = TRUE;
- Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
-
- /* Determine PHY type. */
- switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
- {
- case T3_NIC_CFG_PHY_TYPE_COPPER:
- EePhyTypeSerdes = FALSE;
- break;
+ pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
+ pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
+ pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
+ pDevice->EnableTbi = FALSE;
+#if INCLUDE_TBI_SUPPORT
+ pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
+#endif
- case T3_NIC_CFG_PHY_TYPE_FIBER:
- EePhyTypeSerdes = TRUE;
+ switch (T3_ASIC_REV (pDevice->ChipRevId)) {
+ case T3_ASIC_REV_5704:
+ pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
+ pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
break;
-
- default:
- EePhyTypeSerdes = FALSE;
+ default:
+ pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
+ pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
break;
}
- /* Determine PHY led mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
- {
- case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
- EePhyLedMode = LED_MODE_THREE_LINK;
- break;
+ pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
+ pDevice->QueueRxPackets = TRUE;
- case T3_NIC_CFG_LED_MODE_LINK_SPEED:
- EePhyLedMode = LED_MODE_LINK10;
- break;
+ pDevice->EnableWireSpeed = TRUE;
- default:
- EePhyLedMode = LED_MODE_AUTO;
- break;
- }
- }
- else
- {
- switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
- {
- case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
- EePhyLedMode = LED_MODE_OPEN_DRAIN;
- break;
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+ pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Make this is a known adapter. */
+ pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId,
+ pDevice->SubsystemId);
+
+ pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
+ if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5701 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
+ pDevice->BondId != GRC_MISC_BD_ID_5703 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5703S &&
+ pDevice->BondId != GRC_MISC_BD_ID_5704 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) {
+ return LM_STATUS_UNKNOWN_ADAPTER;
+ }
+
+ pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
+ if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
+ (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) {
+ pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
+ pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
+ }
+
+ /* Get Eeprom info. */
+ Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR);
+ if (Value32 == T3_NIC_DATA_SIG) {
+ EeSigFound = TRUE;
+ Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
+
+ /* Determine PHY type. */
+ switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) {
+ case T3_NIC_CFG_PHY_TYPE_COPPER:
+ EePhyTypeSerdes = FALSE;
+ break;
- case T3_NIC_CFG_LED_MODE_OUTPUT:
- EePhyLedMode = LED_MODE_OUTPUT;
- break;
+ case T3_NIC_CFG_PHY_TYPE_FIBER:
+ EePhyTypeSerdes = TRUE;
+ break;
default:
- EePhyLedMode = LED_MODE_AUTO;
- break;
- }
- }
- if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
- pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
- {
- /* Enable EEPROM write protection. */
- if(Value32 & T3_NIC_EEPROM_WP)
- {
- pDevice->EepromWp = TRUE;
- }
- }
+ EePhyTypeSerdes = FALSE;
+ break;
+ }
- /* Get the PHY Id. */
- Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
- if (Value32)
- {
- EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
- PHY_ID1_OUI_MASK) << 10;
+ /* Determine PHY led mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
+ case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
+ EePhyLedMode = LED_MODE_THREE_LINK;
+ break;
+
+ case T3_NIC_CFG_LED_MODE_LINK_SPEED:
+ EePhyLedMode = LED_MODE_LINK10;
+ break;
+
+ default:
+ EePhyLedMode = LED_MODE_AUTO;
+ break;
+ }
+ } else {
+ switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
+ case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
+ EePhyLedMode = LED_MODE_OPEN_DRAIN;
+ break;
+
+ case T3_NIC_CFG_LED_MODE_OUTPUT:
+ EePhyLedMode = LED_MODE_OUTPUT;
+ break;
+
+ default:
+ EePhyLedMode = LED_MODE_AUTO;
+ break;
+ }
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
+ /* Enable EEPROM write protection. */
+ if (Value32 & T3_NIC_EEPROM_WP) {
+ pDevice->EepromWp = TRUE;
+ }
+ }
- Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
+ /* Get the PHY Id. */
+ Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR);
+ if (Value32) {
+ EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
+ PHY_ID1_OUI_MASK) << 10;
- EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
- (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
- }
- else
- {
- EePhyId = 0;
+ Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
+
+ EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
+ (Value32 & PHY_ID2_MODEL_MASK) | (Value32 &
+ PHY_ID2_REV_MASK);
+ } else {
+ EePhyId = 0;
+ }
+ } else {
+ EeSigFound = FALSE;
}
- }
- else
- {
- EeSigFound = FALSE;
- }
- /* Set the PHY address. */
- pDevice->PhyAddr = PHY_DEVICE_ID;
+ /* Set the PHY address. */
+ pDevice->PhyAddr = PHY_DEVICE_ID;
- /* Disable auto polling. */
- pDevice->MiMode = 0xc0000;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
+ /* Disable auto polling. */
+ pDevice->MiMode = 0xc0000;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
- /* Get the PHY id. */
- LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
- pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
+ /* Get the PHY id. */
+ LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32);
+ pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
- LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
- pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
- (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
+ LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32);
+ pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
+ (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
- /* Set the EnableTbi flag to false if we have a copper PHY. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Set the EnableTbi flag to false if we have a copper PHY. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM5400_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5401_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5411_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5701_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5703_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5704_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM8002_PHY_ID:
- pDevice->EnableTbi = TRUE;
- break;
+ pDevice->EnableTbi = TRUE;
+ break;
default:
- if (pAdapterInfo)
- {
- pDevice->PhyId = pAdapterInfo->PhyId;
- pDevice->EnableTbi = pAdapterInfo->Serdes;
- }
- else if (EeSigFound)
- {
- pDevice->PhyId = EePhyId;
- pDevice->EnableTbi = EePhyTypeSerdes;
- }
- break;
- }
-
- /* Bail out if we don't know the copper PHY id. */
- if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi)
- {
- return LM_STATUS_FAILURE;
- }
+ if (pAdapterInfo) {
+ pDevice->PhyId = pAdapterInfo->PhyId;
+ pDevice->EnableTbi = pAdapterInfo->Serdes;
+ } else if (EeSigFound) {
+ pDevice->PhyId = EePhyId;
+ pDevice->EnableTbi = EePhyTypeSerdes;
+ }
+ break;
+ }
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
- {
- if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
- {
- pDevice->SavedCacheLineReg &= 0xffff00ff;
- pDevice->SavedCacheLineReg |= 0x4000;
- }
- }
- /* Change driver parameters. */
- Status = MM_GetConfig(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
+ /* Bail out if we don't know the copper PHY id. */
+ if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) {
+ return LM_STATUS_FAILURE;
+ }
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
+ if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) {
+ pDevice->SavedCacheLineReg &= 0xffff00ff;
+ pDevice->SavedCacheLineReg |= 0x4000;
+ }
+ }
+ /* Change driver parameters. */
+ Status = MM_GetConfig (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
#if INCLUDE_5701_AX_FIX
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
- pDevice->ResetPhyOnInit = TRUE;
- }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+ pDevice->ResetPhyOnInit = TRUE;
+ }
#endif
- /* Save the current phy link status. */
- if(!pDevice->EnableTbi)
- {
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-
- /* If we don't have link reset the PHY. */
- if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit)
- {
+ /* Save the current phy link status. */
+ if (!pDevice->EnableTbi) {
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
+ /* If we don't have link reset the PHY. */
+ if (!(Value32 & PHY_STATUS_LINK_PASS)
+ || pDevice->ResetPhyOnInit) {
- for(j = 0; j < 100; j++)
- {
- MM_Wait(10);
+ LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET))
- {
- MM_Wait(40);
- break;
- }
- }
+ for (j = 0; j < 100; j++) {
+ MM_Wait (10);
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) {
+ MM_Wait (40);
+ break;
+ }
+ }
#if INCLUDE_5701_AX_FIX
- /* 5701_AX_BX bug: only advertises 10mb speed. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
-
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
- PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
- PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- Value32 = BCM540X_AN_AD_1000BASET_HALF |
- BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER |
- BCM540X_ENABLE_CONFIG_AS_MASTER;
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
-
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
- PHY_CTRL_RESTART_AUTO_NEG);
- }
+ /* 5701_AX_BX bug: only advertises 10mb speed. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+
+ Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
+ PHY_AN_AD_10BASET_HALF |
+ PHY_AN_AD_10BASET_FULL |
+ PHY_AN_AD_100BASETX_FULL |
+ PHY_AN_AD_100BASETX_HALF;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+
+ Value32 = BCM540X_AN_AD_1000BASET_HALF |
+ BCM540X_AN_AD_1000BASET_FULL |
+ BCM540X_CONFIG_AS_MASTER |
+ BCM540X_ENABLE_CONFIG_AS_MASTER;
+ LM_WritePhy (pDevice,
+ BCM540X_1000BASET_CTRL_REG,
+ Value32);
+ pDevice->advertising1000 = Value32;
+
+ LM_WritePhy (pDevice, PHY_CTRL_REG,
+ PHY_CTRL_AUTO_NEG_ENABLE |
+ PHY_CTRL_RESTART_AUTO_NEG);
+ }
#endif
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
- {
- LM_WritePhy(pDevice, 0x18, 0x0c00);
- LM_WritePhy(pDevice, 0x17, 0x201f);
- LM_WritePhy(pDevice, 0x15, 0x2aaa);
- }
- if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- LM_WritePhy(pDevice, 0x1c, 0x8d68);
- LM_WritePhy(pDevice, 0x1c, 0x8d68);
- }
- /* Enable Ethernet@WireSpeed. */
- if(pDevice->EnableWireSpeed)
- {
- LM_WritePhy(pDevice, 0x18, 0x7007);
- LM_ReadPhy(pDevice, 0x18, &Value32);
- LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
- }
- }
- }
-
- /* Turn off tap power management. */
- if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
- {
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
-
- MM_Wait(40);
- }
+ if (T3_ASIC_REV (pDevice->ChipRevId) ==
+ T3_ASIC_REV_5703) {
+ LM_WritePhy (pDevice, 0x18, 0x0c00);
+ LM_WritePhy (pDevice, 0x17, 0x201f);
+ LM_WritePhy (pDevice, 0x15, 0x2aaa);
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ LM_WritePhy (pDevice, 0x1c, 0x8d68);
+ LM_WritePhy (pDevice, 0x1c, 0x8d68);
+ }
+ /* Enable Ethernet@WireSpeed. */
+ if (pDevice->EnableWireSpeed) {
+ LM_WritePhy (pDevice, 0x18, 0x7007);
+ LM_ReadPhy (pDevice, 0x18, &Value32);
+ LM_WritePhy (pDevice, 0x18,
+ Value32 | BIT_15 | BIT_4);
+ }
+ }
+ }
-#if INCLUDE_TBI_SUPPORT
- pDevice->IgnoreTbiLinkChange = FALSE;
-
- if(pDevice->EnableTbi)
- {
- pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
- pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
- if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
- pDevice->DisableAutoNeg)
- {
- pDevice->PollTbiLink = FALSE;
- }
- }
- else
- {
- pDevice->PollTbiLink = FALSE;
- }
-#endif /* INCLUDE_TBI_SUPPORT */
-
- /* UseTaggedStatus is only valid for 5701 and later. */
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->UseTaggedStatus = FALSE;
+ /* Turn off tap power management. */
+ if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
- pDevice->CoalesceMode = 0;
- }
- else
- {
- pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
- HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
- }
-
- /* Set the status block size. */
- if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
- T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
- {
- pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
- }
-
- /* Check the DURING_INT coalescing ticks parameters. */
- if(pDevice->UseTaggedStatus)
- {
- if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxCoalescingTicksDuringInt =
- DEFAULT_RX_COALESCING_TICKS_DURING_INT;
+ MM_Wait (40);
}
-
- if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxCoalescingTicksDuringInt =
- DEFAULT_TX_COALESCING_TICKS_DURING_INT;
+#if INCLUDE_TBI_SUPPORT
+ pDevice->IgnoreTbiLinkChange = FALSE;
+
+ if (pDevice->EnableTbi) {
+ pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+ if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
+ pDevice->DisableAutoNeg) {
+ pDevice->PollTbiLink = FALSE;
+ }
+ } else {
+ pDevice->PollTbiLink = FALSE;
}
+#endif /* INCLUDE_TBI_SUPPORT */
- if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxMaxCoalescedFramesDuringInt =
- DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
- }
+ /* UseTaggedStatus is only valid for 5701 and later. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->UseTaggedStatus = FALSE;
- if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxMaxCoalescedFramesDuringInt =
- DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
- }
- }
- else
- {
- if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxCoalescingTicksDuringInt = 0;
+ pDevice->CoalesceMode = 0;
+ } else {
+ pDevice->CoalesceMode =
+ HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
+ HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
}
- if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxCoalescingTicksDuringInt = 0;
+ /* Set the status block size. */
+ if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
+ T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) {
+ pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
}
- if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxMaxCoalescedFramesDuringInt = 0;
- }
+ /* Check the DURING_INT coalescing ticks parameters. */
+ if (pDevice->UseTaggedStatus) {
+ if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxCoalescingTicksDuringInt =
+ DEFAULT_RX_COALESCING_TICKS_DURING_INT;
+ }
- if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxMaxCoalescedFramesDuringInt = 0;
- }
- }
+ if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxCoalescingTicksDuringInt =
+ DEFAULT_TX_COALESCING_TICKS_DURING_INT;
+ }
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
- {
- pDevice->RxJumboDescCnt = 0;
- if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
- {
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- }
- }
- else
- {
- pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
- COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
+ if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxMaxCoalescedFramesDuringInt =
+ DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
+ }
- if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
- {
- pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
- pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
- }
- pDevice->TxMtu = pDevice->RxMtu;
+ if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxMaxCoalescedFramesDuringInt =
+ DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
+ }
+ } else {
+ if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxCoalescingTicksDuringInt = 0;
+ }
- }
-#else
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxCoalescingTicksDuringInt = 0;
+ }
+
+ if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxMaxCoalescedFramesDuringInt = 0;
+ }
+
+ if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxMaxCoalescedFramesDuringInt = 0;
+ }
+ }
- pDevice->RxPacketDescCnt =
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboDescCnt +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- pDevice->RxStdDescCnt;
+ if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) {
+ pDevice->RxJumboDescCnt = 0;
+ if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
+ pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+ }
+ } else {
+ pDevice->RxJumboBufferSize =
+ (pDevice->RxMtu + 8 /* CRC + VLAN */ +
+ COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK;
+
+ if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) {
+ pDevice->RxJumboBufferSize =
+ DEFAULT_JUMBO_RCV_BUFFER_SIZE;
+ pDevice->RxMtu =
+ pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ;
+ }
+ pDevice->TxMtu = pDevice->RxMtu;
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
- {
- pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- }
+ }
+#else
+ pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
- {
- pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
- }
+ pDevice->RxPacketDescCnt =
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+ pDevice->RxJumboDescCnt +
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ pDevice->RxStdDescCnt;
- /* Configure the proper ways to get link change interrupt. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
+ pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
}
- else
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+
+ if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) {
+ pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
}
- }
- else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- /* Auto-polling does not work on 5700_AX and 5700_BX. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+
+ /* Configure the proper ways to get link change interrupt. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+ } else {
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+ }
+ } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ /* Auto-polling does not work on 5700_AX and 5700_BX. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+ }
}
- }
- /* Determine the method to get link change status. */
- if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
- {
- /* The link status bit in the status block does not work on 5700_AX */
- /* and 5700_BX chips. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
+ /* Determine the method to get link change status. */
+ if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) {
+ /* The link status bit in the status block does not work on 5700_AX */
+ /* and 5700_BX chips. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->LinkChngMode =
+ T3_LINK_CHNG_MODE_USE_STATUS_REG;
+ } else {
+ pDevice->LinkChngMode =
+ T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
+ }
}
- else
- {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
+
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
}
- }
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
- }
+ /* Configure PHY led mode. */
+ if (pDevice->LedMode == LED_MODE_AUTO) {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ if (pDevice->SubsystemVendorId == T3_SVID_DELL) {
+ pDevice->LedMode = LED_MODE_LINK10;
+ } else {
+ pDevice->LedMode = LED_MODE_THREE_LINK;
- /* Configure PHY led mode. */
- if(pDevice->LedMode == LED_MODE_AUTO)
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- if(pDevice->SubsystemVendorId == T3_SVID_DELL)
- {
- pDevice->LedMode = LED_MODE_LINK10;
- }
- else
- {
- pDevice->LedMode = LED_MODE_THREE_LINK;
-
- if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
- {
- pDevice->LedMode = EePhyLedMode;
- }
- }
-
- /* bug? 5701 in LINK10 mode does not seem to work when */
- /* PhyIntMode is LINK_READY. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
+ pDevice->LedMode = EePhyLedMode;
+ }
+ }
+
+ /* bug? 5701 in LINK10 mode does not seem to work when */
+ /* PhyIntMode is LINK_READY. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700
+ &&
#if INCLUDE_TBI_SUPPORT
- pDevice->EnableTbi == FALSE &&
+ pDevice->EnableTbi == FALSE &&
#endif
- pDevice->LedMode == LED_MODE_LINK10)
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
- }
+ pDevice->LedMode == LED_MODE_LINK10) {
+ pDevice->PhyIntMode =
+ T3_PHY_INT_MODE_MI_INTERRUPT;
+ pDevice->LinkChngMode =
+ T3_LINK_CHNG_MODE_USE_STATUS_REG;
+ }
+
+ if (pDevice->EnableTbi) {
+ pDevice->LedMode = LED_MODE_THREE_LINK;
+ }
+ } else {
+ if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
+ pDevice->LedMode = EePhyLedMode;
+ } else {
+ pDevice->LedMode = LED_MODE_OPEN_DRAIN;
+ }
+ }
+ }
- if(pDevice->EnableTbi)
- {
- pDevice->LedMode = LED_MODE_THREE_LINK;
- }
+ /* Enable OneDmaAtOnce. */
+ if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) {
+ pDevice->OneDmaAtOnce = FALSE;
}
- else
- {
- if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
- {
- pDevice->LedMode = EePhyLedMode;
- }
- else
- {
- pDevice->LedMode = LED_MODE_OPEN_DRAIN;
- }
- }
- }
-
- /* Enable OneDmaAtOnce. */
- if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE)
- {
- pDevice->OneDmaAtOnce = FALSE;
- }
-
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
- {
- pDevice->WolSpeed = WOL_SPEED_10MB;
- }
- else
- {
- pDevice->WolSpeed = WOL_SPEED_100MB;
- }
-
- /* Offloadings. */
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-
- /* Turn off task offloading on Ax. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
- {
- pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
- }
- pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
- LM_ReadVPD(pDevice);
- LM_ReadBootCodeVersion(pDevice);
- LM_GetBusSpeed(pDevice);
-
- return LM_STATUS_SUCCESS;
-} /* LM_GetAdapterInfo */
-
-STATIC PLM_ADAPTER_INFO
-LM_GetAdapterInfoBySsid(
- LM_UINT16 Svid,
- LM_UINT16 Ssid)
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B2) {
+ pDevice->WolSpeed = WOL_SPEED_10MB;
+ } else {
+ pDevice->WolSpeed = WOL_SPEED_100MB;
+ }
+
+ /* Offloadings. */
+ pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+
+ /* Turn off task offloading on Ax. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
+ pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
+ LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
+ }
+ pDevice->PciState = REG_RD (pDevice, PciCfg.PciState);
+ LM_ReadVPD (pDevice);
+ LM_ReadBootCodeVersion (pDevice);
+ LM_GetBusSpeed (pDevice);
+
+ return LM_STATUS_SUCCESS;
+} /* LM_GetAdapterInfo */
+
+STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid)
{
- static LM_ADAPTER_INFO AdapterArr[] =
- {
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0},
-
- { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
- { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
- { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
-
- { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
- { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
- { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
- { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
-
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
-
- };
- LM_UINT32 j;
-
- for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
- {
- if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
- {
- return &AdapterArr[j];
+ static LM_ADAPTER_INFO AdapterArr[] = {
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6,
+ PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6,
+ PHY_BCM8002_PHY_ID, 1},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2,
+ PHY_BCM5701_PHY_ID, 0},
+
+ {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1},
+ {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0},
+
+ {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0},
+ {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0},
+
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID,
+ 0},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID,
+ 0},
+
+ };
+ LM_UINT32 j;
+
+ for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) {
+ if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) {
+ return &AdapterArr[j];
+ }
}
- }
- return NULL;
+ return NULL;
}
-
/******************************************************************************/
/* Description: */
/* This routine sets up receive/transmit buffer descriptions queues. */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_InitializeAdapter(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice)
{
- LM_PHYSICAL_ADDRESS MemPhy;
- PLM_UINT8 pMemVirt;
- PLM_PACKET pPacket;
- LM_STATUS Status;
- LM_UINT32 Size;
- LM_UINT32 j;
-
- /* Set power state to D0. */
- LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
-
- /* Intialize the queues. */
- QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
- MAX_RX_PACKET_DESC_COUNT);
- QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
- MAX_RX_PACKET_DESC_COUNT);
-
- QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
- QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT);
- QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
-
- /* Allocate shared memory for: status block, the buffers for receive */
- /* rings -- standard, mini, jumbo, and return rings. */
- Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
- T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
+ LM_PHYSICAL_ADDRESS MemPhy;
+ PLM_UINT8 pMemVirt;
+ PLM_PACKET pPacket;
+ LM_STATUS Status;
+ LM_UINT32 Size;
+ LM_UINT32 j;
+
+ /* Set power state to D0. */
+ LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
+
+ /* Intialize the queues. */
+ QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container,
+ MAX_RX_PACKET_DESC_COUNT);
+ QQ_InitQueue (&pDevice->RxPacketFreeQ.Container,
+ MAX_RX_PACKET_DESC_COUNT);
+
+ QQ_InitQueue (&pDevice->TxPacketFreeQ.Container,
+ MAX_TX_PACKET_DESC_COUNT);
+ QQ_InitQueue (&pDevice->TxPacketActiveQ.Container,
+ MAX_TX_PACKET_DESC_COUNT);
+ QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container,
+ MAX_TX_PACKET_DESC_COUNT);
+
+ /* Allocate shared memory for: status block, the buffers for receive */
+ /* rings -- standard, mini, jumbo, and return rings. */
+ Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) +
+ T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
-
- /* Memory for host based Send BD. */
- if(pDevice->NicSendBd == FALSE)
- {
- Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
- }
-
- /* Allocate the memory block. */
- Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
-
- /* Program DMA Read/Write */
- if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
- {
- pDevice->DmaReadWriteCtrl = 0x763f000f;
- }
- else
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
- {
- pDevice->DmaReadWriteCtrl = 0x761f0000;
+ T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+
+ /* Memory for host based Send BD. */
+ if (pDevice->NicSendBd == FALSE) {
+ Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
+ }
+
+ /* Allocate the memory block. */
+ Status =
+ MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt,
+ &MemPhy, FALSE);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+
+ /* Program DMA Read/Write */
+ if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) {
+ pDevice->DmaReadWriteCtrl = 0x763f000f;
+ } else {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) {
+ pDevice->DmaReadWriteCtrl = 0x761f0000;
+ } else {
+ pDevice->DmaReadWriteCtrl = 0x761b000f;
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
+ pDevice->OneDmaAtOnce = TRUE;
+ }
}
- else
- {
- pDevice->DmaReadWriteCtrl = 0x761b000f;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
+ pDevice->DmaReadWriteCtrl &= 0xfffffff0;
+ }
+
+ if (pDevice->OneDmaAtOnce) {
+ pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
+ }
+ REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
+
+ if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) {
+ return LM_STATUS_FAILURE;
}
- if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
- pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
- {
- pDevice->OneDmaAtOnce = TRUE;
- }
- }
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
- {
- pDevice->DmaReadWriteCtrl &= 0xfffffff0;
- }
-
- if(pDevice->OneDmaAtOnce)
- {
- pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
- }
- REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
-
- if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
- /* Status block. */
- pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
- pDevice->StatusBlkPhy = MemPhy;
- pMemVirt += T3_STATUS_BLOCK_SIZE;
- LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
+ /* Status block. */
+ pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
+ pDevice->StatusBlkPhy = MemPhy;
+ pMemVirt += T3_STATUS_BLOCK_SIZE;
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE);
- /* Statistics block. */
- pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
- pDevice->StatsBlkPhy = MemPhy;
- pMemVirt += sizeof(T3_STATS_BLOCK);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
+ /* Statistics block. */
+ pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
+ pDevice->StatsBlkPhy = MemPhy;
+ pMemVirt += sizeof (T3_STATS_BLOCK);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK));
- /* Receive standard BD buffer. */
- pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RxStdBdPhy = MemPhy;
+ /* Receive standard BD buffer. */
+ pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
+ pDevice->RxStdBdPhy = MemPhy;
- pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
+ pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ T3_STD_RCV_RCB_ENTRY_COUNT *
+ sizeof (T3_RCV_BD));
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Receive jumbo BD buffer. */
- pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RxJumboBdPhy = MemPhy;
-
- pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Receive return BD buffer. */
- pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RcvRetBdPhy = MemPhy;
-
- pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
-
- /* Set up Send BD. */
- if(pDevice->NicSendBd == FALSE)
- {
- pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
- pDevice->SendBdPhy = MemPhy;
-
- pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
- }
- else
- {
- pDevice->pSendBdVirt = (PT3_SND_BD)
- pDevice->pMemView->uIntMem.First32k.BufferDesc;
- pDevice->SendBdPhy.High = 0;
- pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
- }
-
- /* Allocate memory for packet descriptors. */
- Size = (pDevice->RxPacketDescCnt +
- pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
- Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->pPacketDescBase = (PLM_VOID) pPacket;
-
- /* Create transmit packet descriptors from the memory block and add them */
- /* to the TxPacketFreeQ for each send ring. */
- for(j = 0; j < pDevice->TxPacketDescCnt; j++)
- {
- /* Ring index. */
- pPacket->Flags = 0;
-
- /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
- QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for(j.. */
-
- /* Create receive packet descriptors from the memory block and add them */
- /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
- for(j = 0; j < pDevice->RxStdDescCnt; j++)
- {
- /* Receive producer ring. */
- pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
-
- /* Receive buffer size. */
- pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
-
- /* Add the descriptor to RxPacketFreeQ. */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for */
+ /* Receive jumbo BD buffer. */
+ pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
+ pDevice->RxJumboBdPhy = MemPhy;
+
+ pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ T3_JUMBO_RCV_RCB_ENTRY_COUNT *
+ sizeof (T3_RCV_BD));
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Receive return BD buffer. */
+ pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
+ pDevice->RcvRetBdPhy = MemPhy;
+
+ pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ T3_RCV_RETURN_RCB_ENTRY_COUNT *
+ sizeof (T3_RCV_BD));
+
+ /* Set up Send BD. */
+ if (pDevice->NicSendBd == FALSE) {
+ pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
+ pDevice->SendBdPhy = MemPhy;
+
+ pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ sizeof (T3_SND_BD) *
+ T3_SEND_RCB_ENTRY_COUNT);
+ } else {
+ pDevice->pSendBdVirt = (PT3_SND_BD)
+ pDevice->pMemView->uIntMem.First32k.BufferDesc;
+ pDevice->SendBdPhy.High = 0;
+ pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
+ }
+
+ /* Allocate memory for packet descriptors. */
+ Size = (pDevice->RxPacketDescCnt +
+ pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
+ Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->pPacketDescBase = (PLM_VOID) pPacket;
+
+ /* Create transmit packet descriptors from the memory block and add them */
+ /* to the TxPacketFreeQ for each send ring. */
+ for (j = 0; j < pDevice->TxPacketDescCnt; j++) {
+ /* Ring index. */
+ pPacket->Flags = 0;
+
+ /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
+ QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
+
+ /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
+ /* is the total size of the packet descriptor including the */
+ /* os-specific extensions in the UM_PACKET structure. */
+ pPacket =
+ (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+ } /* for(j.. */
+
+ /* Create receive packet descriptors from the memory block and add them */
+ /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
+ for (j = 0; j < pDevice->RxStdDescCnt; j++) {
+ /* Receive producer ring. */
+ pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
+
+ /* Receive buffer size. */
+ pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
+
+ /* Add the descriptor to RxPacketFreeQ. */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+
+ /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
+ /* is the total size of the packet descriptor including the */
+ /* os-specific extensions in the UM_PACKET structure. */
+ pPacket =
+ (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+ } /* for */
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Create the Jumbo packet descriptors. */
- for(j = 0; j < pDevice->RxJumboDescCnt; j++)
- {
- /* Receive producer ring. */
- pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
-
- /* Receive buffer size. */
- pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
-
- /* Add the descriptor to RxPacketFreeQ. */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for */
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Initialize the rest of the packet descriptors. */
- Status = MM_InitializeUmPackets(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- } /* if */
+ /* Create the Jumbo packet descriptors. */
+ for (j = 0; j < pDevice->RxJumboDescCnt; j++) {
+ /* Receive producer ring. */
+ pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
- /* Default receive mask. */
- pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
- LM_ACCEPT_UNICAST;
+ /* Receive buffer size. */
+ pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
- /* Make sure we are in the first 32k memory window or NicSendBd. */
- REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
+ /* Add the descriptor to RxPacketFreeQ. */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- /* Initialize the hardware. */
- Status = LM_ResetAdapter(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
+ /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
+ /* is the total size of the packet descriptor including the */
+ /* os-specific extensions in the UM_PACKET structure. */
+ pPacket =
+ (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+ } /* for */
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Initialize the rest of the packet descriptors. */
+ Status = MM_InitializeUmPackets (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
- /* We are done with initialization. */
- pDevice->InitDone = TRUE;
+ /* if */
+ /* Default receive mask. */
+ pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
+ LM_ACCEPT_UNICAST;
- return LM_STATUS_SUCCESS;
-} /* LM_InitializeAdapter */
+ /* Make sure we are in the first 32k memory window or NicSendBd. */
+ REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
+ /* Initialize the hardware. */
+ Status = LM_ResetAdapter (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+
+ /* We are done with initialization. */
+ pDevice->InitDone = TRUE;
+
+ return LM_STATUS_SUCCESS;
+} /* LM_InitializeAdapter */
/******************************************************************************/
/* Description: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
LM_STATUS
-LM_CntrlBlock(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 mask,LM_UINT32 cntrl)
+LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl)
{
- LM_UINT32 j,i,data;
- LM_UINT32 MaxWaitCnt;
-
- MaxWaitCnt = 2;
- j = 0;
-
- for(i = 0 ; i < 32; i++)
- {
- if(!(mask & (1 << i)))
- continue;
-
- switch (1 << i)
- {
- case T3_BLOCK_DMA_RD:
- data = REG_RD(pDevice, DmaRead.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~DMA_READ_MODE_ENABLE;
- REG_WR(pDevice, DmaRead.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE);
- break;
-
- case T3_BLOCK_DMA_COMP:
- data = REG_RD(pDevice,DmaComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~DMA_COMP_MODE_ENABLE;
- REG_WR(pDevice, DmaComp.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE);
- break;
+ LM_UINT32 j, i, data;
+ LM_UINT32 MaxWaitCnt;
+
+ MaxWaitCnt = 2;
+ j = 0;
+
+ for (i = 0; i < 32; i++) {
+ if (!(mask & (1 << i)))
+ continue;
+
+ switch (1 << i) {
+ case T3_BLOCK_DMA_RD:
+ data = REG_RD (pDevice, DmaRead.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~DMA_READ_MODE_ENABLE;
+ REG_WR (pDevice, DmaRead.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, DmaRead.Mode) &
+ DMA_READ_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, DmaRead.Mode,
+ data | DMA_READ_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_BD_INITIATOR:
- data = REG_RD(pDevice, RcvBdIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_BD_IN_MODE_ENABLE;
- REG_WR(pDevice, RcvBdIn.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_DMA_COMP:
+ data = REG_RD (pDevice, DmaComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~DMA_COMP_MODE_ENABLE;
+ REG_WR (pDevice, DmaComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, DmaComp.Mode) &
+ DMA_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, DmaComp.Mode,
+ data | DMA_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_BD_COMP:
- data = REG_RD(pDevice, RcvBdComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_BD_COMP_MODE_ENABLE;
- REG_WR(pDevice, RcvBdComp.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_BD_INITIATOR:
+ data = REG_RD (pDevice, RcvBdIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_BD_IN_MODE_ENABLE;
+ REG_WR (pDevice, RcvBdIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvBdIn.Mode) &
+ RCV_BD_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvBdIn.Mode,
+ data | RCV_BD_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_DMA_WR:
- data = REG_RD(pDevice, DmaWrite.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~DMA_WRITE_MODE_ENABLE;
- REG_WR(pDevice, DmaWrite.Mode,data);
+ case T3_BLOCK_RX_BD_COMP:
+ data = REG_RD (pDevice, RcvBdComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_BD_COMP_MODE_ENABLE;
+ REG_WR (pDevice, RcvBdComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvBdComp.Mode) &
+ RCV_BD_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvBdComp.Mode,
+ data | RCV_BD_COMP_MODE_ENABLE);
+ break;
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE);
- break;
+ case T3_BLOCK_DMA_WR:
+ data = REG_RD (pDevice, DmaWrite.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~DMA_WRITE_MODE_ENABLE;
+ REG_WR (pDevice, DmaWrite.Mode, data);
+
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, DmaWrite.Mode) &
+ DMA_WRITE_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, DmaWrite.Mode,
+ data | DMA_WRITE_MODE_ENABLE);
+ break;
- case T3_BLOCK_MSI_HANDLER:
- data = REG_RD(pDevice, Msi.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~MSI_MODE_ENABLE;
- REG_WR(pDevice, Msi.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE);
- break;
+ case T3_BLOCK_MSI_HANDLER:
+ data = REG_RD (pDevice, Msi.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~MSI_MODE_ENABLE;
+ REG_WR (pDevice, Msi.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, Msi.Mode) &
+ MSI_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, Msi.Mode,
+ data | MSI_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_LIST_PLMT:
- data = REG_RD(pDevice, RcvListPlmt.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_LIST_PLMT_MODE_ENABLE;
- REG_WR(pDevice, RcvListPlmt.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_LIST_PLMT:
+ data = REG_RD (pDevice, RcvListPlmt.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_LIST_PLMT_MODE_ENABLE;
+ REG_WR (pDevice, RcvListPlmt.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvListPlmt.Mode)
+ & RCV_LIST_PLMT_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvListPlmt.Mode,
+ data | RCV_LIST_PLMT_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_LIST_SELECTOR:
- data = REG_RD(pDevice, RcvListSel.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_LIST_SEL_MODE_ENABLE;
- REG_WR(pDevice, RcvListSel.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_LIST_SELECTOR:
+ data = REG_RD (pDevice, RcvListSel.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_LIST_SEL_MODE_ENABLE;
+ REG_WR (pDevice, RcvListSel.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvListSel.Mode) &
+ RCV_LIST_SEL_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvListSel.Mode,
+ data | RCV_LIST_SEL_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_DATA_INITIATOR:
- data = REG_RD(pDevice, RcvDataBdIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
- REG_WR(pDevice, RcvDataBdIn.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_DATA_INITIATOR:
+ data = REG_RD (pDevice, RcvDataBdIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
+ REG_WR (pDevice, RcvDataBdIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvDataBdIn.Mode)
+ & RCV_DATA_BD_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvDataBdIn.Mode,
+ data | RCV_DATA_BD_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_DATA_COMP:
- data = REG_RD(pDevice, RcvDataComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_DATA_COMP_MODE_ENABLE;
- REG_WR(pDevice, RcvDataComp.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_DATA_COMP:
+ data = REG_RD (pDevice, RcvDataComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_DATA_COMP_MODE_ENABLE;
+ REG_WR (pDevice, RcvDataComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvDataBdIn.Mode)
+ & RCV_DATA_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvDataComp.Mode,
+ data | RCV_DATA_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_HOST_COALESING:
- data = REG_RD(pDevice, HostCoalesce.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~HOST_COALESCE_ENABLE;
- REG_WR(pDevice, HostCoalesce.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE);
- break;
+ case T3_BLOCK_HOST_COALESING:
+ data = REG_RD (pDevice, HostCoalesce.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~HOST_COALESCE_ENABLE;
+ REG_WR (pDevice, HostCoalesce.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdIn.Mode) &
+ HOST_COALESCE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, HostCoalesce.Mode,
+ data | HOST_COALESCE_ENABLE);
+ break;
- case T3_BLOCK_MAC_RX_ENGINE:
- if(cntrl == LM_DISABLE)
- {
- pDevice->RxMode &= ~RX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
- {
- break;
+ case T3_BLOCK_MAC_RX_ENGINE:
+ if (cntrl == LM_DISABLE) {
+ pDevice->RxMode &= ~RX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.RxMode,
+ pDevice->RxMode);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, MacCtrl.RxMode) &
+ RX_MODE_ENABLE)) {
+ break;
+ }
+ MM_Wait (10);
+ }
+ } else {
+ pDevice->RxMode |= RX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.RxMode,
+ pDevice->RxMode);
}
- MM_Wait(10);
- }
- }
- else
- {
- pDevice->RxMode |= RX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
- }
- break;
+ break;
- case T3_BLOCK_MBUF_CLUSTER_FREE:
- data = REG_RD(pDevice, MbufClusterFree.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
- REG_WR(pDevice, MbufClusterFree.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE);
- break;
+ case T3_BLOCK_MBUF_CLUSTER_FREE:
+ data = REG_RD (pDevice, MbufClusterFree.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
+ REG_WR (pDevice, MbufClusterFree.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD
+ (pDevice,
+ MbufClusterFree.
+ Mode) &
+ MBUF_CLUSTER_FREE_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, MbufClusterFree.Mode,
+ data | MBUF_CLUSTER_FREE_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_BD_INITIATOR:
- data = REG_RD(pDevice, SndBdIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_BD_IN_MODE_ENABLE;
- REG_WR(pDevice, SndBdIn.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_BD_INITIATOR:
+ data = REG_RD (pDevice, SndBdIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_BD_IN_MODE_ENABLE;
+ REG_WR (pDevice, SndBdIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdIn.Mode) &
+ SND_BD_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndBdIn.Mode,
+ data | SND_BD_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_BD_COMP:
- data = REG_RD(pDevice, SndBdComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_BD_COMP_MODE_ENABLE;
- REG_WR(pDevice, SndBdComp.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_BD_COMP:
+ data = REG_RD (pDevice, SndBdComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_BD_COMP_MODE_ENABLE;
+ REG_WR (pDevice, SndBdComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdComp.Mode) &
+ SND_BD_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndBdComp.Mode,
+ data | SND_BD_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_BD_SELECTOR:
- data = REG_RD(pDevice, SndBdSel.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_BD_SEL_MODE_ENABLE;
- REG_WR(pDevice, SndBdSel.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_BD_SELECTOR:
+ data = REG_RD (pDevice, SndBdSel.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_BD_SEL_MODE_ENABLE;
+ REG_WR (pDevice, SndBdSel.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdSel.Mode) &
+ SND_BD_SEL_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndBdSel.Mode,
+ data | SND_BD_SEL_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_DATA_INITIATOR:
- data = REG_RD(pDevice, SndDataIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~T3_SND_DATA_IN_MODE_ENABLE;
- REG_WR(pDevice, SndDataIn.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_DATA_INITIATOR:
+ data = REG_RD (pDevice, SndDataIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~T3_SND_DATA_IN_MODE_ENABLE;
+ REG_WR (pDevice, SndDataIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndDataIn.Mode) &
+ T3_SND_DATA_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndDataIn.Mode,
+ data | T3_SND_DATA_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_DATA_COMP:
- data = REG_RD(pDevice, SndDataComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_DATA_COMP_MODE_ENABLE;
- REG_WR(pDevice, SndDataComp.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_DATA_COMP:
+ data = REG_RD (pDevice, SndDataComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_DATA_COMP_MODE_ENABLE;
+ REG_WR (pDevice, SndDataComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndDataComp.Mode)
+ & SND_DATA_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndDataComp.Mode,
+ data | SND_DATA_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_MAC_TX_ENGINE:
- if(cntrl == LM_DISABLE)
- {
- pDevice->TxMode &= ~TX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- {
- pDevice->TxMode |= TX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
- }
- break;
+ case T3_BLOCK_MAC_TX_ENGINE:
+ if (cntrl == LM_DISABLE) {
+ pDevice->TxMode &= ~TX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.TxMode,
+ pDevice->TxMode);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, MacCtrl.TxMode) &
+ TX_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else {
+ pDevice->TxMode |= TX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.TxMode,
+ pDevice->TxMode);
+ }
+ break;
- case T3_BLOCK_MEM_ARBITOR:
- data = REG_RD(pDevice, MemArbiter.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~T3_MEM_ARBITER_MODE_ENABLE;
- REG_WR(pDevice, MemArbiter.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE);
- break;
+ case T3_BLOCK_MEM_ARBITOR:
+ data = REG_RD (pDevice, MemArbiter.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~T3_MEM_ARBITER_MODE_ENABLE;
+ REG_WR (pDevice, MemArbiter.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, MemArbiter.Mode) &
+ T3_MEM_ARBITER_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, MemArbiter.Mode,
+ data | T3_MEM_ARBITER_MODE_ENABLE);
+ break;
- case T3_BLOCK_MBUF_MANAGER:
- data = REG_RD(pDevice, BufMgr.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~BUFMGR_MODE_ENABLE;
- REG_WR(pDevice, BufMgr.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE);
- break;
+ case T3_BLOCK_MBUF_MANAGER:
+ data = REG_RD (pDevice, BufMgr.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~BUFMGR_MODE_ENABLE;
+ REG_WR (pDevice, BufMgr.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, BufMgr.Mode) &
+ BUFMGR_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, BufMgr.Mode,
+ data | BUFMGR_MODE_ENABLE);
+ break;
- case T3_BLOCK_MAC_GLOBAL:
- if(cntrl == LM_DISABLE)
- {
- pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE |
- MAC_MODE_ENABLE_FHDE);
- }
- else
- {
- pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE |
- MAC_MODE_ENABLE_FHDE);
- }
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
- break;
+ case T3_BLOCK_MAC_GLOBAL:
+ if (cntrl == LM_DISABLE) {
+ pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
+ MAC_MODE_ENABLE_RDE |
+ MAC_MODE_ENABLE_FHDE);
+ } else {
+ pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
+ MAC_MODE_ENABLE_RDE |
+ MAC_MODE_ENABLE_FHDE);
+ }
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
+ break;
- default:
- return LM_STATUS_FAILURE;
- } /* switch */
+ default:
+ return LM_STATUS_FAILURE;
+ } /* switch */
- if(j >= MaxWaitCnt)
- {
- return LM_STATUS_FAILURE;
+ if (j >= MaxWaitCnt) {
+ return LM_STATUS_FAILURE;
+ }
}
- }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
/******************************************************************************/
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_ResetAdapter(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT16 Value16;
- LM_UINT32 j, k;
+ LM_UINT32 Value32;
+ LM_UINT16 Value16;
+ LM_UINT32 j, k;
- /* Disable interrupt. */
- LM_DisableInterrupt(pDevice);
+ /* Disable interrupt. */
+ LM_DisableInterrupt (pDevice);
- /* May get a spurious interrupt */
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
+ /* May get a spurious interrupt */
+ pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
- /* Disable transmit and receive DMA engines. Abort all pending requests. */
- if(pDevice->InitDone)
- {
- LM_Abort(pDevice);
- }
+ /* Disable transmit and receive DMA engines. Abort all pending requests. */
+ if (pDevice->InitDone) {
+ LM_Abort (pDevice);
+ }
- pDevice->ShuttingDown = FALSE;
+ pDevice->ShuttingDown = FALSE;
- LM_ResetChip(pDevice);
+ LM_ResetChip (pDevice);
- /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
- /* in other chip revisions. */
- if(pDevice->DelayPciGrant)
- {
- Value32 = REG_RD(pDevice, PciCfg.ClockCtrl);
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
- }
+ /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
+ /* in other chip revisions. */
+ if (pDevice->DelayPciGrant) {
+ Value32 = REG_RD (pDevice, PciCfg.ClockCtrl);
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
+ }
- if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- Value32 = REG_RD(pDevice, PciCfg.PciState);
- Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
- REG_WR(pDevice, PciCfg.PciState, Value32);
- }
- }
-
- /* Enable TaggedStatus mode. */
- if(pDevice->UseTaggedStatus)
- {
- pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
- }
-
- /* Restore PCI configuration registers. */
- MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
- pDevice->SavedCacheLineReg);
- MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
- (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
-
- /* Clear the statistics block. */
- for(j = 0x0300; j < 0x0b00; j++)
- {
- MEM_WR_OFFSET(pDevice, j, 0);
- }
-
- /* Initialize the statistis Block */
- pDevice->pStatusBlkVirt->Status = 0;
- pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
- pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
- pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
-
- for(j = 0; j < 16; j++)
- {
- pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
- pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
- }
-
- for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
- {
- pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
- pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
- }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ Value32 = REG_RD (pDevice, PciCfg.PciState);
+ Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+ REG_WR (pDevice, PciCfg.PciState, Value32);
+ }
+ }
+
+ /* Enable TaggedStatus mode. */
+ if (pDevice->UseTaggedStatus) {
+ pDevice->MiscHostCtrl |=
+ MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
+ }
+
+ /* Restore PCI configuration registers. */
+ MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
+ pDevice->SavedCacheLineReg);
+ MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
+ (pDevice->SubsystemId << 16) | pDevice->
+ SubsystemVendorId);
+
+ /* Clear the statistics block. */
+ for (j = 0x0300; j < 0x0b00; j++) {
+ MEM_WR_OFFSET (pDevice, j, 0);
+ }
+
+ /* Initialize the statistis Block */
+ pDevice->pStatusBlkVirt->Status = 0;
+ pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+
+ for (j = 0; j < 16; j++) {
+ pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
+ pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
+ }
+
+ for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) {
+ pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
+ pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
+ }
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Receive jumbo BD buffer. */
- for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
- {
- pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
- pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
- }
+ /* Receive jumbo BD buffer. */
+ for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) {
+ pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
+ pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
+ }
#endif
- REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
+ REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
- /* GRC mode control register. */
-#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */
- Value32 =
- GRC_MODE_WORD_SWAP_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_INT_ON_MAC_ATTN |
- GRC_MODE_HOST_STACK_UP;
+ /* GRC mode control register. */
+#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */
+ Value32 =
+ GRC_MODE_WORD_SWAP_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
#else
- /* No CPU Swap modes for PCI IO */
- Value32 =
+ /* No CPU Swap modes for PCI IO */
+ Value32 =
#ifdef BIG_ENDIAN_HOST
- GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA |
- GRC_MODE_WORD_SWAP_DATA |
+ GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
#else
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA |
- GRC_MODE_WORD_SWAP_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
#endif
- GRC_MODE_INT_ON_MAC_ATTN |
- GRC_MODE_HOST_STACK_UP;
-#endif /* !BIG_ENDIAN_PCI */
-
- /* Configure send BD mode. */
- if(pDevice->NicSendBd == FALSE)
- {
- Value32 |= GRC_MODE_HOST_SEND_BDS;
- }
- else
- {
- Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
- }
-
- /* Configure pseudo checksum mode. */
- if(pDevice->NoTxPseudoHdrChksum)
- {
- Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
- }
-
- if(pDevice->NoRxPseudoHdrChksum)
- {
- Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
- }
-
- REG_WR(pDevice, Grc.Mode, Value32);
-
- /* Setup the timer prescalar register. */
- REG_WR(pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
-
- /* Set up the MBUF pool base address and size. */
- REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
- REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
-
- /* Set up the DMA descriptor pool base address and size. */
- REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
- REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
-
- /* Configure MBUF and Threshold watermarks */
- /* Configure the DMA read MBUF low water mark. */
- if(pDevice->DmaMbufLowMark)
- {
- REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
- pDevice->DmaMbufLowMark);
- }
- else
- {
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
- {
- REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
- T3_DEF_DMA_MBUF_LOW_WMARK);
+ GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
+#endif /* !BIG_ENDIAN_PCI */
+
+ /* Configure send BD mode. */
+ if (pDevice->NicSendBd == FALSE) {
+ Value32 |= GRC_MODE_HOST_SEND_BDS;
+ } else {
+ Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
}
- else
- {
- REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
- T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
- }
- }
-
- /* Configure the MAC Rx MBUF low water mark. */
- if(pDevice->RxMacMbufLowMark)
- {
- REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
- pDevice->RxMacMbufLowMark);
- }
- else
- {
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
- {
- REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
- T3_DEF_RX_MAC_MBUF_LOW_WMARK);
+
+ /* Configure pseudo checksum mode. */
+ if (pDevice->NoTxPseudoHdrChksum) {
+ Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
}
- else
- {
- REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
- T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
- }
- }
-
- /* Configure the MBUF high water mark. */
- if(pDevice->MbufHighMark)
- {
- REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark);
- }
- else
- {
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
- {
- REG_WR(pDevice, BufMgr.MbufHighWaterMark,
- T3_DEF_MBUF_HIGH_WMARK);
+
+ if (pDevice->NoRxPseudoHdrChksum) {
+ Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
}
- else
- {
- REG_WR(pDevice, BufMgr.MbufHighWaterMark,
- T3_DEF_MBUF_HIGH_WMARK_JUMBO);
+
+ REG_WR (pDevice, Grc.Mode, Value32);
+
+ /* Setup the timer prescalar register. */
+ REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
+
+ /* Set up the MBUF pool base address and size. */
+ REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
+ REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
+
+ /* Set up the DMA descriptor pool base address and size. */
+ REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
+ REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
+
+ /* Configure MBUF and Threshold watermarks */
+ /* Configure the DMA read MBUF low water mark. */
+ if (pDevice->DmaMbufLowMark) {
+ REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+ pDevice->DmaMbufLowMark);
+ } else {
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+ REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+ T3_DEF_DMA_MBUF_LOW_WMARK);
+ } else {
+ REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+ T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
+ }
}
- }
- REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
- REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
+ /* Configure the MAC Rx MBUF low water mark. */
+ if (pDevice->RxMacMbufLowMark) {
+ REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+ pDevice->RxMacMbufLowMark);
+ } else {
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+ REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+ T3_DEF_RX_MAC_MBUF_LOW_WMARK);
+ } else {
+ REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+ T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
+ }
+ }
- /* Enable buffer manager. */
- REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
+ /* Configure the MBUF high water mark. */
+ if (pDevice->MbufHighMark) {
+ REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+ pDevice->MbufHighMark);
+ } else {
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+ REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+ T3_DEF_MBUF_HIGH_WMARK);
+ } else {
+ REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+ T3_DEF_MBUF_HIGH_WMARK_JUMBO);
+ }
+ }
- for(j = 0 ;j < 2000; j++)
- {
- if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
- break;
- MM_Wait(10);
- }
+ REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
+ REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
- if(j >= 2000)
- {
- return LM_STATUS_FAILURE;
- }
-
- /* Enable the FTQs. */
- REG_WR(pDevice, Ftq.Reset, 0xffffffff);
- REG_WR(pDevice, Ftq.Reset, 0);
-
- /* Wait until FTQ is ready */
- for(j = 0; j < 2000; j++)
- {
- if(REG_RD(pDevice, Ftq.Reset) == 0)
- break;
- MM_Wait(10);
- }
-
- if(j >= 2000)
- {
- return LM_STATUS_FAILURE;
- }
-
- /* Initialize the Standard Receive RCB. */
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
- pDevice->RxStdBdPhy.High);
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
- pDevice->RxStdBdPhy.Low);
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
- MAX_STD_RCV_BUFFER_SIZE << 16);
-
- /* Initialize the Jumbo Receive RCB. */
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
- pDevice->RxJumboBdPhy.High);
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
- pDevice->RxJumboBdPhy.Low);
+ /* Enable buffer manager. */
+ REG_WR (pDevice, BufMgr.Mode,
+ BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
+
+ for (j = 0; j < 2000; j++) {
+ if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
+ break;
+ MM_Wait (10);
+ }
+
+ if (j >= 2000) {
+ return LM_STATUS_FAILURE;
+ }
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
+ /* Enable the FTQs. */
+ REG_WR (pDevice, Ftq.Reset, 0xffffffff);
+ REG_WR (pDevice, Ftq.Reset, 0);
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ /* Wait until FTQ is ready */
+ for (j = 0; j < 2000; j++) {
+ if (REG_RD (pDevice, Ftq.Reset) == 0)
+ break;
+ MM_Wait (10);
+ }
- /* Initialize the Mini Receive RCB. */
- REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
+ if (j >= 2000) {
+ return LM_STATUS_FAILURE;
+ }
- {
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
- (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
- (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
- }
+ /* Initialize the Standard Receive RCB. */
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
+ pDevice->RxStdBdPhy.High);
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
+ pDevice->RxStdBdPhy.Low);
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
+ MAX_STD_RCV_BUFFER_SIZE << 16);
- /* Receive BD Ring replenish threshold. */
- REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
+ /* Initialize the Jumbo Receive RCB. */
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
+ pDevice->RxJumboBdPhy.High);
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
+ pDevice->RxJumboBdPhy.Low);
+
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
- /* Disable all the unused rings. */
- for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
- MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
- } /* for */
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- /* Initialize the indices. */
- pDevice->SendProdIdx = 0;
- pDevice->SendConIdx = 0;
+ /* Initialize the Mini Receive RCB. */
+ REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
+ {
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
+ (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
+ (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
+ }
+
+ /* Receive BD Ring replenish threshold. */
+ REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8);
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+ REG_WR (pDevice, RcvBdIn.JumboRcvThreshold,
+ pDevice->RxJumboDescCnt / 8);
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Disable all the unused rings. */
+ for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
+ MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
+ } /* for */
+
+ /* Initialize the indices. */
+ pDevice->SendProdIdx = 0;
+ pDevice->SendConIdx = 0;
+
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
+
+ /* Set up host or NIC based send RCB. */
+ if (pDevice->NicSendBd == FALSE) {
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.High,
+ pDevice->SendBdPhy.High);
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low,
+ pDevice->SendBdPhy.Low);
+
+ /* Set up the NIC ring address in the RCB. */
+ MEM_WR (pDevice, SendRcb[0].NicRingAddr,
+ T3_NIC_SND_BUFFER_DESC_ADDR);
+
+ /* Setup the RCB. */
+ MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags,
+ T3_SEND_RCB_ENTRY_COUNT << 16);
+
+ for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
+ pDevice->pSendBdVirt[k].HostAddr.High = 0;
+ pDevice->pSendBdVirt[k].HostAddr.Low = 0;
+ }
+ } else {
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0);
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0);
+ MEM_WR (pDevice, SendRcb[0].NicRingAddr,
+ pDevice->SendBdPhy.Low);
+
+ for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
+ __raw_writel (0,
+ &(pDevice->pSendBdVirt[k].HostAddr.High));
+ __raw_writel (0,
+ &(pDevice->pSendBdVirt[k].HostAddr.Low));
+ __raw_writel (0,
+ &(pDevice->pSendBdVirt[k].u1.Len_Flags));
+ pDevice->ShadowSendBd[k].HostAddr.High = 0;
+ pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
+ }
+ }
+ atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1);
+
+ /* Configure the receive return rings. */
+ for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) {
+ MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
+ }
- /* Set up host or NIC based send RCB. */
- if(pDevice->NicSendBd == FALSE)
- {
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
- pDevice->SendBdPhy.High);
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
- pDevice->SendBdPhy.Low);
+ pDevice->RcvRetConIdx = 0;
+
+ MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High,
+ pDevice->RcvRetBdPhy.High);
+ MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low,
+ pDevice->RcvRetBdPhy.Low);
/* Set up the NIC ring address in the RCB. */
- MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
+ /* Not very clear from the spec. I am guessing that for Receive */
+ /* Return Ring, NicRingAddr is not used. */
+ MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0);
/* Setup the RCB. */
- MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
- T3_SEND_RCB_ENTRY_COUNT << 16);
+ MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags,
+ T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
- for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
- {
- pDevice->pSendBdVirt[k].HostAddr.High = 0;
- pDevice->pSendBdVirt[k].HostAddr.Low = 0;
- }
- }
- else
- {
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
- MEM_WR(pDevice, SendRcb[0].NicRingAddr,
- pDevice->SendBdPhy.Low);
-
- for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
- {
- __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High));
- __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low));
- __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags));
- pDevice->ShadowSendBd[k].HostAddr.High = 0;
- pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
- }
- }
- atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
-
- /* Configure the receive return rings. */
- for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
- {
- MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
- }
-
- pDevice->RcvRetConIdx = 0;
-
- MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
- pDevice->RcvRetBdPhy.High);
- MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
- pDevice->RcvRetBdPhy.Low);
-
- /* Set up the NIC ring address in the RCB. */
- /* Not very clear from the spec. I am guessing that for Receive */
- /* Return Ring, NicRingAddr is not used. */
- MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
-
- /* Setup the RCB. */
- MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
- T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
-
- /* Reinitialize RX ring producer index */
- MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
- MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
- MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
+ /* Reinitialize RX ring producer index */
+ MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0);
+ MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
+ MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboProdIdx = 0;
- pDevice->RxJumboQueuedCnt = 0;
+ pDevice->RxJumboProdIdx = 0;
+ pDevice->RxJumboQueuedCnt = 0;
#endif
- /* Reinitialize our copy of the indices. */
- pDevice->RxStdProdIdx = 0;
- pDevice->RxStdQueuedCnt = 0;
+ /* Reinitialize our copy of the indices. */
+ pDevice->RxStdProdIdx = 0;
+ pDevice->RxStdQueuedCnt = 0;
#if T3_JUMBO_RCV_ENTRY_COUNT
- pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_ENTRY_COUNT */
-
- /* Configure the MAC address. */
- LM_SetMacAddress(pDevice, pDevice->NodeAddress);
-
- /* Initialize the transmit random backoff seed. */
- Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
- pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
- pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
- MAC_TX_BACKOFF_SEED_MASK;
- REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
-
- /* Receive MTU. Frames larger than the MTU is marked as oversized. */
- REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
-
- /* Configure Time slot/IPG per 802.3 */
- REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
-
- /*
- * Configure Receive Rules so that packets don't match
- * Programmble rule will be queued to Return Ring 1
- */
- REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
-
- /*
- * Configure to have 16 Classes of Services (COS) and one
- * queue per class. Bad frames are queued to RRR#1.
- * And frames don't match rules are also queued to COS#1.
- */
- REG_WR(pDevice, RcvListPlmt.Config, 0x181);
-
- /* Enable Receive Placement Statistics */
- REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
- REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
-
- /* Enable Send Data Initator Statistics */
- REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
- REG_WR(pDevice, SndDataIn.StatsCtrl,
- T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
- T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
-
- /* Disable the host coalescing state machine before configuring it's */
- /* parameters. */
- REG_WR(pDevice, HostCoalesce.Mode, 0);
- for(j = 0; j < 2000; j++)
- {
- Value32 = REG_RD(pDevice, HostCoalesce.Mode);
- if(!(Value32 & HOST_COALESCE_ENABLE))
- {
- break;
- }
- MM_Wait(10);
- }
-
- /* Host coalescing configurations. */
- REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
- REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
- REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
- pDevice->RxMaxCoalescedFrames);
- REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
- pDevice->TxMaxCoalescedFrames);
- REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
- pDevice->RxCoalescingTicksDuringInt);
- REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
- pDevice->TxCoalescingTicksDuringInt);
- REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
- pDevice->RxMaxCoalescedFramesDuringInt);
- REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
- pDevice->TxMaxCoalescedFramesDuringInt);
-
- /* Initialize the address of the status block. The NIC will DMA */
- /* the status block to this memory which resides on the host. */
- REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
- pDevice->StatusBlkPhy.High);
- REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
- pDevice->StatusBlkPhy.Low);
-
- /* Initialize the address of the statistics block. The NIC will DMA */
- /* the statistics to this block of memory. */
- REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
- pDevice->StatsBlkPhy.High);
- REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
- pDevice->StatsBlkPhy.Low);
-
- REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
- pDevice->StatsCoalescingTicks);
-
- REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
- REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
-
- /* Enable Host Coalesing state machine */
- REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
- pDevice->CoalesceMode);
-
- /* Enable the Receive BD Completion state machine. */
- REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
- RCV_BD_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Receive List Placement state machine. */
- REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
-
- /* Enable the Receive List Selector state machine. */
- REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
- RCV_LIST_SEL_MODE_ATTN_ENABLE);
-
- /* Enable transmit DMA, clear statistics. */
- pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
- MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
-
- /* GRC miscellaneous local control register. */
- pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
- GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
- }
-
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
- MM_Wait(40);
-
- /* Reset RX counters. */
- for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
- {
- ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
- }
-
- /* Reset TX counters. */
- for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
- {
- ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
- }
-
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
-
- /* Enable the DMA Completion state machine. */
- REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
-
- /* Enable the DMA Write state machine. */
- Value32 = DMA_WRITE_MODE_ENABLE |
- DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
- DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
- DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
- DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
- DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
- REG_WR(pDevice, DmaWrite.Mode, Value32);
-
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- Value16 = REG_RD(pDevice, PciCfg.PciXCommand);
- Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
- Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
- PCIX_CMD_MAX_BURST_MASK);
- if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE)
- {
- Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
- & PCIX_CMD_MAX_SPLIT_MASK;
- }
- REG_WR(pDevice, PciCfg.PciXCommand, Value16);
- }
- }
-
- /* Enable the Read DMA state machine. */
- Value32 = DMA_READ_MODE_ENABLE |
- DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
- DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
- DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
- DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
- DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
-
- if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE)
- {
- Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
- }
- REG_WR(pDevice, DmaRead.Mode, Value32);
-
- /* Enable the Receive Data Completion state machine. */
- REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
- RCV_DATA_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Mbuf Cluster Free state machine. */
- REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
-
- /* Enable the Send Data Completion state machine. */
- REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
-
- /* Enable the Send BD Completion state machine. */
- REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
- SND_BD_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Receive BD Initiator state machine. */
- REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
- RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
-
- /* Enable the Receive Data and Receive BD Initiator state machine. */
- REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
- RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
-
- /* Enable the Send Data Initiator state machine. */
- REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
-
- /* Enable the Send BD Initiator state machine. */
- REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
- SND_BD_IN_MODE_ATTN_ENABLE);
-
- /* Enable the Send BD Selector state machine. */
- REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
- SND_BD_SEL_MODE_ATTN_ENABLE);
+ pDevice->RxJumboProdIdx = 0;
+#endif /* T3_JUMBO_RCV_ENTRY_COUNT */
+
+ /* Configure the MAC address. */
+ LM_SetMacAddress (pDevice, pDevice->NodeAddress);
+
+ /* Initialize the transmit random backoff seed. */
+ Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
+ pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
+ pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
+ MAC_TX_BACKOFF_SEED_MASK;
+ REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32);
+
+ /* Receive MTU. Frames larger than the MTU is marked as oversized. */
+ REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
+
+ /* Configure Time slot/IPG per 802.3 */
+ REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
+
+ /*
+ * Configure Receive Rules so that packets don't match
+ * Programmble rule will be queued to Return Ring 1
+ */
+ REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
+
+ /*
+ * Configure to have 16 Classes of Services (COS) and one
+ * queue per class. Bad frames are queued to RRR#1.
+ * And frames don't match rules are also queued to COS#1.
+ */
+ REG_WR (pDevice, RcvListPlmt.Config, 0x181);
+
+ /* Enable Receive Placement Statistics */
+ REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff);
+ REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
+
+ /* Enable Send Data Initator Statistics */
+ REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff);
+ REG_WR (pDevice, SndDataIn.StatsCtrl,
+ T3_SND_DATA_IN_STATS_CTRL_ENABLE |
+ T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
+
+ /* Disable the host coalescing state machine before configuring it's */
+ /* parameters. */
+ REG_WR (pDevice, HostCoalesce.Mode, 0);
+ for (j = 0; j < 2000; j++) {
+ Value32 = REG_RD (pDevice, HostCoalesce.Mode);
+ if (!(Value32 & HOST_COALESCE_ENABLE)) {
+ break;
+ }
+ MM_Wait (10);
+ }
+
+ /* Host coalescing configurations. */
+ REG_WR (pDevice, HostCoalesce.RxCoalescingTicks,
+ pDevice->RxCoalescingTicks);
+ REG_WR (pDevice, HostCoalesce.TxCoalescingTicks,
+ pDevice->TxCoalescingTicks);
+ REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames,
+ pDevice->RxMaxCoalescedFrames);
+ REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames,
+ pDevice->TxMaxCoalescedFrames);
+ REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt,
+ pDevice->RxCoalescingTicksDuringInt);
+ REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt,
+ pDevice->TxCoalescingTicksDuringInt);
+ REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
+ pDevice->RxMaxCoalescedFramesDuringInt);
+ REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
+ pDevice->TxMaxCoalescedFramesDuringInt);
+
+ /* Initialize the address of the status block. The NIC will DMA */
+ /* the status block to this memory which resides on the host. */
+ REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High,
+ pDevice->StatusBlkPhy.High);
+ REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low,
+ pDevice->StatusBlkPhy.Low);
+
+ /* Initialize the address of the statistics block. The NIC will DMA */
+ /* the statistics to this block of memory. */
+ REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High,
+ pDevice->StatsBlkPhy.High);
+ REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low,
+ pDevice->StatsBlkPhy.Low);
+
+ REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks,
+ pDevice->StatsCoalescingTicks);
+
+ REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
+ REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00);
+
+ /* Enable Host Coalesing state machine */
+ REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
+ pDevice->CoalesceMode);
+
+ /* Enable the Receive BD Completion state machine. */
+ REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
+ RCV_BD_COMP_MODE_ATTN_ENABLE);
+
+ /* Enable the Receive List Placement state machine. */
+ REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
+
+ /* Enable the Receive List Selector state machine. */
+ REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
+ RCV_LIST_SEL_MODE_ATTN_ENABLE);
+
+ /* Enable transmit DMA, clear statistics. */
+ pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
+ MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
+ MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+ MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
+
+ /* GRC miscellaneous local control register. */
+ pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
+ GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
+ }
+
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
+ MM_Wait (40);
+
+ /* Reset RX counters. */
+ for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) {
+ ((PLM_UINT8) & pDevice->RxCounters)[j] = 0;
+ }
+
+ /* Reset TX counters. */
+ for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) {
+ ((PLM_UINT8) & pDevice->TxCounters)[j] = 0;
+ }
+
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
+
+ /* Enable the DMA Completion state machine. */
+ REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
+
+ /* Enable the DMA Write state machine. */
+ Value32 = DMA_WRITE_MODE_ENABLE |
+ DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
+ DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
+ DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
+ DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
+ DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
+ DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
+ DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
+ DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
+ REG_WR (pDevice, DmaWrite.Mode, Value32);
+
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ Value16 = REG_RD (pDevice, PciCfg.PciXCommand);
+ Value16 &=
+ ~(PCIX_CMD_MAX_SPLIT_MASK |
+ PCIX_CMD_MAX_BURST_MASK);
+ Value16 |=
+ ((PCIX_CMD_MAX_BURST_CPIOB <<
+ PCIX_CMD_MAX_BURST_SHL) &
+ PCIX_CMD_MAX_BURST_MASK);
+ if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
+ Value16 |=
+ (pDevice->
+ SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
+ & PCIX_CMD_MAX_SPLIT_MASK;
+ }
+ REG_WR (pDevice, PciCfg.PciXCommand, Value16);
+ }
+ }
+
+ /* Enable the Read DMA state machine. */
+ Value32 = DMA_READ_MODE_ENABLE |
+ DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
+ DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
+ DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
+ DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
+ DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
+ DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
+ DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
+ DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
+
+ if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
+ Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
+ }
+ REG_WR (pDevice, DmaRead.Mode, Value32);
+
+ /* Enable the Receive Data Completion state machine. */
+ REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
+ RCV_DATA_COMP_MODE_ATTN_ENABLE);
+
+ /* Enable the Mbuf Cluster Free state machine. */
+ REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
+
+ /* Enable the Send Data Completion state machine. */
+ REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
+
+ /* Enable the Send BD Completion state machine. */
+ REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
+ SND_BD_COMP_MODE_ATTN_ENABLE);
+
+ /* Enable the Receive BD Initiator state machine. */
+ REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
+ RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
+
+ /* Enable the Receive Data and Receive BD Initiator state machine. */
+ REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
+ RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
+
+ /* Enable the Send Data Initiator state machine. */
+ REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
+
+ /* Enable the Send BD Initiator state machine. */
+ REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
+ SND_BD_IN_MODE_ATTN_ENABLE);
+
+ /* Enable the Send BD Selector state machine. */
+ REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
+ SND_BD_SEL_MODE_ATTN_ENABLE);
#if INCLUDE_5701_AX_FIX
- /* Load the firmware for the 5701_A0 workaround. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
- {
- LM_LoadRlsFirmware(pDevice);
- }
+ /* Load the firmware for the 5701_A0 workaround. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) {
+ LM_LoadRlsFirmware (pDevice);
+ }
#endif
- /* Enable the transmitter. */
- pDevice->TxMode = TX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
- /* Enable the receiver. */
- pDevice->RxMode = RX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
- if (pDevice->RestoreOnWakeUp)
- {
- pDevice->RestoreOnWakeUp = FALSE;
- pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
- pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
- }
-
- /* Disable auto polling. */
- pDevice->MiMode = 0xc0000;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- else
- {
- if(pDevice->LedMode == LED_MODE_OUTPUT)
- {
- Value32 = LED_CTRL_PHY_MODE_2;
- }
- else
- {
- Value32 = LED_CTRL_PHY_MODE_1;
+ /* Enable the transmitter. */
+ pDevice->TxMode = TX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
+
+ /* Enable the receiver. */
+ pDevice->RxMode = RX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+
+ if (pDevice->RestoreOnWakeUp) {
+ pDevice->RestoreOnWakeUp = FALSE;
+ pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
+ pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
}
- }
- REG_WR(pDevice, MacCtrl.LedCtrl, Value32);
- /* Activate Link to enable MAC state machine */
- REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
+ /* Disable auto polling. */
+ pDevice->MiMode = 0xc0000;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- if (pDevice->EnableTbi)
- {
- REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
- MM_Wait(10);
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
- if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
- {
- REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ } else {
+ if (pDevice->LedMode == LED_MODE_OUTPUT) {
+ Value32 = LED_CTRL_PHY_MODE_2;
+ } else {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ }
}
- }
- /* Setup the phy chip. */
- LM_SetupPhy(pDevice);
+ REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
- if (!pDevice->EnableTbi) {
- /* Clear CRC stats */
- LM_ReadPhy(pDevice, 0x1e, &Value32);
- LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
- LM_ReadPhy(pDevice, 0x14, &Value32);
- }
+ /* Activate Link to enable MAC state machine */
+ REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
- /* Set up the receive mask. */
- LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
+ if (pDevice->EnableTbi) {
+ REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET);
+ MM_Wait (10);
+ REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+ if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) {
+ REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000);
+ }
+ }
+ /* Setup the phy chip. */
+ LM_SetupPhy (pDevice);
- /* Queue Rx packet buffers. */
- if(pDevice->QueueRxPackets)
- {
- LM_QueueRxPackets(pDevice);
- }
+ if (!pDevice->EnableTbi) {
+ /* Clear CRC stats */
+ LM_ReadPhy (pDevice, 0x1e, &Value32);
+ LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000);
+ LM_ReadPhy (pDevice, 0x14, &Value32);
+ }
- /* Enable interrupt to the host. */
- if(pDevice->InitDone)
- {
- LM_EnableInterrupt(pDevice);
- }
+ /* Set up the receive mask. */
+ LM_SetReceiveMask (pDevice, pDevice->ReceiveMask);
- return LM_STATUS_SUCCESS;
-} /* LM_ResetAdapter */
+ /* Queue Rx packet buffers. */
+ if (pDevice->QueueRxPackets) {
+ LM_QueueRxPackets (pDevice);
+ }
+ /* Enable interrupt to the host. */
+ if (pDevice->InitDone) {
+ LM_EnableInterrupt (pDevice);
+ }
+
+ return LM_STATUS_SUCCESS;
+} /* LM_ResetAdapter */
/******************************************************************************/
/* Description: */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_DisableInterrupt(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice)
{
- REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
- MISC_HOST_CTRL_MASK_PCI_INT);
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
+ MISC_HOST_CTRL_MASK_PCI_INT);
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
/******************************************************************************/
/* Description: */
/* This routine enables the adapter to generate interrupts. */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_EnableInterrupt(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice)
{
- REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
- ~MISC_HOST_CTRL_MASK_PCI_INT);
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
+ ~MISC_HOST_CTRL_MASK_PCI_INT);
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
- if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED)
- {
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_SET_INT);
- }
+ if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_SET_INT);
+ }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
/******************************************************************************/
/* Description: */
/* This routine puts a packet on the wire if there is a transmit DMA */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
#if 0
-LM_STATUS
-LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- LM_UINT32 FragCount;
- PT3_SND_BD pSendBd;
- PT3_SND_BD pShadowSendBd;
- LM_UINT32 Value32, Len;
- LM_UINT32 Idx;
+ LM_UINT32 FragCount;
+ PT3_SND_BD pSendBd;
+ PT3_SND_BD pShadowSendBd;
+ LM_UINT32 Value32, Len;
+ LM_UINT32 Idx;
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- return LM_5700SendPacket(pDevice, pPacket);
- }
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ return LM_5700SendPacket (pDevice, pPacket);
+ }
- /* Update the SendBdLeft count. */
- atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+ /* Update the SendBdLeft count. */
+ atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
- /* Initalize the send buffer descriptors. */
- Idx = pDevice->SendProdIdx;
+ /* Initalize the send buffer descriptors. */
+ Idx = pDevice->SendProdIdx;
- pSendBd = &pDevice->pSendBdVirt[Idx];
+ pSendBd = &pDevice->pSendBdVirt[Idx];
- /* Next producer index. */
- if (pDevice->NicSendBd == TRUE)
- {
- T3_64BIT_HOST_ADDR paddr;
+ /* Next producer index. */
+ if (pDevice->NicSendBd == TRUE) {
+ T3_64BIT_HOST_ADDR paddr;
+
+ pShadowSendBd = &pDevice->ShadowSendBd[Idx];
+ for (FragCount = 0;;) {
+ MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount);
+ /* Initialize the pointer to the send buffer fragment. */
+ if (paddr.High != pShadowSendBd->HostAddr.High) {
+ __raw_writel (paddr.High,
+ &(pSendBd->HostAddr.High));
+ pShadowSendBd->HostAddr.High = paddr.High;
+ }
+ __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low));
+
+ /* Setup the control flags and send buffer size. */
+ Value32 = (Len << 16) | pPacket->Flags;
+
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ Value32 |= SND_BD_FLAG_END;
+ if (Value32 != pShadowSendBd->u1.Len_Flags) {
+ __raw_writel (Value32,
+ &(pSendBd->u1.Len_Flags));
+ pShadowSendBd->u1.Len_Flags = Value32;
+ }
+ if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+ __raw_writel (pPacket->VlanTag,
+ &(pSendBd->u2.VlanTag));
+ }
+ break;
+ } else {
+ if (Value32 != pShadowSendBd->u1.Len_Flags) {
+ __raw_writel (Value32,
+ &(pSendBd->u1.Len_Flags));
+ pShadowSendBd->u1.Len_Flags = Value32;
+ }
+ if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+ __raw_writel (pPacket->VlanTag,
+ &(pSendBd->u2.VlanTag));
+ }
+ }
- pShadowSendBd = &pDevice->ShadowSendBd[Idx];
- for(FragCount = 0; ; )
- {
- MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount);
- /* Initialize the pointer to the send buffer fragment. */
- if (paddr.High != pShadowSendBd->HostAddr.High)
- {
- __raw_writel(paddr.High, &(pSendBd->HostAddr.High));
- pShadowSendBd->HostAddr.High = paddr.High;
- }
- __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low));
-
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
-
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- Value32 |= SND_BD_FLAG_END;
- if (Value32 != pShadowSendBd->u1.Len_Flags)
- {
- __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag));
- }
- break;
- }
- else
- {
- if (Value32 != pShadowSendBd->u1.Len_Flags)
- {
- __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag));
- }
- }
-
- pSendBd++;
- pShadowSendBd++;
- if (Idx == 0)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- pShadowSendBd = &pDevice->ShadowSendBd[0];
- }
- } /* for */
+ pSendBd++;
+ pShadowSendBd++;
+ if (Idx == 0) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ pShadowSendBd = &pDevice->ShadowSendBd[0];
+ }
+ } /* for */
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
+ /* Put the packet descriptor in the ActiveQ. */
+ QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- }
- else
- {
- for(FragCount = 0; ; )
- {
- /* Initialize the pointer to the send buffer fragment. */
- MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
+ } else {
+ for (FragCount = 0;;) {
+ /* Initialize the pointer to the send buffer fragment. */
+ MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
+ FragCount);
- pSendBd->u2.VlanTag = pPacket->VlanTag;
+ pSendBd->u2.VlanTag = pPacket->VlanTag;
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
+ /* Setup the control flags and send buffer size. */
+ Value32 = (Len << 16) | pPacket->Flags;
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
- break;
- }
- else
- {
- pSendBd->u1.Len_Flags = Value32;
- }
- pSendBd++;
- if (Idx == 0)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- } /* for */
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ pSendBd->u1.Len_Flags =
+ Value32 | SND_BD_FLAG_END;
+ break;
+ } else {
+ pSendBd->u1.Len_Flags = Value32;
+ }
+ pSendBd++;
+ if (Idx == 0) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ }
+ } /* for */
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
+ /* Put the packet descriptor in the ActiveQ. */
+ QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
- }
+ }
- /* Update the producer index. */
- pDevice->SendProdIdx = Idx;
+ /* Update the producer index. */
+ pDevice->SendProdIdx = Idx;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
#endif
-LM_STATUS
-LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- LM_UINT32 FragCount;
- PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
- T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
- LM_UINT32 StartIdx, Idx;
+ LM_UINT32 FragCount;
+ PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
+ T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
+ LM_UINT32 StartIdx, Idx;
+
+ while (1) {
+ /* Initalize the send buffer descriptors. */
+ StartIdx = Idx = pDevice->SendProdIdx;
+
+ if (pDevice->NicSendBd) {
+ pTmpSendBd = pSendBd = &NicSendBdArr[0];
+ } else {
+ pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
+ }
- while (1)
- {
- /* Initalize the send buffer descriptors. */
- StartIdx = Idx = pDevice->SendProdIdx;
+ /* Next producer index. */
+ for (FragCount = 0;;) {
+ LM_UINT32 Value32, Len;
- if (pDevice->NicSendBd)
- {
- pTmpSendBd = pSendBd = &NicSendBdArr[0];
- }
- else
- {
- pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
+ /* Initialize the pointer to the send buffer fragment. */
+ MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
+ FragCount);
+
+ pSendBd->u2.VlanTag = pPacket->VlanTag;
+
+ /* Setup the control flags and send buffer size. */
+ Value32 = (Len << 16) | pPacket->Flags;
+
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ pSendBd->u1.Len_Flags =
+ Value32 | SND_BD_FLAG_END;
+ break;
+ } else {
+ pSendBd->u1.Len_Flags = Value32;
+ }
+ pSendBd++;
+ if ((Idx == 0) && !pDevice->NicSendBd) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ }
+ } /* for */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) ==
+ LM_STATUS_SUCCESS) {
+ if (MM_CoalesceTxBuffer (pDevice, pPacket) !=
+ LM_STATUS_SUCCESS) {
+ QQ_PushHead (&pDevice->TxPacketFreeQ.
+ Container, pPacket);
+ return LM_STATUS_FAILURE;
+ }
+ continue;
+ }
+ }
+ break;
}
+ /* Put the packet descriptor in the ActiveQ. */
+ QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
- /* Next producer index. */
- for(FragCount = 0; ; )
- {
- LM_UINT32 Value32, Len;
+ if (pDevice->NicSendBd) {
+ pSendBd = &pDevice->pSendBdVirt[StartIdx];
+ pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
- /* Initialize the pointer to the send buffer fragment. */
- MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
+ while (StartIdx != Idx) {
+ LM_UINT32 Value32;
- pSendBd->u2.VlanTag = pPacket->VlanTag;
+ if ((Value32 = pTmpSendBd->HostAddr.High) !=
+ pShadowSendBd->HostAddr.High) {
+ __raw_writel (Value32,
+ &(pSendBd->HostAddr.High));
+ pShadowSendBd->HostAddr.High = Value32;
+ }
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
+ __raw_writel (pTmpSendBd->HostAddr.Low,
+ &(pSendBd->HostAddr.Low));
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
+ pShadowSendBd->u1.Len_Flags) {
+ __raw_writel (Value32,
+ &(pSendBd->u1.Len_Flags));
+ pShadowSendBd->u1.Len_Flags = Value32;
+ }
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
- break;
- }
- else
- {
- pSendBd->u1.Len_Flags = Value32;
- }
- pSendBd++;
- if ((Idx == 0) && !pDevice->NicSendBd)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- } /* for */
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
- LM_STATUS_SUCCESS)
- {
- if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
- {
- QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
- return LM_STATUS_FAILURE;
- }
- continue;
- }
- }
- break;
- }
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
-
- if (pDevice->NicSendBd)
- {
- pSendBd = &pDevice->pSendBdVirt[StartIdx];
- pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
-
- while (StartIdx != Idx)
- {
- LM_UINT32 Value32;
-
- if ((Value32 = pTmpSendBd->HostAddr.High) !=
- pShadowSendBd->HostAddr.High)
- {
- __raw_writel(Value32, &(pSendBd->HostAddr.High));
- pShadowSendBd->HostAddr.High = Value32;
- }
-
- __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low));
-
- if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
- pShadowSendBd->u1.Len_Flags)
- {
- __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
-
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
- {
- __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag));
- }
-
- StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- if (StartIdx == 0)
- pSendBd = &pDevice->pSendBdVirt[0];
- else
- pSendBd++;
- pTmpSendBd++;
- }
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+ if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+ __raw_writel (pTmpSendBd->u2.VlanTag,
+ &(pSendBd->u2.VlanTag));
+ }
- if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
- {
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- }
- }
- else
- {
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+ StartIdx =
+ (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ if (StartIdx == 0)
+ pSendBd = &pDevice->pSendBdVirt[0];
+ else
+ pSendBd++;
+ pTmpSendBd++;
+ }
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
- {
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+ if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+ }
+ } else {
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+
+ if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low,
+ Idx);
+ }
}
- }
- /* Update the SendBdLeft count. */
- atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+ /* Update the SendBdLeft count. */
+ atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
- /* Update the producer index. */
- pDevice->SendProdIdx = Idx;
+ /* Update the producer index. */
+ pDevice->SendProdIdx = Idx;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
STATIC LM_STATUS
-LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
- PT3_SND_BD pSendBd)
+LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
+ PT3_SND_BD pSendBd)
{
- int FragCount;
- LM_UINT32 Idx, Base, Len;
-
- Idx = pDevice->SendProdIdx;
- for(FragCount = 0; ; )
- {
- Len = pSendBd->u1.Len_Flags >> 16;
- if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
- (pSendBd->HostAddr.High == 0) &&
- ((Base + 8 + Len) < Base))
- {
- return LM_STATUS_SUCCESS;
- }
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- break;
+ int FragCount;
+ LM_UINT32 Idx, Base, Len;
+
+ Idx = pDevice->SendProdIdx;
+ for (FragCount = 0;;) {
+ Len = pSendBd->u1.Len_Flags >> 16;
+ if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
+ (pSendBd->HostAddr.High == 0) &&
+ ((Base + 8 + Len) < Base)) {
+ return LM_STATUS_SUCCESS;
+ }
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ break;
+ }
+ pSendBd++;
+ if (!pDevice->NicSendBd) {
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ if (Idx == 0) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ }
+ }
}
- pSendBd++;
- if (!pDevice->NicSendBd)
- {
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- if (Idx == 0)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- }
- }
- return LM_STATUS_FAILURE;
+ return LM_STATUS_FAILURE;
}
/******************************************************************************/
/* Return: */
/******************************************************************************/
__inline static unsigned long
-ComputeCrc32(
-unsigned char *pBuffer,
-unsigned long BufferSize) {
- unsigned long Reg;
- unsigned long Tmp;
- unsigned long j, k;
+ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize)
+{
+ unsigned long Reg;
+ unsigned long Tmp;
+ unsigned long j, k;
- Reg = 0xffffffff;
+ Reg = 0xffffffff;
- for(j = 0; j < BufferSize; j++)
- {
- Reg ^= pBuffer[j];
+ for (j = 0; j < BufferSize; j++) {
+ Reg ^= pBuffer[j];
- for(k = 0; k < 8; k++)
- {
- Tmp = Reg & 0x01;
+ for (k = 0; k < 8; k++) {
+ Tmp = Reg & 0x01;
- Reg >>= 1;
+ Reg >>= 1;
- if(Tmp)
- {
- Reg ^= 0xedb88320;
- }
+ if (Tmp) {
+ Reg ^= 0xedb88320;
+ }
+ }
}
- }
-
- return ~Reg;
-} /* ComputeCrc32 */
+ return ~Reg;
+} /* ComputeCrc32 */
/******************************************************************************/
/* Description: */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_SetReceiveMask(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Mask) {
- LM_UINT32 ReceiveMask;
- LM_UINT32 RxMode;
- LM_UINT32 j, k;
-
- ReceiveMask = Mask;
-
- RxMode = pDevice->RxMode;
-
- if(Mask & LM_ACCEPT_UNICAST)
- {
- Mask &= ~LM_ACCEPT_UNICAST;
- }
-
- if(Mask & LM_ACCEPT_MULTICAST)
- {
- Mask &= ~LM_ACCEPT_MULTICAST;
- }
-
- if(Mask & LM_ACCEPT_ALL_MULTICAST)
- {
- Mask &= ~LM_ACCEPT_ALL_MULTICAST;
- }
-
- if(Mask & LM_ACCEPT_BROADCAST)
- {
- Mask &= ~LM_ACCEPT_BROADCAST;
- }
-
- RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
- if(Mask & LM_PROMISCUOUS_MODE)
- {
- RxMode |= RX_MODE_PROMISCUOUS_MODE;
- Mask &= ~LM_PROMISCUOUS_MODE;
- }
-
- RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
- if(Mask & LM_ACCEPT_ERROR_PACKET)
- {
- RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
- Mask &= ~LM_ACCEPT_ERROR_PACKET;
- }
-
- /* Make sure all the bits are valid before committing changes. */
- if(Mask)
- {
- return LM_STATUS_FAILURE;
- }
+LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
+{
+ LM_UINT32 ReceiveMask;
+ LM_UINT32 RxMode;
+ LM_UINT32 j, k;
- /* Commit the new filter. */
- pDevice->RxMode = RxMode;
- REG_WR(pDevice, MacCtrl.RxMode, RxMode);
+ ReceiveMask = Mask;
- pDevice->ReceiveMask = ReceiveMask;
+ RxMode = pDevice->RxMode;
- /* Set up the MC hash table. */
- if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
- {
- for(k = 0; k < 4; k++)
- {
- REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
+ if (Mask & LM_ACCEPT_UNICAST) {
+ Mask &= ~LM_ACCEPT_UNICAST;
}
- }
- else if(ReceiveMask & LM_ACCEPT_MULTICAST)
- {
- LM_UINT32 HashReg[4];
- HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0;
- for(j = 0; j < pDevice->McEntryCount; j++)
- {
- LM_UINT32 RegIndex;
- LM_UINT32 Bitpos;
- LM_UINT32 Crc32;
+ if (Mask & LM_ACCEPT_MULTICAST) {
+ Mask &= ~LM_ACCEPT_MULTICAST;
+ }
+
+ if (Mask & LM_ACCEPT_ALL_MULTICAST) {
+ Mask &= ~LM_ACCEPT_ALL_MULTICAST;
+ }
- Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE);
+ if (Mask & LM_ACCEPT_BROADCAST) {
+ Mask &= ~LM_ACCEPT_BROADCAST;
+ }
+
+ RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
+ if (Mask & LM_PROMISCUOUS_MODE) {
+ RxMode |= RX_MODE_PROMISCUOUS_MODE;
+ Mask &= ~LM_PROMISCUOUS_MODE;
+ }
+
+ RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
+ if (Mask & LM_ACCEPT_ERROR_PACKET) {
+ RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
+ Mask &= ~LM_ACCEPT_ERROR_PACKET;
+ }
+
+ /* Make sure all the bits are valid before committing changes. */
+ if (Mask) {
+ return LM_STATUS_FAILURE;
+ }
- /* The most significant 7 bits of the CRC32 (no inversion), */
- /* are used to index into one of the possible 128 bit positions. */
- Bitpos = ~Crc32 & 0x7f;
+ /* Commit the new filter. */
+ pDevice->RxMode = RxMode;
+ REG_WR (pDevice, MacCtrl.RxMode, RxMode);
- /* Hash register index. */
- RegIndex = (Bitpos & 0x60) >> 5;
+ pDevice->ReceiveMask = ReceiveMask;
- /* Bit to turn on within a hash register. */
- Bitpos &= 0x1f;
+ /* Set up the MC hash table. */
+ if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) {
+ for (k = 0; k < 4; k++) {
+ REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff);
+ }
+ } else if (ReceiveMask & LM_ACCEPT_MULTICAST) {
+ LM_UINT32 HashReg[4];
+
+ HashReg[0] = 0;
+ HashReg[1] = 0;
+ HashReg[2] = 0;
+ HashReg[3] = 0;
+ for (j = 0; j < pDevice->McEntryCount; j++) {
+ LM_UINT32 RegIndex;
+ LM_UINT32 Bitpos;
+ LM_UINT32 Crc32;
+
+ Crc32 =
+ ComputeCrc32 (pDevice->McTable[j],
+ ETHERNET_ADDRESS_SIZE);
+
+ /* The most significant 7 bits of the CRC32 (no inversion), */
+ /* are used to index into one of the possible 128 bit positions. */
+ Bitpos = ~Crc32 & 0x7f;
+
+ /* Hash register index. */
+ RegIndex = (Bitpos & 0x60) >> 5;
+
+ /* Bit to turn on within a hash register. */
+ Bitpos &= 0x1f;
+
+ /* Enable the multicast bit. */
+ HashReg[RegIndex] |= (1 << Bitpos);
+ }
- /* Enable the multicast bit. */
- HashReg[RegIndex] |= (1 << Bitpos);
+ /* REV_AX has problem with multicast filtering where it uses both */
+ /* DA and SA to perform hashing. */
+ for (k = 0; k < 4; k++) {
+ REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]);
+ }
+ } else {
+ /* Reject all multicast frames. */
+ for (j = 0; j < 4; j++) {
+ REG_WR (pDevice, MacCtrl.HashReg[j], 0);
+ }
}
- /* REV_AX has problem with multicast filtering where it uses both */
- /* DA and SA to perform hashing. */
- for(k = 0; k < 4; k++)
- {
- REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]);
+ /* By default, Tigon3 will accept broadcast frames. We need to setup */
+ if (ReceiveMask & LM_ACCEPT_BROADCAST) {
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
+ } else {
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE1_RULE);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE1_VALUE);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE2_RULE);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE2_VALUE);
+ }
+
+ /* disable the rest of the rules. */
+ for (j = RCV_LAST_RULE_IDX; j < 16; j++) {
+ REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0);
+ REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0);
}
- }
- else
- {
- /* Reject all multicast frames. */
- for(j = 0; j < 4; j++)
- {
- REG_WR(pDevice, MacCtrl.HashReg[j], 0);
- }
- }
-
- /* By default, Tigon3 will accept broadcast frames. We need to setup */
- if(ReceiveMask & LM_ACCEPT_BROADCAST)
- {
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
- }
- else
- {
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE2_RULE);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE2_VALUE);
- }
-
- /* disable the rest of the rules. */
- for(j = RCV_LAST_RULE_IDX; j < 16; j++)
- {
- REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
- REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetReceiveMask */
+ return LM_STATUS_SUCCESS;
+} /* LM_SetReceiveMask */
/******************************************************************************/
/* Description: */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_Abort(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice)
{
- PLM_PACKET pPacket;
- LM_UINT Idx;
-
- LM_DisableInterrupt(pDevice);
-
- /* Disable all the state machines. */
- LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE);
-
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE);
-
- /* Clear TDE bit */
- pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE);
-
- /* Reset all FTQs */
- REG_WR(pDevice, Ftq.Reset, 0xffffffff);
- REG_WR(pDevice, Ftq.Reset, 0x0);
-
- LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE);
-
- MM_ACQUIRE_INT_LOCK(pDevice);
-
- /* Abort packets that have already queued to go out. */
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container);
- while(pPacket)
- {
-
- pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
- pDevice->TxCounters.TxPacketAbortedCnt++;
-
- atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
-
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->TxPacketActiveQ.Container);
- }
-
- /* Cleanup the receive return rings. */
- LM_ServiceRxInterrupt(pDevice);
-
- /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
- /* Doing so may cause system crash. */
- if(!pDevice->ShuttingDown)
- {
- /* Indicate packets to the protocol. */
- MM_IndicateTxPackets(pDevice);
-
- /* Indicate received packets to the protocols. */
- MM_IndicateRxPackets(pDevice);
- }
- else
- {
- /* Move the receive packet descriptors in the ReceivedQ to the */
- /* free queue. */
- for(; ;)
- {
- pPacket = (PLM_PACKET) QQ_PopHead(
- &pDevice->RxPacketReceivedQ.Container);
- if(pPacket == NULL)
- {
- break;
- }
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ PLM_PACKET pPacket;
+ LM_UINT Idx;
+
+ LM_DisableInterrupt (pDevice);
+
+ /* Disable all the state machines. */
+ LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE);
+
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE);
+
+ /* Clear TDE bit */
+ pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
+
+ LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE);
+
+ /* Reset all FTQs */
+ REG_WR (pDevice, Ftq.Reset, 0xffffffff);
+ REG_WR (pDevice, Ftq.Reset, 0x0);
+
+ LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE);
+
+ MM_ACQUIRE_INT_LOCK (pDevice);
+
+ /* Abort packets that have already queued to go out. */
+ pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
+ while (pPacket) {
+
+ pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
+ pDevice->TxCounters.TxPacketAbortedCnt++;
+
+ atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+
+ QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
+
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
+ }
+
+ /* Cleanup the receive return rings. */
+ LM_ServiceRxInterrupt (pDevice);
+
+ /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
+ /* Doing so may cause system crash. */
+ if (!pDevice->ShuttingDown) {
+ /* Indicate packets to the protocol. */
+ MM_IndicateTxPackets (pDevice);
+
+ /* Indicate received packets to the protocols. */
+ MM_IndicateRxPackets (pDevice);
+ } else {
+ /* Move the receive packet descriptors in the ReceivedQ to the */
+ /* free queue. */
+ for (;;) {
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->
+ RxPacketReceivedQ.
+ Container);
+ if (pPacket == NULL) {
+ break;
+ }
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+ pPacket);
+ }
}
- }
- /* Clean up the Std Receive Producer ring. */
- Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
+ /* Clean up the Std Receive Producer ring. */
+ Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
- while(Idx != pDevice->RxStdProdIdx) {
- pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
- MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque));
+ while (Idx != pDevice->RxStdProdIdx) {
+ pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+ MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx].
+ Opaque));
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
- } /* while */
+ Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
+ } /* while */
- /* Reinitialize our copy of the indices. */
- pDevice->RxStdProdIdx = 0;
+ /* Reinitialize our copy of the indices. */
+ pDevice->RxStdProdIdx = 0;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Clean up the Jumbo Receive Producer ring. */
- Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
+ /* Clean up the Jumbo Receive Producer ring. */
+ Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
- while(Idx != pDevice->RxJumboProdIdx) {
- pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
- MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque));
+ while (Idx != pDevice->RxJumboProdIdx) {
+ pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+ MM_UINT_PTR (pDevice->
+ pRxJumboBdVirt[Idx].
+ Opaque));
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
- } /* while */
+ Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
+ } /* while */
- /* Reinitialize our copy of the indices. */
- pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ /* Reinitialize our copy of the indices. */
+ pDevice->RxJumboProdIdx = 0;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- MM_RELEASE_INT_LOCK(pDevice);
+ MM_RELEASE_INT_LOCK (pDevice);
- /* Initialize the statistis Block */
- pDevice->pStatusBlkVirt->Status = 0;
- pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
- pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
- pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
-
- return LM_STATUS_SUCCESS;
-} /* LM_Abort */
+ /* Initialize the statistis Block */
+ pDevice->pStatusBlkVirt->Status = 0;
+ pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+ return LM_STATUS_SUCCESS;
+} /* LM_Abort */
/******************************************************************************/
/* Description: */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_Halt(
-PLM_DEVICE_BLOCK pDevice) {
- PLM_PACKET pPacket;
- LM_UINT32 EntryCnt;
-
- LM_Abort(pDevice);
+LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice)
+{
+ PLM_PACKET pPacket;
+ LM_UINT32 EntryCnt;
- /* Get the number of entries in the queue. */
- EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
+ LM_Abort (pDevice);
- /* Make sure all the packets have been accounted for. */
- for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
- {
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- if (pPacket == 0)
- break;
+ /* Get the number of entries in the queue. */
+ EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container);
- MM_FreeRxBuffer(pDevice, pPacket);
+ /* Make sure all the packets have been accounted for. */
+ for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) {
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ if (pPacket == 0)
+ break;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- }
+ MM_FreeRxBuffer (pDevice, pPacket);
- LM_ResetChip(pDevice);
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+ }
- /* Restore PCI configuration registers. */
- MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
- pDevice->SavedCacheLineReg);
- LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
- (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
+ LM_ResetChip (pDevice);
- /* Reprogram the MAC address. */
- LM_SetMacAddress(pDevice, pDevice->NodeAddress);
+ /* Restore PCI configuration registers. */
+ MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
+ pDevice->SavedCacheLineReg);
+ LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
+ (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
- return LM_STATUS_SUCCESS;
-} /* LM_Halt */
+ /* Reprogram the MAC address. */
+ LM_SetMacAddress (pDevice, pDevice->NodeAddress);
+ return LM_STATUS_SUCCESS;
+} /* LM_Halt */
-STATIC LM_STATUS
-LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- /* Wait for access to the nvram interface before resetting. This is */
- /* a workaround to prevent EEPROM corruption. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
- {
- /* Request access to the flash interface. */
- REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
-
- for(j = 0; j < 100000; j++)
- {
- Value32 = REG_RD(pDevice, Nvram.SwArb);
- if(Value32 & SW_ARB_GNT1)
- {
- break;
- }
- MM_Wait(10);
+ LM_UINT32 Value32;
+ LM_UINT32 j;
+
+ /* Wait for access to the nvram interface before resetting. This is */
+ /* a workaround to prevent EEPROM corruption. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+ /* Request access to the flash interface. */
+ REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
+
+ for (j = 0; j < 100000; j++) {
+ Value32 = REG_RD (pDevice, Nvram.SwArb);
+ if (Value32 & SW_ARB_GNT1) {
+ break;
+ }
+ MM_Wait (10);
+ }
}
- }
- /* Global reset. */
- REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
- MM_Wait(40); MM_Wait(40); MM_Wait(40);
+ /* Global reset. */
+ REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
+ MM_Wait (40);
+ MM_Wait (40);
+ MM_Wait (40);
- /* make sure we re-enable indirect accesses */
- MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
- pDevice->MiscHostCtrl);
+ /* make sure we re-enable indirect accesses */
+ MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+ pDevice->MiscHostCtrl);
- /* Set MAX PCI retry to zero. */
- Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+ /* Set MAX PCI retry to zero. */
+ Value32 =
+ T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+ }
}
- }
- MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32);
- /* Restore PCI command register. */
- MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
- pDevice->PciCommandStatusWords);
+ /* Restore PCI command register. */
+ MM_WriteConfig32 (pDevice, PCI_COMMAND_REG,
+ pDevice->PciCommandStatusWords);
- /* Disable PCI-X relaxed ordering bit. */
- MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
- Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
- MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
+ /* Disable PCI-X relaxed ordering bit. */
+ MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32);
+ Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
+ MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32);
- /* Enable memory arbiter. */
- REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
+ /* Enable memory arbiter. */
+ REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-#ifdef BIG_ENDIAN_PCI /* This from jfd */
- Value32 = GRC_MODE_WORD_SWAP_DATA|
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+#ifdef BIG_ENDIAN_PCI /* This from jfd */
+ Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
#ifdef BIG_ENDIAN_HOST
- /* Reconfigure the mode register. */
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA |
- GRC_MODE_WORD_SWAP_DATA;
+ /* Reconfigure the mode register. */
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA;
#else
- /* Reconfigure the mode register. */
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
+ /* Reconfigure the mode register. */
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
#endif
#endif
- REG_WR(pDevice, Grc.Mode, Value32);
-
- /* Prevent PXE from restarting. */
- MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM);
-
- if(pDevice->EnableTbi) {
- pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
- REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
- }
- else {
- REG_WR(pDevice, MacCtrl.Mode, 0);
- }
-
- /* Wait for the firmware to finish initialization. */
- for(j = 0; j < 100000; j++)
- {
- MM_Wait(10);
-
- Value32 = MEM_RD_OFFSET(pDevice, 0x0b50);
- if(Value32 == ~T3_MAGIC_NUM)
- {
- break;
+ REG_WR (pDevice, Grc.Mode, Value32);
+
+ /* Prevent PXE from restarting. */
+ MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM);
+
+ if (pDevice->EnableTbi) {
+ pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
+ REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
+ } else {
+ REG_WR (pDevice, MacCtrl.Mode, 0);
+ }
+
+ /* Wait for the firmware to finish initialization. */
+ for (j = 0; j < 100000; j++) {
+ MM_Wait (10);
+
+ Value32 = MEM_RD_OFFSET (pDevice, 0x0b50);
+ if (Value32 == ~T3_MAGIC_NUM) {
+ break;
+ }
}
- }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
/******************************************************************************/
/* */
/* Return: */
/******************************************************************************/
-__inline static void
-LM_ServiceTxInterrupt(
-PLM_DEVICE_BLOCK pDevice) {
- PLM_PACKET pPacket;
- LM_UINT32 HwConIdx;
- LM_UINT32 SwConIdx;
-
- HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
-
- /* Get our copy of the consumer index. The buffer descriptors */
- /* that are in between the consumer indices are freed. */
- SwConIdx = pDevice->SendConIdx;
-
- /* Move the packets from the TxPacketActiveQ that are sent out to */
- /* the TxPacketXmittedQ. Packets that are sent use the */
- /* descriptors that are between SwConIdx and HwConIdx. */
- while(SwConIdx != HwConIdx)
- {
- /* Get the packet that was sent from the TxPacketActiveQ. */
- pPacket = (PLM_PACKET) QQ_PopHead(
- &pDevice->TxPacketActiveQ.Container);
-
- /* Set the return status. */
- pPacket->PacketStatus = LM_STATUS_SUCCESS;
-
- /* Put the packet in the TxPacketXmittedQ for indication later. */
- QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
-
- /* Move to the next packet's BD. */
- SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
- T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- /* Update the number of unused BDs. */
- atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- /* Get the new updated HwConIdx. */
+__inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice)
+{
+ PLM_PACKET pPacket;
+ LM_UINT32 HwConIdx;
+ LM_UINT32 SwConIdx;
+
HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
- } /* while */
- /* Save the new SwConIdx. */
- pDevice->SendConIdx = SwConIdx;
+ /* Get our copy of the consumer index. The buffer descriptors */
+ /* that are in between the consumer indices are freed. */
+ SwConIdx = pDevice->SendConIdx;
+
+ /* Move the packets from the TxPacketActiveQ that are sent out to */
+ /* the TxPacketXmittedQ. Packets that are sent use the */
+ /* descriptors that are between SwConIdx and HwConIdx. */
+ while (SwConIdx != HwConIdx) {
+ /* Get the packet that was sent from the TxPacketActiveQ. */
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.
+ Container);
+
+ /* Set the return status. */
+ pPacket->PacketStatus = LM_STATUS_SUCCESS;
+
+ /* Put the packet in the TxPacketXmittedQ for indication later. */
+ QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
-} /* LM_ServiceTxInterrupt */
+ /* Move to the next packet's BD. */
+ SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
+ T3_SEND_RCB_ENTRY_COUNT_MASK;
+ /* Update the number of unused BDs. */
+ atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+
+ /* Get the new updated HwConIdx. */
+ HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
+ } /* while */
+
+ /* Save the new SwConIdx. */
+ pDevice->SendConIdx = SwConIdx;
+
+} /* LM_ServiceTxInterrupt */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-__inline static void
-LM_ServiceRxInterrupt(
-PLM_DEVICE_BLOCK pDevice) {
- PLM_PACKET pPacket;
- PT3_RCV_BD pRcvBd;
- LM_UINT32 HwRcvRetProdIdx;
- LM_UINT32 SwRcvRetConIdx;
-
- /* Loop thru the receive return rings for received packets. */
- HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
-
- SwRcvRetConIdx = pDevice->RcvRetConIdx;
- while(SwRcvRetConIdx != HwRcvRetProdIdx)
- {
- pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
-
- /* Get the received packet descriptor. */
- pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
- MM_UINT_PTR(pRcvBd->Opaque));
-
- /* Check the error flag. */
- if(pRcvBd->ErrorFlag &&
- pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
- {
- pPacket->PacketStatus = LM_STATUS_FAILURE;
-
- pDevice->RxCounters.RxPacketErrCnt++;
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
- {
- pDevice->RxCounters.RxErrCrcCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
- {
- pDevice->RxCounters.RxErrCollCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
- {
- pDevice->RxCounters.RxErrLinkLostCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
- {
- pDevice->RxCounters.RxErrPhyDecodeCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
- {
- pDevice->RxCounters.RxErrOddNibbleCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
- {
- pDevice->RxCounters.RxErrMacAbortCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
- {
- pDevice->RxCounters.RxErrShortPacketCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
- {
- pDevice->RxCounters.RxErrNoResourceCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
- {
- pDevice->RxCounters.RxErrLargePacketCnt++;
- }
- }
- else
- {
- pPacket->PacketStatus = LM_STATUS_SUCCESS;
- pPacket->PacketSize = pRcvBd->Len - 4;
+__inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice)
+{
+ PLM_PACKET pPacket;
+ PT3_RCV_BD pRcvBd;
+ LM_UINT32 HwRcvRetProdIdx;
+ LM_UINT32 SwRcvRetConIdx;
- pPacket->Flags = pRcvBd->Flags;
- if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
- {
- pPacket->VlanTag = pRcvBd->VlanTag;
- }
+ /* Loop thru the receive return rings for received packets. */
+ HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
- pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
- }
+ SwRcvRetConIdx = pDevice->RcvRetConIdx;
+ while (SwRcvRetConIdx != HwRcvRetProdIdx) {
+ pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
- /* Put the packet descriptor containing the received packet */
- /* buffer in the RxPacketReceivedQ for indication later. */
- QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
+ /* Get the received packet descriptor. */
+ pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+ MM_UINT_PTR (pRcvBd->Opaque));
- /* Go to the next buffer descriptor. */
- SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
- T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
+ /* Check the error flag. */
+ if (pRcvBd->ErrorFlag &&
+ pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
+ pPacket->PacketStatus = LM_STATUS_FAILURE;
- /* Get the updated HwRcvRetProdIdx. */
- HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
- } /* while */
+ pDevice->RxCounters.RxPacketErrCnt++;
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) {
+ pDevice->RxCounters.RxErrCrcCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) {
+ pDevice->RxCounters.RxErrCollCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) {
+ pDevice->RxCounters.RxErrLinkLostCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) {
+ pDevice->RxCounters.RxErrPhyDecodeCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
+ pDevice->RxCounters.RxErrOddNibbleCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) {
+ pDevice->RxCounters.RxErrMacAbortCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) {
+ pDevice->RxCounters.RxErrShortPacketCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) {
+ pDevice->RxCounters.RxErrNoResourceCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) {
+ pDevice->RxCounters.RxErrLargePacketCnt++;
+ }
+ } else {
+ pPacket->PacketStatus = LM_STATUS_SUCCESS;
+ pPacket->PacketSize = pRcvBd->Len - 4;
+
+ pPacket->Flags = pRcvBd->Flags;
+ if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) {
+ pPacket->VlanTag = pRcvBd->VlanTag;
+ }
+
+ pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
+ }
+
+ /* Put the packet descriptor containing the received packet */
+ /* buffer in the RxPacketReceivedQ for indication later. */
+ QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket);
- pDevice->RcvRetConIdx = SwRcvRetConIdx;
+ /* Go to the next buffer descriptor. */
+ SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
+ T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
- /* Update the receive return ring consumer index. */
- MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
-} /* LM_ServiceRxInterrupt */
+ /* Get the updated HwRcvRetProdIdx. */
+ HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
+ } /* while */
+ pDevice->RcvRetConIdx = SwRcvRetConIdx;
+
+ /* Update the receive return ring consumer index. */
+ MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
+} /* LM_ServiceRxInterrupt */
/******************************************************************************/
/* Description: */
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_ServiceInterrupts(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- int ServicePhyInt = FALSE;
-
- /* Setup the phy chip whenever the link status changes. */
- if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
- {
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
- {
- if (Value32 & MAC_STATUS_MI_INTERRUPT)
- {
- ServicePhyInt = TRUE;
- }
- }
- else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
- {
- ServicePhyInt = TRUE;
- }
- }
- else
- {
- if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
- {
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
- (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
- ServicePhyInt = TRUE;
+ LM_UINT32 Value32;
+ int ServicePhyInt = FALSE;
+
+ /* Setup the phy chip whenever the link status changes. */
+ if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) {
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+ if (Value32 & MAC_STATUS_MI_INTERRUPT) {
+ ServicePhyInt = TRUE;
+ }
+ } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) {
+ ServicePhyInt = TRUE;
+ }
+ } else {
+ if (pDevice->pStatusBlkVirt->
+ Status & STATUS_BLOCK_LINK_CHANGED_STATUS) {
+ pDevice->pStatusBlkVirt->Status =
+ STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt->
+ Status &
+ ~STATUS_BLOCK_LINK_CHANGED_STATUS);
+ ServicePhyInt = TRUE;
+ }
}
- }
#if INCLUDE_TBI_SUPPORT
- if (pDevice->IgnoreTbiLinkChange == TRUE)
- {
- ServicePhyInt = FALSE;
- }
+ if (pDevice->IgnoreTbiLinkChange == TRUE) {
+ ServicePhyInt = FALSE;
+ }
#endif
- if (ServicePhyInt == TRUE)
- {
- LM_SetupPhy(pDevice);
- }
-
- /* Service receive and transmit interrupts. */
- LM_ServiceRxInterrupt(pDevice);
- LM_ServiceTxInterrupt(pDevice);
+ if (ServicePhyInt == TRUE) {
+ LM_SetupPhy (pDevice);
+ }
- /* No spinlock for this queue since this routine is serialized. */
- if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
- {
- /* Indicate receive packets. */
- MM_IndicateRxPackets(pDevice);
- /* LM_QueueRxPackets(pDevice); */
- }
+ /* Service receive and transmit interrupts. */
+ LM_ServiceRxInterrupt (pDevice);
+ LM_ServiceTxInterrupt (pDevice);
- /* No spinlock for this queue since this routine is serialized. */
- if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
- {
- MM_IndicateTxPackets(pDevice);
- }
+ /* No spinlock for this queue since this routine is serialized. */
+ if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) {
+ /* Indicate receive packets. */
+ MM_IndicateRxPackets (pDevice);
+ /* LM_QueueRxPackets(pDevice); */
+ }
- return LM_STATUS_SUCCESS;
-} /* LM_ServiceInterrupts */
+ /* No spinlock for this queue since this routine is serialized. */
+ if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) {
+ MM_IndicateTxPackets (pDevice);
+ }
+ return LM_STATUS_SUCCESS;
+} /* LM_ServiceInterrupts */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_MulticastAdd(
-PLM_DEVICE_BLOCK pDevice,
-PLM_UINT8 pMcAddress) {
- PLM_UINT8 pEntry;
- LM_UINT32 j;
-
- pEntry = pDevice->McTable[0];
- for(j = 0; j < pDevice->McEntryCount; j++)
- {
- if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress))
- {
- /* Found a match, increment the instance count. */
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
+LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
+{
+ PLM_UINT8 pEntry;
+ LM_UINT32 j;
- return LM_STATUS_SUCCESS;
- }
+ pEntry = pDevice->McTable[0];
+ for (j = 0; j < pDevice->McEntryCount; j++) {
+ if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
+ /* Found a match, increment the instance count. */
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
- pEntry += LM_MC_ENTRY_SIZE;
- }
+ return LM_STATUS_SUCCESS;
+ }
- if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE)
- {
- return LM_STATUS_FAILURE;
- }
+ pEntry += LM_MC_ENTRY_SIZE;
+ }
- pEntry = pDevice->McTable[pDevice->McEntryCount];
+ if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) {
+ return LM_STATUS_FAILURE;
+ }
- COPY_ETH_ADDRESS(pMcAddress, pEntry);
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
+ pEntry = pDevice->McTable[pDevice->McEntryCount];
- pDevice->McEntryCount++;
+ COPY_ETH_ADDRESS (pMcAddress, pEntry);
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
- LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
+ pDevice->McEntryCount++;
- return LM_STATUS_SUCCESS;
-} /* LM_MulticastAdd */
+ LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
+ return LM_STATUS_SUCCESS;
+} /* LM_MulticastAdd */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_MulticastDel(
-PLM_DEVICE_BLOCK pDevice,
-PLM_UINT8 pMcAddress) {
- PLM_UINT8 pEntry;
- LM_UINT32 j;
-
- pEntry = pDevice->McTable[0];
- for(j = 0; j < pDevice->McEntryCount; j++)
- {
- if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress))
- {
- /* Found a match, decrement the instance count. */
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
-
- /* No more instance left, remove the address from the table. */
- /* Move the last entry in the table to the delete slot. */
- if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
- pDevice->McEntryCount > 1)
- {
-
- COPY_ETH_ADDRESS(
- pDevice->McTable[pDevice->McEntryCount-1], pEntry);
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
- pDevice->McTable[pDevice->McEntryCount-1]
- [LM_MC_INSTANCE_COUNT_INDEX];
- }
- pDevice->McEntryCount--;
+LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
+{
+ PLM_UINT8 pEntry;
+ LM_UINT32 j;
+
+ pEntry = pDevice->McTable[0];
+ for (j = 0; j < pDevice->McEntryCount; j++) {
+ if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
+ /* Found a match, decrement the instance count. */
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
+
+ /* No more instance left, remove the address from the table. */
+ /* Move the last entry in the table to the delete slot. */
+ if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
+ pDevice->McEntryCount > 1) {
+
+ COPY_ETH_ADDRESS (pDevice->
+ McTable[pDevice->
+ McEntryCount - 1],
+ pEntry);
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
+ pDevice->McTable[pDevice->McEntryCount - 1]
+ [LM_MC_INSTANCE_COUNT_INDEX];
+ }
+ pDevice->McEntryCount--;
+
+ /* Update the receive mask if the table is empty. */
+ if (pDevice->McEntryCount == 0) {
+ LM_SetReceiveMask (pDevice,
+ pDevice->
+ ReceiveMask &
+ ~LM_ACCEPT_MULTICAST);
+ }
- /* Update the receive mask if the table is empty. */
- if(pDevice->McEntryCount == 0)
- {
- LM_SetReceiveMask(pDevice,
- pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
- }
+ return LM_STATUS_SUCCESS;
+ }
- return LM_STATUS_SUCCESS;
+ pEntry += LM_MC_ENTRY_SIZE;
}
- pEntry += LM_MC_ENTRY_SIZE;
- }
-
- return LM_STATUS_FAILURE;
-} /* LM_MulticastDel */
-
+ return LM_STATUS_FAILURE;
+} /* LM_MulticastDel */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_MulticastClear(
-PLM_DEVICE_BLOCK pDevice) {
- pDevice->McEntryCount = 0;
-
- LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
+LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice)
+{
+ pDevice->McEntryCount = 0;
- return LM_STATUS_SUCCESS;
-} /* LM_MulticastClear */
+ LM_SetReceiveMask (pDevice,
+ pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
+ return LM_STATUS_SUCCESS;
+} /* LM_MulticastClear */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetMacAddress(
- PLM_DEVICE_BLOCK pDevice,
- PLM_UINT8 pMacAddress)
+LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress)
{
- LM_UINT32 j;
-
- for(j = 0; j < 4; j++)
- {
- REG_WR(pDevice, MacCtrl.MacAddr[j].High,
- (pMacAddress[0] << 8) | pMacAddress[1]);
- REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
- (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
- (pMacAddress[4] << 8) | pMacAddress[5]);
- }
-
- return LM_STATUS_SUCCESS;
-}
+ LM_UINT32 j;
+
+ for (j = 0; j < 4; j++) {
+ REG_WR (pDevice, MacCtrl.MacAddr[j].High,
+ (pMacAddress[0] << 8) | pMacAddress[1]);
+ REG_WR (pDevice, MacCtrl.MacAddr[j].Low,
+ (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
+ (pMacAddress[4] << 8) | pMacAddress[5]);
+ }
+ return LM_STATUS_SUCCESS;
+}
/******************************************************************************/
/* Description: */
/* None. */
/******************************************************************************/
static LM_STATUS
-LM_TranslateRequestedMediaType(
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
-PLM_MEDIA_TYPE pMediaType,
-PLM_LINE_SPEED pLineSpeed,
-PLM_DUPLEX_MODE pDuplexMode) {
- *pMediaType = LM_MEDIA_TYPE_AUTO;
- *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
- *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
-
- /* determine media type */
- switch(RequestedMediaType) {
+LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
+ PLM_MEDIA_TYPE pMediaType,
+ PLM_LINE_SPEED pLineSpeed,
+ PLM_DUPLEX_MODE pDuplexMode)
+{
+ *pMediaType = LM_MEDIA_TYPE_AUTO;
+ *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
+ *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+
+ /* determine media type */
+ switch (RequestedMediaType) {
case LM_REQUESTED_MEDIA_TYPE_BNC:
- *pMediaType = LM_MEDIA_TYPE_BNC;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_BNC;
+ *pLineSpeed = LM_LINE_SPEED_10MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_10MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_10MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
default:
- break;
- } /* switch */
+ break;
+ } /* switch */
- return LM_STATUS_SUCCESS;
-} /* LM_TranslateRequestedMediaType */
+ return LM_STATUS_SUCCESS;
+} /* LM_TranslateRequestedMediaType */
/******************************************************************************/
/* Description: */
/* LM_STATUS_LINK_ACTIVE */
/* LM_STATUS_LINK_DOWN */
/******************************************************************************/
-static LM_STATUS
-LM_InitBcm540xPhy(
-PLM_DEVICE_BLOCK pDevice)
+static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_LINE_SPEED CurrentLineSpeed;
- LM_DUPLEX_MODE CurrentDuplexMode;
- LM_STATUS CurrentLinkStatus;
- LM_UINT32 Value32;
- LM_UINT32 j;
-
-#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2);
+ LM_LINE_SPEED CurrentLineSpeed;
+ LM_DUPLEX_MODE CurrentDuplexMode;
+ LM_STATUS CurrentLinkStatus;
+ LM_UINT32 Value32;
+ LM_UINT32 j;
+
+#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2);
#endif
- if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
- {
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-
- if(!pDevice->InitDone)
- {
- Value32 = 0;
- }
-
- if(!(Value32 & PHY_STATUS_LINK_PASS))
- {
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
+ if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
+ if (!pDevice->InitDone) {
+ Value32 = 0;
+ }
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
+ if (!(Value32 & PHY_STATUS_LINK_PASS)) {
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- for(j = 0; j < 1000; j++)
- {
- MM_Wait(10);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
- MM_Wait(40);
- break;
- }
- }
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
- if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
- {
- if(!(Value32 & PHY_STATUS_LINK_PASS) &&
- (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
- {
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
- for(j = 0; j < 100; j++)
- {
- MM_Wait(10);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ for (j = 0; j < 1000; j++) {
+ MM_Wait (10);
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(!(Value32 & PHY_CTRL_PHY_RESET))
- {
- MM_Wait(40);
- break;
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ if (Value32 & PHY_STATUS_LINK_PASS) {
+ MM_Wait (40);
+ break;
+ }
}
- }
-
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
+ if ((pDevice->PhyId & PHY_ID_REV_MASK) ==
+ PHY_BCM5401_B0_REV) {
+ if (!(Value32 & PHY_STATUS_LINK_PASS)
+ && (pDevice->OldLineSpeed ==
+ LM_LINE_SPEED_1000MBPS)) {
+ LM_WritePhy (pDevice, PHY_CTRL_REG,
+ PHY_CTRL_PHY_RESET);
+ for (j = 0; j < 100; j++) {
+ MM_Wait (10);
+
+ LM_ReadPhy (pDevice,
+ PHY_CTRL_REG,
+ &Value32);
+ if (!
+ (Value32 &
+ PHY_CTRL_PHY_RESET)) {
+ MM_Wait (40);
+ break;
+ }
+ }
+
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL,
+ 0x0c20);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x0012);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x1804);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x0013);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x1204);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x8006);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x0132);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x8006);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x0232);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x201f);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x0a20);
+ }
+ }
+ }
+ } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+ /* Bug: 5701 A0, B0 TX CRC workaround. */
+ LM_WritePhy (pDevice, 0x15, 0x0a75);
+ LM_WritePhy (pDevice, 0x1c, 0x8c68);
+ LM_WritePhy (pDevice, 0x1c, 0x8d68);
+ LM_WritePhy (pDevice, 0x1c, 0x8c68);
+ }
+
+ /* Acknowledge interrupts. */
+ LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
+
+ /* Configure the interrupt mask. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+ LM_WritePhy (pDevice, BCM540X_INT_MASK_REG,
+ ~BCM540X_INT_LINK_CHANGE);
+ }
+
+ /* Configure PHY led mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
+ (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) {
+ if (pDevice->LedMode == LED_MODE_THREE_LINK) {
+ LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG,
+ BCM540X_EXT_CTRL_LINK3_LED_MODE);
+ } else {
+ LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0);
}
- }
- }
- }
- else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
- /* Bug: 5701 A0, B0 TX CRC workaround. */
- LM_WritePhy(pDevice, 0x15, 0x0a75);
- LM_WritePhy(pDevice, 0x1c, 0x8c68);
- LM_WritePhy(pDevice, 0x1c, 0x8d68);
- LM_WritePhy(pDevice, 0x1c, 0x8c68);
- }
-
- /* Acknowledge interrupts. */
- LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
-
- /* Configure the interrupt mask. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
- {
- LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
- }
-
- /* Configure PHY led mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
- (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
- {
- if(pDevice->LedMode == LED_MODE_THREE_LINK)
- {
- LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
- BCM540X_EXT_CTRL_LINK3_LED_MODE);
- }
- else
- {
- LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);
}
- }
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- /* Get current link and duplex mode. */
- for(j = 0; j < 100; j++)
- {
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+ /* Get current link and duplex mode. */
+ for (j = 0; j < 100; j++) {
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
- break;
+ if (Value32 & PHY_STATUS_LINK_PASS) {
+ break;
+ }
+ MM_Wait (40);
}
- MM_Wait(40);
- }
-
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
-
- /* Determine the current line and duplex settings. */
- LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
- for(j = 0; j < 2000; j++)
- {
- MM_Wait(10);
- LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
- if(Value32)
- {
- break;
- }
- }
+ if (Value32 & PHY_STATUS_LINK_PASS) {
- switch(Value32 & BCM540X_AUX_SPEED_MASK)
- {
- case BCM540X_AUX_10BASET_HD:
- CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ /* Determine the current line and duplex settings. */
+ LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
+ for (j = 0; j < 2000; j++) {
+ MM_Wait (10);
- case BCM540X_AUX_10BASET_FD:
- CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
+ if (Value32) {
+ break;
+ }
+ }
- case BCM540X_AUX_100BASETX_HD:
- CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ switch (Value32 & BCM540X_AUX_SPEED_MASK) {
+ case BCM540X_AUX_10BASET_HD:
+ CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
- case BCM540X_AUX_100BASETX_FD:
- CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ case BCM540X_AUX_10BASET_FD:
+ CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
- case BCM540X_AUX_100BASET_HD:
- CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ case BCM540X_AUX_100BASETX_HD:
+ CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
- case BCM540X_AUX_100BASET_FD:
- CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ case BCM540X_AUX_100BASETX_FD:
+ CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
- default:
+ case BCM540X_AUX_100BASET_HD:
+ CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
- CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
- CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
- break;
- }
+ case BCM540X_AUX_100BASET_FD:
+ CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
- /* Make sure we are in auto-neg mode. */
- for (j = 0; j < 200; j++)
- {
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(Value32 && Value32 != 0x7fff)
- {
- break;
- }
+ default:
- if(Value32 == 0 && pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS)
- {
- break;
- }
+ CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
+ CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+ break;
+ }
- MM_Wait(10);
- }
+ /* Make sure we are in auto-neg mode. */
+ for (j = 0; j < 200; j++) {
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if (Value32 && Value32 != 0x7fff) {
+ break;
+ }
- /* Use the current line settings for "auto" mode. */
- if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
- {
- if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ if (Value32 == 0 && pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) {
+ break;
+ }
- /* We may be exiting low power mode and the link is in */
- /* 10mb. In this case, we need to restart autoneg. */
- LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32);
- pDevice->advertising1000 = Value32;
- /* 5702FE supports 10/100Mb only. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 ||
- pDevice->BondId != GRC_MISC_BD_ID_5702FE)
- {
- if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF |
- BCM540X_AN_AD_1000BASET_FULL)))
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- }
- else
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- else
- {
- /* Force line settings. */
- /* Use the current setting if it matches the user's requested */
- /* setting. */
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if((pDevice->LineSpeed == CurrentLineSpeed) &&
- (pDevice->DuplexMode == CurrentDuplexMode))
- {
- if ((pDevice->DisableAutoNeg &&
- !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
- (!pDevice->DisableAutoNeg &&
- (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ MM_Wait (10);
}
- else
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
+
+ /* Use the current line settings for "auto" mode. */
+ if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO
+ || pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+ if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) {
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+
+ /* We may be exiting low power mode and the link is in */
+ /* 10mb. In this case, we need to restart autoneg. */
+ LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG,
+ &Value32);
+ pDevice->advertising1000 = Value32;
+ /* 5702FE supports 10/100Mb only. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) !=
+ T3_ASIC_REV_5703
+ || pDevice->BondId !=
+ GRC_MISC_BD_ID_5702FE) {
+ if (!
+ (Value32 &
+ (BCM540X_AN_AD_1000BASET_HALF |
+ BCM540X_AN_AD_1000BASET_FULL))) {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
+ }
+ } else {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
+ } else {
+ /* Force line settings. */
+ /* Use the current setting if it matches the user's requested */
+ /* setting. */
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if ((pDevice->LineSpeed == CurrentLineSpeed) &&
+ (pDevice->DuplexMode == CurrentDuplexMode)) {
+ if ((pDevice->DisableAutoNeg &&
+ !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
+ (!pDevice->DisableAutoNeg &&
+ (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_ACTIVE;
+ } else {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
+ } else {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
}
- }
- else
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- /* Save line settings. */
- pDevice->LineSpeed = CurrentLineSpeed;
- pDevice->DuplexMode = CurrentDuplexMode;
- pDevice->MediaType = LM_MEDIA_TYPE_UTP;
- }
+ /* Save line settings. */
+ pDevice->LineSpeed = CurrentLineSpeed;
+ pDevice->DuplexMode = CurrentDuplexMode;
+ pDevice->MediaType = LM_MEDIA_TYPE_UTP;
+ }
- return CurrentLinkStatus;
-} /* LM_InitBcm540xPhy */
+ return CurrentLinkStatus;
+} /* LM_InitBcm540xPhy */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
LM_STATUS
-LM_SetFlowControl(
- PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 LocalPhyAd,
- LM_UINT32 RemotePhyAd)
+LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd)
{
- LM_FLOW_CONTROL FlowCap;
+ LM_FLOW_CONTROL FlowCap;
- /* Resolve flow control. */
- FlowCap = LM_FLOW_CONTROL_NONE;
+ /* Resolve flow control. */
+ FlowCap = LM_FLOW_CONTROL_NONE;
- /* See Table 28B-3 of 802.3ab-1999 spec. */
- if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
- {
- if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
- {
- if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
- {
- if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
- {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
- {
- FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- }
- else
- {
- if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
- {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- }
- }
- else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
- {
- if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
- (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
- {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- }
- }
- }
- else
- {
- FlowCap = pDevice->FlowControlCap;
- }
-
- /* Enable/disable rx PAUSE. */
- pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
- if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
- (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
- pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
- {
- pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
- pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
-
- }
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
- /* Enable/disable tx PAUSE. */
- pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
- if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
- (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
- pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
- {
- pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
-
- }
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
- return LM_STATUS_SUCCESS;
-}
+ /* See Table 28B-3 of 802.3ab-1999 spec. */
+ if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) {
+ if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) {
+ if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
+ if (RemotePhyAd &
+ PHY_LINK_PARTNER_PAUSE_CAPABLE) {
+ FlowCap =
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+ LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ } else if (RemotePhyAd &
+ PHY_LINK_PARTNER_ASYM_PAUSE) {
+ FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ }
+ } else {
+ if (RemotePhyAd &
+ PHY_LINK_PARTNER_PAUSE_CAPABLE) {
+ FlowCap =
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+ LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ }
+ }
+ } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
+ if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
+ (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) {
+ FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
+ }
+ }
+ } else {
+ FlowCap = pDevice->FlowControlCap;
+ }
+
+ /* Enable/disable rx PAUSE. */
+ pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
+ if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
+ (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
+ pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) {
+ pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
+
+ }
+ REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+
+ /* Enable/disable tx PAUSE. */
+ pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
+ if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
+ (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
+ pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) {
+ pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
+ pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
+
+ }
+ REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
+ return LM_STATUS_SUCCESS;
+}
#if INCLUDE_TBI_SUPPORT
/******************************************************************************/
/* */
/* Return: */
/******************************************************************************/
-STATIC LM_STATUS
-LM_InitBcm800xPhy(
- PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT32 j;
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- Value32 = REG_RD(pDevice, MacCtrl.Status);
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
- /* Reset the SERDES during init and when we have link. */
- if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
- {
- /* Set PLL lock range. */
- LM_WritePhy(pDevice, 0x16, 0x8007);
+ /* Reset the SERDES during init and when we have link. */
+ if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) {
+ /* Set PLL lock range. */
+ LM_WritePhy (pDevice, 0x16, 0x8007);
- /* Software reset. */
- LM_WritePhy(pDevice, 0x00, 0x8000);
+ /* Software reset. */
+ LM_WritePhy (pDevice, 0x00, 0x8000);
- /* Wait for reset to complete. */
- for(j = 0; j < 500; j++)
- {
- MM_Wait(10);
- }
+ /* Wait for reset to complete. */
+ for (j = 0; j < 500; j++) {
+ MM_Wait (10);
+ }
- /* Config mode; seletct PMA/Ch 1 regs. */
- LM_WritePhy(pDevice, 0x10, 0x8411);
+ /* Config mode; seletct PMA/Ch 1 regs. */
+ LM_WritePhy (pDevice, 0x10, 0x8411);
- /* Enable auto-lock and comdet, select txclk for tx. */
- LM_WritePhy(pDevice, 0x11, 0x0a10);
+ /* Enable auto-lock and comdet, select txclk for tx. */
+ LM_WritePhy (pDevice, 0x11, 0x0a10);
- LM_WritePhy(pDevice, 0x18, 0x00a0);
- LM_WritePhy(pDevice, 0x16, 0x41ff);
+ LM_WritePhy (pDevice, 0x18, 0x00a0);
+ LM_WritePhy (pDevice, 0x16, 0x41ff);
- /* Assert and deassert POR. */
- LM_WritePhy(pDevice, 0x13, 0x0400);
- MM_Wait(40);
- LM_WritePhy(pDevice, 0x13, 0x0000);
+ /* Assert and deassert POR. */
+ LM_WritePhy (pDevice, 0x13, 0x0400);
+ MM_Wait (40);
+ LM_WritePhy (pDevice, 0x13, 0x0000);
- LM_WritePhy(pDevice, 0x11, 0x0a50);
- MM_Wait(40);
- LM_WritePhy(pDevice, 0x11, 0x0a10);
+ LM_WritePhy (pDevice, 0x11, 0x0a50);
+ MM_Wait (40);
+ LM_WritePhy (pDevice, 0x11, 0x0a10);
- /* Delay for signal to stabilize. */
- for(j = 0; j < 15000; j++)
- {
- MM_Wait(10);
- }
+ /* Delay for signal to stabilize. */
+ for (j = 0; j < 15000; j++) {
+ MM_Wait (10);
+ }
- /* Deselect the channel register so we can read the PHY id later. */
- LM_WritePhy(pDevice, 0x10, 0x8011);
- }
+ /* Deselect the channel register so we can read the PHY id later. */
+ LM_WritePhy (pDevice, 0x10, 0x8011);
+ }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-STATIC LM_STATUS
-LM_SetupFiberPhy(
- PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_STATUS CurrentLinkStatus;
- AUTONEG_STATUS AnStatus = 0;
- LM_UINT32 Value32;
- LM_UINT32 Cnt;
- LM_UINT32 j, k;
+ LM_STATUS CurrentLinkStatus;
+ AUTONEG_STATUS AnStatus = 0;
+ LM_UINT32 Value32;
+ LM_UINT32 Cnt;
+ LM_UINT32 j, k;
- pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
+ pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
- /* Initialize the send_config register. */
- REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
+ /* Initialize the send_config register. */
+ REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
- /* Enable TBI and full duplex mode. */
- pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
+ /* Enable TBI and full duplex mode. */
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- /* Initialize the BCM8002 SERDES PHY. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Initialize the BCM8002 SERDES PHY. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM8002_PHY_ID:
- LM_InitBcm800xPhy(pDevice);
- break;
+ LM_InitBcm800xPhy (pDevice);
+ break;
default:
- break;
- }
-
- /* Enable link change interrupt. */
- REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
-
- /* Default to link down. */
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ break;
+ }
- /* Get the link status. */
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if(Value32 & MAC_STATUS_PCS_SYNCED)
- {
- if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) ||
- (pDevice->DisableAutoNeg == FALSE))
- {
- /* auto-negotiation mode. */
- /* Initialize the autoneg default capaiblities. */
- AutonegInit(&pDevice->AnInfo);
-
- /* Set the context pointer to point to the main device structure. */
- pDevice->AnInfo.pContext = pDevice;
-
- /* Setup flow control advertisement register. */
- Value32 = GetPhyAdFlowCntrlSettings(pDevice);
- if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
- {
- pDevice->AnInfo.mr_adv_sym_pause = 1;
- }
- else
- {
- pDevice->AnInfo.mr_adv_sym_pause = 0;
- }
-
- if(Value32 & PHY_AN_AD_ASYM_PAUSE)
- {
- pDevice->AnInfo.mr_adv_asym_pause = 1;
- }
- else
- {
- pDevice->AnInfo.mr_adv_asym_pause = 0;
- }
-
- /* Try to autoneg up to six times. */
- if (pDevice->IgnoreTbiLinkChange)
- {
- Cnt = 1;
- }
- else
- {
- Cnt = 6;
- }
- for (j = 0; j < Cnt; j++)
- {
- REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
-
- Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
- REG_WR(pDevice, MacCtrl.Mode, Value32);
- MM_Wait(20);
-
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
-
- MM_Wait(20);
-
- pDevice->AnInfo.State = AN_STATE_UNKNOWN;
- pDevice->AnInfo.CurrentTime_us = 0;
-
- REG_WR(pDevice, Grc.Timer, 0);
- for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
- (k < 75000); k++)
- {
- AnStatus = Autoneg8023z(&pDevice->AnInfo);
-
- if((AnStatus == AUTONEG_STATUS_DONE) ||
- (AnStatus == AUTONEG_STATUS_FAILED))
- {
- break;
- }
+ /* Enable link change interrupt. */
+ REG_WR (pDevice, MacCtrl.MacEvent,
+ MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
- pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
+ /* Default to link down. */
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- }
- if((AnStatus == AUTONEG_STATUS_DONE) ||
- (AnStatus == AUTONEG_STATUS_FAILED))
- {
- break;
- }
- if (j >= 1)
- {
- if (!(REG_RD(pDevice, MacCtrl.Status) &
- MAC_STATUS_PCS_SYNCED)) {
- break;
- }
- }
- }
+ /* Get the link status. */
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (Value32 & MAC_STATUS_PCS_SYNCED) {
+ if ((pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_AUTO)
+ || (pDevice->DisableAutoNeg == FALSE)) {
+ /* auto-negotiation mode. */
+ /* Initialize the autoneg default capaiblities. */
+ AutonegInit (&pDevice->AnInfo);
+
+ /* Set the context pointer to point to the main device structure. */
+ pDevice->AnInfo.pContext = pDevice;
+
+ /* Setup flow control advertisement register. */
+ Value32 = GetPhyAdFlowCntrlSettings (pDevice);
+ if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) {
+ pDevice->AnInfo.mr_adv_sym_pause = 1;
+ } else {
+ pDevice->AnInfo.mr_adv_sym_pause = 0;
+ }
- /* Stop sending configs. */
- MM_AnTxIdle(&pDevice->AnInfo);
+ if (Value32 & PHY_AN_AD_ASYM_PAUSE) {
+ pDevice->AnInfo.mr_adv_asym_pause = 1;
+ } else {
+ pDevice->AnInfo.mr_adv_asym_pause = 0;
+ }
- /* Resolve flow control settings. */
- if((AnStatus == AUTONEG_STATUS_DONE) &&
- pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
- pDevice->AnInfo.mr_lp_adv_full_duplex)
- {
- LM_UINT32 RemotePhyAd;
- LM_UINT32 LocalPhyAd;
+ /* Try to autoneg up to six times. */
+ if (pDevice->IgnoreTbiLinkChange) {
+ Cnt = 1;
+ } else {
+ Cnt = 6;
+ }
+ for (j = 0; j < Cnt; j++) {
+ REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
+
+ Value32 =
+ pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
+ REG_WR (pDevice, MacCtrl.Mode, Value32);
+ MM_Wait (20);
+
+ REG_WR (pDevice, MacCtrl.Mode,
+ pDevice->
+ MacMode | MAC_MODE_SEND_CONFIGS);
+
+ MM_Wait (20);
+
+ pDevice->AnInfo.State = AN_STATE_UNKNOWN;
+ pDevice->AnInfo.CurrentTime_us = 0;
+
+ REG_WR (pDevice, Grc.Timer, 0);
+ for (k = 0;
+ (pDevice->AnInfo.CurrentTime_us < 75000)
+ && (k < 75000); k++) {
+ AnStatus =
+ Autoneg8023z (&pDevice->AnInfo);
+
+ if ((AnStatus == AUTONEG_STATUS_DONE) ||
+ (AnStatus == AUTONEG_STATUS_FAILED))
+ {
+ break;
+ }
+
+ pDevice->AnInfo.CurrentTime_us =
+ REG_RD (pDevice, Grc.Timer);
+
+ }
+ if ((AnStatus == AUTONEG_STATUS_DONE) ||
+ (AnStatus == AUTONEG_STATUS_FAILED)) {
+ break;
+ }
+ if (j >= 1) {
+ if (!(REG_RD (pDevice, MacCtrl.Status) &
+ MAC_STATUS_PCS_SYNCED)) {
+ break;
+ }
+ }
+ }
- LocalPhyAd = 0;
- if(pDevice->AnInfo.mr_adv_sym_pause)
- {
- LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
+ /* Stop sending configs. */
+ MM_AnTxIdle (&pDevice->AnInfo);
+
+ /* Resolve flow control settings. */
+ if ((AnStatus == AUTONEG_STATUS_DONE) &&
+ pDevice->AnInfo.mr_an_complete
+ && pDevice->AnInfo.mr_link_ok
+ && pDevice->AnInfo.mr_lp_adv_full_duplex) {
+ LM_UINT32 RemotePhyAd;
+ LM_UINT32 LocalPhyAd;
+
+ LocalPhyAd = 0;
+ if (pDevice->AnInfo.mr_adv_sym_pause) {
+ LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
+ }
+
+ if (pDevice->AnInfo.mr_adv_asym_pause) {
+ LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
+ }
+
+ RemotePhyAd = 0;
+ if (pDevice->AnInfo.mr_lp_adv_sym_pause) {
+ RemotePhyAd |=
+ PHY_LINK_PARTNER_PAUSE_CAPABLE;
+ }
+
+ if (pDevice->AnInfo.mr_lp_adv_asym_pause) {
+ RemotePhyAd |=
+ PHY_LINK_PARTNER_ASYM_PAUSE;
+ }
+
+ LM_SetFlowControl (pDevice, LocalPhyAd,
+ RemotePhyAd);
+
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ }
+ for (j = 0; j < 30; j++) {
+ MM_Wait (20);
+ REG_WR (pDevice, MacCtrl.Status,
+ MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
+ MM_Wait (20);
+ if ((REG_RD (pDevice, MacCtrl.Status) &
+ (MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED)) == 0)
+ break;
+ }
+ if (pDevice->PollTbiLink) {
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (Value32 & MAC_STATUS_RECEIVING_CFG) {
+ pDevice->IgnoreTbiLinkChange = TRUE;
+ } else {
+ pDevice->IgnoreTbiLinkChange = FALSE;
+ }
+ }
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
+ (Value32 & MAC_STATUS_PCS_SYNCED) &&
+ ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) {
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ }
+ } else {
+ /* We are forcing line speed. */
+ pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
+ LM_SetFlowControl (pDevice, 0, 0);
+
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+ MAC_MODE_SEND_CONFIGS);
}
+ }
+ /* Set the link polarity bit. */
+ pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- if(pDevice->AnInfo.mr_adv_asym_pause)
- {
- LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
- }
+ pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
+ (pDevice->pStatusBlkVirt->
+ Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
- RemotePhyAd = 0;
- if(pDevice->AnInfo.mr_lp_adv_sym_pause)
- {
- RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
- }
+ for (j = 0; j < 100; j++) {
+ REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
+ MM_Wait (5);
+ if ((REG_RD (pDevice, MacCtrl.Status) &
+ (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
+ break;
+ }
- if(pDevice->AnInfo.mr_lp_adv_asym_pause)
- {
- RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) {
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ if (pDevice->DisableAutoNeg == FALSE) {
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+ MAC_MODE_SEND_CONFIGS);
+ MM_Wait (1);
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
}
+ }
- LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
+ /* Initialize the current link status. */
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
+ pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
+ REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
+ LED_CTRL_1000MBPS_LED_ON);
+ } else {
+ pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
+ pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+ REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
+ LED_CTRL_OVERRIDE_TRAFFIC_LED);
+ }
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
- for (j = 0; j < 30; j++)
- {
- MM_Wait(20);
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MM_Wait(20);
- if ((REG_RD(pDevice, MacCtrl.Status) &
- (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
- break;
- }
- if (pDevice->PollTbiLink)
- {
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if (Value32 & MAC_STATUS_RECEIVING_CFG)
- {
- pDevice->IgnoreTbiLinkChange = TRUE;
- }
- else
- {
- pDevice->IgnoreTbiLinkChange = FALSE;
- }
- }
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
- (Value32 & MAC_STATUS_PCS_SYNCED) &&
- ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
+ /* Indicate link status. */
+ if (pDevice->LinkStatus != CurrentLinkStatus) {
+ pDevice->LinkStatus = CurrentLinkStatus;
+ MM_IndicateStatus (pDevice, CurrentLinkStatus);
}
- else
- {
- /* We are forcing line speed. */
- pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
- LM_SetFlowControl(pDevice, 0, 0);
-
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
- }
- }
- /* Set the link polarity bit. */
- pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
- (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
-
- for (j = 0; j < 100; j++)
- {
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MM_Wait(5);
- if ((REG_RD(pDevice, MacCtrl.Status) &
- (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
- break;
- }
-
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
- {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- if (pDevice->DisableAutoNeg == FALSE)
- {
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
- MM_Wait(1);
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
- }
- }
-
- /* Initialize the current link status. */
- if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
- pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
- REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_1000MBPS_LED_ON);
- }
- else
- {
- pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
- pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
- REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_OVERRIDE_TRAFFIC_LED);
- }
-
- /* Indicate link status. */
- if (pDevice->LinkStatus != CurrentLinkStatus) {
- pDevice->LinkStatus = CurrentLinkStatus;
- MM_IndicateStatus(pDevice, CurrentLinkStatus);
- }
-
- return LM_STATUS_SUCCESS;
-}
-#endif /* INCLUDE_TBI_SUPPORT */
+ return LM_STATUS_SUCCESS;
+}
+#endif /* INCLUDE_TBI_SUPPORT */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetupCopperPhy(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_STATUS CurrentLinkStatus;
- LM_UINT32 Value32;
+ LM_STATUS CurrentLinkStatus;
+ LM_UINT32 Value32;
- /* Assume there is not link first. */
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ /* Assume there is not link first. */
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- /* Disable phy link change attention. */
- REG_WR(pDevice, MacCtrl.MacEvent, 0);
+ /* Disable phy link change attention. */
+ REG_WR (pDevice, MacCtrl.MacEvent, 0);
- /* Clear link change attention. */
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
+ /* Clear link change attention. */
+ REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
- /* Disable auto-polling for the moment. */
- pDevice->MiMode = 0xc0000;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
+ /* Disable auto-polling for the moment. */
+ pDevice->MiMode = 0xc0000;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
- /* Determine the requested line speed and duplex. */
- pDevice->OldLineSpeed = pDevice->LineSpeed;
- LM_TranslateRequestedMediaType(pDevice->RequestedMediaType,
- &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode);
+ /* Determine the requested line speed and duplex. */
+ pDevice->OldLineSpeed = pDevice->LineSpeed;
+ LM_TranslateRequestedMediaType (pDevice->RequestedMediaType,
+ &pDevice->MediaType,
+ &pDevice->LineSpeed,
+ &pDevice->DuplexMode);
- /* Initialize the phy chip. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Initialize the phy chip. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM5400_PHY_ID:
case PHY_BCM5401_PHY_ID:
case PHY_BCM5411_PHY_ID:
case PHY_BCM5701_PHY_ID:
case PHY_BCM5703_PHY_ID:
case PHY_BCM5704_PHY_ID:
- CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
- break;
+ CurrentLinkStatus = LM_InitBcm540xPhy (pDevice);
+ break;
default:
- break;
- }
-
- if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
- {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- }
+ break;
+ }
- /* Setup flow control. */
- pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
- if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
+ if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) {
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ }
+
+ /* Setup flow control. */
+ pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
+
+ FlowCap = LM_FLOW_CONTROL_NONE;
+
+ if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
+ if (pDevice->DisableAutoNeg == FALSE ||
+ pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_AUTO
+ || pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+ LM_UINT32 ExpectedPhyAd;
+ LM_UINT32 LocalPhyAd;
+ LM_UINT32 RemotePhyAd;
+
+ LM_ReadPhy (pDevice, PHY_AN_AD_REG,
+ &LocalPhyAd);
+ pDevice->advertising = LocalPhyAd;
+ LocalPhyAd &=
+ (PHY_AN_AD_ASYM_PAUSE |
+ PHY_AN_AD_PAUSE_CAPABLE);
+
+ ExpectedPhyAd =
+ GetPhyAdFlowCntrlSettings (pDevice);
+
+ if (LocalPhyAd != ExpectedPhyAd) {
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ } else {
+ LM_ReadPhy (pDevice,
+ PHY_LINK_PARTNER_ABILITY_REG,
+ &RemotePhyAd);
+
+ LM_SetFlowControl (pDevice, LocalPhyAd,
+ RemotePhyAd);
+ }
+ } else {
+ pDevice->FlowControlCap &=
+ ~LM_FLOW_CONTROL_AUTO_PAUSE;
+ LM_SetFlowControl (pDevice, 0, 0);
+ }
+ }
+ }
- FlowCap = LM_FLOW_CONTROL_NONE;
+ if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) {
+ LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType);
- if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
- {
- if(pDevice->DisableAutoNeg == FALSE ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
- {
- LM_UINT32 ExpectedPhyAd;
- LM_UINT32 LocalPhyAd;
- LM_UINT32 RemotePhyAd;
+ /* If we force line speed, we make get link right away. */
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ if (Value32 & PHY_STATUS_LINK_PASS) {
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ }
+ }
- LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
- pDevice->advertising = LocalPhyAd;
- LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
+ /* GMII interface. */
+ pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
+ pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
+ } else {
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
+ }
+ } else {
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
+ }
- ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
+ /* Set the MAC to operate in the appropriate duplex mode. */
+ pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
+ if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) {
+ pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
+ }
- if(LocalPhyAd != ExpectedPhyAd)
- {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ /* Set the link polarity bit. */
+ pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ if ((pDevice->LedMode == LED_MODE_LINK10) ||
+ (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
+ pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) {
+ pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+ }
+ } else {
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
}
- else
- {
- LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
- &RemotePhyAd);
- LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
+ /* Set LED mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ } else {
+ if (pDevice->LedMode == LED_MODE_OUTPUT) {
+ Value32 = LED_CTRL_PHY_MODE_2;
+ } else {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ }
}
- }
- else
- {
- pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
- LM_SetFlowControl(pDevice, 0, 0);
- }
+ REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
}
- }
- if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
- {
- LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType);
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- /* If we force line speed, we make get link right away. */
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ /* Enable auto polling. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
}
- }
- /* GMII interface. */
- pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
- if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
- pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
- {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
- }
- else
- {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
- }
- }
- else {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
- }
-
- /* Set the MAC to operate in the appropriate duplex mode. */
- pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
- if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
- {
- pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
- }
-
- /* Set the link polarity bit. */
- pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- if((pDevice->LedMode == LED_MODE_LINK10) ||
- (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
- pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
- {
- pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+ /* Enable phy link change attention. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+ REG_WR (pDevice, MacCtrl.MacEvent,
+ MAC_EVENT_ENABLE_MI_INTERRUPT);
+ } else {
+ REG_WR (pDevice, MacCtrl.MacEvent,
+ MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
}
- }
- else
- {
- if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+ if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
+ (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
+ (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
+ (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
+ (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
+ !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) {
+ MM_Wait (120);
+ REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
+ MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX,
+ T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
}
- /* Set LED mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = LED_CTRL_PHY_MODE_1;
+ /* Indicate link status. */
+ if (pDevice->LinkStatus != CurrentLinkStatus) {
+ pDevice->LinkStatus = CurrentLinkStatus;
+ MM_IndicateStatus (pDevice, CurrentLinkStatus);
}
- else
- {
- if(pDevice->LedMode == LED_MODE_OUTPUT)
- {
- Value32 = LED_CTRL_PHY_MODE_2;
- }
- else
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- }
- REG_WR(pDevice, MacCtrl.LedCtrl, Value32);
- }
-
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- /* Enable auto polling. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- }
-
- /* Enable phy link change attention. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
- {
- REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
- }
- else
- {
- REG_WR(pDevice, MacCtrl.MacEvent,
- MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
- }
- if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
- (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
- (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
- (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
- (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
- !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
- {
- MM_Wait(120);
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
- T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
- }
-
- /* Indicate link status. */
- if (pDevice->LinkStatus != CurrentLinkStatus) {
- pDevice->LinkStatus = CurrentLinkStatus;
- MM_IndicateStatus(pDevice, CurrentLinkStatus);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetupCopperPhy */
+
+ return LM_STATUS_SUCCESS;
+} /* LM_SetupCopperPhy */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetupPhy(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_STATUS LmStatus;
- LM_UINT32 Value32;
+ LM_STATUS LmStatus;
+ LM_UINT32 Value32;
#if INCLUDE_TBI_SUPPORT
- if(pDevice->EnableTbi)
- {
- LmStatus = LM_SetupFiberPhy(pDevice);
- }
- else
-#endif /* INCLUDE_TBI_SUPPORT */
- {
- LmStatus = LM_SetupCopperPhy(pDevice);
- }
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- Value32 = REG_RD(pDevice, PciCfg.PciState);
- REG_WR(pDevice, PciCfg.PciState,
- Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
- }
- }
- if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
- (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
- {
- REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
- }
- else
- {
- REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
- }
-
- return LmStatus;
+ if (pDevice->EnableTbi) {
+ LmStatus = LM_SetupFiberPhy (pDevice);
+ } else
+#endif /* INCLUDE_TBI_SUPPORT */
+ {
+ LmStatus = LM_SetupCopperPhy (pDevice);
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ Value32 = REG_RD (pDevice, PciCfg.PciState);
+ REG_WR (pDevice, PciCfg.PciState,
+ Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
+ }
+ }
+ if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
+ (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) {
+ REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff);
+ } else {
+ REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
+ }
+
+ return LmStatus;
}
/******************************************************************************/
/* Return: */
/******************************************************************************/
LM_VOID
-LM_ReadPhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 PhyReg,
-PLM_UINT32 pData32) {
- LM_UINT32 Value32;
- LM_UINT32 j;
+LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32)
+{
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
- ~MI_MODE_AUTO_POLLING_ENABLE);
- MM_Wait(40);
- }
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
+ ~MI_MODE_AUTO_POLLING_ENABLE);
+ MM_Wait (40);
+ }
- Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
- ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
- MI_COM_CMD_READ | MI_COM_START;
+ Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
+ ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
+ MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START;
- REG_WR(pDevice, MacCtrl.MiCom, Value32);
+ REG_WR (pDevice, MacCtrl.MiCom, Value32);
- for(j = 0; j < 20; j++)
- {
- MM_Wait(25);
+ for (j = 0; j < 20; j++) {
+ MM_Wait (25);
- Value32 = REG_RD(pDevice, MacCtrl.MiCom);
+ Value32 = REG_RD (pDevice, MacCtrl.MiCom);
- if(!(Value32 & MI_COM_BUSY))
- {
- MM_Wait(5);
- Value32 = REG_RD(pDevice, MacCtrl.MiCom);
- Value32 &= MI_COM_PHY_DATA_MASK;
- break;
+ if (!(Value32 & MI_COM_BUSY)) {
+ MM_Wait (5);
+ Value32 = REG_RD (pDevice, MacCtrl.MiCom);
+ Value32 &= MI_COM_PHY_DATA_MASK;
+ break;
+ }
}
- }
-
- if(Value32 & MI_COM_BUSY)
- {
- Value32 = 0;
- }
- *pData32 = Value32;
+ if (Value32 & MI_COM_BUSY) {
+ Value32 = 0;
+ }
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
- }
-} /* LM_ReadPhy */
+ *pData32 = Value32;
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
+ }
+} /* LM_ReadPhy */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
LM_VOID
-LM_WritePhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 PhyReg,
-LM_UINT32 Data32) {
- LM_UINT32 Value32;
- LM_UINT32 j;
+LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32)
+{
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
- ~MI_MODE_AUTO_POLLING_ENABLE);
- MM_Wait(40);
- }
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
+ ~MI_MODE_AUTO_POLLING_ENABLE);
+ MM_Wait (40);
+ }
- Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
- ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
- (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
+ Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
+ ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
+ MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) |
+ MI_COM_CMD_WRITE | MI_COM_START;
- REG_WR(pDevice, MacCtrl.MiCom, Value32);
+ REG_WR (pDevice, MacCtrl.MiCom, Value32);
- for(j = 0; j < 20; j++)
- {
- MM_Wait(25);
+ for (j = 0; j < 20; j++) {
+ MM_Wait (25);
- Value32 = REG_RD(pDevice, MacCtrl.MiCom);
+ Value32 = REG_RD (pDevice, MacCtrl.MiCom);
- if(!(Value32 & MI_COM_BUSY))
- {
- MM_Wait(5);
- break;
+ if (!(Value32 & MI_COM_BUSY)) {
+ MM_Wait (5);
+ break;
+ }
}
- }
-
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
- }
-} /* LM_WritePhy */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
+ }
+} /* LM_WritePhy */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetPowerState(
-PLM_DEVICE_BLOCK pDevice,
-LM_POWER_STATE PowerLevel) {
- LM_UINT32 PmeSupport;
- LM_UINT32 Value32;
- LM_UINT32 PmCtrl;
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel)
+{
+ LM_UINT32 PmeSupport;
+ LM_UINT32 Value32;
+ LM_UINT32 PmCtrl;
- /* make sureindirect accesses are enabled*/
- MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
+ /* make sureindirect accesses are enabled */
+ MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+ pDevice->MiscHostCtrl);
- /* Clear the PME_ASSERT bit and the power state bits. Also enable */
- /* the PME bit. */
- MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
+ /* Clear the PME_ASSERT bit and the power state bits. Also enable */
+ /* the PME bit. */
+ MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
- PmCtrl |= T3_PM_PME_ASSERTED;
- PmCtrl &= ~T3_PM_POWER_STATE_MASK;
+ PmCtrl |= T3_PM_PME_ASSERTED;
+ PmCtrl &= ~T3_PM_POWER_STATE_MASK;
- /* Set the appropriate power state. */
- if(PowerLevel == LM_POWER_STATE_D0)
- {
+ /* Set the appropriate power state. */
+ if (PowerLevel == LM_POWER_STATE_D0) {
- /* Bring the card out of low power mode. */
- PmCtrl |= T3_PM_POWER_STATE_D0;
- MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
+ /* Bring the card out of low power mode. */
+ PmCtrl |= T3_PM_POWER_STATE_D0;
+ MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
- MM_Wait (40);
-#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
+ MM_Wait (40);
+#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02);
#endif
- return LM_STATUS_SUCCESS;
- }
- else if(PowerLevel == LM_POWER_STATE_D1)
- {
- PmCtrl |= T3_PM_POWER_STATE_D1;
- }
- else if(PowerLevel == LM_POWER_STATE_D2)
- {
- PmCtrl |= T3_PM_POWER_STATE_D2;
- }
- else if(PowerLevel == LM_POWER_STATE_D3)
- {
- PmCtrl |= T3_PM_POWER_STATE_D3;
- }
- else
- {
- return LM_STATUS_FAILURE;
- }
- PmCtrl |= T3_PM_PME_ENABLE;
-
- /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
- /* setting new line speed. */
- Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
- REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
-
- if(!pDevice->RestoreOnWakeUp)
- {
- pDevice->RestoreOnWakeUp = TRUE;
- pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
- pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
- }
-
- /* Force auto-negotiation to 10 line speed. */
- pDevice->DisableAutoNeg = FALSE;
- pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
- LM_SetupPhy(pDevice);
-
- /* Put the driver in the initial state, and go through the power down */
- /* sequence. */
- LM_Halt(pDevice);
-
- MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
-
- if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
- {
-
- /* Enable WOL. */
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
- MM_Wait(40);
-
- /* Set LED mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- else
- {
- if(pDevice->LedMode == LED_MODE_OUTPUT)
- {
- Value32 = LED_CTRL_PHY_MODE_2;
- }
- else
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
+ return LM_STATUS_SUCCESS;
+ } else if (PowerLevel == LM_POWER_STATE_D1) {
+ PmCtrl |= T3_PM_POWER_STATE_D1;
+ } else if (PowerLevel == LM_POWER_STATE_D2) {
+ PmCtrl |= T3_PM_POWER_STATE_D2;
+ } else if (PowerLevel == LM_POWER_STATE_D3) {
+ PmCtrl |= T3_PM_POWER_STATE_D3;
+ } else {
+ return LM_STATUS_FAILURE;
}
+ PmCtrl |= T3_PM_PME_ENABLE;
- Value32 = MAC_MODE_PORT_MODE_MII;
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- if(pDevice->LedMode == LED_MODE_LINK10 ||
- pDevice->WolSpeed == WOL_SPEED_10MB)
- {
- Value32 |= MAC_MODE_LINK_POLARITY;
- }
- }
- else
- {
- Value32 |= MAC_MODE_LINK_POLARITY;
- }
- REG_WR(pDevice, MacCtrl.Mode, Value32);
- MM_Wait(40); MM_Wait(40); MM_Wait(40);
+ /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
+ /* setting new line speed. */
+ Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl,
+ Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
- /* Always enable magic packet wake-up if we have vaux. */
- if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
- (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
- {
- Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
+ if (!pDevice->RestoreOnWakeUp) {
+ pDevice->RestoreOnWakeUp = TRUE;
+ pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
+ pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
}
- REG_WR(pDevice, MacCtrl.Mode, Value32);
+ /* Force auto-negotiation to 10 line speed. */
+ pDevice->DisableAutoNeg = FALSE;
+ pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
+ LM_SetupPhy (pDevice);
- /* Enable the receiver. */
- REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
- }
-
- /* Disable tx/rx clocks, and seletect an alternate clock. */
- if(pDevice->WolSpeed == WOL_SPEED_100MB)
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK;
- }
- else
- {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
- }
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
+ /* Put the driver in the initial state, and go through the power down */
+ /* sequence. */
+ LM_Halt (pDevice);
- MM_Wait(40);
+ MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
- }
- else
- {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- }
+ if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) {
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
+ /* Enable WOL. */
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a);
+ MM_Wait (40);
- MM_Wait(40);
+ /* Set LED mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ } else {
+ if (pDevice->LedMode == LED_MODE_OUTPUT) {
+ Value32 = LED_CTRL_PHY_MODE_2;
+ } else {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ }
+ }
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- }
- else
- {
- Value32 = T3_PCI_44MHZ_CORE_CLOCK;
- }
+ Value32 = MAC_MODE_PORT_MODE_MII;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ if (pDevice->LedMode == LED_MODE_LINK10 ||
+ pDevice->WolSpeed == WOL_SPEED_10MB) {
+ Value32 |= MAC_MODE_LINK_POLARITY;
+ }
+ } else {
+ Value32 |= MAC_MODE_LINK_POLARITY;
+ }
+ REG_WR (pDevice, MacCtrl.Mode, Value32);
+ MM_Wait (40);
+ MM_Wait (40);
+ MM_Wait (40);
+
+ /* Always enable magic packet wake-up if we have vaux. */
+ if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
+ (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) {
+ Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
+ }
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
- }
- else
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_POWER_DOWN_PCI_PLL133;
- }
- else
- {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_POWER_DOWN_PCI_PLL133;
+ REG_WR (pDevice, MacCtrl.Mode, Value32);
+
+ /* Enable the receiver. */
+ REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
}
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
- }
+ /* Disable tx/rx clocks, and seletect an alternate clock. */
+ if (pDevice->WolSpeed == WOL_SPEED_100MB) {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK;
+ } else {
+ Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
+ }
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+
+ MM_Wait (40);
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_44MHZ_CORE_CLOCK;
+ } else {
+ Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_44MHZ_CORE_CLOCK;
+ }
- MM_Wait(40);
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
- if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE))
- {
- /* Switch adapter to auxilliary power. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
- MM_Wait(40);
+ MM_Wait (40);
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_44MHZ_CORE_CLOCK;
+ } else {
+ Value32 = T3_PCI_44MHZ_CORE_CLOCK;
+ }
+
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+ } else {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_POWER_DOWN_PCI_PLL133;
+ } else {
+ Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_POWER_DOWN_PCI_PLL133;
+ }
+
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+ }
+
+ MM_Wait (40);
+
+ if (!pDevice->EepromWp
+ && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) {
+ /* Switch adapter to auxilliary power. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
+ MM_Wait (40);
+ } else {
+ /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
+ MM_Wait (40);
+
+ /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
+ MM_Wait (40);
+
+ /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
+ MM_Wait (40);
+ }
}
- else
- {
- /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
- MM_Wait(40);
-
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
- MM_Wait(40);
-
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
- MM_Wait(40);
- }
- }
-
- /* Set the phy to low power mode. */
- /* Put the the hardware in low power mode. */
- MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetPowerState */
+ /* Set the phy to low power mode. */
+ /* Put the the hardware in low power mode. */
+ MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
+
+ return LM_STATUS_SUCCESS;
+} /* LM_SetPowerState */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-static LM_UINT32
-GetPhyAdFlowCntrlSettings(
- PLM_DEVICE_BLOCK pDevice)
+static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
-
- Value32 = 0;
-
- /* Auto negotiation flow control only when autonegotiation is enabled. */
- if(pDevice->DisableAutoNeg == FALSE ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
- {
- /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
- if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
- ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
- (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
- {
- Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
- }
- else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
- {
- Value32 |= PHY_AN_AD_ASYM_PAUSE;
- }
- else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
- {
- Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
+ LM_UINT32 Value32;
+
+ Value32 = 0;
+
+ /* Auto negotiation flow control only when autonegotiation is enabled. */
+ if (pDevice->DisableAutoNeg == FALSE ||
+ pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
+ pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+ /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
+ if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
+ ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
+ && (pDevice->
+ FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) {
+ Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
+ } else if (pDevice->
+ FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) {
+ Value32 |= PHY_AN_AD_ASYM_PAUSE;
+ } else if (pDevice->
+ FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
+ Value32 |=
+ PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
+ }
}
- }
- return Value32;
+ return Value32;
}
-
/******************************************************************************/
/* Description: */
/* */
/* */
/******************************************************************************/
static LM_STATUS
-LM_ForceAutoNegBcm540xPhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
+LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
{
- LM_MEDIA_TYPE MediaType;
- LM_LINE_SPEED LineSpeed;
- LM_DUPLEX_MODE DuplexMode;
- LM_UINT32 NewPhyCtrl;
- LM_UINT32 Value32;
- LM_UINT32 Cnt;
-
- /* Get the interface type, line speed, and duplex mode. */
- LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed,
- &DuplexMode);
-
- if (pDevice->RestoreOnWakeUp)
- {
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
- Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
- if (pDevice->WolSpeed == WOL_SPEED_100MB)
- {
- Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- }
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- /* Setup the auto-negotiation advertisement register. */
- else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
- {
- /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
- PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
- PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- /* Advertise 1000Mbps */
- Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
+ LM_MEDIA_TYPE MediaType;
+ LM_LINE_SPEED LineSpeed;
+ LM_DUPLEX_MODE DuplexMode;
+ LM_UINT32 NewPhyCtrl;
+ LM_UINT32 Value32;
+ LM_UINT32 Cnt;
+
+ /* Get the interface type, line speed, and duplex mode. */
+ LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType,
+ &LineSpeed, &DuplexMode);
+
+ if (pDevice->RestoreOnWakeUp) {
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+ pDevice->advertising1000 = 0;
+ Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
+ if (pDevice->WolSpeed == WOL_SPEED_100MB) {
+ Value32 |=
+ PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
+ }
+ Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+ }
+ /* Setup the auto-negotiation advertisement register. */
+ else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) {
+ /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
+ Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
+ PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
+ PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+
+ /* Advertise 1000Mbps */
+ Value32 =
+ BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
#if INCLUDE_5701_AX_FIX
- /* Bug: workaround for CRC error in gigabit mode when we are in */
- /* slave mode. This will force the PHY to operate in */
- /* master mode. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
- Value32 |= BCM540X_CONFIG_AS_MASTER |
- BCM540X_ENABLE_CONFIG_AS_MASTER;
- }
+ /* Bug: workaround for CRC error in gigabit mode when we are in */
+ /* slave mode. This will force the PHY to operate in */
+ /* master mode. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+ Value32 |= BCM540X_CONFIG_AS_MASTER |
+ BCM540X_ENABLE_CONFIG_AS_MASTER;
+ }
#endif
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
- }
- else
- {
- if(LineSpeed == LM_LINE_SPEED_1000MBPS)
- {
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
+ pDevice->advertising1000 = Value32;
+ } else {
+ if (LineSpeed == LM_LINE_SPEED_1000MBPS) {
+ Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+
+ if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+ Value32 = BCM540X_AN_AD_1000BASET_HALF;
+ } else {
+ Value32 = BCM540X_AN_AD_1000BASET_FULL;
+ }
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG,
+ Value32);
+ pDevice->advertising1000 = Value32;
+ } else if (LineSpeed == LM_LINE_SPEED_100MBPS) {
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+ pDevice->advertising1000 = 0;
+
+ if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+ Value32 = PHY_AN_AD_100BASETX_HALF;
+ } else {
+ Value32 = PHY_AN_AD_100BASETX_FULL;
+ }
- if(DuplexMode != LM_DUPLEX_MODE_FULL)
- {
- Value32 = BCM540X_AN_AD_1000BASET_HALF;
- }
- else
- {
- Value32 = BCM540X_AN_AD_1000BASET_FULL;
- }
+ Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
- }
- else if(LineSpeed == LM_LINE_SPEED_100MBPS)
- {
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+ } else if (LineSpeed == LM_LINE_SPEED_10MBPS) {
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+ pDevice->advertising1000 = 0;
- if(DuplexMode != LM_DUPLEX_MODE_FULL)
- {
- Value32 = PHY_AN_AD_100BASETX_HALF;
- }
- else
- {
- Value32 = PHY_AN_AD_100BASETX_FULL;
- }
+ if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+ Value32 = PHY_AN_AD_10BASET_HALF;
+ } else {
+ Value32 = PHY_AN_AD_10BASET_FULL;
+ }
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
+ Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- else if(LineSpeed == LM_LINE_SPEED_10MBPS)
- {
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
-
- if(DuplexMode != LM_DUPLEX_MODE_FULL)
- {
- Value32 = PHY_AN_AD_10BASET_HALF;
- }
- else
- {
- Value32 = PHY_AN_AD_10BASET_FULL;
- }
-
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- }
-
- /* Force line speed if auto-negotiation is disabled. */
- if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
- {
- /* This code path is executed only when there is link. */
- pDevice->MediaType = MediaType;
- pDevice->LineSpeed = LineSpeed;
- pDevice->DuplexMode = DuplexMode;
-
- /* Force line seepd. */
- NewPhyCtrl = 0;
- switch(LineSpeed)
- {
- case LM_LINE_SPEED_10MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
- break;
- case LM_LINE_SPEED_100MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
- break;
- case LM_LINE_SPEED_1000MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
- break;
- default:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
- break;
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+ }
}
- if(DuplexMode == LM_DUPLEX_MODE_FULL)
- {
- NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
- }
+ /* Force line speed if auto-negotiation is disabled. */
+ if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) {
+ /* This code path is executed only when there is link. */
+ pDevice->MediaType = MediaType;
+ pDevice->LineSpeed = LineSpeed;
+ pDevice->DuplexMode = DuplexMode;
- /* Don't do anything if the PHY_CTRL is already what we wanted. */
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(Value32 != NewPhyCtrl)
- {
- /* Temporary bring the link down before forcing line speed. */
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
+ /* Force line seepd. */
+ NewPhyCtrl = 0;
+ switch (LineSpeed) {
+ case LM_LINE_SPEED_10MBPS:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
+ break;
+ case LM_LINE_SPEED_100MBPS:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
+ break;
+ case LM_LINE_SPEED_1000MBPS:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
+ break;
+ default:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
+ break;
+ }
- /* Wait for link to go down. */
- for(Cnt = 0; Cnt < 15000; Cnt++)
- {
- MM_Wait(10);
+ if (DuplexMode == LM_DUPLEX_MODE_FULL) {
+ NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
+ }
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+ /* Don't do anything if the PHY_CTRL is already what we wanted. */
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if (Value32 != NewPhyCtrl) {
+ /* Temporary bring the link down before forcing line speed. */
+ LM_WritePhy (pDevice, PHY_CTRL_REG,
+ PHY_CTRL_LOOPBACK_MODE);
- if(!(Value32 & PHY_STATUS_LINK_PASS))
- {
- MM_Wait(40);
- break;
- }
- }
+ /* Wait for link to go down. */
+ for (Cnt = 0; Cnt < 15000; Cnt++) {
+ MM_Wait (10);
- LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
- MM_Wait(40);
- }
- }
- else
- {
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
- PHY_CTRL_RESTART_AUTO_NEG);
- }
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- return LM_STATUS_SUCCESS;
-} /* LM_ForceAutoNegBcm540xPhy */
+ if (!(Value32 & PHY_STATUS_LINK_PASS)) {
+ MM_Wait (40);
+ break;
+ }
+ }
+
+ LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl);
+ MM_Wait (40);
+ }
+ } else {
+ LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
+ PHY_CTRL_RESTART_AUTO_NEG);
+ }
+ return LM_STATUS_SUCCESS;
+} /* LM_ForceAutoNegBcm540xPhy */
/******************************************************************************/
/* Description: */
/* Return: */
/******************************************************************************/
static LM_STATUS
-LM_ForceAutoNeg(
-PLM_DEVICE_BLOCK pDevice,
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
+LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
{
- LM_STATUS LmStatus;
+ LM_STATUS LmStatus;
- /* Initialize the phy chip. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Initialize the phy chip. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM5400_PHY_ID:
case PHY_BCM5401_PHY_ID:
case PHY_BCM5411_PHY_ID:
case PHY_BCM5701_PHY_ID:
case PHY_BCM5703_PHY_ID:
case PHY_BCM5704_PHY_ID:
- LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType);
- break;
+ LmStatus =
+ LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType);
+ break;
default:
- LmStatus = LM_STATUS_FAILURE;
- break;
- }
+ LmStatus = LM_STATUS_FAILURE;
+ break;
+ }
- return LmStatus;
-} /* LM_ForceAutoNeg */
+ return LmStatus;
+} /* LM_ForceAutoNeg */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu,
- LM_UINT32 StartCpu)
+LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
+ PT3_FWIMG_INFO pFwImg,
+ LM_UINT32 LoadCpu, LM_UINT32 StartCpu)
{
- LM_UINT32 i;
- LM_UINT32 address;
+ LM_UINT32 i;
+ LM_UINT32 address;
- if (LoadCpu & T3_RX_CPU_ID)
- {
- if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
+ if (LoadCpu & T3_RX_CPU_ID) {
+ if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) {
+ return LM_STATUS_FAILURE;
+ }
- /* First of all clear scrach pad memory */
- for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4)
- {
- LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0);
- }
+ /* First of all clear scrach pad memory */
+ for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) {
+ LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0);
+ }
- /* Copy code first */
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
- for (i = 0; i <= pFwImg->Text.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
- }
+ /* Copy code first */
+ address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Text.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
+ 4]);
+ }
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
- for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
- }
+ address =
+ T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->ROnlyData.
+ Buffer)[i / 4]);
+ }
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
- for (i= 0; i <= pFwImg->Data.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
+ address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Data.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
+ 4]);
+ }
}
- }
- if (LoadCpu & T3_TX_CPU_ID)
- {
- if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
+ if (LoadCpu & T3_TX_CPU_ID) {
+ if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) {
+ return LM_STATUS_FAILURE;
+ }
- /* First of all clear scrach pad memory */
- for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
- {
- LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
- }
+ /* First of all clear scrach pad memory */
+ for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) {
+ LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0);
+ }
- /* Copy code first */
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
- for (i= 0; i <= pFwImg->Text.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
- }
+ /* Copy code first */
+ address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Text.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
+ 4]);
+ }
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
- for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
- }
+ address =
+ T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->ROnlyData.
+ Buffer)[i / 4]);
+ }
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
- for (i= 0; i <= pFwImg->Data.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
+ address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Data.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
+ 4]);
+ }
}
- }
- if (StartCpu & T3_RX_CPU_ID)
- {
- /* Start Rx CPU */
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
- for (i = 0 ; i < 5; i++)
- {
- if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
- break;
+ if (StartCpu & T3_RX_CPU_ID) {
+ /* Start Rx CPU */
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
+ for (i = 0; i < 5; i++) {
+ if (pFwImg->StartAddress ==
+ REG_RD (pDevice, rxCpu.reg.PC))
+ break;
+
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
+ REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
+ MM_Wait (1000);
+ }
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
- REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
- MM_Wait(1000);
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, 0);
}
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode, 0);
- }
+ if (StartCpu & T3_TX_CPU_ID) {
+ /* Start Tx CPU */
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
+ for (i = 0; i < 5; i++) {
+ if (pFwImg->StartAddress ==
+ REG_RD (pDevice, txCpu.reg.PC))
+ break;
- if (StartCpu & T3_TX_CPU_ID)
- {
- /* Start Tx CPU */
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
- for (i = 0 ; i < 5; i++)
- {
- if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
- break;
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
+ REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
+ MM_Wait (1000);
+ }
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
- REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
- MM_Wait(1000);
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.mode, 0);
}
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.mode, 0);
- }
-
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
+STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number)
{
- LM_UINT32 i;
+ LM_UINT32 i;
- if (cpu_number == T3_RX_CPU_ID)
- {
- for (i = 0 ; i < 10000; i++)
- {
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
+ if (cpu_number == T3_RX_CPU_ID) {
+ for (i = 0; i < 10000; i++) {
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
- if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
- break;
- }
+ if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT)
+ break;
+ }
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
- MM_Wait(10);
- }
- else
- {
- for (i = 0 ; i < 10000; i++)
- {
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
+ MM_Wait (10);
+ } else {
+ for (i = 0; i < 10000; i++) {
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
- if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
- break;
+ if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT)
+ break;
+ }
}
- }
- return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
+ return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
}
-
-int
-LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
+int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
{
LM_UINT32 Oldcfg;
int j;
int ret = 0;
- if(BlinkDurationSec == 0)
- {
+ if (BlinkDurationSec == 0) {
return 0;
}
- if(BlinkDurationSec > 120)
- {
+ if (BlinkDurationSec > 120) {
BlinkDurationSec = 120;
}
- Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl);
- for(j = 0; j < BlinkDurationSec * 2; j++)
- {
- if(j % 2)
- {
+ Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl);
+ for (j = 0; j < BlinkDurationSec * 2; j++) {
+ if (j % 2) {
/* Turn on the LEDs. */
- REG_WR(pDevice, MacCtrl.LedCtrl,
+ REG_WR (pDevice, MacCtrl.LedCtrl,
LED_CTRL_OVERRIDE_LINK_LED |
LED_CTRL_1000MBPS_LED_ON |
LED_CTRL_100MBPS_LED_ON |
LED_CTRL_OVERRIDE_TRAFFIC_LED |
LED_CTRL_BLINK_TRAFFIC_LED |
LED_CTRL_TRAFFIC_LED);
- }
- else
- {
+ } else {
/* Turn off the LEDs. */
- REG_WR(pDevice, MacCtrl.LedCtrl,
+ REG_WR (pDevice, MacCtrl.LedCtrl,
LED_CTRL_OVERRIDE_LINK_LED |
LED_CTRL_OVERRIDE_TRAFFIC_LED);
}
#ifndef EMBEDDED
current->state = TASK_INTERRUPTIBLE;
- if (schedule_timeout(HZ/2) != 0) {
+ if (schedule_timeout (HZ / 2) != 0) {
ret = -EINTR;
break;
}
#else
- udelay(100000); /* 1s sleep */
+ udelay (100000); /* 1s sleep */
#endif
}
- REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg);
+ REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg);
return ret;
}
-int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
- LM_PHYSICAL_ADDRESS host_addr_phy, int length,
- int dma_read)
+int t3_do_dma (PLM_DEVICE_BLOCK pDevice,
+ LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read)
{
- T3_DMA_DESC dma_desc;
- int i;
- LM_UINT32 dma_desc_addr;
- LM_UINT32 value32;
-
- REG_WR(pDevice, BufMgr.Mode, 0);
- REG_WR(pDevice, Ftq.Reset, 0);
-
- dma_desc.host_addr.High = host_addr_phy.High;
- dma_desc.host_addr.Low = host_addr_phy.Low;
- dma_desc.nic_mbuf = 0x2100;
- dma_desc.len = length;
- dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */
-
- if (dma_read)
- {
- dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
- T3_QID_DMA_HIGH_PRI_READ;
- REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
- }
- else
- {
- dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
- T3_QID_DMA_HIGH_PRI_WRITE;
- REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
- }
-
- dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
-
- /* Writing this DMA descriptor to DMA memory */
- for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
- {
- value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32));
- }
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
-
- if (dma_read)
- REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
- else
- REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
-
- for (i = 0; i < 40; i++)
- {
+ T3_DMA_DESC dma_desc;
+ int i;
+ LM_UINT32 dma_desc_addr;
+ LM_UINT32 value32;
+
+ REG_WR (pDevice, BufMgr.Mode, 0);
+ REG_WR (pDevice, Ftq.Reset, 0);
+
+ dma_desc.host_addr.High = host_addr_phy.High;
+ dma_desc.host_addr.Low = host_addr_phy.Low;
+ dma_desc.nic_mbuf = 0x2100;
+ dma_desc.len = length;
+ dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */
+
+ if (dma_read) {
+ dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
+ T3_QID_DMA_HIGH_PRI_READ;
+ REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
+ } else {
+ dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
+ T3_QID_DMA_HIGH_PRI_WRITE;
+ REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
+ }
+
+ dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
+
+ /* Writing this DMA descriptor to DMA memory */
+ for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) {
+ value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i));
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG,
+ dma_desc_addr + i);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG,
+ cpu_to_le32 (value32));
+ }
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
+
if (dma_read)
- value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
+ REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue,
+ dma_desc_addr);
else
- value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
+ REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue,
+ dma_desc_addr);
+
+ for (i = 0; i < 40; i++) {
+ if (dma_read)
+ value32 =
+ REG_RD (pDevice,
+ Ftq.RcvBdCompFtqFifoEnqueueDequeue);
+ else
+ value32 =
+ REG_RD (pDevice,
+ Ftq.RcvDataCompFtqFifoEnqueueDequeue);
- if ((value32 & 0xffff) == dma_desc_addr)
- break;
+ if ((value32 & 0xffff) == dma_desc_addr)
+ break;
- MM_Wait(10);
- }
+ MM_Wait (10);
+ }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
STATIC LM_STATUS
-LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
- LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
+LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
+ LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
{
- int j;
- LM_UINT32 *ptr;
- int dma_success = 0;
+ int j;
+ LM_UINT32 *ptr;
+ int dma_success = 0;
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+ return LM_STATUS_SUCCESS;
+ }
+ while (!dma_success) {
+ /* Fill data with incremental patterns */
+ ptr = (LM_UINT32 *) pBufferVirt;
+ for (j = 0; j < BufferSize / 4; j++)
+ *ptr++ = j;
+
+ if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) ==
+ LM_STATUS_FAILURE) {
+ return LM_STATUS_FAILURE;
+ }
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
- {
- return LM_STATUS_SUCCESS;
- }
- while (!dma_success)
- {
- /* Fill data with incremental patterns */
- ptr = (LM_UINT32 *)pBufferVirt;
- for (j = 0; j < BufferSize/4; j++)
- *ptr++ = j;
-
- if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
- {
- return LM_STATUS_FAILURE;
- }
+ MM_Wait (40);
+ ptr = (LM_UINT32 *) pBufferVirt;
+ /* Fill data with zero */
+ for (j = 0; j < BufferSize / 4; j++)
+ *ptr++ = 0;
- MM_Wait(40);
- ptr = (LM_UINT32 *)pBufferVirt;
- /* Fill data with zero */
- for (j = 0; j < BufferSize/4; j++)
- *ptr++ = 0;
+ if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) ==
+ LM_STATUS_FAILURE) {
+ return LM_STATUS_FAILURE;
+ }
- if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
- {
- return LM_STATUS_FAILURE;
+ MM_Wait (40);
+ /* Check for data */
+ ptr = (LM_UINT32 *) pBufferVirt;
+ for (j = 0; j < BufferSize / 4; j++) {
+ if (*ptr++ != j) {
+ if ((pDevice->
+ DmaReadWriteCtrl &
+ DMA_CTRL_WRITE_BOUNDARY_MASK)
+ == DMA_CTRL_WRITE_BOUNDARY_DISABLE) {
+ pDevice->DmaReadWriteCtrl =
+ (pDevice->
+ DmaReadWriteCtrl &
+ ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
+ DMA_CTRL_WRITE_BOUNDARY_16;
+ REG_WR (pDevice,
+ PciCfg.DmaReadWriteCtrl,
+ pDevice->DmaReadWriteCtrl);
+ break;
+ } else {
+ return LM_STATUS_FAILURE;
+ }
+ }
+ }
+ if (j == (BufferSize / 4))
+ dma_success = 1;
}
-
- MM_Wait(40);
- /* Check for data */
- ptr = (LM_UINT32 *)pBufferVirt;
- for (j = 0; j < BufferSize/4; j++)
- {
- if (*ptr++ != j)
- {
- if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
- == DMA_CTRL_WRITE_BOUNDARY_DISABLE)
- {
- pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
- ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
- DMA_CTRL_WRITE_BOUNDARY_16;
- REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
- pDevice->DmaReadWriteCtrl);
- break;
- }
- else
- {
- return LM_STATUS_FAILURE;
- }
- }
- }
- if (j == (BufferSize/4))
- dma_success = 1;
- }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
+
#endif
#include "bcm570x_autoneg.h"
#endif
-
/* io defines */
#if !defined(BIG_ENDIAN_HOST)
#define readl(addr) \
#define writel(b,addr) \
((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
#else
-#if 0 /* !defined(PPC603) */
+#if 0 /* !defined(PPC603) */
#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
#else
#define readl(addr) (*(volatile unsigned int*)(addr))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
#else
-extern int sprintf(char* buf, const char* f, ...);
-static __inline unsigned int readl(void* addr){
- char buf[128];
- unsigned int tmp = (*(volatile unsigned int*)(addr));
- sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0);
- sysSerialPrintString(buf);
- return tmp;
+extern int sprintf (char *buf, const char *f, ...);
+static __inline unsigned int readl (void *addr)
+{
+ char buf[128];
+ unsigned int tmp = (*(volatile unsigned int *)(addr));
+ sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp,
+ addr, 0, 0);
+ sysSerialPrintString (buf);
+ return tmp;
}
-static __inline void writel(unsigned int b, unsigned int addr){
- char buf[128];
- ((*(volatile unsigned int *) (addr)) = (b));
- sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0);
- sysSerialPrintString(buf);
+static __inline void writel (unsigned int b, unsigned int addr)
+{
+ char buf[128];
+ ((*(volatile unsigned int *)(addr)) = (b));
+ sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b,
+ addr, 0, 0);
+ sysSerialPrintString (buf);
}
#endif
-#endif /* PPC603 */
+#endif /* PPC603 */
#endif
-
/******************************************************************************/
/* Constants. */
/******************************************************************************/
/* B0 bug. */
#define BCM5700_BX_MIN_FRAG_SIZE 10
-#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
+#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
MAX_FRAGMENT_COUNT)
/* Number of entries in the Standard Receive RCB. Must be 512 entries. */
#define T3_STD_RCV_RCB_ENTRY_COUNT 512
#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1)
-#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
+#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
#define MAX_STD_RCV_BUFFER_SIZE 0x600
/* Number of entries in the Mini Receive RCB. This value can either be */
/* 0, 1024. Currently Mini Receive RCB is disabled. */
#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
#define T3_MINI_RCV_RCB_ENTRY_COUNT 0
-#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
+#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
#define MAX_MINI_RCV_BUFFER_SIZE 512
#define DEFAULT_MINI_RCV_BUFFER_SIZE 64
-#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
+#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */
/* Currently, Jumbo Receive RCB is disabled. */
#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
-#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
+#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
-#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
+#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */
#define T3_MAX_RCV_RETURN_RCB_COUNT 16
/* or 2048. */
#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024
-#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
+#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
-
/* Default coalescing parameters. */
#define DEFAULT_RX_COALESCING_TICKS 100
#define MAX_RX_COALESCING_TICKS 500
#define DEFAULT_STATS_COALESCING_TICKS 1000000
#define MAX_STATS_COALESCING_TICKS 3600000000U
-
/* Receive BD Replenish thresholds. */
#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4
#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4
/* Maximum physical fragment size. */
#define MAX_FRAGMENT_SIZE (64 * 1024)
-
/* Standard view. */
#define T3_STD_VIEW_SIZE (64 * 1024)
#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024)
-
/* Buffer descriptor base address on the NIC's memory. */
#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000
#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
sizeof(T3_EXT_RCV_BD) / 4)
-
/* MBUF pool. */
#define T3_NIC_MBUF_POOL_ADDR 0x8000
/* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */
#define T3_NIC_MBUF_POOL_SIZE96 0x18000
#define T3_NIC_MBUF_POOL_SIZE64 0x10000
-
#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000
/* DMA descriptor pool */
#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000
-#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
+#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
#define T3_DEF_DMA_MBUF_LOW_WMARK 0x40
#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20
#define T3_TX_CPU_SPAD_ADDR 0x34000
#define T3_TX_CPU_SPAD_SIZE 0x4000
-typedef struct T3_DIR_ENTRY
-{
- PLM_UINT8 Buffer;
- LM_UINT32 Offset;
- LM_UINT32 Length;
-} T3_DIR_ENTRY,*PT3_DIR_ENTRY;
-
-typedef struct T3_FWIMG_INFO
-{
- LM_UINT32 StartAddress;
- T3_DIR_ENTRY Text;
- T3_DIR_ENTRY ROnlyData;
- T3_DIR_ENTRY Data;
- T3_DIR_ENTRY Sbss;
- T3_DIR_ENTRY Bss;
+typedef struct T3_DIR_ENTRY {
+ PLM_UINT8 Buffer;
+ LM_UINT32 Offset;
+ LM_UINT32 Length;
+} T3_DIR_ENTRY, *PT3_DIR_ENTRY;
+
+typedef struct T3_FWIMG_INFO {
+ LM_UINT32 StartAddress;
+ T3_DIR_ENTRY Text;
+ T3_DIR_ENTRY ROnlyData;
+ T3_DIR_ENTRY Data;
+ T3_DIR_ENTRY Sbss;
+ T3_DIR_ENTRY Bss;
} T3_FWIMG_INFO, *PT3_FWIMG_INFO;
-
/******************************************************************************/
/* Tigon3 PCI Registers. */
/******************************************************************************/
#define T3_ASIC_REV_5703 0x01
#define T3_ASIC_REV_5704 0x02
-
/* Chip id and revision. */
#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8)
#define T3_CHIP_REV_5700_AX 0x70
#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15
#define T3_PCI_44MHZ_CORE_CLOCK BIT_18
-
#define T3_PCI_REG_ADDR_REG 0x78
#define T3_PCI_REG_DATA_REG 0x80
#define T3_PM_PME_ENABLE BIT_8
#define T3_PM_PME_ASSERTED BIT_15
-
/* PCI state register. */
#define T3_PCI_STATE_REG 0x70
#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3
#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
-
/* Broadcom subsystem/subvendor IDs. */
#define T3_SVID_BROADCOM 0x14e4
#define T3_SSID_BROADCOM_BCM95700A6 0x1644
#define T3_SSID_BROADCOM_BCM95701A5 0x0001
-#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
-#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
+#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
+#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
#define T3_SSID_BROADCOM_BCM95701T1 0x0005
#define T3_SSID_BROADCOM_BCM95701T8 0x0006
-#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
+#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
#define T3_SSID_BROADCOM_BCM95701A10 0x0008
#define T3_SSID_BROADCOM_BCM95701A12 0x8008
#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009
#define T3_SSID_3COM_3C996SX 0x1004
#define T3_SSID_3COM_3C997SX 0x1005
-
/* Dell subsystem/subvendor IDs. */
#define T3_SVID_DELL 0x1028
#define T3_SSID_COMPAQ_NC7780 0x0085
#define T3_SSID_COMPAQ_NC7780_2 0x0099
-
/******************************************************************************/
/* MII registers. */
/******************************************************************************/
#define PHY_CTRL_LOOPBACK_MODE BIT_14
#define PHY_CTRL_PHY_RESET BIT_15
-
/* Status register. */
#define PHY_STATUS_REG 0x01
#define PHY_STATUS_LINK_PASS BIT_2
#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
-
/* Phy Id registers. */
#define PHY_ID1_REG 0x02
#define PHY_ID1_OUI_MASK 0xffff
#define PHY_ID2_MODEL_MASK 0x03f0
#define PHY_ID2_OUI_MASK 0xfc00
-
/* Auto-negotiation advertisement register. */
#define PHY_AN_AD_REG 0x04
#define PHY_AN_AD_100BASETX_FULL BIT_8
#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01
-
/* Auto-negotiation Link Partner Ability register. */
#define PHY_LINK_PARTNER_ABILITY_REG 0x05
#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
-
/* Auto-negotiation expansion register. */
#define PHY_AN_EXPANSION_REG 0x06
-
/******************************************************************************/
/* BCM5400 and BCM5401 phy info. */
/******************************************************************************/
#define PHY_ID_MASK (PHY_ID_OUI_MASK | \
PHY_ID_MODEL_MASK)
-
#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
-
/* 1000Base-T control register. */
#define BCM540X_1000BASET_CTRL_REG 0x09
#define BCM540X_CONFIG_AS_MASTER BIT_11
#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12
-
/* Extended control register. */
#define BCM540X_EXT_CTRL_REG 0x10
#define BCM540X_EXT_STATUS_LINK_PASS BIT_8
-
/* DSP Coefficient Read/Write Port. */
#define BCM540X_DSP_RW_PORT 0x15
-
/* DSP Coeficient Address Register. */
#define BCM540X_DSP_ADDRESS_REG 0x17
#define BCM540X_CONTROL_ALL_CHANNELS BIT_15
-
/* Auxilliary Control Register (Shadow Register) */
#define BCM5401_AUX_CTRL 0x18
#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05
#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06
-
/* Shadow register selector == '000' */
#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3
#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4
#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14
#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15
-
/* Auxilliary status summary. */
#define BCM540X_AUX_STATUS_REG 0x19
#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10)
#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10)
-
/* Interrupt status. */
#define BCM540X_INT_STATUS_REG 0x1a
#define BCM540X_INT_DUPLEX_CHANGE BIT_3
#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10
-
/* Interrupt mask register. */
#define BCM540X_INT_MASK_REG 0x1b
-
/******************************************************************************/
/* Register definitions. */
/******************************************************************************/
typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
typedef struct {
- /* Big endian format. */
- T3_32BIT_REGISTER High;
- T3_32BIT_REGISTER Low;
+ /* Big endian format. */
+ T3_32BIT_REGISTER High;
+ T3_32BIT_REGISTER Low;
} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
#define T3_NUM_OF_DMA_DESC 256
#define T3_NUM_OF_MBUF 768
-typedef struct
-{
- T3_64BIT_REGISTER host_addr;
- T3_32BIT_REGISTER nic_mbuf;
- T3_16BIT_REGISTER len;
- T3_16BIT_REGISTER cqid_sqid;
- T3_32BIT_REGISTER flags;
- T3_32BIT_REGISTER opaque1;
- T3_32BIT_REGISTER opaque2;
- T3_32BIT_REGISTER opaque3;
-}T3_DMA_DESC, *PT3_DMA_DESC;
-
+typedef struct {
+ T3_64BIT_REGISTER host_addr;
+ T3_32BIT_REGISTER nic_mbuf;
+ T3_16BIT_REGISTER len;
+ T3_16BIT_REGISTER cqid_sqid;
+ T3_32BIT_REGISTER flags;
+ T3_32BIT_REGISTER opaque1;
+ T3_32BIT_REGISTER opaque2;
+ T3_32BIT_REGISTER opaque3;
+} T3_DMA_DESC, *PT3_DMA_DESC;
/******************************************************************************/
/* Ring control block. */
/******************************************************************************/
typedef struct {
- T3_64BIT_REGISTER HostRingAddr;
+ T3_64BIT_REGISTER HostRingAddr;
- union {
- struct {
+ union {
+ struct {
#ifdef BIG_ENDIAN_HOST
- T3_16BIT_REGISTER MaxLen;
- T3_16BIT_REGISTER Flags;
-#else /* BIG_ENDIAN_HOST */
- T3_16BIT_REGISTER Flags;
- T3_16BIT_REGISTER MaxLen;
+ T3_16BIT_REGISTER MaxLen;
+ T3_16BIT_REGISTER Flags;
+#else /* BIG_ENDIAN_HOST */
+ T3_16BIT_REGISTER Flags;
+ T3_16BIT_REGISTER MaxLen;
#endif
- } s;
+ } s;
- T3_32BIT_REGISTER MaxLen_Flags;
- } u;
+ T3_32BIT_REGISTER MaxLen_Flags;
+ } u;
- T3_32BIT_REGISTER NicRingAddr;
+ T3_32BIT_REGISTER NicRingAddr;
} T3_RCB, *PT3_RCB;
#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0
#define T3_RCB_FLAG_RING_DISABLED BIT_1
-
/******************************************************************************/
/* Status block. */
/******************************************************************************/
#define T3_STATUS_BLOCK_SIZE 0x80
typedef struct {
- volatile LM_UINT32 Status;
- #define STATUS_BLOCK_UPDATED BIT_0
- #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
- #define STATUS_BLOCK_ERROR BIT_2
+ volatile LM_UINT32 Status;
+#define STATUS_BLOCK_UPDATED BIT_0
+#define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
+#define STATUS_BLOCK_ERROR BIT_2
- volatile LM_UINT32 StatusTag;
+ volatile LM_UINT32 StatusTag;
#ifdef BIG_ENDIAN_HOST
- volatile LM_UINT16 RcvStdConIdx;
- volatile LM_UINT16 RcvJumboConIdx;
-
- volatile LM_UINT16 Reserved2;
- volatile LM_UINT16 RcvMiniConIdx;
-
- struct {
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- } Idx[16];
-#else /* BIG_ENDIAN_HOST */
- volatile LM_UINT16 RcvJumboConIdx;
- volatile LM_UINT16 RcvStdConIdx;
-
- volatile LM_UINT16 RcvMiniConIdx;
- volatile LM_UINT16 Reserved2;
-
- struct {
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- } Idx[16];
+ volatile LM_UINT16 RcvStdConIdx;
+ volatile LM_UINT16 RcvJumboConIdx;
+
+ volatile LM_UINT16 Reserved2;
+ volatile LM_UINT16 RcvMiniConIdx;
+
+ struct {
+ volatile LM_UINT16 SendConIdx; /* Send consumer index. */
+ volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
+ } Idx[16];
+#else /* BIG_ENDIAN_HOST */
+ volatile LM_UINT16 RcvJumboConIdx;
+ volatile LM_UINT16 RcvStdConIdx;
+
+ volatile LM_UINT16 RcvMiniConIdx;
+ volatile LM_UINT16 Reserved2;
+
+ struct {
+ volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
+ volatile LM_UINT16 SendConIdx; /* Send consumer index. */
+ } Idx[16];
#endif
} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
-
/******************************************************************************/
/* Receive buffer descriptors. */
/******************************************************************************/
typedef struct {
- T3_64BIT_HOST_ADDR HostAddr;
+ T3_64BIT_HOST_ADDR HostAddr;
#ifdef BIG_ENDIAN_HOST
- volatile LM_UINT16 Index;
- volatile LM_UINT16 Len;
+ volatile LM_UINT16 Index;
+ volatile LM_UINT16 Len;
- volatile LM_UINT16 Type;
- volatile LM_UINT16 Flags;
+ volatile LM_UINT16 Type;
+ volatile LM_UINT16 Flags;
- volatile LM_UINT16 IpCksum;
- volatile LM_UINT16 TcpUdpCksum;
+ volatile LM_UINT16 IpCksum;
+ volatile LM_UINT16 TcpUdpCksum;
- volatile LM_UINT16 ErrorFlag;
- volatile LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
- volatile LM_UINT16 Len;
- volatile LM_UINT16 Index;
+ volatile LM_UINT16 ErrorFlag;
+ volatile LM_UINT16 VlanTag;
+#else /* BIG_ENDIAN_HOST */
+ volatile LM_UINT16 Len;
+ volatile LM_UINT16 Index;
- volatile LM_UINT16 Flags;
- volatile LM_UINT16 Type;
+ volatile LM_UINT16 Flags;
+ volatile LM_UINT16 Type;
- volatile LM_UINT16 TcpUdpCksum;
- volatile LM_UINT16 IpCksum;
+ volatile LM_UINT16 TcpUdpCksum;
+ volatile LM_UINT16 IpCksum;
- volatile LM_UINT16 VlanTag;
- volatile LM_UINT16 ErrorFlag;
+ volatile LM_UINT16 VlanTag;
+ volatile LM_UINT16 ErrorFlag;
#endif
- volatile LM_UINT32 Reserved;
- volatile LM_UINT32 Opaque;
+ volatile LM_UINT32 Reserved;
+ volatile LM_UINT32 Opaque;
} T3_RCV_BD, *PT3_RCV_BD;
-
typedef struct {
- T3_64BIT_HOST_ADDR HostAddr[3];
+ T3_64BIT_HOST_ADDR HostAddr[3];
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len1;
- LM_UINT16 Len2;
+ LM_UINT16 Len1;
+ LM_UINT16 Len2;
- LM_UINT16 Len3;
- LM_UINT16 Reserved1;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Len2;
- LM_UINT16 Len1;
+ LM_UINT16 Len3;
+ LM_UINT16 Reserved1;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT16 Len2;
+ LM_UINT16 Len1;
- LM_UINT16 Reserved1;
- LM_UINT16 Len3;
+ LM_UINT16 Reserved1;
+ LM_UINT16 Len3;
#endif
- T3_RCV_BD StdRcvBd;
+ T3_RCV_BD StdRcvBd;
} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
-
/* Error flags. */
#define RCV_BD_ERR_BAD_CRC 0x0001
#define RCV_BD_ERR_COLL_DETECT 0x0002
#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080
#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100
-
/* Buffer descriptor flags. */
#define RCV_BD_FLAG_END 0x0004
#define RCV_BD_FLAG_JUMBO_RING 0x0020
#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000
#define RCV_BD_FLAG_TCP_PACKET 0x4000
-
/******************************************************************************/
/* Send buffer descriptor. */
/******************************************************************************/
typedef struct {
- T3_64BIT_HOST_ADDR HostAddr;
+ T3_64BIT_HOST_ADDR HostAddr;
- union {
- struct {
+ union {
+ struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len;
- LM_UINT16 Flags;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Flags;
- LM_UINT16 Len;
+ LM_UINT16 Len;
+ LM_UINT16 Flags;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT16 Flags;
+ LM_UINT16 Len;
#endif
- } s1;
+ } s1;
- LM_UINT32 Len_Flags;
- } u1;
+ LM_UINT32 Len_Flags;
+ } u1;
- union {
- struct {
+ union {
+ struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Reserved;
- LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 VlanTag;
- LM_UINT16 Reserved;
+ LM_UINT16 Reserved;
+ LM_UINT16 VlanTag;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT16 VlanTag;
+ LM_UINT16 Reserved;
#endif
- } s2;
+ } s2;
- LM_UINT32 VlanTag;
- } u2;
+ LM_UINT32 VlanTag;
+ } u2;
} T3_SND_BD, *PT3_SND_BD;
-
/* Send buffer descriptor flags. */
#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001
#define SND_BD_FLAG_IP_CKSUM 0x0002
/* MBUFs */
typedef struct T3_MBUF_FRAME_DESC {
#ifdef BIG_ENDIAN_HOST
- LM_UINT32 status_control;
- union {
- struct {
- LM_UINT8 cqid;
- LM_UINT8 reserved1;
- LM_UINT16 length;
- }s1;
- LM_UINT32 word;
- }u1;
- union {
- struct
- {
- LM_UINT16 ip_hdr_start;
- LM_UINT16 tcp_udp_hdr_start;
- }s2;
-
- LM_UINT32 word;
- }u2;
-
- union {
- struct {
- LM_UINT16 data_start;
- LM_UINT16 vlan_id;
- }s3;
-
- LM_UINT32 word;
- }u3;
-
- union {
- struct {
- LM_UINT16 ip_checksum;
- LM_UINT16 tcp_udp_checksum;
- }s4;
-
- LM_UINT32 word;
- }u4;
-
- union {
- struct {
- LM_UINT16 pseudo_checksum;
- LM_UINT16 checksum_status;
- }s5;
-
- LM_UINT32 word;
- }u5;
-
- union {
- struct {
- LM_UINT16 rule_match;
- LM_UINT8 class;
- LM_UINT8 rupt;
- }s6;
-
- LM_UINT32 word;
- }u6;
-
- union {
- struct {
- LM_UINT16 reserved2;
- LM_UINT16 mbuf_num;
- }s7;
-
- LM_UINT32 word;
- }u7;
-
- LM_UINT32 reserved3;
- LM_UINT32 reserved4;
+ LM_UINT32 status_control;
+ union {
+ struct {
+ LM_UINT8 cqid;
+ LM_UINT8 reserved1;
+ LM_UINT16 length;
+ } s1;
+ LM_UINT32 word;
+ } u1;
+ union {
+ struct {
+ LM_UINT16 ip_hdr_start;
+ LM_UINT16 tcp_udp_hdr_start;
+ } s2;
+
+ LM_UINT32 word;
+ } u2;
+
+ union {
+ struct {
+ LM_UINT16 data_start;
+ LM_UINT16 vlan_id;
+ } s3;
+
+ LM_UINT32 word;
+ } u3;
+
+ union {
+ struct {
+ LM_UINT16 ip_checksum;
+ LM_UINT16 tcp_udp_checksum;
+ } s4;
+
+ LM_UINT32 word;
+ } u4;
+
+ union {
+ struct {
+ LM_UINT16 pseudo_checksum;
+ LM_UINT16 checksum_status;
+ } s5;
+
+ LM_UINT32 word;
+ } u5;
+
+ union {
+ struct {
+ LM_UINT16 rule_match;
+ LM_UINT8 class;
+ LM_UINT8 rupt;
+ } s6;
+
+ LM_UINT32 word;
+ } u6;
+
+ union {
+ struct {
+ LM_UINT16 reserved2;
+ LM_UINT16 mbuf_num;
+ } s7;
+
+ LM_UINT32 word;
+ } u7;
+
+ LM_UINT32 reserved3;
+ LM_UINT32 reserved4;
#else
- LM_UINT32 status_control;
- union {
- struct {
- LM_UINT16 length;
- LM_UINT8 reserved1;
- LM_UINT8 cqid;
- }s1;
- LM_UINT32 word;
- }u1;
- union {
- struct
- {
- LM_UINT16 tcp_udp_hdr_start;
- LM_UINT16 ip_hdr_start;
- }s2;
-
- LM_UINT32 word;
- }u2;
-
- union {
- struct {
- LM_UINT16 vlan_id;
- LM_UINT16 data_start;
- }s3;
-
- LM_UINT32 word;
- }u3;
-
- union {
- struct {
- LM_UINT16 tcp_udp_checksum;
- LM_UINT16 ip_checksum;
- }s4;
-
- LM_UINT32 word;
- }u4;
-
- union {
- struct {
- LM_UINT16 checksum_status;
- LM_UINT16 pseudo_checksum;
- }s5;
-
- LM_UINT32 word;
- }u5;
-
- union {
- struct {
- LM_UINT8 rupt;
- LM_UINT8 class;
- LM_UINT16 rule_match;
- }s6;
-
- LM_UINT32 word;
- }u6;
-
- union {
- struct {
- LM_UINT16 mbuf_num;
- LM_UINT16 reserved2;
- }s7;
-
- LM_UINT32 word;
- }u7;
-
- LM_UINT32 reserved3;
- LM_UINT32 reserved4;
+ LM_UINT32 status_control;
+ union {
+ struct {
+ LM_UINT16 length;
+ LM_UINT8 reserved1;
+ LM_UINT8 cqid;
+ } s1;
+ LM_UINT32 word;
+ } u1;
+ union {
+ struct {
+ LM_UINT16 tcp_udp_hdr_start;
+ LM_UINT16 ip_hdr_start;
+ } s2;
+
+ LM_UINT32 word;
+ } u2;
+
+ union {
+ struct {
+ LM_UINT16 vlan_id;
+ LM_UINT16 data_start;
+ } s3;
+
+ LM_UINT32 word;
+ } u3;
+
+ union {
+ struct {
+ LM_UINT16 tcp_udp_checksum;
+ LM_UINT16 ip_checksum;
+ } s4;
+
+ LM_UINT32 word;
+ } u4;
+
+ union {
+ struct {
+ LM_UINT16 checksum_status;
+ LM_UINT16 pseudo_checksum;
+ } s5;
+
+ LM_UINT32 word;
+ } u5;
+
+ union {
+ struct {
+ LM_UINT8 rupt;
+ LM_UINT8 class;
+ LM_UINT16 rule_match;
+ } s6;
+
+ LM_UINT32 word;
+ } u6;
+
+ union {
+ struct {
+ LM_UINT16 mbuf_num;
+ LM_UINT16 reserved2;
+ } s7;
+
+ LM_UINT32 word;
+ } u7;
+
+ LM_UINT32 reserved3;
+ LM_UINT32 reserved4;
#endif
-}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC;
+} T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC;
typedef struct T3_MBUF_HDR {
- union {
- struct {
- unsigned int C:1;
- unsigned int F:1;
- unsigned int reserved1:7;
- unsigned int next_mbuf:16;
- unsigned int length:7;
- }s1;
-
- LM_UINT32 word;
- }u1;
-
- LM_UINT32 next_frame_ptr;
-}T3_MBUF_HDR, *PT3_MBUF_HDR;
-
-typedef struct T3_MBUF
-{
- T3_MBUF_HDR hdr;
- union
- {
- struct {
- T3_MBUF_FRAME_DESC frame_hdr;
- LM_UINT32 data[20];
- }s1;
-
- struct {
- LM_UINT32 data[30];
- }s2;
- }body;
-}T3_MBUF, *PT3_MBUF;
+ union {
+ struct {
+ unsigned int C:1;
+ unsigned int F:1;
+ unsigned int reserved1:7;
+ unsigned int next_mbuf:16;
+ unsigned int length:7;
+ } s1;
+
+ LM_UINT32 word;
+ } u1;
+
+ LM_UINT32 next_frame_ptr;
+} T3_MBUF_HDR, *PT3_MBUF_HDR;
+
+typedef struct T3_MBUF {
+ T3_MBUF_HDR hdr;
+ union {
+ struct {
+ T3_MBUF_FRAME_DESC frame_hdr;
+ LM_UINT32 data[20];
+ } s1;
+
+ struct {
+ LM_UINT32 data[30];
+ } s2;
+ } body;
+} T3_MBUF, *PT3_MBUF;
#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7)
#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
-
/******************************************************************************/
/* Statistics block. */
/******************************************************************************/
typedef struct {
- LM_UINT8 Reserved0[0x400-0x300];
-
- /* Statistics maintained by Receive MAC. */
- T3_64BIT_REGISTER ifHCInOctets;
- T3_64BIT_REGISTER Reserved1;
- T3_64BIT_REGISTER etherStatsFragments;
- T3_64BIT_REGISTER ifHCInUcastPkts;
- T3_64BIT_REGISTER ifHCInMulticastPkts;
- T3_64BIT_REGISTER ifHCInBroadcastPkts;
- T3_64BIT_REGISTER dot3StatsFCSErrors;
- T3_64BIT_REGISTER dot3StatsAlignmentErrors;
- T3_64BIT_REGISTER xonPauseFramesReceived;
- T3_64BIT_REGISTER xoffPauseFramesReceived;
- T3_64BIT_REGISTER macControlFramesReceived;
- T3_64BIT_REGISTER xoffStateEntered;
- T3_64BIT_REGISTER dot3StatsFramesTooLong;
- T3_64BIT_REGISTER etherStatsJabbers;
- T3_64BIT_REGISTER etherStatsUndersizePkts;
- T3_64BIT_REGISTER inRangeLengthError;
- T3_64BIT_REGISTER outRangeLengthError;
- T3_64BIT_REGISTER etherStatsPkts64Octets;
- T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
- T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
- T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
- T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
- T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
- T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
- T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
- T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
- T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
-
- T3_64BIT_REGISTER Unused1[37];
-
- /* Statistics maintained by Transmit MAC. */
- T3_64BIT_REGISTER ifHCOutOctets;
- T3_64BIT_REGISTER Reserved2;
- T3_64BIT_REGISTER etherStatsCollisions;
- T3_64BIT_REGISTER outXonSent;
- T3_64BIT_REGISTER outXoffSent;
- T3_64BIT_REGISTER flowControlDone;
- T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
- T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
- T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
- T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
- T3_64BIT_REGISTER Reserved3;
- T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
- T3_64BIT_REGISTER dot3StatsLateCollisions;
- T3_64BIT_REGISTER dot3Collided2Times;
- T3_64BIT_REGISTER dot3Collided3Times;
- T3_64BIT_REGISTER dot3Collided4Times;
- T3_64BIT_REGISTER dot3Collided5Times;
- T3_64BIT_REGISTER dot3Collided6Times;
- T3_64BIT_REGISTER dot3Collided7Times;
- T3_64BIT_REGISTER dot3Collided8Times;
- T3_64BIT_REGISTER dot3Collided9Times;
- T3_64BIT_REGISTER dot3Collided10Times;
- T3_64BIT_REGISTER dot3Collided11Times;
- T3_64BIT_REGISTER dot3Collided12Times;
- T3_64BIT_REGISTER dot3Collided13Times;
- T3_64BIT_REGISTER dot3Collided14Times;
- T3_64BIT_REGISTER dot3Collided15Times;
- T3_64BIT_REGISTER ifHCOutUcastPkts;
- T3_64BIT_REGISTER ifHCOutMulticastPkts;
- T3_64BIT_REGISTER ifHCOutBroadcastPkts;
- T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
- T3_64BIT_REGISTER ifOutDiscards;
- T3_64BIT_REGISTER ifOutErrors;
-
- T3_64BIT_REGISTER Unused2[31];
-
- /* Statistics maintained by Receive List Placement. */
- T3_64BIT_REGISTER COSIfHCInPkts[16];
- T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
- T3_64BIT_REGISTER nicDmaWriteQueueFull;
- T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
- T3_64BIT_REGISTER nicNoMoreRxBDs;
- T3_64BIT_REGISTER ifInDiscards;
- T3_64BIT_REGISTER ifInErrors;
- T3_64BIT_REGISTER nicRecvThresholdHit;
-
- T3_64BIT_REGISTER Unused3[9];
-
- /* Statistics maintained by Send Data Initiator. */
- T3_64BIT_REGISTER COSIfHCOutPkts[16];
- T3_64BIT_REGISTER nicDmaReadQueueFull;
- T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
- T3_64BIT_REGISTER nicSendDataCompQueueFull;
-
- /* Statistics maintained by Host Coalescing. */
- T3_64BIT_REGISTER nicRingSetSendProdIndex;
- T3_64BIT_REGISTER nicRingStatusUpdate;
- T3_64BIT_REGISTER nicInterrupts;
- T3_64BIT_REGISTER nicAvoidedInterrupts;
- T3_64BIT_REGISTER nicSendThresholdHit;
-
- LM_UINT8 Reserved4[0xb00-0x9c0];
+ LM_UINT8 Reserved0[0x400 - 0x300];
+
+ /* Statistics maintained by Receive MAC. */
+ T3_64BIT_REGISTER ifHCInOctets;
+ T3_64BIT_REGISTER Reserved1;
+ T3_64BIT_REGISTER etherStatsFragments;
+ T3_64BIT_REGISTER ifHCInUcastPkts;
+ T3_64BIT_REGISTER ifHCInMulticastPkts;
+ T3_64BIT_REGISTER ifHCInBroadcastPkts;
+ T3_64BIT_REGISTER dot3StatsFCSErrors;
+ T3_64BIT_REGISTER dot3StatsAlignmentErrors;
+ T3_64BIT_REGISTER xonPauseFramesReceived;
+ T3_64BIT_REGISTER xoffPauseFramesReceived;
+ T3_64BIT_REGISTER macControlFramesReceived;
+ T3_64BIT_REGISTER xoffStateEntered;
+ T3_64BIT_REGISTER dot3StatsFramesTooLong;
+ T3_64BIT_REGISTER etherStatsJabbers;
+ T3_64BIT_REGISTER etherStatsUndersizePkts;
+ T3_64BIT_REGISTER inRangeLengthError;
+ T3_64BIT_REGISTER outRangeLengthError;
+ T3_64BIT_REGISTER etherStatsPkts64Octets;
+ T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
+ T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
+ T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
+ T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
+ T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
+ T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
+ T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
+ T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
+ T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
+
+ T3_64BIT_REGISTER Unused1[37];
+
+ /* Statistics maintained by Transmit MAC. */
+ T3_64BIT_REGISTER ifHCOutOctets;
+ T3_64BIT_REGISTER Reserved2;
+ T3_64BIT_REGISTER etherStatsCollisions;
+ T3_64BIT_REGISTER outXonSent;
+ T3_64BIT_REGISTER outXoffSent;
+ T3_64BIT_REGISTER flowControlDone;
+ T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
+ T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
+ T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
+ T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
+ T3_64BIT_REGISTER Reserved3;
+ T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
+ T3_64BIT_REGISTER dot3StatsLateCollisions;
+ T3_64BIT_REGISTER dot3Collided2Times;
+ T3_64BIT_REGISTER dot3Collided3Times;
+ T3_64BIT_REGISTER dot3Collided4Times;
+ T3_64BIT_REGISTER dot3Collided5Times;
+ T3_64BIT_REGISTER dot3Collided6Times;
+ T3_64BIT_REGISTER dot3Collided7Times;
+ T3_64BIT_REGISTER dot3Collided8Times;
+ T3_64BIT_REGISTER dot3Collided9Times;
+ T3_64BIT_REGISTER dot3Collided10Times;
+ T3_64BIT_REGISTER dot3Collided11Times;
+ T3_64BIT_REGISTER dot3Collided12Times;
+ T3_64BIT_REGISTER dot3Collided13Times;
+ T3_64BIT_REGISTER dot3Collided14Times;
+ T3_64BIT_REGISTER dot3Collided15Times;
+ T3_64BIT_REGISTER ifHCOutUcastPkts;
+ T3_64BIT_REGISTER ifHCOutMulticastPkts;
+ T3_64BIT_REGISTER ifHCOutBroadcastPkts;
+ T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
+ T3_64BIT_REGISTER ifOutDiscards;
+ T3_64BIT_REGISTER ifOutErrors;
+
+ T3_64BIT_REGISTER Unused2[31];
+
+ /* Statistics maintained by Receive List Placement. */
+ T3_64BIT_REGISTER COSIfHCInPkts[16];
+ T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
+ T3_64BIT_REGISTER nicDmaWriteQueueFull;
+ T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
+ T3_64BIT_REGISTER nicNoMoreRxBDs;
+ T3_64BIT_REGISTER ifInDiscards;
+ T3_64BIT_REGISTER ifInErrors;
+ T3_64BIT_REGISTER nicRecvThresholdHit;
+
+ T3_64BIT_REGISTER Unused3[9];
+
+ /* Statistics maintained by Send Data Initiator. */
+ T3_64BIT_REGISTER COSIfHCOutPkts[16];
+ T3_64BIT_REGISTER nicDmaReadQueueFull;
+ T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
+ T3_64BIT_REGISTER nicSendDataCompQueueFull;
+
+ /* Statistics maintained by Host Coalescing. */
+ T3_64BIT_REGISTER nicRingSetSendProdIndex;
+ T3_64BIT_REGISTER nicRingStatusUpdate;
+ T3_64BIT_REGISTER nicInterrupts;
+ T3_64BIT_REGISTER nicAvoidedInterrupts;
+ T3_64BIT_REGISTER nicSendThresholdHit;
+
+ LM_UINT8 Reserved4[0xb00 - 0x9c0];
} T3_STATS_BLOCK, *PT3_STATS_BLOCK;
-
/******************************************************************************/
/* PCI configuration registers. */
/******************************************************************************/
typedef struct {
- T3_16BIT_REGISTER VendorId;
- T3_16BIT_REGISTER DeviceId;
-
- T3_16BIT_REGISTER Command;
- T3_16BIT_REGISTER Status;
-
- T3_32BIT_REGISTER ClassCodeRevId;
-
- T3_8BIT_REGISTER CacheLineSize;
- T3_8BIT_REGISTER LatencyTimer;
- T3_8BIT_REGISTER HeaderType;
- T3_8BIT_REGISTER Bist;
-
- T3_32BIT_REGISTER MemBaseAddrLow;
- T3_32BIT_REGISTER MemBaseAddrHigh;
-
- LM_UINT8 Unused1[20];
-
- T3_16BIT_REGISTER SubsystemVendorId;
- T3_16BIT_REGISTER SubsystemId;
-
- T3_32BIT_REGISTER RomBaseAddr;
-
- T3_8BIT_REGISTER PciXCapiblityPtr;
- LM_UINT8 Unused2[7];
-
- T3_8BIT_REGISTER IntLine;
- T3_8BIT_REGISTER IntPin;
- T3_8BIT_REGISTER MinGnt;
- T3_8BIT_REGISTER MaxLat;
-
- T3_8BIT_REGISTER PciXCapabilities;
- T3_8BIT_REGISTER PmCapabilityPtr;
- T3_16BIT_REGISTER PciXCommand;
-
- T3_32BIT_REGISTER PciXStatus;
-
- T3_8BIT_REGISTER PmCapabilityId;
- T3_8BIT_REGISTER VpdCapabilityPtr;
- T3_16BIT_REGISTER PmCapabilities;
-
- T3_16BIT_REGISTER PmCtrlStatus;
- #define PM_CTRL_PME_STATUS BIT_15
- #define PM_CTRL_PME_ENABLE BIT_8
- #define PM_CTRL_PME_POWER_STATE_D0 0
- #define PM_CTRL_PME_POWER_STATE_D1 1
- #define PM_CTRL_PME_POWER_STATE_D2 2
- #define PM_CTRL_PME_POWER_STATE_D3H 3
-
- T3_8BIT_REGISTER BridgeSupportExt;
- T3_8BIT_REGISTER PmData;
-
- T3_8BIT_REGISTER VpdCapabilityId;
- T3_8BIT_REGISTER MsiCapabilityPtr;
- T3_16BIT_REGISTER VpdAddrFlag;
- #define VPD_FLAG_WRITE (1 << 15)
- #define VPD_FLAG_RW_MASK (1 << 15)
- #define VPD_FLAG_READ 0
-
-
- T3_32BIT_REGISTER VpdData;
-
- T3_8BIT_REGISTER MsiCapabilityId;
- T3_8BIT_REGISTER NextCapabilityPtr;
- T3_16BIT_REGISTER MsiCtrl;
- #define MSI_CTRL_64BIT_CAP (1 << 7)
- #define MSI_CTRL_MSG_ENABLE(x) (x << 4)
- #define MSI_CTRL_MSG_CAP(x) (x << 1)
- #define MSI_CTRL_ENABLE (1 << 0)
-
-
- T3_32BIT_REGISTER MsiAddrLow;
- T3_32BIT_REGISTER MsiAddrHigh;
-
- T3_16BIT_REGISTER MsiData;
- T3_16BIT_REGISTER Unused3;
-
- T3_32BIT_REGISTER MiscHostCtrl;
- #define MISC_HOST_CTRL_CLEAR_INT BIT_0
- #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
- #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
- #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
- #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
- #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
- #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
- #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
- #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
- #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
-
- T3_32BIT_REGISTER DmaReadWriteCtrl;
- #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
- #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
- #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
- #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
- #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
- #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
- #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
- #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
- #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
- #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
-
-
- T3_32BIT_REGISTER PciState;
- #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
- #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
- #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
- #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
- #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
- #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
- #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
- #define T3_PCI_STATE_FLAT_VIEW BIT_8
- #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
-
- T3_32BIT_REGISTER ClockCtrl;
- #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
- #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
- #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
-
- T3_32BIT_REGISTER RegBaseAddr;
-
- T3_32BIT_REGISTER MemWindowBaseAddr;
+ T3_16BIT_REGISTER VendorId;
+ T3_16BIT_REGISTER DeviceId;
+
+ T3_16BIT_REGISTER Command;
+ T3_16BIT_REGISTER Status;
+
+ T3_32BIT_REGISTER ClassCodeRevId;
+
+ T3_8BIT_REGISTER CacheLineSize;
+ T3_8BIT_REGISTER LatencyTimer;
+ T3_8BIT_REGISTER HeaderType;
+ T3_8BIT_REGISTER Bist;
+
+ T3_32BIT_REGISTER MemBaseAddrLow;
+ T3_32BIT_REGISTER MemBaseAddrHigh;
+
+ LM_UINT8 Unused1[20];
+
+ T3_16BIT_REGISTER SubsystemVendorId;
+ T3_16BIT_REGISTER SubsystemId;
+
+ T3_32BIT_REGISTER RomBaseAddr;
+
+ T3_8BIT_REGISTER PciXCapiblityPtr;
+ LM_UINT8 Unused2[7];
+
+ T3_8BIT_REGISTER IntLine;
+ T3_8BIT_REGISTER IntPin;
+ T3_8BIT_REGISTER MinGnt;
+ T3_8BIT_REGISTER MaxLat;
+
+ T3_8BIT_REGISTER PciXCapabilities;
+ T3_8BIT_REGISTER PmCapabilityPtr;
+ T3_16BIT_REGISTER PciXCommand;
+
+ T3_32BIT_REGISTER PciXStatus;
+
+ T3_8BIT_REGISTER PmCapabilityId;
+ T3_8BIT_REGISTER VpdCapabilityPtr;
+ T3_16BIT_REGISTER PmCapabilities;
+
+ T3_16BIT_REGISTER PmCtrlStatus;
+#define PM_CTRL_PME_STATUS BIT_15
+#define PM_CTRL_PME_ENABLE BIT_8
+#define PM_CTRL_PME_POWER_STATE_D0 0
+#define PM_CTRL_PME_POWER_STATE_D1 1
+#define PM_CTRL_PME_POWER_STATE_D2 2
+#define PM_CTRL_PME_POWER_STATE_D3H 3
+
+ T3_8BIT_REGISTER BridgeSupportExt;
+ T3_8BIT_REGISTER PmData;
+
+ T3_8BIT_REGISTER VpdCapabilityId;
+ T3_8BIT_REGISTER MsiCapabilityPtr;
+ T3_16BIT_REGISTER VpdAddrFlag;
+#define VPD_FLAG_WRITE (1 << 15)
+#define VPD_FLAG_RW_MASK (1 << 15)
+#define VPD_FLAG_READ 0
+
+ T3_32BIT_REGISTER VpdData;
+
+ T3_8BIT_REGISTER MsiCapabilityId;
+ T3_8BIT_REGISTER NextCapabilityPtr;
+ T3_16BIT_REGISTER MsiCtrl;
+#define MSI_CTRL_64BIT_CAP (1 << 7)
+#define MSI_CTRL_MSG_ENABLE(x) (x << 4)
+#define MSI_CTRL_MSG_CAP(x) (x << 1)
+#define MSI_CTRL_ENABLE (1 << 0)
+
+ T3_32BIT_REGISTER MsiAddrLow;
+ T3_32BIT_REGISTER MsiAddrHigh;
+
+ T3_16BIT_REGISTER MsiData;
+ T3_16BIT_REGISTER Unused3;
+
+ T3_32BIT_REGISTER MiscHostCtrl;
+#define MISC_HOST_CTRL_CLEAR_INT BIT_0
+#define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
+#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
+#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
+#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
+#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
+#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
+#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
+#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
+#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
+
+ T3_32BIT_REGISTER DmaReadWriteCtrl;
+#define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
+#define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
+#define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
+#define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
+#define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
+#define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
+#define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
+#define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
+#define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
+#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
+
+ T3_32BIT_REGISTER PciState;
+#define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
+#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
+#define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
+#define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
+#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
+#define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
+#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
+#define T3_PCI_STATE_FLAT_VIEW BIT_8
+#define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
+
+ T3_32BIT_REGISTER ClockCtrl;
+#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
+#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
+#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
+
+ T3_32BIT_REGISTER RegBaseAddr;
+
+ T3_32BIT_REGISTER MemWindowBaseAddr;
#ifdef NIC_CPU_VIEW
- /* These registers are ONLY visible to NIC CPU */
- T3_32BIT_REGISTER PowerConsumed;
- T3_32BIT_REGISTER PowerDissipated;
-#else /* NIC_CPU_VIEW */
- T3_32BIT_REGISTER RegData;
- T3_32BIT_REGISTER MemWindowData;
-#endif /* !NIC_CPU_VIEW */
+ /* These registers are ONLY visible to NIC CPU */
+ T3_32BIT_REGISTER PowerConsumed;
+ T3_32BIT_REGISTER PowerDissipated;
+#else /* NIC_CPU_VIEW */
+ T3_32BIT_REGISTER RegData;
+ T3_32BIT_REGISTER MemWindowData;
+#endif /* !NIC_CPU_VIEW */
- T3_32BIT_REGISTER ModeCtrl;
+ T3_32BIT_REGISTER ModeCtrl;
- T3_32BIT_REGISTER MiscCfg;
+ T3_32BIT_REGISTER MiscCfg;
- T3_32BIT_REGISTER MiscLocalCtrl;
+ T3_32BIT_REGISTER MiscLocalCtrl;
- T3_32BIT_REGISTER Unused4;
+ T3_32BIT_REGISTER Unused4;
- /* NOTE: Big/Little-endian clarification needed. Are these register */
- /* in big or little endian formate. */
- T3_64BIT_REGISTER StdRingProdIdx;
- T3_64BIT_REGISTER RcvRetRingConIdx;
- T3_64BIT_REGISTER SndProdIdx;
+ /* NOTE: Big/Little-endian clarification needed. Are these register */
+ /* in big or little endian formate. */
+ T3_64BIT_REGISTER StdRingProdIdx;
+ T3_64BIT_REGISTER RcvRetRingConIdx;
+ T3_64BIT_REGISTER SndProdIdx;
- LM_UINT8 Unused5[80];
+ LM_UINT8 Unused5[80];
} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
#define PCIX_CMD_MAX_SPLIT_MASK 0x0070
/******************************************************************************/
typedef struct {
- /* MAC mode control. */
- T3_32BIT_REGISTER Mode;
- #define MAC_MODE_GLOBAL_RESET BIT_0
- #define MAC_MODE_HALF_DUPLEX BIT_1
- #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
- #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
- #define MAC_MODE_PORT_MODE_GMII BIT_3
- #define MAC_MODE_PORT_MODE_MII BIT_2
- #define MAC_MODE_PORT_MODE_NONE BIT_NONE
- #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
- #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
- #define MAC_MODE_TX_BURSTING BIT_8
- #define MAC_MODE_MAX_DEFER BIT_9
- #define MAC_MODE_LINK_POLARITY BIT_10
- #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
- #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
- #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
- #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
- #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
- #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
- #define MAC_MODE_SEND_CONFIGS BIT_17
- #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
- #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
- #define MAC_MODE_ENABLE_MIP BIT_20
- #define MAC_MODE_ENABLE_TDE BIT_21
- #define MAC_MODE_ENABLE_RDE BIT_22
- #define MAC_MODE_ENABLE_FHDE BIT_23
-
- /* MAC status */
- T3_32BIT_REGISTER Status;
- #define MAC_STATUS_PCS_SYNCED BIT_0
- #define MAC_STATUS_SIGNAL_DETECTED BIT_1
- #define MAC_STATUS_RECEIVING_CFG BIT_2
- #define MAC_STATUS_CFG_CHANGED BIT_3
- #define MAC_STATUS_SYNC_CHANGED BIT_4
- #define MAC_STATUS_PORT_DECODE_ERROR BIT_10
- #define MAC_STATUS_LINK_STATE_CHANGED BIT_12
- #define MAC_STATUS_MI_COMPLETION BIT_22
- #define MAC_STATUS_MI_INTERRUPT BIT_23
- #define MAC_STATUS_AP_ERROR BIT_24
- #define MAC_STATUS_ODI_ERROR BIT_25
- #define MAC_STATUS_RX_STATS_OVERRUN BIT_26
- #define MAC_STATUS_TX_STATS_OVERRUN BIT_27
-
- /* Event Enable */
- T3_32BIT_REGISTER MacEvent;
- #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
- #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
- #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
- #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
- #define MAC_EVENT_ENABLE_AP_ERROR BIT_24
- #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
- #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
- #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
-
- /* Led control. */
- T3_32BIT_REGISTER LedCtrl;
- #define LED_CTRL_OVERRIDE_LINK_LED BIT_0
- #define LED_CTRL_1000MBPS_LED_ON BIT_1
- #define LED_CTRL_100MBPS_LED_ON BIT_2
- #define LED_CTRL_10MBPS_LED_ON BIT_3
- #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
- #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
- #define LED_CTRL_TRAFFIC_LED BIT_6
- #define LED_CTRL_1000MBPS_LED_STATUS BIT_7
- #define LED_CTRL_100MBPS_LED_STATUS BIT_8
- #define LED_CTRL_10MBPS_LED_STATUS BIT_9
- #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
- #define LED_CTRL_MAC_MODE BIT_NONE
- #define LED_CTRL_PHY_MODE_1 BIT_11
- #define LED_CTRL_PHY_MODE_2 BIT_12
- #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
- #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
- #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
-
- /* MAC addresses. */
- struct {
- T3_32BIT_REGISTER High; /* Upper 2 bytes. */
- T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
- } MacAddr[4];
-
- /* ACPI Mbuf pointer. */
- T3_32BIT_REGISTER AcpiMbufPtr;
-
- /* ACPI Length and Offset. */
- T3_32BIT_REGISTER AcpiLengthOffset;
- #define ACPI_LENGTH_MASK 0xffff
- #define ACPI_OFFSET_MASK 0x0fff0000
- #define ACPI_LENGTH(x) x
- #define ACPI_OFFSET(x) ((x) << 16)
-
- /* Transmit random backoff. */
- T3_32BIT_REGISTER TxBackoffSeed;
- #define MAC_TX_BACKOFF_SEED_MASK 0x3ff
-
- /* Receive MTU */
- T3_32BIT_REGISTER MtuSize;
- #define MAC_RX_MTU_MASK 0xffff
-
- /* Gigabit PCS Test. */
- T3_32BIT_REGISTER PcsTest;
- #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
- #define MAC_PCS_TEST_ENABLE BIT_20
-
- /* Transmit Gigabit Auto-Negotiation. */
- T3_32BIT_REGISTER TxAutoNeg;
- #define MAC_AN_TX_AN_DATA_MASK 0xffff
-
- /* Receive Gigabit Auto-Negotiation. */
- T3_32BIT_REGISTER RxAutoNeg;
- #define MAC_AN_RX_AN_DATA_MASK 0xffff
-
- /* MI Communication. */
- T3_32BIT_REGISTER MiCom;
- #define MI_COM_CMD_MASK (BIT_26 | BIT_27)
- #define MI_COM_CMD_WRITE BIT_26
- #define MI_COM_CMD_READ BIT_27
- #define MI_COM_READ_FAILED BIT_28
- #define MI_COM_START BIT_29
- #define MI_COM_BUSY BIT_29
-
- #define MI_COM_PHY_ADDR_MASK 0x1f
- #define MI_COM_FIRST_PHY_ADDR_BIT 21
-
- #define MI_COM_PHY_REG_ADDR_MASK 0x1f
- #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
-
- #define MI_COM_PHY_DATA_MASK 0xffff
-
- /* MI Status. */
- T3_32BIT_REGISTER MiStatus;
- #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
-
- /* MI Mode. */
- T3_32BIT_REGISTER MiMode;
- #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
- #define MI_MODE_USE_SHORT_PREAMBLE BIT_1
- #define MI_MODE_AUTO_POLLING_ENABLE BIT_4
- #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
-
- /* Auto-polling status. */
- T3_32BIT_REGISTER AutoPollStatus;
- #define AUTO_POLL_ERROR BIT_0
-
- /* Transmit MAC mode. */
- T3_32BIT_REGISTER TxMode;
- #define TX_MODE_RESET BIT_0
- #define TX_MODE_ENABLE BIT_1
- #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
- #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
- #define TX_MODE_ENABLE_LONG_PAUSE BIT_6
-
- /* Transmit MAC status. */
- T3_32BIT_REGISTER TxStatus;
- #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
- #define TX_STATUS_SENT_XOFF BIT_1
- #define TX_STATUS_SENT_XON BIT_2
- #define TX_STATUS_LINK_UP BIT_3
- #define TX_STATUS_ODI_UNDERRUN BIT_4
- #define TX_STATUS_ODI_OVERRUN BIT_5
-
- /* Transmit MAC length. */
- T3_32BIT_REGISTER TxLengths;
- #define TX_LEN_SLOT_TIME_MASK 0xff
- #define TX_LEN_IPG_MASK 0x0f00
- #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
-
- /* Receive MAC mode. */
- T3_32BIT_REGISTER RxMode;
- #define RX_MODE_RESET BIT_0
- #define RX_MODE_ENABLE BIT_1
- #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
- #define RX_MODE_KEEP_MAC_CONTROL BIT_3
- #define RX_MODE_KEEP_PAUSE BIT_4
- #define RX_MODE_ACCEPT_OVERSIZED BIT_5
- #define RX_MODE_ACCEPT_RUNTS BIT_6
- #define RX_MODE_LENGTH_CHECK BIT_7
- #define RX_MODE_PROMISCUOUS_MODE BIT_8
- #define RX_MODE_NO_CRC_CHECK BIT_9
- #define RX_MODE_KEEP_VLAN_TAG BIT_10
-
- /* Receive MAC status. */
- T3_32BIT_REGISTER RxStatus;
- #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
- #define RX_STATUS_XOFF_RECEIVED BIT_1
- #define RX_STATUS_XON_RECEIVED BIT_2
-
- /* Hash registers. */
- T3_32BIT_REGISTER HashReg[4];
-
- /* Receive placement rules registers. */
- struct {
- T3_32BIT_REGISTER Rule;
- T3_32BIT_REGISTER Value;
- } RcvRules[16];
-
- #define RCV_DISABLE_RULE_MASK 0x7fffffff
-
- #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
- #define REJECT_BROADCAST_RULE1_RULE 0xc2000000
- #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
-
- #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
- #define REJECT_BROADCAST_RULE2_RULE 0x86000004
- #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
+ /* MAC mode control. */
+ T3_32BIT_REGISTER Mode;
+#define MAC_MODE_GLOBAL_RESET BIT_0
+#define MAC_MODE_HALF_DUPLEX BIT_1
+#define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
+#define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
+#define MAC_MODE_PORT_MODE_GMII BIT_3
+#define MAC_MODE_PORT_MODE_MII BIT_2
+#define MAC_MODE_PORT_MODE_NONE BIT_NONE
+#define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
+#define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
+#define MAC_MODE_TX_BURSTING BIT_8
+#define MAC_MODE_MAX_DEFER BIT_9
+#define MAC_MODE_LINK_POLARITY BIT_10
+#define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
+#define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
+#define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
+#define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
+#define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
+#define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
+#define MAC_MODE_SEND_CONFIGS BIT_17
+#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
+#define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
+#define MAC_MODE_ENABLE_MIP BIT_20
+#define MAC_MODE_ENABLE_TDE BIT_21
+#define MAC_MODE_ENABLE_RDE BIT_22
+#define MAC_MODE_ENABLE_FHDE BIT_23
+
+ /* MAC status */
+ T3_32BIT_REGISTER Status;
+#define MAC_STATUS_PCS_SYNCED BIT_0
+#define MAC_STATUS_SIGNAL_DETECTED BIT_1
+#define MAC_STATUS_RECEIVING_CFG BIT_2
+#define MAC_STATUS_CFG_CHANGED BIT_3
+#define MAC_STATUS_SYNC_CHANGED BIT_4
+#define MAC_STATUS_PORT_DECODE_ERROR BIT_10
+#define MAC_STATUS_LINK_STATE_CHANGED BIT_12
+#define MAC_STATUS_MI_COMPLETION BIT_22
+#define MAC_STATUS_MI_INTERRUPT BIT_23
+#define MAC_STATUS_AP_ERROR BIT_24
+#define MAC_STATUS_ODI_ERROR BIT_25
+#define MAC_STATUS_RX_STATS_OVERRUN BIT_26
+#define MAC_STATUS_TX_STATS_OVERRUN BIT_27
+
+ /* Event Enable */
+ T3_32BIT_REGISTER MacEvent;
+#define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
+#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
+#define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
+#define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
+#define MAC_EVENT_ENABLE_AP_ERROR BIT_24
+#define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
+#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
+#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
+
+ /* Led control. */
+ T3_32BIT_REGISTER LedCtrl;
+#define LED_CTRL_OVERRIDE_LINK_LED BIT_0
+#define LED_CTRL_1000MBPS_LED_ON BIT_1
+#define LED_CTRL_100MBPS_LED_ON BIT_2
+#define LED_CTRL_10MBPS_LED_ON BIT_3
+#define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
+#define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
+#define LED_CTRL_TRAFFIC_LED BIT_6
+#define LED_CTRL_1000MBPS_LED_STATUS BIT_7
+#define LED_CTRL_100MBPS_LED_STATUS BIT_8
+#define LED_CTRL_10MBPS_LED_STATUS BIT_9
+#define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
+#define LED_CTRL_MAC_MODE BIT_NONE
+#define LED_CTRL_PHY_MODE_1 BIT_11
+#define LED_CTRL_PHY_MODE_2 BIT_12
+#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
+#define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
+#define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
+
+ /* MAC addresses. */
+ struct {
+ T3_32BIT_REGISTER High; /* Upper 2 bytes. */
+ T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
+ } MacAddr[4];
+
+ /* ACPI Mbuf pointer. */
+ T3_32BIT_REGISTER AcpiMbufPtr;
+
+ /* ACPI Length and Offset. */
+ T3_32BIT_REGISTER AcpiLengthOffset;
+#define ACPI_LENGTH_MASK 0xffff
+#define ACPI_OFFSET_MASK 0x0fff0000
+#define ACPI_LENGTH(x) x
+#define ACPI_OFFSET(x) ((x) << 16)
+
+ /* Transmit random backoff. */
+ T3_32BIT_REGISTER TxBackoffSeed;
+#define MAC_TX_BACKOFF_SEED_MASK 0x3ff
+
+ /* Receive MTU */
+ T3_32BIT_REGISTER MtuSize;
+#define MAC_RX_MTU_MASK 0xffff
+
+ /* Gigabit PCS Test. */
+ T3_32BIT_REGISTER PcsTest;
+#define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
+#define MAC_PCS_TEST_ENABLE BIT_20
+
+ /* Transmit Gigabit Auto-Negotiation. */
+ T3_32BIT_REGISTER TxAutoNeg;
+#define MAC_AN_TX_AN_DATA_MASK 0xffff
+
+ /* Receive Gigabit Auto-Negotiation. */
+ T3_32BIT_REGISTER RxAutoNeg;
+#define MAC_AN_RX_AN_DATA_MASK 0xffff
+
+ /* MI Communication. */
+ T3_32BIT_REGISTER MiCom;
+#define MI_COM_CMD_MASK (BIT_26 | BIT_27)
+#define MI_COM_CMD_WRITE BIT_26
+#define MI_COM_CMD_READ BIT_27
+#define MI_COM_READ_FAILED BIT_28
+#define MI_COM_START BIT_29
+#define MI_COM_BUSY BIT_29
+
+#define MI_COM_PHY_ADDR_MASK 0x1f
+#define MI_COM_FIRST_PHY_ADDR_BIT 21
+
+#define MI_COM_PHY_REG_ADDR_MASK 0x1f
+#define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
+
+#define MI_COM_PHY_DATA_MASK 0xffff
+
+ /* MI Status. */
+ T3_32BIT_REGISTER MiStatus;
+#define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
+
+ /* MI Mode. */
+ T3_32BIT_REGISTER MiMode;
+#define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
+#define MI_MODE_USE_SHORT_PREAMBLE BIT_1
+#define MI_MODE_AUTO_POLLING_ENABLE BIT_4
+#define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
+
+ /* Auto-polling status. */
+ T3_32BIT_REGISTER AutoPollStatus;
+#define AUTO_POLL_ERROR BIT_0
+
+ /* Transmit MAC mode. */
+ T3_32BIT_REGISTER TxMode;
+#define TX_MODE_RESET BIT_0
+#define TX_MODE_ENABLE BIT_1
+#define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
+#define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
+#define TX_MODE_ENABLE_LONG_PAUSE BIT_6
+
+ /* Transmit MAC status. */
+ T3_32BIT_REGISTER TxStatus;
+#define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
+#define TX_STATUS_SENT_XOFF BIT_1
+#define TX_STATUS_SENT_XON BIT_2
+#define TX_STATUS_LINK_UP BIT_3
+#define TX_STATUS_ODI_UNDERRUN BIT_4
+#define TX_STATUS_ODI_OVERRUN BIT_5
+
+ /* Transmit MAC length. */
+ T3_32BIT_REGISTER TxLengths;
+#define TX_LEN_SLOT_TIME_MASK 0xff
+#define TX_LEN_IPG_MASK 0x0f00
+#define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
+
+ /* Receive MAC mode. */
+ T3_32BIT_REGISTER RxMode;
+#define RX_MODE_RESET BIT_0
+#define RX_MODE_ENABLE BIT_1
+#define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
+#define RX_MODE_KEEP_MAC_CONTROL BIT_3
+#define RX_MODE_KEEP_PAUSE BIT_4
+#define RX_MODE_ACCEPT_OVERSIZED BIT_5
+#define RX_MODE_ACCEPT_RUNTS BIT_6
+#define RX_MODE_LENGTH_CHECK BIT_7
+#define RX_MODE_PROMISCUOUS_MODE BIT_8
+#define RX_MODE_NO_CRC_CHECK BIT_9
+#define RX_MODE_KEEP_VLAN_TAG BIT_10
+
+ /* Receive MAC status. */
+ T3_32BIT_REGISTER RxStatus;
+#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
+#define RX_STATUS_XOFF_RECEIVED BIT_1
+#define RX_STATUS_XON_RECEIVED BIT_2
+
+ /* Hash registers. */
+ T3_32BIT_REGISTER HashReg[4];
+
+ /* Receive placement rules registers. */
+ struct {
+ T3_32BIT_REGISTER Rule;
+ T3_32BIT_REGISTER Value;
+ } RcvRules[16];
+
+#define RCV_DISABLE_RULE_MASK 0x7fffffff
+
+#define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
+#define REJECT_BROADCAST_RULE1_RULE 0xc2000000
+#define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
+
+#define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
+#define REJECT_BROADCAST_RULE2_RULE 0x86000004
+#define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
#if INCLUDE_5701_AX_FIX
- #define RCV_LAST_RULE_IDX 0x04
+#define RCV_LAST_RULE_IDX 0x04
#else
- #define RCV_LAST_RULE_IDX 0x02
+#define RCV_LAST_RULE_IDX 0x02
#endif
- T3_32BIT_REGISTER RcvRuleCfg;
- #define RX_RULE_DEFAULT_CLASS (1 << 3)
+ T3_32BIT_REGISTER RcvRuleCfg;
+#define RX_RULE_DEFAULT_CLASS (1 << 3)
- LM_UINT8 Reserved1[140];
+ LM_UINT8 Reserved1[140];
- T3_32BIT_REGISTER SerdesCfg;
- T3_32BIT_REGISTER SerdesStatus;
+ T3_32BIT_REGISTER SerdesCfg;
+ T3_32BIT_REGISTER SerdesStatus;
- LM_UINT8 Reserved2[104];
+ LM_UINT8 Reserved2[104];
- volatile LM_UINT8 TxMacState[16];
- volatile LM_UINT8 RxMacState[20];
+ volatile LM_UINT8 TxMacState[16];
+ volatile LM_UINT8 RxMacState[20];
- LM_UINT8 Reserved3[476];
+ LM_UINT8 Reserved3[476];
- T3_32BIT_REGISTER RxStats[26];
+ T3_32BIT_REGISTER RxStats[26];
- LM_UINT8 Reserved4[24];
+ LM_UINT8 Reserved4[24];
- T3_32BIT_REGISTER TxStats[28];
+ T3_32BIT_REGISTER TxStats[28];
- LM_UINT8 Reserved5[784];
+ LM_UINT8 Reserved5[784];
} T3_MAC_CONTROL, *PT3_MAC_CONTROL;
-
/******************************************************************************/
/* Send data initiator control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define T3_SND_DATA_IN_MODE_RESET BIT_0
- #define T3_SND_DATA_IN_MODE_ENABLE BIT_1
- #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
- #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
-
- T3_32BIT_REGISTER StatsCtrl;
- #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
- #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
- #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
- #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
- #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
-
- T3_32BIT_REGISTER StatsEnableMask;
- T3_32BIT_REGISTER StatsIncMask;
-
- LM_UINT8 Reserved[108];
-
- T3_32BIT_REGISTER ClassOfServCnt[16];
- T3_32BIT_REGISTER DmaReadQFullCnt;
- T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
- T3_32BIT_REGISTER SdcQFullCnt;
-
- T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
- T3_32BIT_REGISTER StatusUpdatedCnt;
- T3_32BIT_REGISTER InterruptsCnt;
- T3_32BIT_REGISTER AvoidInterruptsCnt;
- T3_32BIT_REGISTER SendThresholdHitCnt;
-
- /* Unused space. */
- LM_UINT8 Unused[800];
-} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
+ T3_32BIT_REGISTER Mode;
+#define T3_SND_DATA_IN_MODE_RESET BIT_0
+#define T3_SND_DATA_IN_MODE_ENABLE BIT_1
+#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
+
+ T3_32BIT_REGISTER Status;
+#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
+
+ T3_32BIT_REGISTER StatsCtrl;
+#define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
+#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
+#define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
+#define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
+#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
+
+ T3_32BIT_REGISTER StatsEnableMask;
+ T3_32BIT_REGISTER StatsIncMask;
+
+ LM_UINT8 Reserved[108];
+ T3_32BIT_REGISTER ClassOfServCnt[16];
+ T3_32BIT_REGISTER DmaReadQFullCnt;
+ T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
+ T3_32BIT_REGISTER SdcQFullCnt;
+
+ T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
+ T3_32BIT_REGISTER StatusUpdatedCnt;
+ T3_32BIT_REGISTER InterruptsCnt;
+ T3_32BIT_REGISTER AvoidInterruptsCnt;
+ T3_32BIT_REGISTER SendThresholdHitCnt;
+
+ /* Unused space. */
+ LM_UINT8 Unused[800];
+} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
/******************************************************************************/
/* Send data completion control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_DATA_COMP_MODE_RESET BIT_0
- #define SND_DATA_COMP_MODE_ENABLE BIT_1
+ T3_32BIT_REGISTER Mode;
+#define SND_DATA_COMP_MODE_RESET BIT_0
+#define SND_DATA_COMP_MODE_ENABLE BIT_1
- /* Unused space. */
- LM_UINT8 Unused[1020];
+ /* Unused space. */
+ LM_UINT8 Unused[1020];
} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
-
/******************************************************************************/
/* Send BD Ring Selector Control Registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_BD_SEL_MODE_RESET BIT_0
- #define SND_BD_SEL_MODE_ENABLE BIT_1
- #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define SND_BD_SEL_MODE_RESET BIT_0
+#define SND_BD_SEL_MODE_ENABLE BIT_1
+#define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
- T3_32BIT_REGISTER HwDiag;
+ T3_32BIT_REGISTER HwDiag;
- /* Unused space. */
- LM_UINT8 Unused1[52];
+ /* Unused space. */
+ LM_UINT8 Unused1[52];
- /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
- T3_32BIT_REGISTER NicSendBdSelConIdx[16];
+ /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
+ T3_32BIT_REGISTER NicSendBdSelConIdx[16];
- /* Unused space. */
- LM_UINT8 Unused2[896];
+ /* Unused space. */
+ LM_UINT8 Unused2[896];
} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
-
/******************************************************************************/
/* Send BD initiator control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_BD_IN_MODE_RESET BIT_0
- #define SND_BD_IN_MODE_ENABLE BIT_1
- #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define SND_BD_IN_MODE_RESET BIT_0
+#define SND_BD_IN_MODE_ENABLE BIT_1
+#define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
- /* Send BD initiator local NIC send BD producer index. */
- T3_32BIT_REGISTER NicSendBdInProdIdx[16];
+ /* Send BD initiator local NIC send BD producer index. */
+ T3_32BIT_REGISTER NicSendBdInProdIdx[16];
- /* Unused space. */
- LM_UINT8 Unused2[952];
+ /* Unused space. */
+ LM_UINT8 Unused2[952];
} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
-
/******************************************************************************/
/* Send BD Completion Control. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_BD_COMP_MODE_RESET BIT_0
- #define SND_BD_COMP_MODE_ENABLE BIT_1
- #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define SND_BD_COMP_MODE_RESET BIT_0
+#define SND_BD_COMP_MODE_ENABLE BIT_1
+#define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
- /* Unused space. */
- LM_UINT8 Unused2[1020];
+ /* Unused space. */
+ LM_UINT8 Unused2[1020];
} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
-
/******************************************************************************/
/* Receive list placement control registers. */
/******************************************************************************/
typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
- #define RCV_LIST_PLMT_MODE_RESET BIT_0
- #define RCV_LIST_PLMT_MODE_ENABLE BIT_1
- #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
- #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
- #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
-
- /* Status. */
- T3_32BIT_REGISTER Status;
- #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
- #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
- #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
-
- /* Receive selector list lock register. */
- T3_32BIT_REGISTER Lock;
- #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
- #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
-
- /* Selector non-empty bits. */
- T3_32BIT_REGISTER NonEmptyBits;
- #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
-
- /* Receive list placement configuration register. */
- T3_32BIT_REGISTER Config;
-
- /* Receive List Placement statistics Control. */
- T3_32BIT_REGISTER StatsCtrl;
+ /* Mode. */
+ T3_32BIT_REGISTER Mode;
+#define RCV_LIST_PLMT_MODE_RESET BIT_0
+#define RCV_LIST_PLMT_MODE_ENABLE BIT_1
+#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
+#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
+#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
+
+ /* Status. */
+ T3_32BIT_REGISTER Status;
+#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
+#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
+#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
+
+ /* Receive selector list lock register. */
+ T3_32BIT_REGISTER Lock;
+#define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
+#define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
+
+ /* Selector non-empty bits. */
+ T3_32BIT_REGISTER NonEmptyBits;
+#define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
+
+ /* Receive list placement configuration register. */
+ T3_32BIT_REGISTER Config;
+
+ /* Receive List Placement statistics Control. */
+ T3_32BIT_REGISTER StatsCtrl;
#define RCV_LIST_STATS_ENABLE BIT_0
#define RCV_LIST_STATS_FAST_UPDATE BIT_1
- /* Receive List Placement statistics Enable Mask. */
- T3_32BIT_REGISTER StatsEnableMask;
-
- /* Receive List Placement statistics Increment Mask. */
- T3_32BIT_REGISTER StatsIncMask;
-
- /* Unused space. */
- LM_UINT8 Unused1[224];
+ /* Receive List Placement statistics Enable Mask. */
+ T3_32BIT_REGISTER StatsEnableMask;
- struct {
- T3_32BIT_REGISTER Head;
- T3_32BIT_REGISTER Tail;
- T3_32BIT_REGISTER Count;
+ /* Receive List Placement statistics Increment Mask. */
+ T3_32BIT_REGISTER StatsIncMask;
/* Unused space. */
- LM_UINT8 Unused[4];
- } RcvSelectorList[16];
-
- /* Local statistics counter. */
- T3_32BIT_REGISTER ClassOfServCnt[16];
-
- T3_32BIT_REGISTER DropDueToFilterCnt;
- T3_32BIT_REGISTER DmaWriteQFullCnt;
- T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
- T3_32BIT_REGISTER NoMoreReceiveBdCnt;
- T3_32BIT_REGISTER IfInDiscardsCnt;
- T3_32BIT_REGISTER IfInErrorsCnt;
- T3_32BIT_REGISTER RcvThresholdHitCnt;
-
- /* Another unused space. */
- LM_UINT8 Unused2[420];
-} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
+ LM_UINT8 Unused1[224];
+ struct {
+ T3_32BIT_REGISTER Head;
+ T3_32BIT_REGISTER Tail;
+ T3_32BIT_REGISTER Count;
+
+ /* Unused space. */
+ LM_UINT8 Unused[4];
+ } RcvSelectorList[16];
+
+ /* Local statistics counter. */
+ T3_32BIT_REGISTER ClassOfServCnt[16];
+
+ T3_32BIT_REGISTER DropDueToFilterCnt;
+ T3_32BIT_REGISTER DmaWriteQFullCnt;
+ T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
+ T3_32BIT_REGISTER NoMoreReceiveBdCnt;
+ T3_32BIT_REGISTER IfInDiscardsCnt;
+ T3_32BIT_REGISTER IfInErrorsCnt;
+ T3_32BIT_REGISTER RcvThresholdHitCnt;
+
+ /* Another unused space. */
+ LM_UINT8 Unused2[420];
+} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
/******************************************************************************/
/* Receive Data and Receive BD Initiator Control. */
/******************************************************************************/
typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
- #define RCV_DATA_BD_IN_MODE_RESET BIT_0
- #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
- #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
- #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
- #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
-
- /* Status. */
- T3_32BIT_REGISTER Status;
- #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
- #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
- #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
-
- /* Split frame minium size. */
- T3_32BIT_REGISTER SplitFrameMinSize;
-
- /* Unused space. */
- LM_UINT8 Unused1[0x2440-0x240c];
-
- /* Receive RCBs. */
- T3_RCB JumboRcvRcb;
- T3_RCB StdRcvRcb;
- T3_RCB MiniRcvRcb;
-
- /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
- /* BD Consumber Index. */
- T3_32BIT_REGISTER NicJumboConIdx;
- T3_32BIT_REGISTER NicStdConIdx;
- T3_32BIT_REGISTER NicMiniConIdx;
-
- /* Unused space. */
- LM_UINT8 Unused2[4];
-
- /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
- T3_32BIT_REGISTER RcvDataBdProdIdx[16];
-
- /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
- T3_32BIT_REGISTER HwDiag;
-
- /* Unused space. */
- LM_UINT8 Unused3[828];
-} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
+ /* Mode. */
+ T3_32BIT_REGISTER Mode;
+#define RCV_DATA_BD_IN_MODE_RESET BIT_0
+#define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
+#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
+#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
+#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
+
+ /* Status. */
+ T3_32BIT_REGISTER Status;
+#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
+#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
+#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
+
+ /* Split frame minium size. */
+ T3_32BIT_REGISTER SplitFrameMinSize;
+
+ /* Unused space. */
+ LM_UINT8 Unused1[0x2440 - 0x240c];
+
+ /* Receive RCBs. */
+ T3_RCB JumboRcvRcb;
+ T3_RCB StdRcvRcb;
+ T3_RCB MiniRcvRcb;
+
+ /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
+ /* BD Consumber Index. */
+ T3_32BIT_REGISTER NicJumboConIdx;
+ T3_32BIT_REGISTER NicStdConIdx;
+ T3_32BIT_REGISTER NicMiniConIdx;
+
+ /* Unused space. */
+ LM_UINT8 Unused2[4];
+
+ /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
+ T3_32BIT_REGISTER RcvDataBdProdIdx[16];
+ /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
+ T3_32BIT_REGISTER HwDiag;
+
+ /* Unused space. */
+ LM_UINT8 Unused3[828];
+} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
/******************************************************************************/
/* Receive Data Completion Control Registes. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_DATA_COMP_MODE_RESET BIT_0
- #define RCV_DATA_COMP_MODE_ENABLE BIT_1
- #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_DATA_COMP_MODE_RESET BIT_0
+#define RCV_DATA_COMP_MODE_ENABLE BIT_1
+#define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
- /* Unused spaced. */
- LM_UINT8 Unused[1020];
+ /* Unused spaced. */
+ LM_UINT8 Unused[1020];
} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
-
/******************************************************************************/
/* Receive BD Initiator Control. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_BD_IN_MODE_RESET BIT_0
- #define RCV_BD_IN_MODE_ENABLE BIT_1
- #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_BD_IN_MODE_RESET BIT_0
+#define RCV_BD_IN_MODE_ENABLE BIT_1
+#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
- T3_32BIT_REGISTER NicJumboRcvProdIdx;
- T3_32BIT_REGISTER NicStdRcvProdIdx;
- T3_32BIT_REGISTER NicMiniRcvProdIdx;
+ T3_32BIT_REGISTER NicJumboRcvProdIdx;
+ T3_32BIT_REGISTER NicStdRcvProdIdx;
+ T3_32BIT_REGISTER NicMiniRcvProdIdx;
- T3_32BIT_REGISTER MiniRcvThreshold;
- T3_32BIT_REGISTER StdRcvThreshold;
- T3_32BIT_REGISTER JumboRcvThreshold;
+ T3_32BIT_REGISTER MiniRcvThreshold;
+ T3_32BIT_REGISTER StdRcvThreshold;
+ T3_32BIT_REGISTER JumboRcvThreshold;
- /* Unused space. */
- LM_UINT8 Unused[992];
+ /* Unused space. */
+ LM_UINT8 Unused[992];
} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
-
/******************************************************************************/
/* Receive BD Completion Control Registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_BD_COMP_MODE_RESET BIT_0
- #define RCV_BD_COMP_MODE_ENABLE BIT_1
- #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_BD_COMP_MODE_RESET BIT_0
+#define RCV_BD_COMP_MODE_ENABLE BIT_1
+#define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
- T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
- T3_32BIT_REGISTER NicStdRcvBdProdIdx;
- T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
+ T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
+ T3_32BIT_REGISTER NicStdRcvBdProdIdx;
+ T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
- /* Unused space. */
- LM_UINT8 Unused[1004];
+ /* Unused space. */
+ LM_UINT8 Unused[1004];
} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
-
/******************************************************************************/
/* Receive list selector control register. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_LIST_SEL_MODE_RESET BIT_0
- #define RCV_LIST_SEL_MODE_ENABLE BIT_1
- #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_LIST_SEL_MODE_RESET BIT_0
+#define RCV_LIST_SEL_MODE_ENABLE BIT_1
+#define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
- /* Unused space. */
- LM_UINT8 Unused[1016];
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
-
/******************************************************************************/
/* Mbuf cluster free registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
+ T3_32BIT_REGISTER Mode;
#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0
#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER Status;
- /* Unused space. */
- LM_UINT8 Unused[1016];
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
-
/******************************************************************************/
/* Host coalescing control registers. */
/******************************************************************************/
typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
- #define HOST_COALESCE_RESET BIT_0
- #define HOST_COALESCE_ENABLE BIT_1
- #define HOST_COALESCE_ATTN BIT_2
- #define HOST_COALESCE_NOW BIT_3
- #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
- #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
- #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
- #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
- #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
- #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
- #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
+ /* Mode. */
+ T3_32BIT_REGISTER Mode;
+#define HOST_COALESCE_RESET BIT_0
+#define HOST_COALESCE_ENABLE BIT_1
+#define HOST_COALESCE_ATTN BIT_2
+#define HOST_COALESCE_NOW BIT_3
+#define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
+#define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
+#define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
+#define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
+#define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
+#define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
+#define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
- /* Status. */
- T3_32BIT_REGISTER Status;
- #define HOST_COALESCE_ERROR_ATTN BIT_2
+ /* Status. */
+ T3_32BIT_REGISTER Status;
+#define HOST_COALESCE_ERROR_ATTN BIT_2
- /* Receive coalescing ticks. */
- T3_32BIT_REGISTER RxCoalescingTicks;
+ /* Receive coalescing ticks. */
+ T3_32BIT_REGISTER RxCoalescingTicks;
- /* Send coalescing ticks. */
- T3_32BIT_REGISTER TxCoalescingTicks;
+ /* Send coalescing ticks. */
+ T3_32BIT_REGISTER TxCoalescingTicks;
- /* Receive max coalesced frames. */
- T3_32BIT_REGISTER RxMaxCoalescedFrames;
+ /* Receive max coalesced frames. */
+ T3_32BIT_REGISTER RxMaxCoalescedFrames;
- /* Send max coalesced frames. */
- T3_32BIT_REGISTER TxMaxCoalescedFrames;
+ /* Send max coalesced frames. */
+ T3_32BIT_REGISTER TxMaxCoalescedFrames;
- /* Receive coalescing ticks during interrupt. */
- T3_32BIT_REGISTER RxCoalescedTickDuringInt;
+ /* Receive coalescing ticks during interrupt. */
+ T3_32BIT_REGISTER RxCoalescedTickDuringInt;
- /* Send coalescing ticks during interrupt. */
- T3_32BIT_REGISTER TxCoalescedTickDuringInt;
+ /* Send coalescing ticks during interrupt. */
+ T3_32BIT_REGISTER TxCoalescedTickDuringInt;
- /* Receive max coalesced frames during interrupt. */
- T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
+ /* Receive max coalesced frames during interrupt. */
+ T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
- /* Send max coalesced frames during interrupt. */
- T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
+ /* Send max coalesced frames during interrupt. */
+ T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
- /* Statistics tick. */
- T3_32BIT_REGISTER StatsCoalescingTicks;
+ /* Statistics tick. */
+ T3_32BIT_REGISTER StatsCoalescingTicks;
- /* Unused space. */
- LM_UINT8 Unused2[4];
+ /* Unused space. */
+ LM_UINT8 Unused2[4];
- /* Statistics host address. */
- T3_64BIT_REGISTER StatsBlkHostAddr;
+ /* Statistics host address. */
+ T3_64BIT_REGISTER StatsBlkHostAddr;
- /* Status block host address.*/
- T3_64BIT_REGISTER StatusBlkHostAddr;
+ /* Status block host address. */
+ T3_64BIT_REGISTER StatusBlkHostAddr;
- /* Statistics NIC address. */
- T3_32BIT_REGISTER StatsBlkNicAddr;
+ /* Statistics NIC address. */
+ T3_32BIT_REGISTER StatsBlkNicAddr;
- /* Statust block NIC address. */
- T3_32BIT_REGISTER StatusBlkNicAddr;
+ /* Statust block NIC address. */
+ T3_32BIT_REGISTER StatusBlkNicAddr;
- /* Flow attention registers. */
- T3_32BIT_REGISTER FlowAttn;
+ /* Flow attention registers. */
+ T3_32BIT_REGISTER FlowAttn;
- /* Unused space. */
- LM_UINT8 Unused3[4];
+ /* Unused space. */
+ LM_UINT8 Unused3[4];
- T3_32BIT_REGISTER NicJumboRcvBdConIdx;
- T3_32BIT_REGISTER NicStdRcvBdConIdx;
- T3_32BIT_REGISTER NicMiniRcvBdConIdx;
+ T3_32BIT_REGISTER NicJumboRcvBdConIdx;
+ T3_32BIT_REGISTER NicStdRcvBdConIdx;
+ T3_32BIT_REGISTER NicMiniRcvBdConIdx;
- /* Unused space. */
- LM_UINT8 Unused4[36];
+ /* Unused space. */
+ LM_UINT8 Unused4[36];
- T3_32BIT_REGISTER NicRetProdIdx[16];
- T3_32BIT_REGISTER NicSndBdConIdx[16];
+ T3_32BIT_REGISTER NicRetProdIdx[16];
+ T3_32BIT_REGISTER NicSndBdConIdx[16];
- /* Unused space. */
- LM_UINT8 Unused5[768];
+ /* Unused space. */
+ LM_UINT8 Unused5[768];
} T3_HOST_COALESCING, *PT3_HOST_COALESCING;
-
/******************************************************************************/
/* Memory arbiter registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
+ T3_32BIT_REGISTER Mode;
#define T3_MEM_ARBITER_MODE_RESET BIT_0
#define T3_MEM_ARBITER_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER ArbTrapAddrLow;
- T3_32BIT_REGISTER ArbTrapAddrHigh;
+ T3_32BIT_REGISTER ArbTrapAddrLow;
+ T3_32BIT_REGISTER ArbTrapAddrHigh;
- /* Unused space. */
- LM_UINT8 Unused[1008];
+ /* Unused space. */
+ LM_UINT8 Unused[1008];
} T3_MEM_ARBITER, *PT3_MEM_ARBITER;
-
/******************************************************************************/
/* Buffer manager control register. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define BUFMGR_MODE_RESET BIT_0
- #define BUFMGR_MODE_ENABLE BIT_1
- #define BUFMGR_MODE_ATTN_ENABLE BIT_2
- #define BUFMGR_MODE_BM_TEST BIT_3
- #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
-
- T3_32BIT_REGISTER Status;
- #define BUFMGR_STATUS_ERROR BIT_2
- #define BUFMGR_STATUS_MBUF_LOW BIT_4
-
- T3_32BIT_REGISTER MbufPoolAddr;
- T3_32BIT_REGISTER MbufPoolSize;
- T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
- T3_32BIT_REGISTER MbufMacRxLowWaterMark;
- T3_32BIT_REGISTER MbufHighWaterMark;
-
- T3_32BIT_REGISTER RxCpuMbufAllocReq;
- #define BUFMGR_MBUF_ALLOC_BIT BIT_31
- T3_32BIT_REGISTER RxCpuMbufAllocResp;
- T3_32BIT_REGISTER TxCpuMbufAllocReq;
- T3_32BIT_REGISTER TxCpuMbufAllocResp;
-
- T3_32BIT_REGISTER DmaDescPoolAddr;
- T3_32BIT_REGISTER DmaDescPoolSize;
- T3_32BIT_REGISTER DmaLowWaterMark;
- T3_32BIT_REGISTER DmaHighWaterMark;
-
- T3_32BIT_REGISTER RxCpuDmaAllocReq;
- T3_32BIT_REGISTER RxCpuDmaAllocResp;
- T3_32BIT_REGISTER TxCpuDmaAllocReq;
- T3_32BIT_REGISTER TxCpuDmaAllocResp;
-
- T3_32BIT_REGISTER Hwdiag[3];
-
- /* Unused space. */
- LM_UINT8 Unused[936];
-} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
+ T3_32BIT_REGISTER Mode;
+#define BUFMGR_MODE_RESET BIT_0
+#define BUFMGR_MODE_ENABLE BIT_1
+#define BUFMGR_MODE_ATTN_ENABLE BIT_2
+#define BUFMGR_MODE_BM_TEST BIT_3
+#define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
+
+ T3_32BIT_REGISTER Status;
+#define BUFMGR_STATUS_ERROR BIT_2
+#define BUFMGR_STATUS_MBUF_LOW BIT_4
+
+ T3_32BIT_REGISTER MbufPoolAddr;
+ T3_32BIT_REGISTER MbufPoolSize;
+ T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
+ T3_32BIT_REGISTER MbufMacRxLowWaterMark;
+ T3_32BIT_REGISTER MbufHighWaterMark;
+
+ T3_32BIT_REGISTER RxCpuMbufAllocReq;
+#define BUFMGR_MBUF_ALLOC_BIT BIT_31
+ T3_32BIT_REGISTER RxCpuMbufAllocResp;
+ T3_32BIT_REGISTER TxCpuMbufAllocReq;
+ T3_32BIT_REGISTER TxCpuMbufAllocResp;
+
+ T3_32BIT_REGISTER DmaDescPoolAddr;
+ T3_32BIT_REGISTER DmaDescPoolSize;
+ T3_32BIT_REGISTER DmaLowWaterMark;
+ T3_32BIT_REGISTER DmaHighWaterMark;
+
+ T3_32BIT_REGISTER RxCpuDmaAllocReq;
+ T3_32BIT_REGISTER RxCpuDmaAllocResp;
+ T3_32BIT_REGISTER TxCpuDmaAllocReq;
+ T3_32BIT_REGISTER TxCpuDmaAllocResp;
+
+ T3_32BIT_REGISTER Hwdiag[3];
+ /* Unused space. */
+ LM_UINT8 Unused[936];
+} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
/******************************************************************************/
/* Read DMA control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define DMA_READ_MODE_RESET BIT_0
- #define DMA_READ_MODE_ENABLE BIT_1
- #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
- #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
- #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
- #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
- #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
- #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
- #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
- #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
- #define DMA_READ_MODE_SPLIT_ENABLE BIT_11
- #define DMA_READ_MODE_SPLIT_RESET BIT_12
-
- T3_32BIT_REGISTER Status;
- #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
- #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
- #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
- #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
- #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
- #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
- #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
- #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
+ T3_32BIT_REGISTER Mode;
+#define DMA_READ_MODE_RESET BIT_0
+#define DMA_READ_MODE_ENABLE BIT_1
+#define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
+#define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
+#define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
+#define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
+#define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
+#define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
+#define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
+#define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
+#define DMA_READ_MODE_SPLIT_ENABLE BIT_11
+#define DMA_READ_MODE_SPLIT_RESET BIT_12
+
+ T3_32BIT_REGISTER Status;
+#define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
+#define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
+#define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
+#define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
+#define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
+#define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
+#define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
+#define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
+
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
} T3_DMA_READ, *PT3_DMA_READ;
-typedef union T3_CPU
-{
- struct
- {
- T3_32BIT_REGISTER mode;
- #define CPU_MODE_HALT BIT_10
- #define CPU_MODE_RESET BIT_0
- T3_32BIT_REGISTER state;
- T3_32BIT_REGISTER EventMask;
- T3_32BIT_REGISTER reserved1[4];
- T3_32BIT_REGISTER PC;
- T3_32BIT_REGISTER Instruction;
- T3_32BIT_REGISTER SpadUnderflow;
- T3_32BIT_REGISTER WatchdogClear;
- T3_32BIT_REGISTER WatchdogVector;
- T3_32BIT_REGISTER WatchdogSavedPC;
- T3_32BIT_REGISTER HardwareBp;
- T3_32BIT_REGISTER reserved2[3];
- T3_32BIT_REGISTER WatchdogSavedState;
- T3_32BIT_REGISTER LastBrchAddr;
- T3_32BIT_REGISTER SpadUnderflowSet;
- T3_32BIT_REGISTER reserved3[(0x200-0x50)/4];
- T3_32BIT_REGISTER Regs[32];
- T3_32BIT_REGISTER reserved4[(0x400-0x280)/4];
- }reg;
-}T3_CPU, *PT3_CPU;
+typedef union T3_CPU {
+ struct {
+ T3_32BIT_REGISTER mode;
+#define CPU_MODE_HALT BIT_10
+#define CPU_MODE_RESET BIT_0
+ T3_32BIT_REGISTER state;
+ T3_32BIT_REGISTER EventMask;
+ T3_32BIT_REGISTER reserved1[4];
+ T3_32BIT_REGISTER PC;
+ T3_32BIT_REGISTER Instruction;
+ T3_32BIT_REGISTER SpadUnderflow;
+ T3_32BIT_REGISTER WatchdogClear;
+ T3_32BIT_REGISTER WatchdogVector;
+ T3_32BIT_REGISTER WatchdogSavedPC;
+ T3_32BIT_REGISTER HardwareBp;
+ T3_32BIT_REGISTER reserved2[3];
+ T3_32BIT_REGISTER WatchdogSavedState;
+ T3_32BIT_REGISTER LastBrchAddr;
+ T3_32BIT_REGISTER SpadUnderflowSet;
+ T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4];
+ T3_32BIT_REGISTER Regs[32];
+ T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4];
+ } reg;
+} T3_CPU, *PT3_CPU;
/******************************************************************************/
/* Write DMA control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define DMA_WRITE_MODE_RESET BIT_0
- #define DMA_WRITE_MODE_ENABLE BIT_1
- #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
- #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
- #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
- #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
- #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
- #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
- #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
- #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
-
- T3_32BIT_REGISTER Status;
- #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
- #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
- #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
- #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
- #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
- #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
- #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
- #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
-} T3_DMA_WRITE, *PT3_DMA_WRITE;
+ T3_32BIT_REGISTER Mode;
+#define DMA_WRITE_MODE_RESET BIT_0
+#define DMA_WRITE_MODE_ENABLE BIT_1
+#define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
+#define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
+#define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
+#define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
+#define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
+#define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
+#define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
+#define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
+
+ T3_32BIT_REGISTER Status;
+#define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
+#define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
+#define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
+#define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
+#define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
+#define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
+#define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
+#define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
+} T3_DMA_WRITE, *PT3_DMA_WRITE;
/******************************************************************************/
/* Mailbox registers. */
/******************************************************************************/
typedef struct {
- /* Interrupt mailbox registers. */
- T3_64BIT_REGISTER Interrupt[4];
+ /* Interrupt mailbox registers. */
+ T3_64BIT_REGISTER Interrupt[4];
- /* General mailbox registers. */
- T3_64BIT_REGISTER General[8];
+ /* General mailbox registers. */
+ T3_64BIT_REGISTER General[8];
- /* Reload statistics mailbox. */
- T3_64BIT_REGISTER ReloadStat;
+ /* Reload statistics mailbox. */
+ T3_64BIT_REGISTER ReloadStat;
- /* Receive BD ring producer index registers. */
- T3_64BIT_REGISTER RcvStdProdIdx;
- T3_64BIT_REGISTER RcvJumboProdIdx;
- T3_64BIT_REGISTER RcvMiniProdIdx;
+ /* Receive BD ring producer index registers. */
+ T3_64BIT_REGISTER RcvStdProdIdx;
+ T3_64BIT_REGISTER RcvJumboProdIdx;
+ T3_64BIT_REGISTER RcvMiniProdIdx;
- /* Receive return ring consumer index registers. */
- T3_64BIT_REGISTER RcvRetConIdx[16];
+ /* Receive return ring consumer index registers. */
+ T3_64BIT_REGISTER RcvRetConIdx[16];
- /* Send BD ring host producer index registers. */
- T3_64BIT_REGISTER SendHostProdIdx[16];
+ /* Send BD ring host producer index registers. */
+ T3_64BIT_REGISTER SendHostProdIdx[16];
- /* Send BD ring nic producer index registers. */
- T3_64BIT_REGISTER SendNicProdIdx[16];
-}T3_MAILBOX, *PT3_MAILBOX;
+ /* Send BD ring nic producer index registers. */
+ T3_64BIT_REGISTER SendNicProdIdx[16];
+} T3_MAILBOX, *PT3_MAILBOX;
typedef struct {
- T3_MAILBOX Mailbox;
+ T3_MAILBOX Mailbox;
- /* Priority mailbox registers. */
- T3_32BIT_REGISTER HighPriorityEventVector;
- T3_32BIT_REGISTER HighPriorityEventMask;
- T3_32BIT_REGISTER LowPriorityEventVector;
- T3_32BIT_REGISTER LowPriorityEventMask;
+ /* Priority mailbox registers. */
+ T3_32BIT_REGISTER HighPriorityEventVector;
+ T3_32BIT_REGISTER HighPriorityEventMask;
+ T3_32BIT_REGISTER LowPriorityEventVector;
+ T3_32BIT_REGISTER LowPriorityEventMask;
- /* Unused space. */
- LM_UINT8 Unused[496];
+ /* Unused space. */
+ LM_UINT8 Unused[496];
} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
-
/******************************************************************************/
/* Flow through queues. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Reset;
-
- LM_UINT8 Unused[12];
-
- T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
- T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
- T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaHighReadFtqCtrl;
- T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
- T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
- T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
- T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendBdCompFtqCtrl;
- T3_32BIT_REGISTER SendBdCompFtqFullCnt;
- T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
- T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
- T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
- T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
- T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
- T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
- T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SwType1FtqCtrl;
- T3_32BIT_REGISTER SwType1FtqFullCnt;
- T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendDataCompFtqCtrl;
- T3_32BIT_REGISTER SendDataCompFtqFullCnt;
- T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER HostCoalesceFtqCtrl;
- T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
- T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
-
- T3_32BIT_REGISTER MacTxFtqCtrl;
- T3_32BIT_REGISTER MacTxFtqFullCnt;
- T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
-
- T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
- T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
- T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvBdCompFtqCtrl;
- T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
- T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
- T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
- T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvDataCompFtqCtrl;
- T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
- T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SwType2FtqCtrl;
- T3_32BIT_REGISTER SwType2FtqFullCnt;
- T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
-
- /* Unused space. */
- LM_UINT8 Unused2[736];
-} T3_FTQ, *PT3_FTQ;
+ T3_32BIT_REGISTER Reset;
+
+ LM_UINT8 Unused[12];
+
+ T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
+ T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
+ T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaHighReadFtqCtrl;
+ T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
+ T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
+ T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
+ T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SendBdCompFtqCtrl;
+ T3_32BIT_REGISTER SendBdCompFtqFullCnt;
+ T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
+ T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
+ T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
+ T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
+ T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
+ T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
+ T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SwType1FtqCtrl;
+ T3_32BIT_REGISTER SwType1FtqFullCnt;
+ T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SendDataCompFtqCtrl;
+ T3_32BIT_REGISTER SendDataCompFtqFullCnt;
+ T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER HostCoalesceFtqCtrl;
+ T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
+ T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER MacTxFtqCtrl;
+ T3_32BIT_REGISTER MacTxFtqFullCnt;
+ T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
+ T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
+ T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvBdCompFtqCtrl;
+ T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
+ T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
+ T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
+ T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvDataCompFtqCtrl;
+ T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
+ T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SwType2FtqCtrl;
+ T3_32BIT_REGISTER SwType2FtqFullCnt;
+ T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
+ /* Unused space. */
+ LM_UINT8 Unused2[736];
+} T3_FTQ, *PT3_FTQ;
/******************************************************************************/
/* Message signaled interrupt registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
+ T3_32BIT_REGISTER Mode;
#define MSI_MODE_RESET BIT_0
#define MSI_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER MsiFifoAccess;
+ T3_32BIT_REGISTER MsiFifoAccess;
- /* Unused space. */
- LM_UINT8 Unused[1012];
+ /* Unused space. */
+ LM_UINT8 Unused[1012];
} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
-
/******************************************************************************/
/* DMA Completion registes. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define DMA_COMP_MODE_RESET BIT_0
- #define DMA_COMP_MODE_ENABLE BIT_1
+ T3_32BIT_REGISTER Mode;
+#define DMA_COMP_MODE_RESET BIT_0
+#define DMA_COMP_MODE_ENABLE BIT_1
- /* Unused space. */
- LM_UINT8 Unused[1020];
+ /* Unused space. */
+ LM_UINT8 Unused[1020];
} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
-
/******************************************************************************/
/* GRC registers. */
/******************************************************************************/
typedef struct {
- /* Mode control register. */
- T3_32BIT_REGISTER Mode;
- #define GRC_MODE_UPDATE_ON_COALESCING BIT_0
- #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
- #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
- #define GRC_MODE_BYTE_SWAP_DATA BIT_4
- #define GRC_MODE_WORD_SWAP_DATA BIT_5
- #define GRC_MODE_SPLIT_HEADER_MODE BIT_8
- #define GRC_MODE_NO_FRAME_CRACKING BIT_9
- #define GRC_MODE_INCLUDE_CRC BIT_10
- #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
- #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
- #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
- #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
- #define GRC_MODE_HOST_STACK_UP BIT_16
- #define GRC_MODE_HOST_SEND_BDS BIT_17
- #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
- #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
- #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
- #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
- #define GRC_MODE_INT_ON_MAC_ATTN BIT_26
- #define GRC_MODE_INT_ON_DMA_ATTN BIT_27
- #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
- #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
- #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
-
- /* Misc configuration register. */
- T3_32BIT_REGISTER MiscCfg;
- #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
- #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
- #define GRC_MISC_BD_ID_MASK 0x0001e000
- #define GRC_MISC_BD_ID_5700 0x0001e000
- #define GRC_MISC_BD_ID_5701 0x00000000
- #define GRC_MISC_BD_ID_5703 0x00000000
- #define GRC_MISC_BD_ID_5703S 0x00002000
- #define GRC_MISC_BD_ID_5702FE 0x00004000
- #define GRC_MISC_BD_ID_5704 0x00000000
- #define GRC_MISC_BD_ID_5704CIOBE 0x00004000
-
- /* Miscellaneous local control register. */
- T3_32BIT_REGISTER LocalCtrl;
- #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
- #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
- #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
- #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
- #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
- #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
- #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
- #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
- #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
- #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
- #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
- #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
- #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
- #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
- #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
- #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
-
- #define GRC_MISC_MEMSIZE_256K 0
- #define GRC_MISC_MEMSIZE_512K (1 << 18)
- #define GRC_MISC_MEMSIZE_1024K (2 << 18)
- #define GRC_MISC_MEMSIZE_2048K (3 << 18)
- #define GRC_MISC_MEMSIZE_4096K (4 << 18)
- #define GRC_MISC_MEMSIZE_8192K (5 << 18)
- #define GRC_MISC_MEMSIZE_16M (6 << 18)
- #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
-
-
- T3_32BIT_REGISTER Timer;
-
- T3_32BIT_REGISTER RxCpuEvent;
- T3_32BIT_REGISTER RxTimerRef;
- T3_32BIT_REGISTER RxCpuSemaphore;
- T3_32BIT_REGISTER RemoteRxCpuAttn;
-
- T3_32BIT_REGISTER TxCpuEvent;
- T3_32BIT_REGISTER TxTimerRef;
- T3_32BIT_REGISTER TxCpuSemaphore;
- T3_32BIT_REGISTER RemoteTxCpuAttn;
-
- T3_64BIT_REGISTER MemoryPowerUp;
-
- T3_32BIT_REGISTER EepromAddr;
- #define SEEPROM_ADDR_WRITE 0
- #define SEEPROM_ADDR_READ (1 << 31)
- #define SEEPROM_ADDR_RW_MASK 0x80000000
- #define SEEPROM_ADDR_COMPLETE (1 << 30)
- #define SEEPROM_ADDR_FSM_RESET (1 << 29)
- #define SEEPROM_ADDR_DEV_ID(x) (x << 26)
- #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
- #define SEEPROM_ADDR_START (1 << 25)
- #define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
- #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
- #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
-
- #define SEEPROM_CLOCK_PERIOD 60
- #define SEEPROM_CHIP_SIZE (64 * 1024)
-
- T3_32BIT_REGISTER EepromData;
- T3_32BIT_REGISTER EepromCtrl;
-
- T3_32BIT_REGISTER MdiCtrl;
- T3_32BIT_REGISTER SepromDelay;
-
- /* Unused space. */
- LM_UINT8 Unused[948];
-} T3_GRC, *PT3_GRC;
+ /* Mode control register. */
+ T3_32BIT_REGISTER Mode;
+#define GRC_MODE_UPDATE_ON_COALESCING BIT_0
+#define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
+#define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
+#define GRC_MODE_BYTE_SWAP_DATA BIT_4
+#define GRC_MODE_WORD_SWAP_DATA BIT_5
+#define GRC_MODE_SPLIT_HEADER_MODE BIT_8
+#define GRC_MODE_NO_FRAME_CRACKING BIT_9
+#define GRC_MODE_INCLUDE_CRC BIT_10
+#define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
+#define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
+#define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
+#define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
+#define GRC_MODE_HOST_STACK_UP BIT_16
+#define GRC_MODE_HOST_SEND_BDS BIT_17
+#define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
+#define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
+#define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
+#define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
+#define GRC_MODE_INT_ON_MAC_ATTN BIT_26
+#define GRC_MODE_INT_ON_DMA_ATTN BIT_27
+#define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
+#define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
+#define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
+
+ /* Misc configuration register. */
+ T3_32BIT_REGISTER MiscCfg;
+#define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
+#define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
+#define GRC_MISC_BD_ID_MASK 0x0001e000
+#define GRC_MISC_BD_ID_5700 0x0001e000
+#define GRC_MISC_BD_ID_5701 0x00000000
+#define GRC_MISC_BD_ID_5703 0x00000000
+#define GRC_MISC_BD_ID_5703S 0x00002000
+#define GRC_MISC_BD_ID_5702FE 0x00004000
+#define GRC_MISC_BD_ID_5704 0x00000000
+#define GRC_MISC_BD_ID_5704CIOBE 0x00004000
+
+ /* Miscellaneous local control register. */
+ T3_32BIT_REGISTER LocalCtrl;
+#define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
+#define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
+#define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
+#define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
+#define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
+#define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
+#define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
+
+#define GRC_MISC_MEMSIZE_256K 0
+#define GRC_MISC_MEMSIZE_512K (1 << 18)
+#define GRC_MISC_MEMSIZE_1024K (2 << 18)
+#define GRC_MISC_MEMSIZE_2048K (3 << 18)
+#define GRC_MISC_MEMSIZE_4096K (4 << 18)
+#define GRC_MISC_MEMSIZE_8192K (5 << 18)
+#define GRC_MISC_MEMSIZE_16M (6 << 18)
+#define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
+
+ T3_32BIT_REGISTER Timer;
+
+ T3_32BIT_REGISTER RxCpuEvent;
+ T3_32BIT_REGISTER RxTimerRef;
+ T3_32BIT_REGISTER RxCpuSemaphore;
+ T3_32BIT_REGISTER RemoteRxCpuAttn;
+
+ T3_32BIT_REGISTER TxCpuEvent;
+ T3_32BIT_REGISTER TxTimerRef;
+ T3_32BIT_REGISTER TxCpuSemaphore;
+ T3_32BIT_REGISTER RemoteTxCpuAttn;
+
+ T3_64BIT_REGISTER MemoryPowerUp;
+
+ T3_32BIT_REGISTER EepromAddr;
+#define SEEPROM_ADDR_WRITE 0
+#define SEEPROM_ADDR_READ (1 << 31)
+#define SEEPROM_ADDR_RW_MASK 0x80000000
+#define SEEPROM_ADDR_COMPLETE (1 << 30)
+#define SEEPROM_ADDR_FSM_RESET (1 << 29)
+#define SEEPROM_ADDR_DEV_ID(x) (x << 26)
+#define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
+#define SEEPROM_ADDR_START (1 << 25)
+#define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
+#define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
+#define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
+
+#define SEEPROM_CLOCK_PERIOD 60
+#define SEEPROM_CHIP_SIZE (64 * 1024)
+
+ T3_32BIT_REGISTER EepromData;
+ T3_32BIT_REGISTER EepromCtrl;
+
+ T3_32BIT_REGISTER MdiCtrl;
+ T3_32BIT_REGISTER SepromDelay;
+ /* Unused space. */
+ LM_UINT8 Unused[948];
+} T3_GRC, *PT3_GRC;
/******************************************************************************/
/* NVRAM control registers. */
/******************************************************************************/
-typedef struct
-{
- T3_32BIT_REGISTER Cmd;
- #define NVRAM_CMD_RESET BIT_0
- #define NVRAM_CMD_DONE BIT_3
- #define NVRAM_CMD_DO_IT BIT_4
- #define NVRAM_CMD_WR BIT_5
- #define NVRAM_CMD_RD BIT_NONE
- #define NVRAM_CMD_ERASE BIT_6
- #define NVRAM_CMD_FIRST BIT_7
- #define NVRAM_CMD_LAST BIT_8
-
- T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER WriteData;
-
- T3_32BIT_REGISTER Addr;
- #define NVRAM_ADDRESS_MASK 0xffffff
-
- T3_32BIT_REGISTER ReadData;
-
- /* Flash config 1 register. */
- T3_32BIT_REGISTER Config1;
- #define FLASH_INTERFACE_ENABLE BIT_0
- #define FLASH_SSRAM_BUFFERRED_MODE BIT_1
- #define FLASH_PASS_THRU_MODE BIT_2
- #define FLASH_BIT_BANG_MODE BIT_3
- #define FLASH_COMPAT_BYPASS BIT_31
-
- /* Buffered flash (Atmel: AT45DB011B) specific information */
- #define BUFFERED_FLASH_PAGE_POS 9
- #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
- #define BUFFERED_FLASH_PAGE_SIZE 264
- #define BUFFERED_FLASH_PHY_PAGE_SIZE 512
-
- T3_32BIT_REGISTER Config2;
- T3_32BIT_REGISTER Config3;
- T3_32BIT_REGISTER SwArb;
- #define SW_ARB_REQ_SET0 BIT_0
- #define SW_ARB_REQ_SET1 BIT_1
- #define SW_ARB_REQ_SET2 BIT_2
- #define SW_ARB_REQ_SET3 BIT_3
- #define SW_ARB_REQ_CLR0 BIT_4
- #define SW_ARB_REQ_CLR1 BIT_5
- #define SW_ARB_REQ_CLR2 BIT_6
- #define SW_ARB_REQ_CLR3 BIT_7
- #define SW_ARB_GNT0 BIT_8
- #define SW_ARB_GNT1 BIT_9
- #define SW_ARB_GNT2 BIT_10
- #define SW_ARB_GNT3 BIT_11
- #define SW_ARB_REQ0 BIT_12
- #define SW_ARB_REQ1 BIT_13
- #define SW_ARB_REQ2 BIT_14
- #define SW_ARB_REQ3 BIT_15
-
- /* Unused space. */
- LM_UINT8 Unused[988];
-} T3_NVRAM, *PT3_NVRAM;
+typedef struct {
+ T3_32BIT_REGISTER Cmd;
+#define NVRAM_CMD_RESET BIT_0
+#define NVRAM_CMD_DONE BIT_3
+#define NVRAM_CMD_DO_IT BIT_4
+#define NVRAM_CMD_WR BIT_5
+#define NVRAM_CMD_RD BIT_NONE
+#define NVRAM_CMD_ERASE BIT_6
+#define NVRAM_CMD_FIRST BIT_7
+#define NVRAM_CMD_LAST BIT_8
+
+ T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER WriteData;
+
+ T3_32BIT_REGISTER Addr;
+#define NVRAM_ADDRESS_MASK 0xffffff
+
+ T3_32BIT_REGISTER ReadData;
+
+ /* Flash config 1 register. */
+ T3_32BIT_REGISTER Config1;
+#define FLASH_INTERFACE_ENABLE BIT_0
+#define FLASH_SSRAM_BUFFERRED_MODE BIT_1
+#define FLASH_PASS_THRU_MODE BIT_2
+#define FLASH_BIT_BANG_MODE BIT_3
+#define FLASH_COMPAT_BYPASS BIT_31
+
+ /* Buffered flash (Atmel: AT45DB011B) specific information */
+#define BUFFERED_FLASH_PAGE_POS 9
+#define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
+#define BUFFERED_FLASH_PAGE_SIZE 264
+#define BUFFERED_FLASH_PHY_PAGE_SIZE 512
+
+ T3_32BIT_REGISTER Config2;
+ T3_32BIT_REGISTER Config3;
+ T3_32BIT_REGISTER SwArb;
+#define SW_ARB_REQ_SET0 BIT_0
+#define SW_ARB_REQ_SET1 BIT_1
+#define SW_ARB_REQ_SET2 BIT_2
+#define SW_ARB_REQ_SET3 BIT_3
+#define SW_ARB_REQ_CLR0 BIT_4
+#define SW_ARB_REQ_CLR1 BIT_5
+#define SW_ARB_REQ_CLR2 BIT_6
+#define SW_ARB_REQ_CLR3 BIT_7
+#define SW_ARB_GNT0 BIT_8
+#define SW_ARB_GNT1 BIT_9
+#define SW_ARB_GNT2 BIT_10
+#define SW_ARB_GNT3 BIT_11
+#define SW_ARB_REQ0 BIT_12
+#define SW_ARB_REQ1 BIT_13
+#define SW_ARB_REQ2 BIT_14
+#define SW_ARB_REQ3 BIT_15
+ /* Unused space. */
+ LM_UINT8 Unused[988];
+} T3_NVRAM, *PT3_NVRAM;
/******************************************************************************/
/* NIC's internal memory. */
/******************************************************************************/
typedef struct {
- /* Page zero for the internal CPUs. */
- LM_UINT8 PageZero[0x100]; /* 0x0000 */
+ /* Page zero for the internal CPUs. */
+ LM_UINT8 PageZero[0x100]; /* 0x0000 */
- /* Send RCBs. */
- T3_RCB SendRcb[16]; /* 0x0100 */
+ /* Send RCBs. */
+ T3_RCB SendRcb[16]; /* 0x0100 */
- /* Receive Return RCBs. */
- T3_RCB RcvRetRcb[16]; /* 0x0200 */
+ /* Receive Return RCBs. */
+ T3_RCB RcvRetRcb[16]; /* 0x0200 */
- /* Statistics block. */
- T3_STATS_BLOCK StatsBlk; /* 0x0300 */
+ /* Statistics block. */
+ T3_STATS_BLOCK StatsBlk; /* 0x0300 */
- /* Status block. */
- T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
+ /* Status block. */
+ T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
- /* Reserved for software. */
- LM_UINT8 Reserved[1200]; /* 0x0b50 */
+ /* Reserved for software. */
+ LM_UINT8 Reserved[1200]; /* 0x0b50 */
- /* Unmapped region. */
- LM_UINT8 Unmapped[4096]; /* 0x1000 */
+ /* Unmapped region. */
+ LM_UINT8 Unmapped[4096]; /* 0x1000 */
- /* DMA descriptors. */
- LM_UINT8 DmaDesc[8192]; /* 0x2000 */
+ /* DMA descriptors. */
+ LM_UINT8 DmaDesc[8192]; /* 0x2000 */
- /* Buffer descriptors. */
- LM_UINT8 BufferDesc[16384]; /* 0x4000 */
+ /* Buffer descriptors. */
+ LM_UINT8 BufferDesc[16384]; /* 0x4000 */
} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
-
/******************************************************************************/
/* Memory layout. */
/******************************************************************************/
typedef struct {
- /* PCI configuration registers. */
- T3_PCI_CONFIGURATION PciCfg;
-
- /* Unused. */
- LM_UINT8 Unused1[0x100]; /* 0x0100 */
+ /* PCI configuration registers. */
+ T3_PCI_CONFIGURATION PciCfg;
- /* Mailbox . */
- T3_MAILBOX Mailbox; /* 0x0200 */
+ /* Unused. */
+ LM_UINT8 Unused1[0x100]; /* 0x0100 */
- /* MAC control registers. */
- T3_MAC_CONTROL MacCtrl; /* 0x0400 */
+ /* Mailbox . */
+ T3_MAILBOX Mailbox; /* 0x0200 */
- /* Send data initiator control registers. */
- T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
+ /* MAC control registers. */
+ T3_MAC_CONTROL MacCtrl; /* 0x0400 */
- /* Send data completion Control registers. */
- T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
+ /* Send data initiator control registers. */
+ T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
- /* Send BD ring selector. */
- T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
+ /* Send data completion Control registers. */
+ T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
- /* Send BD initiator control registers. */
- T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
+ /* Send BD ring selector. */
+ T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
- /* Send BD completion control registers. */
- T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
+ /* Send BD initiator control registers. */
+ T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
- /* Receive list placement control registers. */
- T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
+ /* Send BD completion control registers. */
+ T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
- /* Receive Data and Receive BD Initiator Control. */
- T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
+ /* Receive list placement control registers. */
+ T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
- /* Receive Data Completion Control */
- T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
+ /* Receive Data and Receive BD Initiator Control. */
+ T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
- /* Receive BD Initiator Control Registers. */
- T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
+ /* Receive Data Completion Control */
+ T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
- /* Receive BD Completion Control Registers. */
- T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
+ /* Receive BD Initiator Control Registers. */
+ T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
- /* Receive list selector control registers. */
- T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
+ /* Receive BD Completion Control Registers. */
+ T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
- /* Mbuf cluster free registers. */
- T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
+ /* Receive list selector control registers. */
+ T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
- /* Host coalescing control registers. */
- T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
+ /* Mbuf cluster free registers. */
+ T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
- /* Memory arbiter control registers. */
- T3_MEM_ARBITER MemArbiter; /* 0x4000 */
+ /* Host coalescing control registers. */
+ T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
- /* Buffer manger control registers. */
- T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
+ /* Memory arbiter control registers. */
+ T3_MEM_ARBITER MemArbiter; /* 0x4000 */
- /* Read DMA control registers. */
- T3_DMA_READ DmaRead; /* 0x4800 */
+ /* Buffer manger control registers. */
+ T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
- /* Write DMA control registers. */
- T3_DMA_WRITE DmaWrite; /* 0x4c00 */
+ /* Read DMA control registers. */
+ T3_DMA_READ DmaRead; /* 0x4800 */
- T3_CPU rxCpu; /* 0x5000 */
- T3_CPU txCpu; /* 0x5400 */
+ /* Write DMA control registers. */
+ T3_DMA_WRITE DmaWrite; /* 0x4c00 */
- /* Mailboxes. */
- T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
+ T3_CPU rxCpu; /* 0x5000 */
+ T3_CPU txCpu; /* 0x5400 */
- /* Flow Through queues. */
- T3_FTQ Ftq; /* 0x5c00 */
+ /* Mailboxes. */
+ T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
- /* Message signaled interrupt registes. */
- T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
+ /* Flow Through queues. */
+ T3_FTQ Ftq; /* 0x5c00 */
- /* DMA completion registers. */
- T3_DMA_COMPLETION DmaComp; /* 0x6400 */
+ /* Message signaled interrupt registes. */
+ T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
- /* GRC registers. */
- T3_GRC Grc; /* 0x6800 */
+ /* DMA completion registers. */
+ T3_DMA_COMPLETION DmaComp; /* 0x6400 */
- /* Unused space. */
- LM_UINT8 Unused2[1024]; /* 0x6c00 */
+ /* GRC registers. */
+ T3_GRC Grc; /* 0x6800 */
- /* NVRAM registers. */
- T3_NVRAM Nvram; /* 0x7000 */
-
- /* Unused space. */
- LM_UINT8 Unused3[3072]; /* 0x7400 */
+ /* Unused space. */
+ LM_UINT8 Unused2[1024]; /* 0x6c00 */
- /* The 32k memory window into the NIC's */
- /* internal memory. The memory window is */
- /* controlled by the Memory Window Base */
- /* Address register. This register is located */
- /* in the PCI configuration space. */
- union { /* 0x8000 */
- T3_FIRST_32K_SRAM First32k;
+ /* NVRAM registers. */
+ T3_NVRAM Nvram; /* 0x7000 */
- /* Use the memory window base address register to determine the */
- /* MBUF segment. */
- LM_UINT32 Mbuf[32768/4];
- LM_UINT32 MemBlock32K[32768/4];
- } uIntMem;
+ /* Unused space. */
+ LM_UINT8 Unused3[3072]; /* 0x7400 */
+
+ /* The 32k memory window into the NIC's */
+ /* internal memory. The memory window is */
+ /* controlled by the Memory Window Base */
+ /* Address register. This register is located */
+ /* in the PCI configuration space. */
+ union { /* 0x8000 */
+ T3_FIRST_32K_SRAM First32k;
+
+ /* Use the memory window base address register to determine the */
+ /* MBUF segment. */
+ LM_UINT32 Mbuf[32768 / 4];
+ LM_UINT32 MemBlock32K[32768 / 4];
+ } uIntMem;
} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
-
/******************************************************************************/
/* Adapter info. */
/******************************************************************************/
-typedef struct
-{
- LM_UINT16 Svid;
- LM_UINT16 Ssid;
- LM_UINT32 PhyId;
- LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
+typedef struct {
+ LM_UINT16 Svid;
+ LM_UINT16 Ssid;
+ LM_UINT32 PhyId;
+ LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
} LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
-
/******************************************************************************/
/* Packet queues. */
/******************************************************************************/
-DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
-DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
-
+DECLARE_QUEUE_TYPE (LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
+DECLARE_QUEUE_TYPE (LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
/******************************************************************************/
/* Tx counters. */
/******************************************************************************/
typedef struct {
- LM_COUNTER TxPacketGoodCnt;
- LM_COUNTER TxBytesGoodCnt;
- LM_COUNTER TxPacketAbortedCnt;
- LM_COUNTER NoSendBdLeftCnt;
- LM_COUNTER NoMapRegisterLeftCnt;
- LM_COUNTER TooManyFragmentsCnt;
- LM_COUNTER NoTxPacketDescCnt;
+ LM_COUNTER TxPacketGoodCnt;
+ LM_COUNTER TxBytesGoodCnt;
+ LM_COUNTER TxPacketAbortedCnt;
+ LM_COUNTER NoSendBdLeftCnt;
+ LM_COUNTER NoMapRegisterLeftCnt;
+ LM_COUNTER TooManyFragmentsCnt;
+ LM_COUNTER NoTxPacketDescCnt;
} LM_TX_COUNTERS, *PLM_TX_COUNTERS;
-
/******************************************************************************/
/* Rx counters. */
/******************************************************************************/
typedef struct {
- LM_COUNTER RxPacketGoodCnt;
- LM_COUNTER RxBytesGoodCnt;
- LM_COUNTER RxPacketErrCnt;
- LM_COUNTER RxErrCrcCnt;
- LM_COUNTER RxErrCollCnt;
- LM_COUNTER RxErrLinkLostCnt;
- LM_COUNTER RxErrPhyDecodeCnt;
- LM_COUNTER RxErrOddNibbleCnt;
- LM_COUNTER RxErrMacAbortCnt;
- LM_COUNTER RxErrShortPacketCnt;
- LM_COUNTER RxErrNoResourceCnt;
- LM_COUNTER RxErrLargePacketCnt;
+ LM_COUNTER RxPacketGoodCnt;
+ LM_COUNTER RxBytesGoodCnt;
+ LM_COUNTER RxPacketErrCnt;
+ LM_COUNTER RxErrCrcCnt;
+ LM_COUNTER RxErrCollCnt;
+ LM_COUNTER RxErrLinkLostCnt;
+ LM_COUNTER RxErrPhyDecodeCnt;
+ LM_COUNTER RxErrOddNibbleCnt;
+ LM_COUNTER RxErrMacAbortCnt;
+ LM_COUNTER RxErrShortPacketCnt;
+ LM_COUNTER RxErrNoResourceCnt;
+ LM_COUNTER RxErrLargePacketCnt;
} LM_RX_COUNTERS, *PLM_RX_COUNTERS;
-
/******************************************************************************/
/* Receive producer rings. */
/******************************************************************************/
typedef enum {
- T3_UNKNOWN_RCV_PROD_RING = 0,
- T3_STD_RCV_PROD_RING = 1,
- T3_MINI_RCV_PROD_RING = 2,
- T3_JUMBO_RCV_PROD_RING = 3
+ T3_UNKNOWN_RCV_PROD_RING = 0,
+ T3_STD_RCV_PROD_RING = 1,
+ T3_MINI_RCV_PROD_RING = 2,
+ T3_JUMBO_RCV_PROD_RING = 3
} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
-
/******************************************************************************/
/* Packet descriptor. */
/******************************************************************************/
#define LM_PACKET_SIGNATURE_RX 0x6b766168
typedef struct _LM_PACKET {
- /* Set in LM. */
- LM_STATUS PacketStatus;
+ /* Set in LM. */
+ LM_STATUS PacketStatus;
- /* Set in LM for Rx, in UM for Tx. */
- LM_UINT32 PacketSize;
+ /* Set in LM for Rx, in UM for Tx. */
+ LM_UINT32 PacketSize;
- LM_UINT16 Flags;
+ LM_UINT16 Flags;
- LM_UINT16 VlanTag;
+ LM_UINT16 VlanTag;
- union {
- /* Send info. */
- struct {
- /* Set up by UM. */
- LM_UINT32 FragCount;
+ union {
+ /* Send info. */
+ struct {
+ /* Set up by UM. */
+ LM_UINT32 FragCount;
- } Tx;
+ } Tx;
- /* Receive info. */
- struct {
- /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
- T3_RCV_PROD_RING RcvProdRing;
+ /* Receive info. */
+ struct {
+ /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
+ T3_RCV_PROD_RING RcvProdRing;
- /* Receive buffer size */
- LM_UINT32 RxBufferSize;
+ /* Receive buffer size */
+ LM_UINT32 RxBufferSize;
- /* Checksum information. */
- LM_UINT16 IpChecksum;
- LM_UINT16 TcpUdpChecksum;
+ /* Checksum information. */
+ LM_UINT16 IpChecksum;
+ LM_UINT16 TcpUdpChecksum;
- } Rx;
- } u;
+ } Rx;
+ } u;
} LM_PACKET;
-
/******************************************************************************/
/* Tigon3 device block. */
/******************************************************************************/
typedef struct _LM_DEVICE_BLOCK {
- int index; /* Device ID */
- /* Memory view. */
- PT3_STD_MEM_MAP pMemView;
+ int index; /* Device ID */
+ /* Memory view. */
+ PT3_STD_MEM_MAP pMemView;
- /* Base address of the block of memory in which the LM_PACKET descriptors */
- /* are allocated from. */
- PLM_VOID pPacketDescBase;
+ /* Base address of the block of memory in which the LM_PACKET descriptors */
+ /* are allocated from. */
+ PLM_VOID pPacketDescBase;
- LM_UINT32 MiscHostCtrl;
- LM_UINT32 GrcLocalCtrl;
- LM_UINT32 DmaReadWriteCtrl;
- LM_UINT32 PciState;
+ LM_UINT32 MiscHostCtrl;
+ LM_UINT32 GrcLocalCtrl;
+ LM_UINT32 DmaReadWriteCtrl;
+ LM_UINT32 PciState;
- /* Rx info */
- LM_UINT32 RxStdDescCnt;
- LM_UINT32 RxStdQueuedCnt;
- LM_UINT32 RxStdProdIdx;
+ /* Rx info */
+ LM_UINT32 RxStdDescCnt;
+ LM_UINT32 RxStdQueuedCnt;
+ LM_UINT32 RxStdProdIdx;
- PT3_RCV_BD pRxStdBdVirt;
- LM_PHYSICAL_ADDRESS RxStdBdPhy;
+ PT3_RCV_BD pRxStdBdVirt;
+ LM_PHYSICAL_ADDRESS RxStdBdPhy;
- LM_UINT32 RxPacketDescCnt;
- LM_RX_PACKET_Q RxPacketFreeQ;
- LM_RX_PACKET_Q RxPacketReceivedQ;
+ LM_UINT32 RxPacketDescCnt;
+ LM_RX_PACKET_Q RxPacketFreeQ;
+ LM_RX_PACKET_Q RxPacketReceivedQ;
- /* Receive info. */
- PT3_RCV_BD pRcvRetBdVirt;
- LM_PHYSICAL_ADDRESS RcvRetBdPhy;
- LM_UINT32 RcvRetConIdx;
+ /* Receive info. */
+ PT3_RCV_BD pRcvRetBdVirt;
+ LM_PHYSICAL_ADDRESS RcvRetBdPhy;
+ LM_UINT32 RcvRetConIdx;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- LM_UINT32 RxJumboDescCnt;
- LM_UINT32 RxJumboBufferSize;
- LM_UINT32 RxJumboQueuedCnt;
+ LM_UINT32 RxJumboDescCnt;
+ LM_UINT32 RxJumboBufferSize;
+ LM_UINT32 RxJumboQueuedCnt;
+
+ LM_UINT32 RxJumboProdIdx;
+
+ PT3_RCV_BD pRxJumboBdVirt;
+ LM_PHYSICAL_ADDRESS RxJumboBdPhy;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- LM_UINT32 RxJumboProdIdx;
+ /* These values are used by the upper module to inform the protocol */
+ /* of the maximum transmit/receive packet size. */
+ LM_UINT32 TxMtu; /* Does not include CRC. */
+ LM_UINT32 RxMtu; /* Does not include CRC. */
- PT3_RCV_BD pRxJumboBdVirt;
- LM_PHYSICAL_ADDRESS RxJumboBdPhy;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
+ /* we may have problems reading any MAC registers in 10mb mode. */
+ LM_UINT32 MacMode;
+ LM_UINT32 RxMode;
+ LM_UINT32 TxMode;
- /* These values are used by the upper module to inform the protocol */
- /* of the maximum transmit/receive packet size. */
- LM_UINT32 TxMtu; /* Does not include CRC. */
- LM_UINT32 RxMtu; /* Does not include CRC. */
+ /* MiMode register. */
+ LM_UINT32 MiMode;
- /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
- /* we may have problems reading any MAC registers in 10mb mode. */
- LM_UINT32 MacMode;
- LM_UINT32 RxMode;
- LM_UINT32 TxMode;
+ /* Host coalesce mode register. */
+ LM_UINT32 CoalesceMode;
- /* MiMode register. */
- LM_UINT32 MiMode;
-
- /* Host coalesce mode register. */
- LM_UINT32 CoalesceMode;
-
- /* Send info. */
- LM_UINT32 TxPacketDescCnt;
-
- /* Tx info. */
- LM_TX_PACKET_Q TxPacketFreeQ;
- LM_TX_PACKET_Q TxPacketActiveQ;
- LM_TX_PACKET_Q TxPacketXmittedQ;
-
- /* Pointers to SendBd. */
- PT3_SND_BD pSendBdVirt;
- LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
-
- /* Send producer and consumer indices. */
- LM_UINT32 SendProdIdx;
- LM_UINT32 SendConIdx;
-
- /* Number of BD left. */
- atomic_t SendBdLeft;
-
- T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
-
- /* Counters. */
- LM_RX_COUNTERS RxCounters;
- LM_TX_COUNTERS TxCounters;
-
- /* Host coalescing parameters. */
- LM_UINT32 RxCoalescingTicks;
- LM_UINT32 TxCoalescingTicks;
- LM_UINT32 RxMaxCoalescedFrames;
- LM_UINT32 TxMaxCoalescedFrames;
- LM_UINT32 StatsCoalescingTicks;
- LM_UINT32 RxCoalescingTicksDuringInt;
- LM_UINT32 TxCoalescingTicksDuringInt;
- LM_UINT32 RxMaxCoalescedFramesDuringInt;
- LM_UINT32 TxMaxCoalescedFramesDuringInt;
-
- /* DMA water marks. */
- LM_UINT32 DmaMbufLowMark;
- LM_UINT32 RxMacMbufLowMark;
- LM_UINT32 MbufHighMark;
-
- /* Status block. */
- PT3_STATUS_BLOCK pStatusBlkVirt;
- LM_PHYSICAL_ADDRESS StatusBlkPhy;
-
- /* Statistics block. */
- PT3_STATS_BLOCK pStatsBlkVirt;
- LM_PHYSICAL_ADDRESS StatsBlkPhy;
-
- /* Current receive mask. */
- LM_UINT32 ReceiveMask;
-
- /* Task offload capabilities. */
- LM_TASK_OFFLOAD TaskOffloadCap;
-
- /* Task offload selected. */
- LM_TASK_OFFLOAD TaskToOffload;
-
- /* Wake up capability. */
- LM_WAKE_UP_MODE WakeUpModeCap;
-
- /* Wake up capability. */
- LM_WAKE_UP_MODE WakeUpMode;
-
- /* Flow control. */
- LM_FLOW_CONTROL FlowControlCap;
- LM_FLOW_CONTROL FlowControl;
-
- /* Enable or disable PCI MWI. */
- LM_UINT32 EnableMWI;
-
- /* Enable 5701 tagged status mode. */
- LM_UINT32 UseTaggedStatus;
-
- /* NIC will not compute the pseudo header checksum. The driver or OS */
- /* must seed the checksum field with the pseudo checksum. */
- LM_UINT32 NoTxPseudoHdrChksum;
-
- /* The receive checksum in the BD does not include the pseudo checksum. */
- /* The OS or the driver must calculate the pseudo checksum and add it to */
- /* the checksum in the BD. */
- LM_UINT32 NoRxPseudoHdrChksum;
-
- /* Current node address. */
- LM_UINT8 NodeAddress[8];
-
- /* The adapter's node address. */
- LM_UINT8 PermanentNodeAddress[8];
-
- /* Adapter info. */
- LM_UINT16 BusNum;
- LM_UINT8 DevNum;
- LM_UINT8 FunctNum;
- LM_UINT16 PciVendorId;
- LM_UINT16 PciDeviceId;
- LM_UINT32 BondId;
- LM_UINT8 Irq;
- LM_UINT8 IntPin;
- LM_UINT8 CacheLineSize;
- LM_UINT8 PciRevId;
+ /* Send info. */
+ LM_UINT32 TxPacketDescCnt;
+
+ /* Tx info. */
+ LM_TX_PACKET_Q TxPacketFreeQ;
+ LM_TX_PACKET_Q TxPacketActiveQ;
+ LM_TX_PACKET_Q TxPacketXmittedQ;
+
+ /* Pointers to SendBd. */
+ PT3_SND_BD pSendBdVirt;
+ LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
+
+ /* Send producer and consumer indices. */
+ LM_UINT32 SendProdIdx;
+ LM_UINT32 SendConIdx;
+
+ /* Number of BD left. */
+ atomic_t SendBdLeft;
+
+ T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
+
+ /* Counters. */
+ LM_RX_COUNTERS RxCounters;
+ LM_TX_COUNTERS TxCounters;
+
+ /* Host coalescing parameters. */
+ LM_UINT32 RxCoalescingTicks;
+ LM_UINT32 TxCoalescingTicks;
+ LM_UINT32 RxMaxCoalescedFrames;
+ LM_UINT32 TxMaxCoalescedFrames;
+ LM_UINT32 StatsCoalescingTicks;
+ LM_UINT32 RxCoalescingTicksDuringInt;
+ LM_UINT32 TxCoalescingTicksDuringInt;
+ LM_UINT32 RxMaxCoalescedFramesDuringInt;
+ LM_UINT32 TxMaxCoalescedFramesDuringInt;
+
+ /* DMA water marks. */
+ LM_UINT32 DmaMbufLowMark;
+ LM_UINT32 RxMacMbufLowMark;
+ LM_UINT32 MbufHighMark;
+
+ /* Status block. */
+ PT3_STATUS_BLOCK pStatusBlkVirt;
+ LM_PHYSICAL_ADDRESS StatusBlkPhy;
+
+ /* Statistics block. */
+ PT3_STATS_BLOCK pStatsBlkVirt;
+ LM_PHYSICAL_ADDRESS StatsBlkPhy;
+
+ /* Current receive mask. */
+ LM_UINT32 ReceiveMask;
+
+ /* Task offload capabilities. */
+ LM_TASK_OFFLOAD TaskOffloadCap;
+
+ /* Task offload selected. */
+ LM_TASK_OFFLOAD TaskToOffload;
+
+ /* Wake up capability. */
+ LM_WAKE_UP_MODE WakeUpModeCap;
+
+ /* Wake up capability. */
+ LM_WAKE_UP_MODE WakeUpMode;
+
+ /* Flow control. */
+ LM_FLOW_CONTROL FlowControlCap;
+ LM_FLOW_CONTROL FlowControl;
+
+ /* Enable or disable PCI MWI. */
+ LM_UINT32 EnableMWI;
+
+ /* Enable 5701 tagged status mode. */
+ LM_UINT32 UseTaggedStatus;
+
+ /* NIC will not compute the pseudo header checksum. The driver or OS */
+ /* must seed the checksum field with the pseudo checksum. */
+ LM_UINT32 NoTxPseudoHdrChksum;
+
+ /* The receive checksum in the BD does not include the pseudo checksum. */
+ /* The OS or the driver must calculate the pseudo checksum and add it to */
+ /* the checksum in the BD. */
+ LM_UINT32 NoRxPseudoHdrChksum;
+
+ /* Current node address. */
+ LM_UINT8 NodeAddress[8];
+
+ /* The adapter's node address. */
+ LM_UINT8 PermanentNodeAddress[8];
+
+ /* Adapter info. */
+ LM_UINT16 BusNum;
+ LM_UINT8 DevNum;
+ LM_UINT8 FunctNum;
+ LM_UINT16 PciVendorId;
+ LM_UINT16 PciDeviceId;
+ LM_UINT32 BondId;
+ LM_UINT8 Irq;
+ LM_UINT8 IntPin;
+ LM_UINT8 CacheLineSize;
+ LM_UINT8 PciRevId;
#if PCIX_TARGET_WORKAROUND
LM_UINT32 EnablePciXFix;
#endif
- LM_UINT32 UndiFix; /* new, jimmy */
- LM_UINT32 PciCommandStatusWords;
- LM_UINT32 ChipRevId;
- LM_UINT16 SubsystemVendorId;
- LM_UINT16 SubsystemId;
-#if 0 /* Jimmy, deleted in new driver */
- LM_UINT32 MemBaseLow;
- LM_UINT32 MemBaseHigh;
- LM_UINT32 MemBaseSize;
+ LM_UINT32 UndiFix; /* new, jimmy */
+ LM_UINT32 PciCommandStatusWords;
+ LM_UINT32 ChipRevId;
+ LM_UINT16 SubsystemVendorId;
+ LM_UINT16 SubsystemId;
+#if 0 /* Jimmy, deleted in new driver */
+ LM_UINT32 MemBaseLow;
+ LM_UINT32 MemBaseHigh;
+ LM_UINT32 MemBaseSize;
#endif
- PLM_UINT8 pMappedMemBase;
-
- /* Saved PCI configuration registers for restoring after a reset. */
- LM_UINT32 SavedCacheLineReg;
+ PLM_UINT8 pMappedMemBase;
- /* Phy info. */
- LM_UINT32 PhyAddr;
- LM_UINT32 PhyId;
+ /* Saved PCI configuration registers for restoring after a reset. */
+ LM_UINT32 SavedCacheLineReg;
- /* Requested phy settings. */
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
+ /* Phy info. */
+ LM_UINT32 PhyAddr;
+ LM_UINT32 PhyId;
- /* Disable auto-negotiation. */
- LM_UINT32 DisableAutoNeg;
+ /* Requested phy settings. */
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
- /* Ways for the MAC to get link change interrupt. */
- LM_UINT32 PhyIntMode;
- #define T3_PHY_INT_MODE_AUTO 0
- #define T3_PHY_INT_MODE_MI_INTERRUPT 1
- #define T3_PHY_INT_MODE_LINK_READY 2
- #define T3_PHY_INT_MODE_AUTO_POLLING 3
+ /* Disable auto-negotiation. */
+ LM_UINT32 DisableAutoNeg;
- /* Ways to determine link change status. */
- LM_UINT32 LinkChngMode;
- #define T3_LINK_CHNG_MODE_AUTO 0
- #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
- #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
+ /* Ways for the MAC to get link change interrupt. */
+ LM_UINT32 PhyIntMode;
+#define T3_PHY_INT_MODE_AUTO 0
+#define T3_PHY_INT_MODE_MI_INTERRUPT 1
+#define T3_PHY_INT_MODE_LINK_READY 2
+#define T3_PHY_INT_MODE_AUTO_POLLING 3
+ /* Ways to determine link change status. */
+ LM_UINT32 LinkChngMode;
+#define T3_LINK_CHNG_MODE_AUTO 0
+#define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
+#define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
- /* LED mode. */
- LM_UINT32 LedMode;
+ /* LED mode. */
+ LM_UINT32 LedMode;
- #define LED_MODE_AUTO 0
+#define LED_MODE_AUTO 0
- /* 5700/01 LED mode. */
- #define LED_MODE_THREE_LINK 1
- #define LED_MODE_LINK10 2
+ /* 5700/01 LED mode. */
+#define LED_MODE_THREE_LINK 1
+#define LED_MODE_LINK10 2
- /* 5703/02/04 LED mode. */
- #define LED_MODE_OPEN_DRAIN 1
- #define LED_MODE_OUTPUT 2
+ /* 5703/02/04 LED mode. */
+#define LED_MODE_OPEN_DRAIN 1
+#define LED_MODE_OUTPUT 2
- /* WOL Speed */
- LM_UINT32 WolSpeed;
- #define WOL_SPEED_10MB 1
- #define WOL_SPEED_100MB 2
+ /* WOL Speed */
+ LM_UINT32 WolSpeed;
+#define WOL_SPEED_10MB 1
+#define WOL_SPEED_100MB 2
- /* Reset the PHY on initialization. */
- LM_UINT32 ResetPhyOnInit;
+ /* Reset the PHY on initialization. */
+ LM_UINT32 ResetPhyOnInit;
- LM_UINT32 RestoreOnWakeUp;
- LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
- LM_UINT32 WakeUpDisableAutoNeg;
+ LM_UINT32 RestoreOnWakeUp;
+ LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
+ LM_UINT32 WakeUpDisableAutoNeg;
- /* Current phy settings. */
- LM_MEDIA_TYPE MediaType;
- LM_LINE_SPEED LineSpeed;
- LM_LINE_SPEED OldLineSpeed;
- LM_DUPLEX_MODE DuplexMode;
- LM_STATUS LinkStatus;
- LM_UINT32 advertising; /* Jimmy, new! */
- LM_UINT32 advertising1000; /* Jimmy, new! */
+ /* Current phy settings. */
+ LM_MEDIA_TYPE MediaType;
+ LM_LINE_SPEED LineSpeed;
+ LM_LINE_SPEED OldLineSpeed;
+ LM_DUPLEX_MODE DuplexMode;
+ LM_STATUS LinkStatus;
+ LM_UINT32 advertising; /* Jimmy, new! */
+ LM_UINT32 advertising1000; /* Jimmy, new! */
- /* Multicast address list. */
- LM_UINT32 McEntryCount;
- LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
+ /* Multicast address list. */
+ LM_UINT32 McEntryCount;
+ LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
- /* Use NIC or Host based send BD. */
- LM_UINT32 NicSendBd;
+ /* Use NIC or Host based send BD. */
+ LM_UINT32 NicSendBd;
- /* Athlon fix. */
- LM_UINT32 DelayPciGrant;
+ /* Athlon fix. */
+ LM_UINT32 DelayPciGrant;
- /* Enable OneDmaAtOnce */
- LM_UINT32 OneDmaAtOnce;
+ /* Enable OneDmaAtOnce */
+ LM_UINT32 OneDmaAtOnce;
- /* Split Mode flags, Jimmy new */
- LM_UINT32 SplitModeEnable;
- LM_UINT32 SplitModeMaxReq;
+ /* Split Mode flags, Jimmy new */
+ LM_UINT32 SplitModeEnable;
+ LM_UINT32 SplitModeMaxReq;
- /* Init flag. */
- LM_BOOL InitDone;
+ /* Init flag. */
+ LM_BOOL InitDone;
- /* Shutdown flag. Set by the upper module. */
- LM_BOOL ShuttingDown;
+ /* Shutdown flag. Set by the upper module. */
+ LM_BOOL ShuttingDown;
- /* Flag to determine whether to call LM_QueueRxPackets or not in */
- /* LM_ResetAdapter routine. */
- LM_BOOL QueueRxPackets;
+ /* Flag to determine whether to call LM_QueueRxPackets or not in */
+ /* LM_ResetAdapter routine. */
+ LM_BOOL QueueRxPackets;
- LM_UINT32 MbufBase;
- LM_UINT32 MbufSize;
+ LM_UINT32 MbufBase;
+ LM_UINT32 MbufSize;
- /* TRUE if we have a SERDES PHY. */
- LM_UINT32 EnableTbi;
+ /* TRUE if we have a SERDES PHY. */
+ LM_UINT32 EnableTbi;
- /* Ethernet@WireSpeed. */
- LM_UINT32 EnableWireSpeed;
+ /* Ethernet@WireSpeed. */
+ LM_UINT32 EnableWireSpeed;
- LM_UINT32 EepromWp;
+ LM_UINT32 EepromWp;
#if INCLUDE_TBI_SUPPORT
- /* Autoneg state info. */
- AN_STATE_INFO AnInfo;
- LM_UINT32 PollTbiLink;
- LM_UINT32 IgnoreTbiLinkChange;
+ /* Autoneg state info. */
+ AN_STATE_INFO AnInfo;
+ LM_UINT32 PollTbiLink;
+ LM_UINT32 IgnoreTbiLinkChange;
#endif
- char PartNo[24];
- char BootCodeVer[16];
- char BusSpeedStr[24]; /* Jimmy, new! */
- LM_UINT32 PhyCrcCount;
+ char PartNo[24];
+ char BootCodeVer[16];
+ char BusSpeedStr[24]; /* Jimmy, new! */
+ LM_UINT32 PhyCrcCount;
} LM_DEVICE_BLOCK;
-
#define T3_REG_CPU_VIEW 0xc0000000
#define T3_BLOCK_DMA_RD (1 << 0)
#define TX_CPU_EVT_SW12 30
#define TX_CPU_EVT_SW13 31
-
/* TX-CPU event */
#define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0)
#define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1)
#define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12)
#define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13)
-
#define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
TX_CPU_EVENT_SDI | \
TX_CPU_EVENT_SDC)
-
#define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29)
#define T3_FTQ_TYPE1_PASS_BIT (1 << 30)
#define T3_FTQ_TYPE1_SKIP_BIT (1 << 31)
#define T3_QID_RX_DATA_COMP 16
#define T3_QID_SW_TYPE2 17
-LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu,
- LM_UINT32 StartCpu);
+LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
+ PT3_FWIMG_INFO pFwImg,
+ LM_UINT32 LoadCpu, LM_UINT32 StartCpu);
/******************************************************************************/
/* NIC register read/write macros. */
/******************************************************************************/
-#if 0 /* Jimmy */
+#if 0 /* Jimmy */
/* MAC register access. */
-LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
- LM_UINT32 Value32);
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
+LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
+ LM_UINT32 Value32);
/* MAC memory access. */
-LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
- LM_UINT32 Value32);
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
+LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
+ LM_UINT32 Value32);
#if PCIX_TARGET_WORKAROUND
#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
LM_MemWrInd(pDevice, Offset, Value32)
-#else /* normal target access path below */
+#else /* normal target access path below */
/* Register access. */
#define REG_RD(pDevice, OffsetName) \
#define REG_WR_OFFSET(pDevice, Offset, Value32) \
writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
-
/* There could be problem access the memory window directly. For now, */
/* we have to go through the PCI configuration register. */
#define MEM_RD(pDevice, AddrName) \
#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
LM_MemWrInd(pDevice, Offset, Value32)
-#endif /* PCIX_TARGET_WORKAROUND */
+#endif /* PCIX_TARGET_WORKAROUND */
-#endif /* Jimmy, merging */
+#endif /* Jimmy, merging */
/* Jimmy...rest of file is new stuff! */
/******************************************************************************/
/******************************************************************************/
/* MAC register access. */
-LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
- LM_UINT32 Value32);
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
+LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
+ LM_UINT32 Value32);
/* MAC memory access. */
-LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
- LM_UINT32 Value32);
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
+LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
+ LM_UINT32 Value32);
#define MB_REG_WR(pDevice, OffsetName, Value32) \
((pDevice)->UndiFix) ? \
#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
LM_MemWrInd(pDevice, Offset, Value32)
-#endif /* TIGON3_H */
+#endif /* TIGON3_H */
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
-#if defined(CONFIG_TSEC1)
-#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
- {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
-#else
- {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
-#endif
+#ifdef CONFIG_TSEC1
+ {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
#else
{0, 0, 0},
#endif
-#if defined(CONFIG_TSEC2)
-#if defined(CONFIG_MPC8641HPCN)
- {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
-#else
- {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
-#endif
+#ifdef CONFIG_TSEC2
+ {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
#else
{0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
- {FEC_PHY_ADDR, 0, FEC_PHYIDX},
+ {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
#else
-#if defined(CONFIG_TSEC3)
- {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
+#ifdef CONFIG_TSEC3
+ {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
#else
{0, 0, 0},
#endif
-#if defined(CONFIG_TSEC4)
- {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#ifdef CONFIG_TSEC4
+ {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
#else
{0, 0, 0},
-#endif
-#endif
+#endif /* CONFIG_TSEC4 */
+#endif /* CONFIG_MPC85XX_FEC */
};
#define MAXCONTROLLERS (4)
unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
+#ifdef CONFIG_MCAST_TFTP
+static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
+#endif
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
+#ifdef CONFIG_MCAST_TFTP
+ dev->mcast = tsec_mcast_addr;
+#endif
/* Tell u-boot to get the addr from the env */
for (i = 0; i < 6; i++)
uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
{
/*
- * Wait if PHY is capable of autonegotiation and autonegotiation
- * is not complete.
+ * Wait if the link is up, and autonegotiation is in progress
+ * (ie - we're capable and it's not done)
*/
mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & PHY_BMSR_AUTN_ABLE)
+ if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
&& !(mii_reg & PHY_BMSR_AUTN_COMP)) {
int i = 0;
puts("Waiting for PHY auto negotiation to complete");
- while (!((mii_reg & PHY_BMSR_AUTN_COMP)
- && (mii_reg & MIIM_STATUS_LINK))) {
+ while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
/*
* Timeout reached ?
*/
priv->link = 1;
udelay(500000); /* another 500 ms (results in faster booting) */
} else {
- priv->link = 1;
+ if (mii_reg & MIIM_STATUS_LINK)
+ priv->link = 1;
+ else
+ priv->link = 0;
}
return 0;
mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
- if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
- (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
+ if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
+ !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
int i = 0;
puts("Waiting for PHY realtime link");
- while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
- (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
- /*
- * Timeout reached ?
- */
+ while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
+ /* Timeout reached ? */
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
priv->link = 0;
}
puts(" done\n");
udelay(500000); /* another 500 ms (results in faster booting) */
+ } else {
+ if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
+ priv->link = 1;
+ else
+ priv->link = 0;
}
if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
case MIIM_LXT971_SR2_100HDX:
priv->speed = 100;
priv->duplexity = 0;
+ break;
default:
priv->speed = 100;
priv->duplexity = 1;
- break;
}
} else {
priv->speed = 0;
#endif
+#ifdef CONFIG_MCAST_TFTP
+
+/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
+
+/* Set the appropriate hash bit for the given addr */
+
+/* The algorithm works like so:
+ * 1) Take the Destination Address (ie the multicast address), and
+ * do a CRC on it (little endian), and reverse the bits of the
+ * result.
+ * 2) Use the 8 most significant bits as a hash into a 256-entry
+ * table. The table is controlled through 8 32-bit registers:
+ * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
+ * gaddr7. This means that the 3 most significant bits in the
+ * hash index which gaddr register to use, and the 5 other bits
+ * indicate which bit (assuming an IBM numbering scheme, which
+ * for PowerPC (tm) is usually the case) in the tregister holds
+ * the entry. */
+static int
+tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
+{
+ struct tsec_private *priv = privlist[1];
+ volatile tsec_t *regs = priv->regs;
+ volatile u32 *reg_array, value;
+ u8 result, whichbit, whichreg;
+
+ result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
+ whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
+ whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
+ value = (1 << (31-whichbit));
+
+ reg_array = &(regs->hash.gaddr0);
+
+ if (set) {
+ reg_array[whichreg] |= value;
+ } else {
+ reg_array[whichreg] &= ~value;
+ }
+ return 0;
+}
+#endif /* Multicast TFTP ? */
+
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_PCI_OHCI
static struct pci_device_id ohci_pci_ids[] = {
{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
+ {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
/* Please add supported PCI OHCI controller ids here */
{0, 0}
};
/* device which was disconnected */
struct usb_device *devgone;
-
-
/*-------------------------------------------------------------------------*/
/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
static u32 roothub_portstatus (struct ohci *hc, int i)
{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
/* forward declaration */
static int hc_interrupt (void);
static void
ep_print_int_eds (controller, "hcca");
dbg ("hcca frame #%04x", controller->hcca->frame_no);
ohci_dump_roothub (controller, 1);
-}
-
#endif /* DEBUG */
ed_p = &(((ed_t *)ed_p)->hwNextED))
inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
ed->hwNextED = *ed_p;
- *ed_p = m32_swap(ed);
+ *ed_p = m32_swap((unsigned long)ed);
}
break;
}
/* ED might have been unlinked through another path */
while (*ed_p != 0) {
- if (((struct ed *)m32_swap (ed_p)) == ed) {
+ if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {
*ed_p = ed->hwNextED;
break;
}
- ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED);
+ ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);
}
}
}
-
/* unlink an ed from one of the HC chains.
* just the link to the ed is unlinked.
* the link from the ed still points to another operational ed or 0
return 0;
}
-
/*-------------------------------------------------------------------------*/
/* add/reinit an endpoint; this should be done once at the
* Done List handling functions
*-------------------------------------------------------------------------*/
-
/* calculate the transfer length and update the urb */
static void dl_transfer_length(td_t * td)
tdBE = m32_swap (td->hwBE);
tdCBP = m32_swap (td->hwCBP);
-
if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
0x01 /* __u8 bNumConfigurations; */
};
-
/* Configuration descriptor */
static __u8 root_hub_config_des[] =
{
/* Hub class-specific descriptor is constructed dynamically */
-
/*-------------------------------------------------------------------------*/
#define OK(x) len = (x); break
#include "usbdcore_mpc8xx.h"
#include "usbdcore_ep0.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define ERR(fmt, args...)\
serial_printf("ERROR : [%s] %s:%d: "fmt,\
__FILE__,__FUNCTION__,__LINE__, ##args)
#elif defined(CFG_USB_BRGCLK)
/* This has been tested with brgclk == 50MHz */
- DECLARE_GLOBAL_DATA_PTR;
int divisor = 0;
if (gd->cpu_clk < 48000000L) {
LIB = $(obj)libdtt.a
-COBJS = lm75.o ds1621.o adm1021.o lm81.o
+COBJS = lm75.o ds1621.o adm1021.o lm81.o ds1775.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DTT_DS1775
+#include <i2c.h>
+#include <dtt.h>
+
+#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */
+
+int dtt_read(int sensor, int reg)
+{
+ int dlen;
+ uchar data[2];
+
+ /*
+ * Calculate sensor address and command
+ */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */
+
+ /*
+ * Prepare to handle 2 byte result
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST))
+ dlen = 2;
+ else
+ dlen = 1;
+
+ /*
+ * Now try to read the register
+ */
+ if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ /*
+ * Handle 2 byte result
+ */
+ if (dlen == 2)
+ return ((int)((short)data[1] + (((short)data[0]) << 8)));
+
+ return (int) data[0];
+}
+
+
+int dtt_write(int sensor, int reg, int val)
+{
+ int dlen;
+ uchar data[2];
+
+ /*
+ * Calculate sensor address and register
+ */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
+
+ /*
+ * Handle various data sizes
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) {
+ dlen = 2;
+ data[0] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[1] = (char)(val & 0xff);
+ } else {
+ dlen = 1;
+ data[0] = (char)(val & 0xff);
+ }
+
+ /*
+ * Write value to device
+ */
+ if (i2c_write(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ return 0;
+}
+
+
+static int _dtt_init(int sensor)
+{
+ int val;
+
+ /*
+ * Setup High Temp
+ */
+ val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_OS, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ /*
+ * Setup Low Temp - hysteresis
+ */
+ val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ /*
+ * Setup configuraton register
+ *
+ * Fault Tolerance limits 4, Thermometer resolution bits is 9,
+ * Polarity = Active Low,continuous conversion mode, Thermostat
+ * mode is interrupt mode
+ */
+ val = 0xa;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ return 0;
+}
+
+
+int dtt_init (void)
+{
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
+
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("DTT%d: FAILED\n", i+1);
+ else
+ printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
+ }
+
+ return (0);
+}
+
+
+int dtt_get_temp(int sensor)
+{
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+}
+
+
+#endif /* CONFIG_DTT_DS1775 */
typedef volatile unsigned int AT91_REG; /* Hardware register definition */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
+/*****************************************************************************/
typedef struct _AT91S_TC
{
AT91_REG TC_CCR; /* Channel Control Register */
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
-#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Usart */
-/******************************************************************************/
+#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/
+#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Usart */
+/*****************************************************************************/
typedef struct _AT91S_USART
{
AT91_REG US_CR; /* Control Register */
AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
+/*****************************************************************************/
typedef struct _AT91S_CKGR
{
AT91_REG CKGR_MOR; /* Main Oscillator Register */
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
+/*****************************************************************************/
typedef struct _AT91S_PIO
{
AT91_REG PIO_PER; /* PIO Enable Register */
} AT91S_PIO, *AT91PS_PIO;
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Debug Unit */
+/*****************************************************************************/
typedef struct _AT91S_DBGU
{
AT91_REG DBGU_CR; /* Control Register */
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
+/*****************************************************************************/
typedef struct _AT91S_SMC2
{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Power Management Controler */
+/*****************************************************************************/
typedef struct _AT91S_PMC
{
AT91_REG PMC_SCER; /* System Clock Enable Register */
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Ethernet MAC */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Ethernet MAC */
+/*****************************************************************************/
typedef struct _AT91S_EMAC
{
AT91_REG EMAC_CTL; /* Network Control Register */
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
-/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
+/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
+/*****************************************************************************/
typedef struct _AT91S_SPI
{
AT91_REG SPI_CR; /* Control Register */
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
+/*****************************************************************************/
typedef struct _AT91S_PDC
{
AT91_REG PDC_RPR; /* Receive Pointer Register */
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
+#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
+#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
+#if 0
+#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */
+#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */
+#endif
+
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */
+#if 0
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */
+#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */
+#endif
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
+#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
+
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
-#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
-#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
-#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
-#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
-#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
-#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
-#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
- ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \
+ ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
#define MACH_TYPE_LN2410SBC 725
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
+#define MACH_TYPE_AT91SAM9261EK 848
#define MACH_TYPE_PDNB3 1002
+#define MACH_TYPE_AT91SAM9260EK 1099
+#define MACH_TYPE_AT91RM9200DF 1119
+#define MACH_TYPE_AT91SAM9263EK 1202
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# define machine_is_mp2usb() (0)
#endif
+#ifdef CONFIG_MACH_AT91SAM9261EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9261EK
+# endif
+# define machine_is_at91sam9261ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9261EK)
+#else
+# define machine_is_at91sam9261ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9260EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9260EK
+# endif
+# define machine_is_at91sam9260ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9260EK)
+#else
+# define machine_is_at91sam9260ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263EK
+# endif
+# define machine_is_at91sam9263ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9263EK)
+#else
+# define machine_is_at91sam9263ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200DF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91RM9200DF
+# endif
+# define machine_is_at91rm9200df() \
+ (machine_arch_type == MACH_TYPE_AT91RM9200DF)
+#else
+# define machine_is_at91rm9200df() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263EK
+# endif
+# define machine_is_at91sam9263ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9263EK)
+#else
+# define machine_is_at91sam9263ek() (0)
+#endif
+
/*
* These have not yet been registered
*/
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+extern __inline__ int ffs(int x)
+{
+ int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+#define __ffs(x) (ffs(x) - 1)
+
+#endif /* __KERNEL__ */
+
#endif /* _M68K_BITOPS_H */
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
+
+#ifdef __GNUC__
+#define __sw16(x) \
+ ((__u16)( \
+ (((__u16)(x) & (__u16)0x00ffU) << 8) | \
+ (((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define __sw32(x) \
+ ((__u32)( \
+ (((__u32)(x)) << 24) | \
+ (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
+ (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
+ (((__u32)(x)) >> 24) ))
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+ unsigned result = *addr;
+ return __sw16(result);
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr,
+ const unsigned val)
+{
+ *addr = __sw16(val);
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+ unsigned result = *addr;
+ return __sw32(result);
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+ *addr = __sw32(val);
+}
+
+#if 0
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+ inline asm correctly, and can cause file corruption. Until I hear that
+ it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+# define __arch_swab16(x) ld_le16(&x)
+# define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__ ((const))
+__u16 ___arch__swab16(__u16 value)
+{
+ return __sw16(value);
+}
+
+static __inline__ __attribute__ ((const))
+__u32 ___arch__swab32(__u32 value)
+{
+ return __sw32(value);
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif /* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+#endif
+
+#endif /* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
#include <linux/byteorder/big_endian.h>
-#endif /* _M68K_BYTEORDER_H */
+#endif /* _M68K_BYTEORDER_H */
--- /dev/null
+#ifndef _PPC_ERRNO_H
+#define _PPC_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+#define EDEADLOCK 58 /* File locking deadlock error */
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS 512
+#define ERESTARTNOINTR 513
+#define ERESTARTNOHAND 514 /* restart if no handler.. */
+#define ENOIOCTLCMD 515 /* No ioctl command */
+
+#define _LAST_ERRNO 515
+
+#endif
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
+ * Add FEC Structure and definitions
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
/* Buffer descriptors used FEC.
*/
typedef struct cpm_buf_desc {
- ushort cbd_sc; /* Status and Control */
- ushort cbd_datlen; /* Data length in buffer */
- uint cbd_bufaddr; /* Buffer address in host memory */
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_RO1 ((ushort)0x4000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080)
+#define BD_ENET_RX_MC ((ushort)0x0040)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_TR BD_ENET_RX_CL
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_ABC BD_ENET_TX_DEF
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
-#endif /* fec_h */
+#ifdef CONFIG_MCFFEC
+/*********************************************************************
+*
+* Fast Ethernet Controller (FEC)
+*
+*********************************************************************/
+/* FEC private information */
+struct fec_info_s {
+ int index;
+ u32 iobase;
+ u32 pinmux;
+ u32 miibase;
+ int phy_addr;
+ int dup_spd;
+ char *phy_name;
+ int phyname_init;
+ cbd_t *rxbd; /* Rx BD */
+ cbd_t *txbd; /* Tx BD */
+ uint rxIdx;
+ uint txIdx;
+ char *txbuf;
+ int initialized;
+};
+
+/* Register read/write struct */
+typedef struct fec {
+#ifdef CONFIG_M5272
+ u32 ecr; /* 0x00 */
+ u32 eir; /* 0x04 */
+ u32 eimr; /* 0x08 */
+ u32 ivsr; /* 0x0C */
+ u32 rdar; /* 0x10 */
+ u32 tdar; /* 0x14 */
+ u8 resv1[0x28]; /* 0x18 */
+ u32 mmfr; /* 0x40 */
+ u32 mscr; /* 0x44 */
+ u8 resv2[0x44]; /* 0x48 */
+ u32 frbr; /* 0x8C */
+ u32 frsr; /* 0x90 */
+ u8 resv3[0x10]; /* 0x94 */
+ u32 tfwr; /* 0xA4 */
+ u32 res4; /* 0xA8 */
+ u32 tfsr; /* 0xAC */
+ u8 resv4[0x50]; /* 0xB0 */
+ u32 opd; /* 0x100 - dummy */
+ u32 rcr; /* 0x104 */
+ u32 mibc; /* 0x108 */
+ u8 resv5[0x38]; /* 0x10C */
+ u32 tcr; /* 0x144 */
+ u8 resv6[0x270]; /* 0x148 */
+ u32 iaur; /* 0x3B8 - dummy */
+ u32 ialr; /* 0x3BC - dummy */
+ u32 palr; /* 0x3C0 */
+ u32 paur; /* 0x3C4 */
+ u32 gaur; /* 0x3C8 */
+ u32 galr; /* 0x3CC */
+ u32 erdsr; /* 0x3D0 */
+ u32 etdsr; /* 0x3D4 */
+ u32 emrbr; /* 0x3D8 */
+ u8 resv12[0x74]; /* 0x18C */
+#else
+ u8 resv0[0x4];
+ u32 eir;
+ u32 eimr;
+ u8 resv1[0x4];
+ u32 rdar;
+ u32 tdar;
+ u8 resv2[0xC];
+ u32 ecr;
+ u8 resv3[0x18];
+ u32 mmfr;
+ u32 mscr;
+ u8 resv4[0x1C];
+ u32 mibc;
+ u8 resv5[0x1C];
+ u32 rcr;
+ u8 resv6[0x3C];
+ u32 tcr;
+ u8 resv7[0x1C];
+ u32 palr;
+ u32 paur;
+ u32 opd;
+ u8 resv8[0x28];
+ u32 iaur;
+ u32 ialr;
+ u32 gaur;
+ u32 galr;
+ u8 resv9[0x1C];
+ u32 tfwr;
+ u8 resv10[0x4];
+ u32 frbr;
+ u32 frsr;
+ u8 resv11[0x2C];
+ u32 erdsr;
+ u32 etdsr;
+ u32 emrbr;
+ u8 resv12[0x74];
+#endif
+
+ u32 rmon_t_drop;
+ u32 rmon_t_packets;
+ u32 rmon_t_bc_pkt;
+ u32 rmon_t_mc_pkt;
+ u32 rmon_t_crc_align;
+ u32 rmon_t_undersize;
+ u32 rmon_t_oversize;
+ u32 rmon_t_frag;
+ u32 rmon_t_jab;
+ u32 rmon_t_col;
+ u32 rmon_t_p64;
+ u32 rmon_t_p65to127;
+ u32 rmon_t_p128to255;
+ u32 rmon_t_p256to511;
+ u32 rmon_t_p512to1023;
+ u32 rmon_t_p1024to2047;
+ u32 rmon_t_p_gte2048;
+ u32 rmon_t_octets;
+
+ u32 ieee_t_drop;
+ u32 ieee_t_frame_ok;
+ u32 ieee_t_1col;
+ u32 ieee_t_mcol;
+ u32 ieee_t_def;
+ u32 ieee_t_lcol;
+ u32 ieee_t_excol;
+ u32 ieee_t_macerr;
+ u32 ieee_t_cserr;
+ u32 ieee_t_sqe;
+ u32 ieee_t_fdxfc;
+ u32 ieee_t_octets_ok;
+ u8 resv13[0x8];
+
+ u32 rmon_r_drop;
+ u32 rmon_r_packets;
+ u32 rmon_r_bc_pkt;
+ u32 rmon_r_mc_pkt;
+ u32 rmon_r_crc_align;
+ u32 rmon_r_undersize;
+ u32 rmon_r_oversize;
+ u32 rmon_r_frag;
+ u32 rmon_r_jab;
+ u32 rmon_r_resvd_0;
+ u32 rmon_r_p64;
+ u32 rmon_r_p65to127;
+ u32 rmon_r_p128to255;
+ u32 rmon_r_p256to511;
+ u32 rmon_r_p512to1023;
+ u32 rmon_r_p1024to2047;
+ u32 rmon_r_p_gte2048;
+ u32 rmon_r_octets;
+
+ u32 ieee_r_drop;
+ u32 ieee_r_frame_ok;
+ u32 ieee_r_crc;
+ u32 ieee_r_align;
+ u32 ieee_r_macerr;
+ u32 ieee_r_fdxfc;
+ u32 ieee_r_octets_ok;
+} fec_t;
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* Bit definitions and macros for FEC_EIR */
+#define FEC_EIR_CLEAR_ALL (0xFFF80000)
+#define FEC_EIR_HBERR (0x80000000)
+#define FEC_EIR_BABR (0x40000000)
+#define FEC_EIR_BABT (0x20000000)
+#define FEC_EIR_GRA (0x10000000)
+#define FEC_EIR_TXF (0x08000000)
+#define FEC_EIR_TXB (0x04000000)
+#define FEC_EIR_RXF (0x02000000)
+#define FEC_EIR_RXB (0x01000000)
+#define FEC_EIR_MII (0x00800000)
+#define FEC_EIR_EBERR (0x00400000)
+#define FEC_EIR_LC (0x00200000)
+#define FEC_EIR_RL (0x00100000)
+#define FEC_EIR_UN (0x00080000)
+
+/* Bit definitions and macros for FEC_RDAR */
+#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
+
+/* Bit definitions and macros for FEC_TDAR */
+#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
+
+/* Bit definitions and macros for FEC_ECR */
+#define FEC_ECR_ETHER_EN (0x00000002)
+#define FEC_ECR_RESET (0x00000001)
+
+/* Bit definitions and macros for FEC_MMFR */
+#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
+#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
+#define FEC_MMFR_ST_01 (0x40000000)
+#define FEC_MMFR_OP_RD (0x20000000)
+#define FEC_MMFR_OP_WR (0x10000000)
+#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
+#define FEC_MMFR_TA_10 (0x00020000)
+
+/* Bit definitions and macros for FEC_MSCR */
+#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
+#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
+
+/* Bit definitions and macros for FEC_MIBC */
+#define FEC_MIBC_MIB_DISABLE (0x80000000)
+#define FEC_MIBC_MIB_IDLE (0x40000000)
+
+/* Bit definitions and macros for FEC_RCR */
+#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
+#define FEC_RCR_FCE (0x00000020)
+#define FEC_RCR_BC_REJ (0x00000010)
+#define FEC_RCR_PROM (0x00000008)
+#define FEC_RCR_MII_MODE (0x00000004)
+#define FEC_RCR_DRT (0x00000002)
+#define FEC_RCR_LOOP (0x00000001)
+
+/* Bit definitions and macros for FEC_TCR */
+#define FEC_TCR_RFC_PAUSE (0x00000010)
+#define FEC_TCR_TFC_PAUSE (0x00000008)
+#define FEC_TCR_FDEN (0x00000004)
+#define FEC_TCR_HBC (0x00000002)
+#define FEC_TCR_GTS (0x00000001)
+
+/* Bit definitions and macros for FEC_PAUR */
+#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for FEC_OPD */
+#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for FEC_TFWR */
+#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
+#define FEC_TFWR_X_WMRK_64 (0x01)
+#define FEC_TFWR_X_WMRK_128 (0x02)
+#define FEC_TFWR_X_WMRK_192 (0x03)
+
+/* Bit definitions and macros for FEC_FRBR */
+#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_FRSR */
+#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_ERDSR */
+#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_ETDSR */
+#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_EMRBR */
+#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
+
+#define FEC_RESET_DELAY 100
+#define FEC_RX_TOUT 100
+
+#endif /* CONFIG_MCFFEC */
+#endif /* fec_h */
--- /dev/null
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c {
+
+ u8 adr; /* I2C slave address */
+ u8 res0[3];
+#define I2C_ADR 0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES ~(I2C_ADR)
+
+ u8 fdr; /* I2C frequency divider register */
+ u8 res1[3];
+#define IC2_FDR 0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES ~(IC2_FDR)
+
+ u8 cr; /* I2C control redister */
+ u8 res2[3];
+#define I2C_CR_MEN 0x80
+#define I2C_CR_MIEN 0x40
+#define I2C_CR_MSTA 0x20
+#define I2C_CR_MTX 0x10
+#define I2C_CR_TXAK 0x08
+#define I2C_CR_RSTA 0x04
+#define I2C_CR_BCST 0x01
+
+ u8 sr; /* I2C status register */
+ u8 res3[3];
+#define I2C_SR_MCF 0x80
+#define I2C_SR_MAAS 0x40
+#define I2C_SR_MBB 0x20
+#define I2C_SR_MAL 0x10
+#define I2C_SR_BCSTM 0x08
+#define I2C_SR_SRW 0x04
+#define I2C_SR_MIF 0x02
+#define I2C_SR_RXAK 0x01
+
+ u8 dr; /* I2C data register */
+ u8 res4[3];
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+
+ u8 dfsrr; /* I2C digital filter sampling rate register */
+ u8 res5[3];
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+
+ /* Fill out the reserved block */
+ u8 res6[0xE8];
+} fsl_i2c_t;
+
+#endif /* _ASM_I2C_H_ */
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
+#ifdef CONFIG_PCI
+ unsigned long pci_clk;
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+ unsigned long inp_clk;
+ unsigned long vco_clk;
+ unsigned long flb_clk;
+#endif
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */
--- /dev/null
+/*
+ * ColdFire Internal Memory Map and Defines
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_H
+#define __IMMAP_H
+
+#ifdef CONFIG_M5235
+#include <asm/immap_5235.h>
+#include <asm/m5235.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE (MMAP_PIT0)
+#define CFG_PIT_BASE (MMAP_PIT1)
+#define CFG_PIT_PRESCALE (6)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+#endif /* CONFIG_M5235 */
+
+#ifdef CONFIG_M5249
+#include <asm/immap_5249.h>
+#include <asm/m5249.h>
+
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC)
+#define CFG_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO (31)
+#define CFG_TMRINTR_MASK (0x00000400)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+#include <asm/immap_5253.h>
+#include <asm/m5249.h>
+#include <asm/m5253.h>
+
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC)
+#define CFG_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO (27)
+#define CFG_TMRINTR_MASK (0x00000400)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5253 */
+
+#ifdef CONFIG_M5271
+#include <asm/immap_5271.h>
+#include <asm/m5271.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+#endif /* CONFIG_M5271 */
+
+#ifdef CONFIG_M5272
+#include <asm/immap_5272.h>
+#include <asm/m5272.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC)
+#define CFG_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_TMR0)
+#define CFG_TMR_BASE (MMAP_TMR3)
+#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
+#define CFG_TMRINTR_NO (INT_TMR3)
+#define CFG_TMRINTR_MASK (INT_ISR_INT24)
+#define CFG_TMRINTR_PEND (0)
+#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5272 */
+
+#ifdef CONFIG_M5282
+#include <asm/immap_5282.h>
+#include <asm/m5282.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5282 */
+
+#ifdef CONFIG_M5329
+#include <asm/immap_5329.h>
+#include <asm/m5329.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+#define CFG_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (6)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE (MMAP_PIT0)
+#define CFG_PIT_BASE (MMAP_PIT1)
+#define CFG_PIT_PRESCALE (6)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+#endif /* CONFIG_M5329 */
+
+#ifdef CONFIG_M54455
+#include <asm/immap_5445x.h>
+#include <asm/m5445x.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC0)
+#define CFG_FEC1_IOBASE (MMAP_FEC1)
+
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+
+#define CFG_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (6)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE (MMAP_PIT0)
+#define CFG_PIT_BASE (MMAP_PIT1)
+#define CFG_PIT_PRESCALE (6)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0 CFG_SDRAM_BASE
+#define CFG_PCI_BAR4 CFG_SDRAM_BASE
+#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
+#endif
+#endif /* CONFIG_M54455 */
+
+#endif /* __IMMAP_H */
--- /dev/null
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5235__
+#define __IMMAP_5235__
+
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
+
+/* System Control Module register */
+typedef struct scm_ctrl {
+ u32 ipsbar; /* 0x00 - MBAR */
+ u32 res1; /* 0x04 */
+ u32 rambar; /* 0x08 - RAMBAR */
+ u32 res2; /* 0x0C */
+ u8 crsr; /* 0x10 Core Reset Status Register */
+ u8 cwcr; /* 0x11 Core Watchdog Control Register */
+ u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
+ u8 cwsr; /* 0x13 Core Watchdog Service Register */
+ u32 dmareqc; /* 0x14 */
+ u32 res3; /* 0x18 */
+ u32 mpark; /* 0x1C */
+ u8 mpr; /* 0x20 */
+ u8 res4[3]; /* 0x21 - 0x23 */
+ u8 pacr0; /* 0x24 */
+ u8 pacr1; /* 0x25 */
+ u8 pacr2; /* 0x26 */
+ u8 pacr3; /* 0x27 */
+ u8 pacr4; /* 0x28 */
+ u32 res5; /* 0x29 */
+ u8 pacr5; /* 0x2a */
+ u8 pacr6; /* 0x2b */
+ u8 pacr7; /* 0x2c */
+ u32 res6; /* 0x2d */
+ u8 pacr8; /* 0x2e */
+ u32 res7; /* 0x2f */
+ u8 gpacr; /* 0x30 */
+ u8 res8[3]; /* 0x31 - 0x33 */
+} scm_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+ u16 dcr; /* 0x00 Control register */
+ u16 res1[3]; /* 0x02 - 0x07 */
+ u32 dacr0; /* 0x08 address and control register 0 */
+ u32 dmr0; /* 0x0C mask register block 0 */
+ u32 dacr1; /* 0x10 address and control register 1 */
+ u32 dmr1; /* 0x14 mask register block 1 */
+} sdram_t;
+
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+ u16 csar0; /* 0x00 Chip-Select Address Register 0 */
+ u16 res0;
+ u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
+ u16 res1; /* 0x08 */
+ u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
+
+ u16 csar1; /* 0x0C Chip-Select Address Register 1 */
+ u16 res2;
+ u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
+ u16 res3; /* 0x14 */
+ u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
+
+ u16 csar2; /* 0x18 Chip-Select Address Register 2 */
+ u16 res4;
+ u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
+ u16 res5; /* 0x20 */
+ u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
+
+ u16 csar3; /* 0x24 Chip-Select Address Register 3 */
+ u16 res6;
+ u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
+ u16 res7; /* 0x2C */
+ u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
+
+ u16 csar4; /* 0x30 Chip-Select Address Register 4 */
+ u16 res8;
+ u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
+ u16 res9; /* 0x38 */
+ u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
+
+ u16 csar5; /* 0x3C Chip-Select Address Register 5 */
+ u16 res10;
+ u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
+ u16 res11; /* 0x44 */
+ u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
+
+ u16 csar6; /* 0x48 Chip-Select Address Register 5 */
+ u16 res12;
+ u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
+ u16 res13; /* 0x50 */
+ u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
+
+ u16 csar7; /* 0x54 Chip-Select Address Register 5 */
+ u16 res14;
+ u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
+ u16 res15; /* 0x5C */
+ u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ u16 qmr; /* Mode register */
+ u16 res1;
+ u16 qdlyr; /* Delay register */
+ u16 res2;
+ u16 qwr; /* Wrap register */
+ u16 res3;
+ u16 qir; /* Interrupt register */
+ u16 res4;
+ u16 qar; /* Address register */
+ u16 res5;
+ u16 qdr; /* Data register */
+ u16 res6;
+} qspi_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending Register High */
+ u32 iprl1; /* 0x04 Pending Register Low */
+ u32 imrh1; /* 0x08 Mask Register High */
+ u32 imrl1; /* 0x0C Mask Register Low */
+ u32 frch1; /* 0x10 Force Register High */
+ u32 frcl1; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+ /* Global IACK Registers */
+ u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
+ u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
+} intgack_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_addr; /* 0x00 */
+ u8 podr_datah; /* 0x01 */
+ u8 podr_datal; /* 0x02 */
+ u8 podr_busctl; /* 0x03 */
+ u8 podr_bs; /* 0x04 */
+ u8 podr_cs; /* 0x05 */
+ u8 podr_sdram; /* 0x06 */
+ u8 podr_feci2c; /* 0x07 */
+ u8 podr_uarth; /* 0x08 */
+ u8 podr_uartl; /* 0x09 */
+ u8 podr_qspi; /* 0x0A */
+ u8 podr_timer; /* 0x0B */
+ u8 podr_etpu; /* 0x0C */
+ u8 res1[3]; /* 0x0D - 0x0F */
+
+ /* Port Data Direction Registers */
+ u8 pddr_addr; /* 0x10 */
+ u8 pddr_datah; /* 0x11 */
+ u8 pddr_datal; /* 0x12 */
+ u8 pddr_busctl; /* 0x13 */
+ u8 pddr_bs; /* 0x14 */
+ u8 pddr_cs; /* 0x15 */
+ u8 pddr_sdram; /* 0x16 */
+ u8 pddr_feci2c; /* 0x17 */
+ u8 pddr_uarth; /* 0x18 */
+ u8 pddr_uartl; /* 0x19 */
+ u8 pddr_qspi; /* 0x1A */
+ u8 pddr_timer; /* 0x1B */
+ u8 pddr_etpu; /* 0x1C */
+ u8 res2[3]; /* 0x1D - 0x1F */
+
+ /* Port Data Direction Registers */
+ u8 ppdsdr_addr; /* 0x20 */
+ u8 ppdsdr_datah; /* 0x21 */
+ u8 ppdsdr_datal; /* 0x22 */
+ u8 ppdsdr_busctl; /* 0x23 */
+ u8 ppdsdr_bs; /* 0x24 */
+ u8 ppdsdr_cs; /* 0x25 */
+ u8 ppdsdr_sdram; /* 0x26 */
+ u8 ppdsdr_feci2c; /* 0x27 */
+ u8 ppdsdr_uarth; /* 0x28 */
+ u8 ppdsdr_uartl; /* 0x29 */
+ u8 ppdsdr_qspi; /* 0x2A */
+ u8 ppdsdr_timer; /* 0x2B */
+ u8 ppdsdr_etpu; /* 0x2C */
+ u8 res3[3]; /* 0x2D - 0x2F */
+
+ /* Port Clear Output Data Registers */
+ u8 pclrr_addr; /* 0x30 */
+ u8 pclrr_datah; /* 0x31 */
+ u8 pclrr_datal; /* 0x32 */
+ u8 pclrr_busctl; /* 0x33 */
+ u8 pclrr_bs; /* 0x34 */
+ u8 pclrr_cs; /* 0x35 */
+ u8 pclrr_sdram; /* 0x36 */
+ u8 pclrr_feci2c; /* 0x37 */
+ u8 pclrr_uarth; /* 0x38 */
+ u8 pclrr_uartl; /* 0x39 */
+ u8 pclrr_qspi; /* 0x3A */
+ u8 pclrr_timer; /* 0x3B */
+ u8 pclrr_etpu; /* 0x3C */
+ u8 res4[3]; /* 0x3D - 0x3F */
+
+ /* Pin Assignment Registers */
+ u8 par_ad; /* 0x40 */
+ u8 res5; /* 0x41 */
+ u16 par_busctl; /* 0x42 */
+ u8 par_bs; /* 0x44 */
+ u8 par_cs; /* 0x45 */
+ u8 par_sdram; /* 0x46 */
+ u8 par_feci2c; /* 0x47 */
+ u16 par_uart; /* 0x48 */
+ u8 par_qspi; /* 0x4A */
+ u8 res6; /* 0x4B */
+ u16 par_timer; /* 0x4C */
+ u8 par_etpu; /* 0x4E */
+ u8 res7; /* 0x4F */
+
+ /* Drive Strength Control Registers */
+ u8 dscr_eim; /* 0x50 */
+ u8 dscr_etpu; /* 0x51 */
+ u8 dscr_feci2c; /* 0x52 */
+ u8 dscr_uart; /* 0x53 */
+ u8 dscr_qspi; /* 0x54 */
+ u8 dscr_timer; /* 0x55 */
+ u16 res8; /* 0x56 */
+} gpio_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+ u8 rcr; /* 0x01 */
+ u8 rsr; /* 0x02 */
+ u16 res1; /* 0x03 */
+ u16 ccr; /* 0x04 Chip configuration register */
+ u16 lpcr; /* 0x06 Low-power Control register */
+ u16 rcon; /* 0x08 Rreset configuration register */
+ u16 cir; /* 0x0a Chip identification register */
+} ccm_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+ u32 syncr; /* 0x00 synthesizer control register */
+ u32 synsr; /* 0x04 synthesizer status register */
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ u16 cr; /* 0x00 Control register */
+ u16 mr; /* 0x02 Modulus register */
+ u16 cntr; /* 0x04 Count register */
+ u16 sr; /* 0x06 Service register */
+} wdog_t;
+
+/* FlexCan module registers */
+typedef struct can_ctrl {
+ u32 mcr; /* 0x00 Module Configuration register */
+ u32 ctrl; /* 0x04 Control register */
+ u32 timer; /* 0x08 Free Running Timer */
+ u32 res1; /* 0x0C */
+ u32 rxgmask; /* 0x10 Rx Global Mask */
+ u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
+ u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
+ u32 errcnt; /* 0x1C Error Counter Register */
+ u32 errstat; /* 0x20 Error and status Register */
+ u32 res2; /* 0x24 */
+ u32 imask; /* 0x28 Interrupt Mask Register */
+ u32 res3; /* 0x2C */
+ u32 iflag; /* 0x30 Interrupt Flag Register */
+ u32 res4[19]; /* 0x34 - 0x7F */
+ u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
+} can_t;
+
+#endif /* __IMMAP_5235__ */
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
-/* Timer module registers
- */
-typedef struct timer_ctrl {
- ushort timer_tmr;
- ushort res1;
- ushort timer_trr;
- ushort res2;
- ushort timer_tcap;
- ushort res3;
- ushort timer_tcn;
- ushort res4;
- ushort timer_ter;
- uchar res5[14];
-} timer_t;
+#define MMAP_INTC (CFG_MBAR + 0x00000040)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_MBAR + 0x00000200)
+#define MMAP_QSPI (CFG_MBAR + 0x00000400)
-#endif /* __IMMAP_5249__ */
+#endif /* __IMMAP_5249__ */
--- /dev/null
+/*
+ * MCF5253 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5249__
+#define __IMMAP_5249__
+
+#define MMAP_INTC (CFG_MBAR + 0x00000040)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_MBAR + 0x00000200)
+#define MMAP_I2C0 (CFG_MBAR + 0x00000280)
+#define MMAP_QSPI (CFG_MBAR + 0x00000400)
+#define MMAP_CAN0 (CFG_MBAR + 0x00010000)
+#define MMAP_CAN1 (CFG_MBAR + 0x00011000)
+
+#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440)
+#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00)
+
+/*********************************************************************
+* ATA Module (ATAC)
+*********************************************************************/
+
+/* Register read/write struct */
+typedef struct atac {
+ /* PIO */
+ u8 toff; /* 0x00 */
+ u8 ton; /* 0x01 */
+ u8 t1; /* 0x02 */
+ u8 t2w; /* 0x03 */
+ u8 t2r; /* 0x04 */
+ u8 ta; /* 0x05 */
+ u8 trd; /* 0x06 */
+ u8 t4; /* 0x07 */
+ u8 t9; /* 0x08 */
+
+ /* DMA */
+ u8 tm; /* 0x09 */
+ u8 tn; /* 0x0A */
+ u8 td; /* 0x0B */
+ u8 tk; /* 0x0C */
+ u8 tack; /* 0x0D */
+ u8 tenv; /* 0x0E */
+ u8 trp; /* 0x0F */
+ u8 tzah; /* 0x10 */
+ u8 tmli; /* 0x11 */
+ u8 tdvh; /* 0x12 */
+ u8 tdzfs; /* 0x13 */
+ u8 tdvs; /* 0x14 */
+ u8 tcvh; /* 0x15 */
+ u8 tss; /* 0x16 */
+ u8 tcyc; /* 0x17 */
+
+ /* FIFO */
+ u32 fifo32; /* 0x18 */
+ u16 fifo16; /* 0x1C */
+ u8 rsvd0[2];
+ u8 ffill; /* 0x20 */
+ u8 rsvd1[3];
+
+ /* ATA */
+ u8 cr; /* 0x24 */
+ u8 rsvd2[3];
+ u8 isr; /* 0x28 */
+ u8 rsvd3[3];
+ u8 ier; /* 0x2C */
+ u8 rsvd4[3];
+ u8 icr; /* 0x30 */
+ u8 rsvd5[3];
+ u8 falarm; /* 0x34 */
+} atac_t;
+
+#endif /* __IMMAP_5249__ */
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
-/* Interrupt module registers
-*/
-typedef struct int_ctrl {
- uint int_icr1;
- uint int_icr2;
- uint int_icr3;
- uint int_icr4;
- uint int_isr;
- uint int_pitr;
- uint int_piwr;
- uchar res1[3];
- uchar int_pivr;
-} intctrl_t;
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
-/* Timer module registers
- */
-typedef struct timer_ctrl {
- ushort timer_tmr;
- ushort res1;
- ushort timer_trr;
- ushort res2;
- ushort timer_tcap;
- ushort res3;
- ushort timer_tcn;
- ushort res4;
- ushort timer_ter;
- uchar res5[14];
-} timer_t;
-
- /* Fast ethernet controller registers
- */
-typedef struct fec {
- uint res1;
- uint fec_ievent;
- uint fec_imask;
- uint res2;
- uint fec_r_des_active;
- uint fec_x_des_active;
- uint res3[3];
- uint fec_ecntrl;
- uint res4[6];
- uint fec_mii_data;
- uint fec_mii_speed;
- uint res5[7];
- uint fec_mibc;
- uint res6[7];
- uint fec_r_cntrl;
- uint res7[15];
- uint fec_x_cntrl;
- uint res8[7];
- uint fec_addr_low;
- uint fec_addr_high;
- uint fec_opd;
- uint res9[10];
- uint fec_ihash_table_high;
- uint fec_ihash_table_low;
- uint fec_ghash_table_high;
- uint fec_ghash_table_low;
- uint res10[7];
- uint fec_tfwr;
- uint res11;
- uint fec_r_bound;
- uint fec_r_fstart;
- uint res12[11];
- uint fec_r_des_start;
- uint fec_x_des_start;
- uint fec_r_buff_size;
-} fec_t;
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
-#endif /* __IMMAP_5271__ */
+#endif /* __IMMAP_5271__ */
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
-/* System configuration registers
-*/
-typedef struct sys_ctrl {
- uint sc_mbar;
- ushort sc_scr;
- ushort sc_spr;
- uint sc_pmr;
- char res1[2];
- ushort sc_alpr;
- uint sc_dir;
- char res2[12];
+#define MMAP_CFG (CFG_MBAR + 0x00000000)
+#define MMAP_INTC (CFG_MBAR + 0x00000020)
+#define MMAP_FBCS (CFG_MBAR + 0x00000040)
+#define MMAP_GPIO (CFG_MBAR + 0x00000080)
+#define MMAP_QSPI (CFG_MBAR + 0x000000A0)
+#define MMAP_PWM (CFG_MBAR + 0x000000C0)
+#define MMAP_DMA0 (CFG_MBAR + 0x000000E0)
+#define MMAP_UART0 (CFG_MBAR + 0x00000100)
+#define MMAP_UART1 (CFG_MBAR + 0x00000140)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000180)
+#define MMAP_TMR0 (CFG_MBAR + 0x00000200)
+#define MMAP_TMR1 (CFG_MBAR + 0x00000220)
+#define MMAP_TMR2 (CFG_MBAR + 0x00000240)
+#define MMAP_TMR3 (CFG_MBAR + 0x00000260)
+#define MMAP_WDOG (CFG_MBAR + 0x00000280)
+#define MMAP_PLIC (CFG_MBAR + 0x00000300)
+#define MMAP_FEC (CFG_MBAR + 0x00000840)
+#define MMAP_USB (CFG_MBAR + 0x00001000)
+
+/* System configuration registers */
+typedef struct sys_ctrl {
+ uint sc_mbar;
+ ushort sc_scr;
+ ushort sc_spr;
+ uint sc_pmr;
+ char res1[2];
+ ushort sc_alpr;
+ uint sc_dir;
+ char res2[12];
} sysctrl_t;
-/* Interrupt module registers
-*/
+/* Interrupt module registers */
typedef struct int_ctrl {
- uint int_icr1;
- uint int_icr2;
- uint int_icr3;
- uint int_icr4;
- uint int_isr;
- uint int_pitr;
- uint int_piwr;
- uchar res1[3];
- uchar int_pivr;
+ uint int_icr1;
+ uint int_icr2;
+ uint int_icr3;
+ uint int_icr4;
+ uint int_isr;
+ uint int_pitr;
+ uint int_piwr;
+ uchar res1[3];
+ uchar int_pivr;
} intctrl_t;
-/* Chip select module registers.
-*/
-typedef struct cs_ctlr {
- uint cs_br0;
- uint cs_or0;
- uint cs_br1;
- uint cs_or1;
- uint cs_br2;
- uint cs_or2;
- uint cs_br3;
- uint cs_or3;
- uint cs_br4;
- uint cs_or4;
- uint cs_br5;
- uint cs_or5;
- uint cs_br6;
- uint cs_or6;
- uint cs_br7;
- uint cs_or7;
+/* Chip select module registers */
+typedef struct cs_ctlr {
+ uint cs_br0;
+ uint cs_or0;
+ uint cs_br1;
+ uint cs_or1;
+ uint cs_br2;
+ uint cs_or2;
+ uint cs_br3;
+ uint cs_or3;
+ uint cs_br4;
+ uint cs_or4;
+ uint cs_br5;
+ uint cs_or5;
+ uint cs_br6;
+ uint cs_or6;
+ uint cs_br7;
+ uint cs_or7;
} csctrl_t;
-/* GPIO port registers
-*/
-typedef struct gpio_ctrl {
- uint gpio_pacnt;
- ushort gpio_paddr;
- ushort gpio_padat;
- uint gpio_pbcnt;
- ushort gpio_pbddr;
- ushort gpio_pbdat;
- uchar res1[4];
- ushort gpio_pcddr;
- ushort gpio_pcdat;
- uint gpio_pdcnt;
- uchar res2[4];
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+ uint gpio_pacnt;
+ ushort gpio_paddr;
+ ushort gpio_padat;
+ uint gpio_pbcnt;
+ ushort gpio_pbddr;
+ ushort gpio_pbdat;
+ uchar res1[4];
+ ushort gpio_pcddr;
+ ushort gpio_pcdat;
+ uint gpio_pdcnt;
+ uchar res2[4];
} gpio_t;
-/* QSPI module registers
- */
-typedef struct qspi_ctrl {
- ushort qspi_qmr;
- uchar res1[2];
- ushort qspi_qdlyr;
- uchar res2[2];
- ushort qspi_qwr;
- uchar res3[2];
- ushort qspi_qir;
- uchar res4[2];
- ushort qspi_qar;
- uchar res5[2];
- ushort qspi_qdr;
- uchar res6[10];
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ ushort qspi_qmr;
+ uchar res1[2];
+ ushort qspi_qdlyr;
+ uchar res2[2];
+ ushort qspi_qwr;
+ uchar res3[2];
+ ushort qspi_qir;
+ uchar res4[2];
+ ushort qspi_qar;
+ uchar res5[2];
+ ushort qspi_qdr;
+ uchar res6[10];
} qspi_t;
-/* PWM module registers
- */
-typedef struct pwm_ctrl {
- uchar pwm_pwcr0;
- uchar res1[3];
- uchar pwm_pwcr1;
- uchar res2[3];
- uchar pwm_pwcr2;
- uchar res3[7];
- uchar pwm_pwwd0;
- uchar res4[3];
- uchar pwm_pwwd1;
- uchar res5[3];
- uchar pwm_pwwd2;
- uchar res6[7];
+/* PWM module registers */
+typedef struct pwm_ctrl {
+ uchar pwm_pwcr0;
+ uchar res1[3];
+ uchar pwm_pwcr1;
+ uchar res2[3];
+ uchar pwm_pwcr2;
+ uchar res3[7];
+ uchar pwm_pwwd0;
+ uchar res4[3];
+ uchar pwm_pwwd1;
+ uchar res5[3];
+ uchar pwm_pwwd2;
+ uchar res6[7];
} pwm_t;
-/* DMA module registers
- */
-typedef struct dma_ctrl {
- ulong dma_dmr;
- uchar res1[2];
- ushort dma_dir;
- ulong dma_dbcr;
- ulong dma_dsar;
- ulong dma_ddar;
- uchar res2[12];
+/* DMA module registers */
+typedef struct dma_ctrl {
+ ulong dma_dmr;
+ uchar res1[2];
+ ushort dma_dir;
+ ulong dma_dbcr;
+ ulong dma_dsar;
+ ulong dma_ddar;
+ uchar res2[12];
} dma_t;
-/* UART module registers
- */
-typedef struct uart_ctrl {
- uchar uart_umr;
- uchar res1[3];
- uchar uart_usr_ucsr;
- uchar res2[3];
- uchar uart_ucr;
- uchar res3[3];
- uchar uart_urb_utb;
- uchar res4[3];
- uchar uart_uipcr_uacr;
- uchar res5[3];
- uchar uart_uisr_uimr;
- uchar res6[3];
- uchar uart_udu;
- uchar res7[3];
- uchar uart_udl;
- uchar res8[3];
- uchar uart_uabu;
- uchar res9[3];
- uchar uart_uabl;
- uchar res10[3];
- uchar uart_utf;
- uchar res11[3];
- uchar uart_urf;
- uchar res12[3];
- uchar uart_ufpd;
- uchar res13[3];
- uchar uart_uip;
- uchar res14[3];
- uchar uart_uop1;
- uchar res15[3];
- uchar uart_uop0;
- uchar res16[3];
-} uart_t;
-
-/* SDRAM controller registers, offset: 0x180
- */
+/* SDRAM controller registers, offset: 0x180 */
typedef struct sdram_ctrl {
- uchar res1[2];
- ushort sdram_sdcr;
- uchar res2[2];
- ushort sdram_sdtr;
- uchar res3[120];
+ uchar res1[2];
+ ushort sdram_sdcr;
+ uchar res2[2];
+ ushort sdram_sdtr;
+ uchar res3[120];
} sdramctrl_t;
-/* Timer module registers
- */
-typedef struct timer_ctrl {
- ushort timer_tmr;
- ushort res1;
- ushort timer_trr;
- ushort res2;
- ushort timer_tcap;
- ushort res3;
- ushort timer_tcn;
- ushort res4;
- ushort timer_ter;
- uchar res5[14];
-} timer_t;
-
-/* Watchdog registers
- */
+/* Watchdog registers */
typedef struct wdog_ctrl {
- ushort wdog_wrrr;
- ushort res1;
- ushort wdog_wirr;
- ushort res2;
- ushort wdog_wcr;
- ushort res3;
- ushort wdog_wer;
- uchar res4[114];
+ ushort wdog_wrrr;
+ ushort res1;
+ ushort wdog_wirr;
+ ushort res2;
+ ushort wdog_wcr;
+ ushort res3;
+ ushort wdog_wer;
+ uchar res4[114];
} wdog_t;
-/* PLIC module registers
- */
+/* PLIC module registers */
typedef struct plic_ctrl {
- ulong plic_p0b1rr;
- ulong plic_p1b1rr;
- ulong plic_p2b1rr;
- ulong plic_p3b1rr;
- ulong plic_p0b2rr;
- ulong plic_p1b2rr;
- ulong plic_p2b2rr;
- ulong plic_p3b2rr;
- uchar plic_p0drr;
- uchar plic_p1drr;
- uchar plic_p2drr;
- uchar plic_p3drr;
- uchar res1[4];
- ulong plic_p0b1tr;
- ulong plic_p1b1tr;
- ulong plic_p2b1tr;
- ulong plic_p3b1tr;
- ulong plic_p0b2tr;
- ulong plic_p1b2tr;
- ulong plic_p2b2tr;
- ulong plic_p3b2tr;
- uchar plic_p0dtr;
- uchar plic_p1dtr;
- uchar plic_p2dtr;
- uchar plic_p3dtr;
- uchar res2[4];
- ushort plic_p0cr;
- ushort plic_p1cr;
- ushort plic_p2cr;
- ushort plic_p3cr;
- ushort plic_p0icr;
- ushort plic_p1icr;
- ushort plic_p2icr;
- ushort plic_p3icr;
- ushort plic_p0gmr;
- ushort plic_p1gmr;
- ushort plic_p2gmr;
- ushort plic_p3gmr;
- ushort plic_p0gmt;
- ushort plic_p1gmt;
- ushort plic_p2gmt;
- ushort plic_p3gmt;
- uchar res3;
- uchar plic_pgmts;
- uchar plic_pgmta;
- uchar res4;
- uchar plic_p0gcir;
- uchar plic_p1gcir;
- uchar plic_p2gcir;
- uchar plic_p3gcir;
- uchar plic_p0gcit;
- uchar plic_p1gcit;
- uchar plic_p2gcit;
- uchar plic_p3gcit;
- uchar res5[3];
- uchar plic_pgcitsr;
- uchar res6[3];
- uchar plic_pdcsr;
- ushort plic_p0psr;
- ushort plic_p1psr;
- ushort plic_p2psr;
- ushort plic_p3psr;
- ushort plic_pasr;
- uchar res7;
- uchar plic_plcr;
- ushort res8;
- ushort plic_pdrqr;
- ushort plic_p0sdr;
- ushort plic_p1sdr;
- ushort plic_p2sdr;
- ushort plic_p3sdr;
- ushort res9;
- ushort plic_pcsr;
- uchar res10[1184];
+ ulong plic_p0b1rr;
+ ulong plic_p1b1rr;
+ ulong plic_p2b1rr;
+ ulong plic_p3b1rr;
+ ulong plic_p0b2rr;
+ ulong plic_p1b2rr;
+ ulong plic_p2b2rr;
+ ulong plic_p3b2rr;
+ uchar plic_p0drr;
+ uchar plic_p1drr;
+ uchar plic_p2drr;
+ uchar plic_p3drr;
+ uchar res1[4];
+ ulong plic_p0b1tr;
+ ulong plic_p1b1tr;
+ ulong plic_p2b1tr;
+ ulong plic_p3b1tr;
+ ulong plic_p0b2tr;
+ ulong plic_p1b2tr;
+ ulong plic_p2b2tr;
+ ulong plic_p3b2tr;
+ uchar plic_p0dtr;
+ uchar plic_p1dtr;
+ uchar plic_p2dtr;
+ uchar plic_p3dtr;
+ uchar res2[4];
+ ushort plic_p0cr;
+ ushort plic_p1cr;
+ ushort plic_p2cr;
+ ushort plic_p3cr;
+ ushort plic_p0icr;
+ ushort plic_p1icr;
+ ushort plic_p2icr;
+ ushort plic_p3icr;
+ ushort plic_p0gmr;
+ ushort plic_p1gmr;
+ ushort plic_p2gmr;
+ ushort plic_p3gmr;
+ ushort plic_p0gmt;
+ ushort plic_p1gmt;
+ ushort plic_p2gmt;
+ ushort plic_p3gmt;
+ uchar res3;
+ uchar plic_pgmts;
+ uchar plic_pgmta;
+ uchar res4;
+ uchar plic_p0gcir;
+ uchar plic_p1gcir;
+ uchar plic_p2gcir;
+ uchar plic_p3gcir;
+ uchar plic_p0gcit;
+ uchar plic_p1gcit;
+ uchar plic_p2gcit;
+ uchar plic_p3gcit;
+ uchar res5[3];
+ uchar plic_pgcitsr;
+ uchar res6[3];
+ uchar plic_pdcsr;
+ ushort plic_p0psr;
+ ushort plic_p1psr;
+ ushort plic_p2psr;
+ ushort plic_p3psr;
+ ushort plic_pasr;
+ uchar res7;
+ uchar plic_plcr;
+ ushort res8;
+ ushort plic_pdrqr;
+ ushort plic_p0sdr;
+ ushort plic_p1sdr;
+ ushort plic_p2sdr;
+ ushort plic_p3sdr;
+ ushort res9;
+ ushort plic_pcsr;
+ uchar res10[1184];
} plic_t;
-/* Fast ethernet controller registers
- */
-typedef struct fec {
- uint fec_ecntrl; /* ethernet control register */
- uint fec_ievent; /* interrupt event register */
- uint fec_imask; /* interrupt mask register */
- uint fec_ivec; /* interrupt level and vector status */
- uint fec_r_des_active; /* Rx ring updated flag */
- uint fec_x_des_active; /* Tx ring updated flag */
- uint res3[10]; /* reserved */
- uint fec_mii_data; /* MII data register */
- uint fec_mii_speed; /* MII speed control register */
- uint res4[17]; /* reserved */
- uint fec_r_bound; /* end of RAM (read-only) */
- uint fec_r_fstart; /* Rx FIFO start address */
- uint res5[6]; /* reserved */
- uint fec_x_fstart; /* Tx FIFO start address */
- uint res7[21]; /* reserved */
- uint fec_r_cntrl; /* Rx control register */
- uint fec_r_hash; /* Rx hash register */
- uint res8[14]; /* reserved */
- uint fec_x_cntrl; /* Tx control register */
- uint res9[0x9e]; /* reserved */
- uint fec_addr_low; /* lower 32 bits of station address */
- uint fec_addr_high; /* upper 16 bits of station address */
- uint fec_hash_table_high; /* upper 32-bits of hash table */
- uint fec_hash_table_low; /* lower 32-bits of hash table */
- uint fec_r_des_start; /* beginning of Rx descriptor ring */
- uint fec_x_des_start; /* beginning of Tx descriptor ring */
- uint fec_r_buff_size; /* Rx buffer size */
- uint res2[9]; /* reserved */
- uchar fec_fifo[960]; /* fifo RAM */
-} fec_t;
-
-/* USB module registers
-*/
+/* USB module registers */
typedef struct usb {
- ushort res1;
- ushort usb_fnr;
- ushort res2;
- ushort usb_fnmr;
- ushort res3;
- ushort usb_rfmr;
- ushort res4;
- ushort usb_rfmmr;
- uchar res5[3];
- uchar usb_far;
- ulong usb_asr;
- ulong usb_drr1;
- ulong usb_drr2;
- ushort res6;
- ushort usb_specr;
- ushort res7;
- ushort usb_ep0sr;
- ulong usb_iep0cfg;
- ulong usb_oep0cfg;
- ulong usb_ep1cfg;
- ulong usb_ep2cfg;
- ulong usb_ep3cfg;
- ulong usb_ep4cfg;
- ulong usb_ep5cfg;
- ulong usb_ep6cfg;
- ulong usb_ep7cfg;
- ulong usb_ep0ctl;
- ushort res8;
- ushort usb_ep1ctl;
- ushort res9;
- ushort usb_ep2ctl;
- ushort res10;
- ushort usb_ep3ctl;
- ushort res11;
- ushort usb_ep4ctl;
- ushort res12;
- ushort usb_ep5ctl;
- ushort res13;
- ushort usb_ep6ctl;
- ushort res14;
- ushort usb_ep7ctl;
- ulong usb_ep0isr;
- ushort res15;
- ushort usb_ep1isr;
- ushort res16;
- ushort usb_ep2isr;
- ushort res17;
- ushort usb_ep3isr;
- ushort res18;
- ushort usb_ep4isr;
- ushort res19;
- ushort usb_ep5isr;
- ushort res20;
- ushort usb_ep6isr;
- ushort res21;
- ushort usb_ep7isr;
- ulong usb_ep0imr;
- ushort res22;
- ushort usb_ep1imr;
- ushort res23;
- ushort usb_ep2imr;
- ushort res24;
- ushort usb_ep3imr;
- ushort res25;
- ushort usb_ep4imr;
- ushort res26;
- ushort usb_ep5imr;
- ushort res27;
- ushort usb_ep6imr;
- ushort res28;
- ushort usb_ep7imr;
- ulong usb_ep0dr;
- ulong usb_ep1dr;
- ulong usb_ep2dr;
- ulong usb_ep3dr;
- ulong usb_ep4dr;
- ulong usb_ep5dr;
- ulong usb_ep6dr;
- ulong usb_ep7dr;
- ushort res29;
- ushort usb_ep0dpr;
- ushort res30;
- ushort usb_ep1dpr;
- ushort res31;
- ushort usb_ep2dpr;
- ushort res32;
- ushort usb_ep3dpr;
- ushort res33;
- ushort usb_ep4dpr;
- ushort res34;
- ushort usb_ep5dpr;
- ushort res35;
- ushort usb_ep6dpr;
- ushort res36;
- ushort usb_ep7dpr;
- uchar res37[788];
- uchar usb_cfgram[1024];
+ ushort res1;
+ ushort usb_fnr;
+ ushort res2;
+ ushort usb_fnmr;
+ ushort res3;
+ ushort usb_rfmr;
+ ushort res4;
+ ushort usb_rfmmr;
+ uchar res5[3];
+ uchar usb_far;
+ ulong usb_asr;
+ ulong usb_drr1;
+ ulong usb_drr2;
+ ushort res6;
+ ushort usb_specr;
+ ushort res7;
+ ushort usb_ep0sr;
+ ulong usb_iep0cfg;
+ ulong usb_oep0cfg;
+ ulong usb_ep1cfg;
+ ulong usb_ep2cfg;
+ ulong usb_ep3cfg;
+ ulong usb_ep4cfg;
+ ulong usb_ep5cfg;
+ ulong usb_ep6cfg;
+ ulong usb_ep7cfg;
+ ulong usb_ep0ctl;
+ ushort res8;
+ ushort usb_ep1ctl;
+ ushort res9;
+ ushort usb_ep2ctl;
+ ushort res10;
+ ushort usb_ep3ctl;
+ ushort res11;
+ ushort usb_ep4ctl;
+ ushort res12;
+ ushort usb_ep5ctl;
+ ushort res13;
+ ushort usb_ep6ctl;
+ ushort res14;
+ ushort usb_ep7ctl;
+ ulong usb_ep0isr;
+ ushort res15;
+ ushort usb_ep1isr;
+ ushort res16;
+ ushort usb_ep2isr;
+ ushort res17;
+ ushort usb_ep3isr;
+ ushort res18;
+ ushort usb_ep4isr;
+ ushort res19;
+ ushort usb_ep5isr;
+ ushort res20;
+ ushort usb_ep6isr;
+ ushort res21;
+ ushort usb_ep7isr;
+ ulong usb_ep0imr;
+ ushort res22;
+ ushort usb_ep1imr;
+ ushort res23;
+ ushort usb_ep2imr;
+ ushort res24;
+ ushort usb_ep3imr;
+ ushort res25;
+ ushort usb_ep4imr;
+ ushort res26;
+ ushort usb_ep5imr;
+ ushort res27;
+ ushort usb_ep6imr;
+ ushort res28;
+ ushort usb_ep7imr;
+ ulong usb_ep0dr;
+ ulong usb_ep1dr;
+ ulong usb_ep2dr;
+ ulong usb_ep3dr;
+ ulong usb_ep4dr;
+ ulong usb_ep5dr;
+ ulong usb_ep6dr;
+ ulong usb_ep7dr;
+ ushort res29;
+ ushort usb_ep0dpr;
+ ushort res30;
+ ushort usb_ep1dpr;
+ ushort res31;
+ ushort usb_ep2dpr;
+ ushort res32;
+ ushort usb_ep3dpr;
+ ushort res33;
+ ushort usb_ep4dpr;
+ ushort res34;
+ ushort usb_ep5dpr;
+ ushort res35;
+ ushort usb_ep6dpr;
+ ushort res36;
+ ushort usb_ep7dpr;
+ uchar res37[788];
+ uchar usb_cfgram[1024];
} usb_t;
-/* Internal memory map.
-*/
-typedef struct immap {
- sysctrl_t sysctrl_reg; /* System configuration registers */
- intctrl_t intctrl_reg; /* Interrupt controller registers */
- csctrl_t csctrl_reg; /* Chip select controller registers */
- gpio_t gpio_reg; /* GPIO controller registers */
- qspi_t qspi_reg; /* QSPI controller registers */
- pwm_t pwm_reg; /* Pulse width modulation registers */
- dma_t dma_reg; /* DMA registers */
- uart_t uart_reg[2]; /* UART registers */
- sdramctrl_t sdram_reg; /* SDRAM controller registers */
- timer_t timer_reg[4]; /* Timer registers */
- wdog_t wdog_reg; /* Watchdog registers */
- plic_t plic_reg; /* Physical layer interface registers */
- fec_t fec_reg; /* Fast ethernet controller registers */
- usb_t usb_reg; /* USB controller registers */
-} immap_t;
-
-#endif /* __IMMAP_5272__ */
+#endif /* __IMMAP_5272__ */
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
-struct sys_ctrl {
- uint ipsbar;
- char res1[4];
- uint rambar;
- char res2[4];
- uchar crsr;
- uchar cwcr;
- uchar lpicr;
- uchar cwsr;
- uint dmareqc;
- char res3[4];
- uint mpark;
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAMC (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000140)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000180)
+#define MMAP_DMA3 (CFG_MBAR + 0x000001C0)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_QADC (CFG_MBAR + 0x00190000)
+#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000)
+#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000)
+#define MMAP_CAN (CFG_MBAR + 0x001C0000)
+#define MMAP_CFMC (CFG_MBAR + 0x001D0000)
+#define MMAP_CFMMEM (CFG_MBAR + 0x04000000)
- /* TODO: finish these */
-};
+/* System Control Module */
+typedef struct scm_ctrl {
+ u32 ipsbar;
+ u32 res1;
+ u32 rambar;
+ u32 res2;
+ u8 crsr;
+ u8 cwcr;
+ u8 lpicr;
+ u8 cwsr;
+ u32 res3;
+ u8 mpark;
+ u8 res4[3];
+ u8 pacr0;
+ u8 pacr1;
+ u8 pacr2;
+ u8 pacr3;
+ u8 pacr4;
+ u8 res5;
+ u8 pacr5;
+ u8 pacr6;
+ u8 pacr7;
+ u8 res6;
+ u8 pacr8;
+ u8 res7;
+ u8 gpacr0;
+ u8 gpacr1;
+ u16 res8;
+} scm_t;
-/* Fast ethernet controller registers
- */
-typedef struct fec {
- uint res1; /* reserved 1000*/
- uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
- uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
- uint res2; /* reserved 100c*/
- uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
- uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
- uint res3[3]; /* reserved 1018*/
- uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
- uint res4[6]; /* reserved 1028*/
- uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
- uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
- /*1044*/
- uint res5[7]; /* reserved 1048*/
- uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
- uint res6[7]; /* reserved 1068*/
- uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
- uint res7[15]; /* reserved 1088*/
- uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
- uint res8[7]; /* reserved 10C8*/
- uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
- uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
- uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
- uint res9[10]; /* reserved 10F0*/
- uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
- uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
- uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
- uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
- uint res10[7]; /* reserved 1128*/
- uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
- uint res11; /* reserved 1148*/
- uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
- uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
- uint res12[11]; /* reserved 1154*/
- uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
- uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
- uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
-} fec_t;
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+ u16 csar0; /* 0x00 Chip-Select Address Register 0 */
+ u16 res0;
+ u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
+ u16 res1; /* 0x08 */
+ u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
+
+ u16 csar1; /* 0x0C Chip-Select Address Register 1 */
+ u16 res2;
+ u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
+ u16 res3; /* 0x14 */
+ u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
+
+ u16 csar2; /* 0x18 Chip-Select Address Register 2 */
+ u16 res4;
+ u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
+ u16 res5; /* 0x20 */
+ u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
+
+ u16 csar3; /* 0x24 Chip-Select Address Register 3 */
+ u16 res6;
+ u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
+ u16 res7; /* 0x2C */
+ u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
+
+ u16 csar4; /* 0x30 Chip-Select Address Register 4 */
+ u16 res8;
+ u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
+ u16 res9; /* 0x38 */
+ u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
+
+ u16 csar5; /* 0x3C Chip-Select Address Register 5 */
+ u16 res10;
+ u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
+ u16 res11; /* 0x44 */
+ u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
+
+ u16 csar6; /* 0x48 Chip-Select Address Register 5 */
+ u16 res12;
+ u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
+ u16 res13; /* 0x50 */
+ u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
+
+ u16 csar7; /* 0x54 Chip-Select Address Register 5 */
+ u16 res14;
+ u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
+ u16 res15; /* 0x5C */
+ u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+ u16 syncr; /* 0x00 synthesizer control register */
+ u16 synsr; /* 0x02 synthesizer status register */
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ ushort wcr;
+ ushort wmr;
+ ushort wcntr;
+ ushort wsr;
+} wdog_t;
-#endif /* __IMMAP_5282__ */
+#endif /* __IMMAP_5282__ */
--- /dev/null
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5329__
+#define __IMMAP_5329__
+
+#define MMAP_SCM1 0xEC000000
+#define MMAP_MDHA 0xEC080000
+#define MMAP_SKHA 0xEC084000
+#define MMAP_RNG 0xEC088000
+#define MMAP_SCM2 0xFC000000
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_CAN 0xFC020000
+#define MMAP_FEC 0xFC030000
+#define MMAP_SCM3 0xFC040000
+#define MMAP_EDMA 0xFC044000
+#define MMAP_TCD 0xFC045000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_INTCACK 0xFC054000
+#define MMAP_I2C 0xFC058000
+#define MMAP_QSPI 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_PWM 0xFC090000
+#define MMAP_EPORT 0xFC094000
+#define MMAP_WDOG 0xFC098000
+#define MMAP_CCM 0xFC0A0000
+#define MMAP_GPIO 0xFC0A4000
+#define MMAP_RTC 0xFC0A8000
+#define MMAP_LCDC 0xFC0AC000
+#define MMAP_USBOTG 0xFC0B0000
+#define MMAP_USBH 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI 0xFC0BC000
+#define MMAP_PLL 0xFC0C0000
+
+/* System control module registers */
+typedef struct scm1_ctrl {
+ u32 mpr0; /* 0x00 Master Privilege Register 0 */
+ u32 res1[15]; /* 0x04 - 0x3F */
+ u32 pacrh; /* 0x40 Peripheral Access Control Register H */
+ u32 res2[3]; /* 0x44 - 0x53 */
+ u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
+} scm1_t;
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+ u32 mdmr; /* 0x00 MDHA Mode Register */
+ u32 mdcr; /* 0x04 Control register */
+ u32 mdcmr; /* 0x08 Command Register */
+ u32 mdsr; /* 0x0C Status Register */
+ u32 mdisr; /* 0x10 Interrupt Status Register */
+ u32 mdimr; /* 0x14 Interrupt Mask Register */
+ u32 mddsr; /* 0x1C Data Size Register */
+ u32 mdin; /* 0x20 Input FIFO */
+ u32 res1[3]; /* 0x24 - 0x2F */
+ u32 mdao; /* 0x30 Message Digest AO Register */
+ u32 mdbo; /* 0x34 Message Digest BO Register */
+ u32 mdco; /* 0x38 Message Digest CO Register */
+ u32 mddo; /* 0x3C Message Digest DO Register */
+ u32 mdeo; /* 0x40 Message Digest EO Register */
+ u32 mdmds; /* 0x44 Message Data Size Register */
+ u32 res[10]; /* 0x48 - 0x6F */
+ u32 mda1; /* 0x70 Message Digest A1 Register */
+ u32 mdb1; /* 0x74 Message Digest B1 Register */
+ u32 mdc1; /* 0x78 Message Digest C1 Register */
+ u32 mdd1; /* 0x7C Message Digest D1 Register */
+ u32 mde1; /* 0x80 Message Digest E1 Register */
+} mdha_t;
+
+/* Symmetric Key Hardware Accelerator */
+typedef struct skha_ctrl {
+ u32 mr; /* 0x00 Mode Register */
+ u32 cr; /* 0x04 Control Register */
+ u32 cmr; /* 0x08 Command Register */
+ u32 sr; /* 0x0C Status Register */
+ u32 esr; /* 0x10 Error Status Register */
+ u32 emr; /* 0x14 Error Status Mask Register) */
+ u32 ksr; /* 0x18 Key Size Register */
+ u32 dsr; /* 0x1C Data Size Register */
+ u32 in; /* 0x20 Input FIFO */
+ u32 out; /* 0x24 Output FIFO */
+ u32 res1[2]; /* 0x28 - 0x2F */
+ u32 kdr1; /* 0x30 Key Data Register 1 */
+ u32 kdr2; /* 0x34 Key Data Register 2 */
+ u32 kdr3; /* 0x38 Key Data Register 3 */
+ u32 kdr4; /* 0x3C Key Data Register 4 */
+ u32 kdr5; /* 0x40 Key Data Register 5 */
+ u32 kdr6; /* 0x44 Key Data Register 6 */
+ u32 res2[10]; /* 0x48 - 0x6F */
+ u32 c1; /* 0x70 Context 1 */
+ u32 c2; /* 0x74 Context 2 */
+ u32 c3; /* 0x78 Context 3 */
+ u32 c4; /* 0x7C Context 4 */
+ u32 c5; /* 0x80 Context 5 */
+ u32 c6; /* 0x84 Context 6 */
+ u32 c7; /* 0x88 Context 7 */
+ u32 c8; /* 0x8C Context 8 */
+ u32 c9; /* 0x90 Context 9 */
+ u32 c10; /* 0x94 Context 10 */
+ u32 c11; /* 0x98 Context 11 */
+} skha_t;
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+ u32 rngcr; /* 0x00 RNG Control Register */
+ u32 rngsr; /* 0x04 RNG Status Register */
+ u32 rnger; /* 0x08 RNG Entropy Register */
+ u32 rngout; /* 0x0C RNG Output FIFO */
+} rng_t;
+
+/* System control module registers 2 */
+typedef struct scm2_ctrl {
+ u32 mpr1; /* 0x00 Master Privilege Register */
+ u32 res1[7]; /* 0x04 - 0x1F */
+ u32 pacra; /* 0x20 Peripheral Access Control Register A */
+ u32 pacrb; /* 0x24 Peripheral Access Control Register B */
+ u32 pacrc; /* 0x28 Peripheral Access Control Register C */
+ u32 pacrd; /* 0x2C Peripheral Access Control Register D */
+ u32 res2[4]; /* 0x30 - 0x3F */
+ u32 pacre; /* 0x40 Peripheral Access Control Register E */
+ u32 pacrf; /* 0x44 Peripheral Access Control Register F */
+ u32 pacrg; /* 0x48 Peripheral Access Control Register G */
+ u32 res3[2]; /* 0x4C - 0x53 */
+ u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
+} scm2_t;
+
+/* Cross-Bar Switch Module */
+typedef struct xbs_ctrl {
+ u32 prs1; /* 0x100 Priority Register Slave 1 */
+ u32 res1[3]; /* 0x104 - 0F */
+ u32 crs1; /* 0x110 Control Register Slave 1 */
+ u32 res2[187]; /* 0x114 - 0x3FF */
+
+ u32 prs4; /* 0x400 Priority Register Slave 4 */
+ u32 res3[3]; /* 0x404 - 0F */
+ u32 crs4; /* 0x410 Control Register Slave 4 */
+ u32 res4[123]; /* 0x414 - 0x5FF */
+
+ u32 prs6; /* 0x600 Priority Register Slave 6 */
+ u32 res5[3]; /* 0x604 - 0F */
+ u32 crs6; /* 0x610 Control Register Slave 6 */
+ u32 res6[59]; /* 0x614 - 0x6FF */
+
+ u32 prs7; /* 0x700 Priority Register Slave 7 */
+ u32 res7[3]; /* 0x704 - 0F */
+ u32 crs7; /* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+ u16 csar0; /* 0x00 Chip-Select Address Register 0 */
+ u16 res0;
+ u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
+ u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
+
+ u16 csar1; /* 0x0C Chip-Select Address Register 1 */
+ u16 res1;
+ u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
+ u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
+
+ u16 csar2; /* 0x18 Chip-Select Address Register 2 */
+ u16 res2;
+ u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
+ u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
+
+ u16 csar3; /* 0x24 Chip-Select Address Register 3 */
+ u16 res3;
+ u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
+ u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
+
+ u16 csar4; /* 0x30 Chip-Select Address Register 4 */
+ u16 res4;
+ u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
+ u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
+
+ u16 csar5; /* 0x3C Chip-Select Address Register 5 */
+ u16 res5;
+ u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
+ u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* FlexCan module registers */
+typedef struct can_ctrl {
+ u32 mcr; /* 0x00 Module Configuration register */
+ u32 ctrl; /* 0x04 Control register */
+ u32 timer; /* 0x08 Free Running Timer */
+ u32 res1; /* 0x0C */
+ u32 rxgmask; /* 0x10 Rx Global Mask */
+ u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
+ u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
+ u32 errcnt; /* 0x1C Error Counter Register */
+ u32 errstat; /* 0x20 Error and status Register */
+ u32 res2; /* 0x24 */
+ u32 imask; /* 0x28 Interrupt Mask Register */
+ u32 res3; /* 0x2C */
+ u32 iflag; /* 0x30 Interrupt Flag Register */
+ u32 res4[19]; /* 0x34 - 0x7F */
+ u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* System Control Module register 3 */
+typedef struct scm3_ctrl {
+ u8 res1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 wakeup control register */
+ u16 res2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 Core Watchdog Control Register */
+ u8 res3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B Core Watchdog Service Register */
+ u8 res4[2]; /* 0x1C - 0x1D */
+ u8 scmisr; /* 0x1F Interrupt Status Register */
+ u32 res5; /* 0x20 */
+ u32 bcr; /* 0x24 Burst Configuration Register */
+ u32 res6[18]; /* 0x28 - 0x6F */
+ u32 cfadr; /* 0x70 Core Fault Address Register */
+ u8 res7[4]; /* 0x71 - 0x74 */
+ u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */
+ u8 cfloc; /* 0x76 Core Fault Location Register */
+ u8 cfatr; /* 0x77 Core Fault Attributes Register */
+ u32 res8; /* 0x78 */
+ u32 cfdtr; /* 0x7C Core Fault Data Register */
+} scm3_t;
+
+/* eDMA module registers */
+typedef struct edma_ctrl {
+ u32 cr; /* 0x00 Control Register */
+ u32 es; /* 0x04 Error Status Register */
+ u16 res1[3]; /* 0x08 - 0x0D */
+ u16 erq; /* 0x0E Enable Request Register */
+ u16 res2[3]; /* 0x10 - 0x15 */
+ u16 eei; /* 0x16 Enable Error Interrupt Request */
+ u8 serq; /* 0x18 Set Enable Request */
+ u8 cerq; /* 0x19 Clear Enable Request */
+ u8 seei; /* 0x1A Set Enable Error Interrupt Request */
+ u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */
+ u8 cint; /* 0x1C Clear Interrupt Enable Register */
+ u8 cerr; /* 0x1D Clear Error Register */
+ u8 ssrt; /* 0x1E Set START Bit Register */
+ u8 cdne; /* 0x1F Clear DONE Status Bit Register */
+ u16 res3[3]; /* 0x20 - 0x25 */
+ u16 intr; /* 0x26 Interrupt Request Register */
+ u16 res4[3]; /* 0x28 - 0x2D */
+ u16 err; /* 0x2E Error Register */
+ u32 res5[52]; /* 0x30 - 0xFF */
+ u8 dchpri0; /* 0x100 Channel 0 Priority Register */
+ u8 dchpri1; /* 0x101 Channel 1 Priority Register */
+ u8 dchpri2; /* 0x102 Channel 2 Priority Register */
+ u8 dchpri3; /* 0x103 Channel 3 Priority Register */
+ u8 dchpri4; /* 0x104 Channel 4 Priority Register */
+ u8 dchpri5; /* 0x105 Channel 5 Priority Register */
+ u8 dchpri6; /* 0x106 Channel 6 Priority Register */
+ u8 dchpri7; /* 0x107 Channel 7 Priority Register */
+ u8 dchpri8; /* 0x108 Channel 8 Priority Register */
+ u8 dchpri9; /* 0x109 Channel 9 Priority Register */
+ u8 dchpri10; /* 0x110 Channel 10 Priority Register */
+ u8 dchpri11; /* 0x111 Channel 11 Priority Register */
+ u8 dchpri12; /* 0x112 Channel 12 Priority Register */
+ u8 dchpri13; /* 0x113 Channel 13 Priority Register */
+ u8 dchpri14; /* 0x114 Channel 14 Priority Register */
+ u8 dchpri15; /* 0x115 Channel 15 Priority Register */
+} edma_t;
+
+/* TCD - eDMA*/
+typedef struct tcd_ctrl {
+ u32 saddr; /* 0x00 Source Address */
+ u16 attr; /* 0x04 Transfer Attributes */
+ u16 soff; /* 0x06 Signed Source Address Offset */
+ u32 nbytes; /* 0x08 Minor Byte Count */
+ u32 slast; /* 0x0C Last Source Address Adjustment */
+ u32 daddr; /* 0x10 Destination address */
+ u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */
+ u16 doff; /* 0x16 Signed Destination Address Offset */
+ u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
+ u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */
+ u16 csr; /* 0x1E Control and Status */
+} tcd_st;
+
+typedef struct tcd_multiple {
+ tcd_st tcd[16];
+} tcd_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 - 0x19 */
+ u16 icfg0; /* 0x1A Configuration Register */
+ u8 simr0; /* 0x1C Set Interrupt Mask */
+ u8 cimr0; /* 0x1D Clear Interrupt Mask */
+ u8 clmask0; /* 0x1E Current Level Mask */
+ u8 slmask; /* 0x1F Saved Level Mask */
+ u32 res2[8]; /* 0x20 - 0x3F */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending Register High */
+ u32 iprl1; /* 0x04 Pending Register Low */
+ u32 imrh1; /* 0x08 Mask Register High */
+ u32 imrl1; /* 0x0C Mask Register Low */
+ u32 frch1; /* 0x10 Force Register High */
+ u32 frcl1; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 */
+ u16 icfg1; /* 0x1A Configuration Register */
+ u8 simr1; /* 0x1C Set Interrupt Mask */
+ u8 cimr1; /* 0x1D Clear Interrupt Mask */
+ u16 res2; /* 0x1E - 0x1F */
+ u32 res3[8]; /* 0x20 - 0x3F */
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+ /* Global IACK Registers */
+ u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
+ u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
+} intgack_t;
+
+/*I2C module registers */
+typedef struct i2c_ctrl {
+ u8 adr; /* 0x00 address register */
+ u8 res1[3]; /* 0x01 - 0x03 */
+ u8 fdr; /* 0x04 frequency divider register */
+ u8 res2[3]; /* 0x05 - 0x07 */
+ u8 cr; /* 0x08 control register */
+ u8 res3[3]; /* 0x09 - 0x0B */
+ u8 sr; /* 0x0C status register */
+ u8 res4[3]; /* 0x0D - 0x0F */
+ u8 dr; /* 0x10 data register */
+ u8 res5[3]; /* 0x11 - 0x13 */
+} i2c_t;
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ u16 qmr; /* Mode register */
+ u16 res1;
+ u16 qdlyr; /* Delay register */
+ u16 res2;
+ u16 qwr; /* Wrap register */
+ u16 res3;
+ u16 qir; /* Interrupt register */
+ u16 res4;
+ u16 qar; /* Address register */
+ u16 res5;
+ u16 qdr; /* Data register */
+ u16 res6;
+} qspi_t;
+
+/* PWM module registers */
+typedef struct pwm_ctrl {
+ u8 en; /* 0x00 PWM Enable Register */
+ u8 pol; /* 0x01 Polarity Register */
+ u8 clk; /* 0x02 Clock Select Register */
+ u8 prclk; /* 0x03 Prescale Clock Select Register */
+ u8 cae; /* 0x04 Center Align Enable Register */
+ u8 ctl; /* 0x05 Control Register */
+ u8 res1[2]; /* 0x06 - 0x07 */
+ u8 scla; /* 0x08 Scale A register */
+ u8 sclb; /* 0x09 Scale B register */
+ u8 res2[2]; /* 0x0A - 0x0B */
+ u8 cnt0; /* 0x0C Channel 0 Counter register */
+ u8 cnt1; /* 0x0D Channel 1 Counter register */
+ u8 cnt2; /* 0x0E Channel 2 Counter register */
+ u8 cnt3; /* 0x0F Channel 3 Counter register */
+ u8 cnt4; /* 0x10 Channel 4 Counter register */
+ u8 cnt5; /* 0x11 Channel 5 Counter register */
+ u8 cnt6; /* 0x12 Channel 6 Counter register */
+ u8 cnt7; /* 0x13 Channel 7 Counter register */
+ u8 per0; /* 0x14 Channel 0 Period register */
+ u8 per1; /* 0x15 Channel 1 Period register */
+ u8 per2; /* 0x16 Channel 2 Period register */
+ u8 per3; /* 0x17 Channel 3 Period register */
+ u8 per4; /* 0x18 Channel 4 Period register */
+ u8 per5; /* 0x19 Channel 5 Period register */
+ u8 per6; /* 0x1A Channel 6 Period register */
+ u8 per7; /* 0x1B Channel 7 Period register */
+ u8 dty0; /* 0x1C Channel 0 Duty register */
+ u8 dty1; /* 0x1D Channel 1 Duty register */
+ u8 dty2; /* 0x1E Channel 2 Duty register */
+ u8 dty3; /* 0x1F Channel 3 Duty register */
+ u8 dty4; /* 0x20 Channel 4 Duty register */
+ u8 dty5; /* 0x21 Channel 5 Duty register */
+ u8 dty6; /* 0x22 Channel 6 Duty register */
+ u8 dty7; /* 0x23 Channel 7 Duty register */
+ u8 sdn; /* 0x24 Shutdown register */
+ u8 res3[3]; /* 0x25 - 0x27 */
+} pwm_t;
+
+/* Edge Port module registers */
+typedef struct eport_ctrl {
+ u16 par; /* 0x00 Pin Assignment Register */
+ u8 ddar; /* 0x02 Data Direction Register */
+ u8 ier; /* 0x03 Interrupt Enable Register */
+ u8 dr; /* 0x04 Data Register */
+ u8 pdr; /* 0x05 Pin Data Register */
+ u8 fr; /* 0x06 Flag_Register */
+ u8 res1;
+} eport_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ u16 cr; /* 0x00 Control register */
+ u16 mr; /* 0x02 Modulus register */
+ u16 cntr; /* 0x04 Count register */
+ u16 sr; /* 0x06 Service register */
+} wdog_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+ u8 rstctrl; /* 0x00 Reset Controller register */
+ u8 rststat; /* 0x01 Reset Status register */
+ u16 res1; /* 0x02 - 0x03 */
+ u16 ccr; /* 0x04 Chip configuration register */
+ u16 res2; /* 0x06 */
+ u16 rcon; /* 0x08 Rreset configuration register */
+ u16 cir; /* 0x0A Chip identification register */
+ u32 res3; /* 0x0C */
+ u16 misccr; /* 0x10 Miscellaneous control register */
+ u16 cdr; /* 0x12 Clock divider register */
+ u16 uhcsr; /* 0x14 USB Host controller status register */
+ u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
+} ccm_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_fech; /* 0x00 */
+ u8 podr_fecl; /* 0x01 */
+ u8 podr_ssi; /* 0x02 */
+ u8 podr_busctl; /* 0x03 */
+ u8 podr_be; /* 0x04 */
+ u8 podr_cs; /* 0x05 */
+ u8 podr_pwm; /* 0x06 */
+ u8 podr_feci2c; /* 0x07 */
+ u8 res1; /* 0x08 */
+ u8 podr_uart; /* 0x09 */
+ u8 podr_qspi; /* 0x0A */
+ u8 podr_timer; /* 0x0B */
+ u8 res2; /* 0x0C */
+ u8 podr_lcddatah; /* 0x0D */
+ u8 podr_lcddatam; /* 0x0E */
+ u8 podr_lcddatal; /* 0x0F */
+ u8 podr_lcdctlh; /* 0x10 */
+ u8 podr_lcdctll; /* 0x11 */
+
+ /* Port Data Direction Registers */
+ u16 res3; /* 0x12 - 0x13 */
+ u8 pddr_fech; /* 0x14 */
+ u8 pddr_fecl; /* 0x15 */
+ u8 pddr_ssi; /* 0x16 */
+ u8 pddr_busctl; /* 0x17 */
+ u8 pddr_be; /* 0x18 */
+ u8 pddr_cs; /* 0x19 */
+ u8 pddr_pwm; /* 0x1A */
+ u8 pddr_feci2c; /* 0x1B */
+ u8 res4; /* 0x1C */
+ u8 pddr_uart; /* 0x1D */
+ u8 pddr_qspi; /* 0x1E */
+ u8 pddr_timer; /* 0x1F */
+ u8 res5; /* 0x20 */
+ u8 pddr_lcddatah; /* 0x21 */
+ u8 pddr_lcddatam; /* 0x22 */
+ u8 pddr_lcddatal; /* 0x23 */
+ u8 pddr_lcdctlh; /* 0x24 */
+ u8 pddr_lcdctll; /* 0x25 */
+ u16 res6; /* 0x26 - 0x27 */
+
+ /* Port Data Direction Registers */
+ u8 ppd_fech; /* 0x28 */
+ u8 ppd_fecl; /* 0x29 */
+ u8 ppd_ssi; /* 0x2A */
+ u8 ppd_busctl; /* 0x2B */
+ u8 ppd_be; /* 0x2C */
+ u8 ppd_cs; /* 0x2D */
+ u8 ppd_pwm; /* 0x2E */
+ u8 ppd_feci2c; /* 0x2F */
+ u8 res7; /* 0x30 */
+ u8 ppd_uart; /* 0x31 */
+ u8 ppd_qspi; /* 0x32 */
+ u8 ppd_timer; /* 0x33 */
+ u8 res8; /* 0x34 */
+ u8 ppd_lcddatah; /* 0x35 */
+ u8 ppd_lcddatam; /* 0x36 */
+ u8 ppd_lcddatal; /* 0x37 */
+ u8 ppd_lcdctlh; /* 0x38 */
+ u8 ppd_lcdctll; /* 0x39 */
+ u16 res9; /* 0x3A - 0x3B */
+
+ /* Port Clear Output Data Registers */
+ u8 pclrr_fech; /* 0x3C */
+ u8 pclrr_fecl; /* 0x3D */
+ u8 pclrr_ssi; /* 0x3E */
+ u8 pclrr_busctl; /* 0x3F */
+ u8 pclrr_be; /* 0x40 */
+ u8 pclrr_cs; /* 0x41 */
+ u8 pclrr_pwm; /* 0x42 */
+ u8 pclrr_feci2c; /* 0x43 */
+ u8 res10; /* 0x44 */
+ u8 pclrr_uart; /* 0x45 */
+ u8 pclrr_qspi; /* 0x46 */
+ u8 pclrr_timer; /* 0x47 */
+ u8 res11; /* 0x48 */
+ u8 pclrr_lcddatah; /* 0x49 */
+ u8 pclrr_lcddatam; /* 0x4A */
+ u8 pclrr_lcddatal; /* 0x4B */
+ u8 pclrr_lcdctlh; /* 0x4C */
+ u8 pclrr_lcdctll; /* 0x4D */
+ u16 res12; /* 0x4E - 0x4F */
+
+ /* Pin Assignment Registers */
+ u8 par_fec; /* 0x50 */
+ u8 par_pwm; /* 0x51 */
+ u8 par_busctl; /* 0x52 */
+ u8 par_feci2c; /* 0x53 */
+ u8 par_be; /* 0x54 */
+ u8 par_cs; /* 0x55 */
+ u16 par_ssi; /* 0x56 */
+ u16 par_uart; /* 0x58 */
+ u16 par_qspi; /* 0x5A */
+ u8 par_timer; /* 0x5C */
+ u8 par_lcddata; /* 0x5D */
+ u16 par_lcdctl; /* 0x5E */
+ u16 par_irq; /* 0x60 */
+ u16 res16; /* 0x62 - 0x63 */
+
+ /* Mode Select Control Registers */
+ u8 mscr_flexbus; /* 0x64 */
+ u8 mscr_sdram; /* 0x65 */
+ u16 res17; /* 0x66 - 0x67 */
+
+ /* Drive Strength Control Registers */
+ u8 dscr_i2c; /* 0x68 */
+ u8 dscr_pwm; /* 0x69 */
+ u8 dscr_fec; /* 0x6A */
+ u8 dscr_uart; /* 0x6B */
+ u8 dscr_qspi; /* 0x6C */
+ u8 dscr_timer; /* 0x6D */
+ u8 dscr_ssi; /* 0x6E */
+ u8 dscr_lcd; /* 0x6F */
+ u8 dscr_debug; /* 0x70 */
+ u8 dscr_clkrst; /* 0x71 */
+ u8 dscr_irq; /* 0x72 */
+} gpio_t;
+
+/* LCD module registers */
+typedef struct lcd_ctrl {
+ u32 ssar; /* 0x00 Screen Start Address Register */
+ u32 sr; /* 0x04 LCD Size Register */
+ u32 vpw; /* 0x08 Virtual Page Width Register */
+ u32 cpr; /* 0x0C Cursor Position Register */
+ u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
+ u32 ccmr; /* 0x14 Color Cursor Mapping Register */
+ u32 pcr; /* 0x18 Panel Configuration Register */
+ u32 hcr; /* 0x1C Horizontal Configuration Register */
+ u32 vcr; /* 0x20 Vertical Configuration Register */
+ u32 por; /* 0x24 Panning Offset Register */
+ u32 scr; /* 0x28 Sharp Configuration Register */
+ u32 pccr; /* 0x2C PWM Contrast Control Register */
+ u32 dcr; /* 0x30 DMA Control Register */
+ u32 rmcr; /* 0x34 Refresh Mode Control Register */
+ u32 icr; /* 0x38 Refresh Mode Control Register */
+ u32 ier; /* 0x3C Interrupt Enable Register */
+ u32 isr; /* 0x40 Interrupt Status Register */
+ u32 res[4];
+ u32 gwsar; /* 0x50 Graphic Window Start Address Register */
+ u32 gwsr; /* 0x54 Graphic Window Size Register */
+ u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
+ u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
+ u32 gwpr; /* 0x60 Graphic Window Position Register */
+ u32 gwcr; /* 0x64 Graphic Window Control Register */
+ u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
+} lcd_t;
+
+typedef struct lcdbg_ctrl {
+ u32 bglut[255];
+} lcdbg_t;
+
+typedef struct lcdgw_ctrl {
+ u32 gwlut[255];
+} lcdgw_t;
+
+/* USB OTG module registers */
+typedef struct usb_otg {
+ u32 id; /* 0x000 Identification Register */
+ u32 hwgeneral; /* 0x004 General HW Parameters */
+ u32 hwhost; /* 0x008 Host HW Parameters */
+ u32 hwdev; /* 0x00C Device HW parameters */
+ u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
+ u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
+ u32 res1[58]; /* 0x18 - 0xFF */
+ u8 caplength; /* 0x100 Capability Register Length */
+ u8 res2; /* 0x101 */
+ u16 hciver; /* 0x102 Host Interface Version Number */
+ u32 hcsparams; /* 0x104 Host Structural Parameters */
+ u32 hccparams; /* 0x108 Host Capability Parameters */
+ u32 res3[5]; /* 0x10C - 0x11F */
+ u16 dciver; /* 0x120 Device Interface Version Number */
+ u16 res4; /* 0x122 */
+ u32 dccparams; /* 0x124 Device Capability Parameters */
+ u32 res5[6]; /* 0x128 - 0x13F */
+ u32 cmd; /* 0x140 USB Command */
+ u32 sts; /* 0x144 USB Status */
+ u32 intr; /* 0x148 USB Interrupt Enable */
+ u32 frindex; /* 0x14C USB Frame Index */
+ u32 res6; /* 0x150 */
+ u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
+ u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
+ u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
+ u32 burstsize; /* 0x160 Master Interface Data Burst Size */
+ u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
+ u32 res7[6]; /* 0x168 - 0x17F */
+ u32 cfgflag; /* 0x180 Configure Flag Register */
+ u32 portsc1; /* 0x184 Port Status/Control */
+ u32 res8[7]; /* 0x188 - 0x1A3 */
+ u32 otgsc; /* 0x1A4 On The Go Status and Control */
+ u32 mode; /* 0x1A8 USB mode register */
+ u32 eptsetstat; /* 0x1AC Endpoint Setup status */
+ u32 eptprime; /* 0x1B0 Endpoint initialization */
+ u32 eptflush; /* 0x1B4 Endpoint de-initialize */
+ u32 eptstat; /* 0x1B8 Endpoint status */
+ u32 eptcomplete; /* 0x1BC Endpoint Complete */
+ u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
+ u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
+ u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
+ u32 eptctrl3; /* 0x1CC Endpoint control 3 */
+} usbotg_t;
+
+/* USB Host module registers */
+typedef struct usb_host {
+ u32 id; /* 0x000 Identification Register */
+ u32 hwgeneral; /* 0x004 General HW Parameters */
+ u32 hwhost; /* 0x008 Host HW Parameters */
+ u32 res1; /* 0x0C */
+ u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
+ u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
+ u32 res2[58]; /* 0x18 - 0xFF */
+
+ /* Host Controller Capability Register */
+ u8 caplength; /* 0x100 Capability Register Length */
+ u8 res3; /* 0x101 */
+ u16 hciver; /* 0x102 Host Interface Version Number */
+ u32 hcsparams; /* 0x104 Host Structural Parameters */
+ u32 hccparams; /* 0x108 Host Capability Parameters */
+ u32 res4[13]; /* 0x10C - 0x13F */
+
+ /* Host Controller Operational Register */
+ u32 cmd; /* 0x140 USB Command */
+ u32 sts; /* 0x144 USB Status */
+ u32 intr; /* 0x148 USB Interrupt Enable */
+ u32 frindex; /* 0x14C USB Frame Index */
+ u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
+ u32 prdlst; /* 0x154 Periodic Frame List Base Address */
+ u32 aynclst; /* 0x158 Current Asynchronous List Address */
+ u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
+ u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
+ u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
+ u32 res6[6]; /* 0x168 - 0x17F */
+ u32 cfgflag; /* 0x180 Configure Flag Register */
+ u32 portsc1; /* 0x184 Port Status/Control */
+ u32 res7[8]; /* 0x188 - 0x1A7 */
+
+ /* non-ehci registers */
+ u32 mode; /* 0x1A8 USB mode register */
+ u32 eptsetstat; /* 0x1AC Endpoint Setup status */
+ u32 eptprime; /* 0x1B0 Endpoint initialization */
+ u32 eptflush; /* 0x1B4 Endpoint de-initialize */
+ u32 eptstat; /* 0x1B8 Endpoint status */
+ u32 eptcomplete; /* 0x1BC Endpoint Complete */
+ u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
+ u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
+ u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
+ u32 eptctrl3; /* 0x1CC Endpoint control 3 */
+} usbhost_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+ u32 mode; /* 0x00 Mode/Extended Mode register */
+ u32 ctrl; /* 0x04 Control register */
+ u32 cfg1; /* 0x08 Configuration register 1 */
+ u32 cfg2; /* 0x0C Configuration register 2 */
+ u32 res1[64]; /* 0x10 - 0x10F */
+ u32 cs0; /* 0x110 Chip Select 0 Configuration */
+ u32 cs1; /* 0x114 Chip Select 1 Configuration */
+} sdram_t;
+
+/* Synchronous serial interface */
+typedef struct ssi_ctrl {
+ u32 tx0; /* 0x00 Transmit Data Register 0 */
+ u32 tx1; /* 0x04 Transmit Data Register 1 */
+ u32 rx0; /* 0x08 Receive Data Register 0 */
+ u32 rx1; /* 0x0C Receive Data Register 1 */
+ u32 cr; /* 0x10 Control Register */
+ u32 isr; /* 0x14 Interrupt Status Register */
+ u32 ier; /* 0x18 Interrupt Enable Register */
+ u32 tcr; /* 0x1C Transmit Configuration Register */
+ u32 rcr; /* 0x20 Receive Configuration Register */
+ u32 ccr; /* 0x24 Clock Control Register */
+ u32 res1; /* 0x28 */
+ u32 fcsr; /* 0x2C FIFO Control/Status Register */
+ u32 res2[2]; /* 0x30 - 0x37 */
+ u32 acr; /* 0x38 AC97 Control Register */
+ u32 acadd; /* 0x3C AC97 Command Address Register */
+ u32 acdat; /* 0x40 AC97 Command Data Register */
+ u32 atag; /* 0x44 AC97 Tag Register */
+ u32 tmask; /* 0x48 Transmit Time Slot Mask Register */
+ u32 rmask; /* 0x4C Receive Time Slot Mask Register */
+} ssi_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+ u8 podr; /* 0x00 Output Divider Register */
+ u8 res1[3];
+ u8 pcr; /* 0x04 Control Register */
+ u8 res2[3];
+ u8 pmdr; /* 0x08 Modulation Divider Register */
+ u8 res3[3];
+ u8 pfdr; /* 0x0C Feedback Divider Register */
+ u8 res4[3];
+} pll_t;
+
+#endif /* __IMMAP_5329__ */
--- /dev/null
+/*
+ * MCF5445x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5445X__
+#define __IMMAP_5445X__
+
+/* Module Base Addresses */
+#define MMAP_SCM1 0xFC000000
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_FEC0 0xFC030000
+#define MMAP_FEC1 0xFC034000
+#define MMAP_RTC 0xFC03C000
+#define MMAP_EDMA 0xFC044000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_IACK 0xFC054000
+#define MMAP_I2C 0xFC058000
+#define MMAP_DSPI 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_EPORT 0xFC094000
+#define MMAP_WTM 0xFC098000
+#define MMAP_SBF 0xFC0A0000
+#define MMAP_RCM 0xFC0A0000
+#define MMAP_CCM 0xFC0A0000
+#define MMAP_GPIO 0xFC0A4000
+#define MMAP_PCI 0xFC0A8000
+#define MMAP_PCIARB 0xFC0AC000
+#define MMAP_RNG 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI 0xFC0BC000
+#define MMAP_PLL 0xFC0C4000
+#define MMAP_ATA 0x90000000
+
+/*********************************************************************
+* ATA
+*********************************************************************/
+
+typedef struct atac {
+ /* PIO */
+ u8 toff; /* 0x00 */
+ u8 ton; /* 0x01 */
+ u8 t1; /* 0x02 */
+ u8 t2w; /* 0x03 */
+ u8 t2r; /* 0x04 */
+ u8 ta; /* 0x05 */
+ u8 trd; /* 0x06 */
+ u8 t4; /* 0x07 */
+ u8 t9; /* 0x08 */
+
+ /* DMA */
+ u8 tm; /* 0x09 */
+ u8 tn; /* 0x0A */
+ u8 td; /* 0x0B */
+ u8 tk; /* 0x0C */
+ u8 tack; /* 0x0D */
+ u8 tenv; /* 0x0E */
+ u8 trp; /* 0x0F */
+ u8 tzah; /* 0x10 */
+ u8 tmli; /* 0x11 */
+ u8 tdvh; /* 0x12 */
+ u8 tdzfs; /* 0x13 */
+ u8 tdvs; /* 0x14 */
+ u8 tcvh; /* 0x15 */
+ u8 tss; /* 0x16 */
+ u8 tcyc; /* 0x17 */
+
+ /* FIFO */
+ u32 fifo32; /* 0x18 */
+ u16 fifo16; /* 0x1C */
+ u8 rsvd0[2];
+ u8 ffill; /* 0x20 */
+ u8 rsvd1[3];
+
+ /* ATA */
+ u8 cr; /* 0x24 */
+ u8 rsvd2[3];
+ u8 isr; /* 0x28 */
+ u8 rsvd3[3];
+ u8 ier; /* 0x2C */
+ u8 rsvd4[3];
+ u8 icr; /* 0x30 */
+ u8 rsvd5[3];
+ u8 falarm; /* 0x34 */
+ u8 rsvd6[106];
+} atac_t;
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+
+typedef struct xbs {
+ u8 resv0[0x100];
+ u32 prs1; /* XBS Priority Register */
+ u8 resv1[0xC];
+ u32 crs1; /* XBS Control Register */
+ u8 resv2[0xEC];
+ u32 prs2; /* XBS Priority Register */
+ u8 resv3[0xC];
+ u32 crs2; /* XBS Control Register */
+ u8 resv4[0xEC];
+ u32 prs3; /* XBS Priority Register */
+ u8 resv5[0xC];
+ u32 crs3; /* XBS Control Register */
+ u8 resv6[0xEC];
+ u32 prs4; /* XBS Priority Register */
+ u8 resv7[0xC];
+ u32 crs4; /* XBS Control Register */
+ u8 resv8[0xEC];
+ u32 prs5; /* XBS Priority Register */
+ u8 resv9[0xC];
+ u32 crs5; /* XBS Control Register */
+ u8 resv10[0xEC];
+ u32 prs6; /* XBS Priority Register */
+ u8 resv11[0xC];
+ u32 crs6; /* XBS Control Register */
+ u8 resv12[0xEC];
+ u32 prs7; /* XBS Priority Register */
+ u8 resv13[0xC];
+ u32 crs7; /* XBS Control Register */
+} xbs_t;
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+
+typedef struct fbcs {
+ u32 csar0; /* Chip-select Address Register */
+ u32 csmr0; /* Chip-select Mask Register */
+ u32 cscr0; /* Chip-select Control Register */
+ u32 csar1; /* Chip-select Address Register */
+ u32 csmr1; /* Chip-select Mask Register */
+ u32 cscr1; /* Chip-select Control Register */
+ u32 csar2; /* Chip-select Address Register */
+ u32 csmr2; /* Chip-select Mask Register */
+ u32 cscr2; /* Chip-select Control Register */
+ u32 csar3; /* Chip-select Address Register */
+ u32 csmr3; /* Chip-select Mask Register */
+ u32 cscr3; /* Chip-select Control Register */
+} fbcs_t;
+
+/*********************************************************************
+* Enhanced DMA (EDMA)
+*********************************************************************/
+
+typedef struct edma {
+ u32 cr;
+ u32 es;
+ u8 resv0[0x6];
+ u16 erq;
+ u8 resv1[0x6];
+ u16 eei;
+ u8 serq;
+ u8 cerq;
+ u8 seei;
+ u8 ceei;
+ u8 cint;
+ u8 cerr;
+ u8 ssrt;
+ u8 cdne;
+ u8 resv2[0x6];
+ u16 intr;
+ u8 resv3[0x6];
+ u16 err;
+ u8 resv4[0xD0];
+ u8 dchpri0;
+ u8 dchpri1;
+ u8 dchpri2;
+ u8 dchpri3;
+ u8 dchpri4;
+ u8 dchpri5;
+ u8 dchpri6;
+ u8 dchpri7;
+ u8 dchpri8;
+ u8 dchpri9;
+ u8 dchpri10;
+ u8 dchpri11;
+ u8 dchpri12;
+ u8 dchpri13;
+ u8 dchpri14;
+ u8 dchpri15;
+ u8 resv5[0xEF0];
+ u32 tcd0_saddr;
+ u16 tcd0_attr;
+ u16 tcd0_soff;
+ u32 tcd0_nbytes;
+ u32 tcd0_slast;
+ u32 tcd0_daddr;
+ union {
+ u16 tcd0_citer_elink;
+ u16 tcd0_citer;
+ };
+ u16 tcd0_doff;
+ u32 tcd0_dlast_sga;
+ union {
+ u16 tcd0_biter_elink;
+ u16 tcd0_biter;
+ };
+ u16 tcd0_csr;
+ u32 tcd1_saddr;
+ u16 tcd1_attr;
+ u16 tcd1_soff;
+ u32 tcd1_nbytes;
+ u32 tcd1_slast;
+ u32 tcd1_daddr;
+ union {
+ u16 tcd1_citer_elink;
+ u16 tcd1_citer;
+ };
+ u16 tcd1_doff;
+ u32 tcd1_dlast_sga;
+ union {
+ u16 tcd1_biter;
+ u16 tcd1_biter_elink;
+ };
+ u16 tcd1_csr;
+ u32 tcd2_saddr;
+ u16 tcd2_attr;
+ u16 tcd2_soff;
+ u32 tcd2_nbytes;
+ u32 tcd2_slast;
+ u32 tcd2_daddr;
+ union {
+ u16 tcd2_citer;
+ u16 tcd2_citer_elink;
+ };
+ u16 tcd2_doff;
+ u32 tcd2_dlast_sga;
+ union {
+ u16 tcd2_biter_elink;
+ u16 tcd2_biter;
+ };
+ u16 tcd2_csr;
+ u32 tcd3_saddr;
+ u16 tcd3_attr;
+ u16 tcd3_soff;
+ u32 tcd3_nbytes;
+ u32 tcd3_slast;
+ u32 tcd3_daddr;
+ union {
+ u16 tcd3_citer;
+ u16 tcd3_citer_elink;
+ };
+ u16 tcd3_doff;
+ u32 tcd3_dlast_sga;
+ union {
+ u16 tcd3_biter_elink;
+ u16 tcd3_biter;
+ };
+ u16 tcd3_csr;
+ u32 tcd4_saddr;
+ u16 tcd4_attr;
+ u16 tcd4_soff;
+ u32 tcd4_nbytes;
+ u32 tcd4_slast;
+ u32 tcd4_daddr;
+ union {
+ u16 tcd4_citer;
+ u16 tcd4_citer_elink;
+ };
+ u16 tcd4_doff;
+ u32 tcd4_dlast_sga;
+ union {
+ u16 tcd4_biter;
+ u16 tcd4_biter_elink;
+ };
+ u16 tcd4_csr;
+ u32 tcd5_saddr;
+ u16 tcd5_attr;
+ u16 tcd5_soff;
+ u32 tcd5_nbytes;
+ u32 tcd5_slast;
+ u32 tcd5_daddr;
+ union {
+ u16 tcd5_citer;
+ u16 tcd5_citer_elink;
+ };
+ u16 tcd5_doff;
+ u32 tcd5_dlast_sga;
+ union {
+ u16 tcd5_biter_elink;
+ u16 tcd5_biter;
+ };
+ u16 tcd5_csr;
+ u32 tcd6_saddr;
+ u16 tcd6_attr;
+ u16 tcd6_soff;
+ u32 tcd6_nbytes;
+ u32 tcd6_slast;
+ u32 tcd6_daddr;
+ union {
+ u16 tcd6_citer;
+ u16 tcd6_citer_elink;
+ };
+ u16 tcd6_doff;
+ u32 tcd6_dlast_sga;
+ union {
+ u16 tcd6_biter_elink;
+ u16 tcd6_biter;
+ };
+ u16 tcd6_csr;
+ u32 tcd7_saddr;
+ u16 tcd7_attr;
+ u16 tcd7_soff;
+ u32 tcd7_nbytes;
+ u32 tcd7_slast;
+ u32 tcd7_daddr;
+ union {
+ u16 tcd7_citer;
+ u16 tcd7_citer_elink;
+ };
+ u16 tcd7_doff;
+ u32 tcd7_dlast_sga;
+ union {
+ u16 tcd7_biter_elink;
+ u16 tcd7_biter;
+ };
+ u16 tcd7_csr;
+ u32 tcd8_saddr;
+ u16 tcd8_attr;
+ u16 tcd8_soff;
+ u32 tcd8_nbytes;
+ u32 tcd8_slast;
+ u32 tcd8_daddr;
+ union {
+ u16 tcd8_citer;
+ u16 tcd8_citer_elink;
+ };
+ u16 tcd8_doff;
+ u32 tcd8_dlast_sga;
+ union {
+ u16 tcd8_biter_elink;
+ u16 tcd8_biter;
+ };
+ u16 tcd8_csr;
+ u32 tcd9_saddr;
+ u16 tcd9_attr;
+ u16 tcd9_soff;
+ u32 tcd9_nbytes;
+ u32 tcd9_slast;
+ u32 tcd9_daddr;
+ union {
+ u16 tcd9_citer_elink;
+ u16 tcd9_citer;
+ };
+ u16 tcd9_doff;
+ u32 tcd9_dlast_sga;
+ union {
+ u16 tcd9_biter_elink;
+ u16 tcd9_biter;
+ };
+ u16 tcd9_csr;
+ u32 tcd10_saddr;
+ u16 tcd10_attr;
+ u16 tcd10_soff;
+ u32 tcd10_nbytes;
+ u32 tcd10_slast;
+ u32 tcd10_daddr;
+ union {
+ u16 tcd10_citer_elink;
+ u16 tcd10_citer;
+ };
+ u16 tcd10_doff;
+ u32 tcd10_dlast_sga;
+ union {
+ u16 tcd10_biter;
+ u16 tcd10_biter_elink;
+ };
+ u16 tcd10_csr;
+ u32 tcd11_saddr;
+ u16 tcd11_attr;
+ u16 tcd11_soff;
+ u32 tcd11_nbytes;
+ u32 tcd11_slast;
+ u32 tcd11_daddr;
+ union {
+ u16 tcd11_citer;
+ u16 tcd11_citer_elink;
+ };
+ u16 tcd11_doff;
+ u32 tcd11_dlast_sga;
+ union {
+ u16 tcd11_biter;
+ u16 tcd11_biter_elink;
+ };
+ u16 tcd11_csr;
+ u32 tcd12_saddr;
+ u16 tcd12_attr;
+ u16 tcd12_soff;
+ u32 tcd12_nbytes;
+ u32 tcd12_slast;
+ u32 tcd12_daddr;
+ union {
+ u16 tcd12_citer;
+ u16 tcd12_citer_elink;
+ };
+ u16 tcd12_doff;
+ u32 tcd12_dlast_sga;
+ union {
+ u16 tcd12_biter;
+ u16 tcd12_biter_elink;
+ };
+ u16 tcd12_csr;
+ u32 tcd13_saddr;
+ u16 tcd13_attr;
+ u16 tcd13_soff;
+ u32 tcd13_nbytes;
+ u32 tcd13_slast;
+ u32 tcd13_daddr;
+ union {
+ u16 tcd13_citer_elink;
+ u16 tcd13_citer;
+ };
+ u16 tcd13_doff;
+ u32 tcd13_dlast_sga;
+ union {
+ u16 tcd13_biter_elink;
+ u16 tcd13_biter;
+ };
+ u16 tcd13_csr;
+ u32 tcd14_saddr;
+ u16 tcd14_attr;
+ u16 tcd14_soff;
+ u32 tcd14_nbytes;
+ u32 tcd14_slast;
+ u32 tcd14_daddr;
+ union {
+ u16 tcd14_citer;
+ u16 tcd14_citer_elink;
+ };
+ u16 tcd14_doff;
+ u32 tcd14_dlast_sga;
+ union {
+ u16 tcd14_biter_elink;
+ u16 tcd14_biter;
+ };
+ u16 tcd14_csr;
+ u32 tcd15_saddr;
+ u16 tcd15_attr;
+ u16 tcd15_soff;
+ u32 tcd15_nbytes;
+ u32 tcd15_slast;
+ u32 tcd15_daddr;
+ union {
+ u16 tcd15_citer_elink;
+ u16 tcd15_citer;
+ };
+ u16 tcd15_doff;
+ u32 tcd15_dlast_sga;
+ union {
+ u16 tcd15_biter;
+ u16 tcd15_biter_elink;
+ };
+ u16 tcd15_csr;
+} edma_t;
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+
+typedef struct int0_ctrl {
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 - 0x19 */
+ u16 icfg0; /* 0x1A Configuration Register */
+ u8 simr0; /* 0x1C Set Interrupt Mask */
+ u8 cimr0; /* 0x1D Clear Interrupt Mask */
+ u8 clmask0; /* 0x1E Current Level Mask */
+ u8 slmask; /* 0x1F Saved Level Mask */
+ u32 res2[8]; /* 0x20 - 0x3F */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending Register High */
+ u32 iprl1; /* 0x04 Pending Register Low */
+ u32 imrh1; /* 0x08 Mask Register High */
+ u32 imrl1; /* 0x0C Mask Register Low */
+ u32 frch1; /* 0x10 Force Register High */
+ u32 frcl1; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 */
+ u16 icfg1; /* 0x1A Configuration Register */
+ u8 simr1; /* 0x1C Set Interrupt Mask */
+ u8 cimr1; /* 0x1D Clear Interrupt Mask */
+ u16 res2; /* 0x1E - 0x1F */
+ u32 res3[8]; /* 0x20 - 0x3F */
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+/*********************************************************************
+* Global Interrupt Acknowledge (IACK)
+*********************************************************************/
+
+typedef struct iack {
+ u8 resv0[0xE0];
+ u8 gswiack;
+ u8 resv1[0x3];
+ u8 gl1iack;
+ u8 resv2[0x3];
+ u8 gl2iack;
+ u8 resv3[0x3];
+ u8 gl3iack;
+ u8 resv4[0x3];
+ u8 gl4iack;
+ u8 resv5[0x3];
+ u8 gl5iack;
+ u8 resv6[0x3];
+ u8 gl6iack;
+ u8 resv7[0x3];
+ u8 gl7iack;
+} iack_t;
+
+/*********************************************************************
+* DMA Serial Peripheral Interface (DSPI)
+*********************************************************************/
+
+typedef struct dspi {
+ u32 dmcr;
+ u8 resv0[0x4];
+ u32 dtcr;
+ u32 dctar0;
+ u32 dctar1;
+ u32 dctar2;
+ u32 dctar3;
+ u32 dctar4;
+ u32 dctar5;
+ u32 dctar6;
+ u32 dctar7;
+ u32 dsr;
+ u32 dirsr;
+ u32 dtfr;
+ u32 drfr;
+ u32 dtfdr0;
+ u32 dtfdr1;
+ u32 dtfdr2;
+ u32 dtfdr3;
+ u8 resv1[0x30];
+ u32 drfdr0;
+ u32 drfdr1;
+ u32 drfdr2;
+ u32 drfdr3;
+} dspi_t;
+
+/*********************************************************************
+* Edge Port Module (EPORT)
+*********************************************************************/
+
+typedef struct eport {
+ u16 eppar;
+ u8 epddr;
+ u8 epier;
+ u8 epdr;
+ u8 eppdr;
+ u8 epfr;
+} eport_t;
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+
+typedef struct wtm {
+ u16 wcr;
+ u16 wmr;
+ u16 wcntr;
+ u16 wsr;
+} wtm_t;
+
+/*********************************************************************
+* Serial Boot Facility (SBF)
+*********************************************************************/
+
+typedef struct sbf {
+ u8 resv0[0x18];
+ u16 sbfsr; /* Serial Boot Facility Status Register */
+ u8 resv1[0x6];
+ u16 sbfcr; /* Serial Boot Facility Control Register */
+} sbf_t;
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+typedef struct ccm {
+ u8 ccm_resv0[0x4];
+ u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
+ u8 resv1[0x2];
+ u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
+ u16 cir; /* Chip Identification Register (Read-only) */
+ u8 resv2[0x4];
+ u16 misccr; /* Miscellaneous Control Register */
+ u16 cdr; /* Clock Divider Register */
+ u16 uocsr; /* USB On-the-Go Controller Status Register */
+} ccm_t;
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+
+typedef struct gpio {
+ u8 podr_fec0h; /* FEC0 High Port Output Data Register */
+ u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
+ u8 podr_ssi; /* SSI Port Output Data Register */
+ u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
+ u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
+ u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
+ u8 podr_dma; /* DMA Port Output Data Register */
+ u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
+ u8 resv0[0x1];
+ u8 podr_uart; /* UART Port Output Data Register */
+ u8 podr_dspi; /* DSPI Port Output Data Register */
+ u8 podr_timer; /* Timer Port Output Data Register */
+ u8 podr_pci; /* PCI Port Output Data Register */
+ u8 podr_usb; /* USB Port Output Data Register */
+ u8 podr_atah; /* ATA High Port Output Data Register */
+ u8 podr_atal; /* ATA Low Port Output Data Register */
+ u8 podr_fec1h; /* FEC1 High Port Output Data Register */
+ u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
+ u8 resv1[0x2];
+ u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
+ u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
+ u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
+ u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
+ u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
+ u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
+ u8 pddr_ssi; /* SSI Port Data Direction Register */
+ u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
+ u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
+ u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
+ u8 pddr_dma; /* DMA Port Data Direction Register */
+ u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
+ u8 resv2[0x1];
+ u8 pddr_uart; /* UART Port Data Direction Register */
+ u8 pddr_dspi; /* DSPI Port Data Direction Register */
+ u8 pddr_timer; /* Timer Port Data Direction Register */
+ u8 pddr_pci; /* PCI Port Data Direction Register */
+ u8 pddr_usb; /* USB Port Data Direction Register */
+ u8 pddr_atah; /* ATA High Port Data Direction Register */
+ u8 pddr_atal; /* ATA Low Port Data Direction Register */
+ u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
+ u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
+ u8 resv3[0x2];
+ u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
+ u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
+ u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
+ u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
+ u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
+ u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
+ u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
+ u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
+ u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
+ u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
+ u8 resv4[0x1];
+ u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
+ u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
+ u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
+ u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
+ u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
+ u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
+ u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
+ u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
+ u8 resv5[0x2];
+ u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
+ u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
+ u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
+ u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
+ u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
+ u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
+ u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
+ u8 pclrr_dma; /* DMA Port Clear Output Data Register */
+ u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
+ u8 resv6[0x1];
+ u8 pclrr_uart; /* UART Port Clear Output Data Register */
+ u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
+ u8 pclrr_timer; /* Timer Port Clear Output Data Register */
+ u8 pclrr_pci; /* PCI Port Clear Output Data Register */
+ u8 pclrr_usb; /* USB Port Clear Output Data Register */
+ u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
+ u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
+ u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
+ u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
+ u8 resv7[0x2];
+ u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
+ u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
+ u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
+ u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
+ u8 par_fec; /* FEC Pin Assignment Register */
+ u8 par_dma; /* DMA Pin Assignment Register */
+ u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
+ u8 par_dspi; /* DSPI Pin Assignment Register */
+ u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
+ u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
+ u8 par_timer; /* Time Pin Assignment Register */
+ u8 par_usb; /* USB Pin Assignment Register */
+ u8 resv8[0x1];
+ u8 par_uart; /* UART Pin Assignment Register */
+ u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
+ u16 par_ssi; /* SSI Pin Assignment Register */
+ u16 par_ata; /* ATA Pin Assignment Register */
+ u8 par_irq; /* IRQ Pin Assignment Register */
+ u8 resv9[0x1];
+ u16 par_pci; /* PCI Pin Assignment Register */
+ u8 mscr_sdram; /* SDRAM Mode Select Control Register */
+ u8 mscr_pci; /* PCI Mode Select Control Register */
+ u8 resv10[0x2];
+ u8 dscr_i2c; /* I2C Drive Strength Control Register */
+ u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
+ u8 dscr_fec; /* FEC Drive Strength Control Register */
+ u8 dscr_uart; /* UART Drive Strength Control Register */
+ u8 dscr_dspi; /* DSPI Drive Strength Control Register */
+ u8 dscr_timer; /* TIMER Drive Strength Control Register */
+ u8 dscr_ssi; /* SSI Drive Strength Control Register */
+ u8 dscr_dma; /* DMA Drive Strength Control Register */
+ u8 dscr_debug; /* DEBUG Drive Strength Control Register */
+ u8 dscr_reset; /* RESET Drive Strength Control Register */
+ u8 dscr_irq; /* IRQ Drive Strength Control Register */
+ u8 dscr_usb; /* USB Drive Strength Control Register */
+ u8 dscr_ata; /* ATA Drive Strength Control Register */
+} gpio_t;
+
+/*********************************************************************
+* Random Number Generator (RNG)
+*********************************************************************/
+
+typedef struct rng {
+ u32 rngcr;
+ u32 rngsr;
+ u32 rnger;
+ u32 rngout;
+} rng_t;
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+typedef struct sdramc {
+ u32 sdmr; /* SDRAM Mode/Extended Mode Register */
+ u32 sdcr; /* SDRAM Control Register */
+ u32 sdcfg1; /* SDRAM Configuration Register 1 */
+ u32 sdcfg2; /* SDRAM Chip Select Register */
+ u8 resv0[0x100];
+ u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
+ u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
+} sdramc_t;
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+
+typedef struct ssi {
+ u32 tx0;
+ u32 tx1;
+ u32 rx0;
+ u32 rx1;
+ u32 cr;
+ u32 isr;
+ u32 ier;
+ u32 tcr;
+ u32 rcr;
+ u32 ccr;
+ u8 resv0[0x4];
+ u32 fcsr;
+ u8 resv1[0x8];
+ u32 acr;
+ u32 acadd;
+ u32 acdat;
+ u32 atag;
+ u32 tmask;
+ u32 rmask;
+} ssi_t;
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+typedef struct pll {
+ u32 pcr; /* PLL Control Register */
+ u32 psr; /* PLL Status Register */
+} pll_t;
+
+typedef struct pci {
+ u32 idr; /* 0x00 Device Id / Vendor Id Register */
+ u32 scr; /* 0x04 Status / command Register */
+ u32 ccrir; /* 0x08 Class Code / Revision Id Register */
+ u32 cr1; /* 0x0c Configuration 1 Register */
+ u32 bar0; /* 0x10 Base address register 0 Register */
+ u32 bar1; /* 0x14 Base address register 1 Register */
+ u32 bar2; /* 0x18 Base address register 2 Register */
+ u32 bar3; /* 0x1c Base address register 3 Register */
+ u32 bar4; /* 0x20 Base address register 4 Register */
+ u32 bar5; /* 0x24 Base address register 5 Register */
+ u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
+ u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
+ u32 erbar; /* 0x30 Expansion ROM Base Address Register */
+ u32 cpr; /* 0x34 Capabilities Pointer Register */
+ u32 rsvd1; /* 0x38 */
+ u32 cr2; /* 0x3c Configuration Register 2 */
+ u32 rsvd2[8]; /* 0x40 - 0x5f */
+
+ /* General control / status registers */
+ u32 gscr; /* 0x60 Global Status / Control Register */
+ u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
+ u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
+ u32 tcr1; /* 0x6c Target Control 1 Register */
+ u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
+ u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
+ u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
+ u32 rsvd3; /* 0x7c */
+ u32 iwcr; /* 0x80 Initiator Window Configuration Register */
+ u32 icr; /* 0x84 Initiator Control Register */
+ u32 isr; /* 0x88 Initiator Status Register */
+ u32 tcr2; /* 0x8c Target Control 2 Register */
+ u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
+ u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
+ u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
+ u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
+ u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
+ u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
+ u32 intr; /* 0xa8 Interrupt Register */
+ u32 rsvd4[19]; /* 0xac - 0xf7 */
+ u32 car; /* 0xf8 Configuration Address Register */
+} pci_t;
+
+typedef struct pci_arbiter {
+ /* Pci Arbiter Registers */
+ union {
+ u32 acr; /* Arbiter Control Register */
+ u32 asr; /* Arbiter Status Register */
+ };
+} pciarb_t;
+
+/* Register read/write struct */
+typedef struct scm1 {
+ u32 mpr; /* 0x00 Master Privilege Register */
+ u32 rsvd1[7];
+ u32 pacra; /* 0x20 Peripheral Access Control Register A */
+ u32 pacrb; /* 0x24 Peripheral Access Control Register B */
+ u32 pacrc; /* 0x28 Peripheral Access Control Register C */
+ u32 pacrd; /* 0x2C Peripheral Access Control Register D */
+ u32 rsvd2[4];
+ u32 pacre; /* 0x40 Peripheral Access Control Register E */
+ u32 pacrf; /* 0x44 Peripheral Access Control Register F */
+ u32 pacrg; /* 0x48 Peripheral Access Control Register G */
+} scm1_t;
+/********************************************************************/
+
+typedef struct rtcex {
+ u32 rsvd1[3];
+ u32 gocu;
+ u32 gocl;
+} rtcex_t;
+#endif /* __IMMAP_5445X__ */
-#ifndef __ASM_M68K_IO_H_
-#define __ASM_M68K_IO_H_
+/*
+ * IO header file
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
-static inline void sync(void)
+#ifndef __ASM_M68K_IO_H__
+#define __ASM_M68K_IO_H__
+
+#include <asm/byteorder.h>
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr) (*(volatile u16 *) (addr))
+#define readl(addr) (*(volatile u32 *) (addr))
+#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case. - paulus
+ */
+#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port) in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+extern inline void _insb(volatile u8 * port, void *buf, int ns)
+{
+ u8 *data = (u8 *) buf;
+ while (ns--)
+ *data++ = *port;
+}
+
+extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
+{
+ u8 *data = (u8 *) buf;
+ while (ns--)
+ *port = *data++;
+}
+
+extern inline void _insw(volatile u16 * port, void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--)
+ *data++ = __sw16(*port);
+}
+
+extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--) {
+ *port = __sw16(*data);
+ data++;
+ }
+}
+
+extern inline void _insl(volatile u32 * port, void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--)
+ *data++ = __sw32(*port);
+}
+
+extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--) {
+ *port = __sw32(*data);
+ data++;
+ }
+}
+
+extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--)
+ *data++ = *port;
+}
+
+extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--) {
+ *port = *data++;
+ }
+}
+
+extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--)
+ *data++ = *port;
+}
+
+extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--) {
+ *port = *data;
+ data++;
+ }
+}
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define IO_SPACE_LIMIT ~0
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile u8 * addr)
+{
+ return (int)*addr;
+}
+
+extern inline void out_8(volatile u8 * addr, int val)
+{
+ *addr = (u8) val;
+}
+
+extern inline int in_le16(volatile u16 * addr)
+{
+ return __sw16(*addr);
+}
+
+extern inline int in_be16(volatile u16 * addr)
+{
+ return (*addr & 0xFFFF);
+}
+
+extern inline void out_le16(volatile u16 * addr, int val)
+{
+ *addr = __sw16(val);
+}
+
+extern inline void out_be16(volatile u16 * addr, int val)
+{
+ *addr = (u16) val;
+}
+
+extern inline unsigned in_le32(volatile u32 * addr)
{
+ return __sw32(*addr);
}
-#endif /* __ASM_M68K_IO_H_ */
+extern inline unsigned in_be32(volatile u32 * addr)
+{
+ return (*addr);
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+ *addr = __sw32(val);
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+ *addr = val;
+}
+
+static inline void sync(void)
+{
+ /* This sync function is for PowerPC or other architecture instruction
+ * ColdFire does not have this instruction. Dummy function, added for
+ * compatibility (CFI driver)
+ */
+}
+#endif /* __ASM_M68K_IO_H__ */
--- /dev/null
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5235_h
+#define mcf5235_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+
+/* Bit definition and macros for SCM_IPSBAR */
+#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
+#define SCM_IPSBAR_V (0x00000001)
+
+/* Bit definition and macros for SCM_RAMBAR */
+#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
+#define SCM_RAMBAR_BDE (0x00000200)
+
+/* Bit definition and macros for SCM_CRSR */
+#define SCM_CRSR_EXT (0x80)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define SCM_CWCR_CWE (0x80)
+#define SCM_CWCR_CWRI (0x40)
+#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
+#define SCM_CWCR_CWTA (0x04)
+#define SCM_CWCR_CWTAVAL (0x02)
+#define SCM_CWCR_CWTIC (0x01)
+
+/* Bit definitions and macros for SCM_LPICR */
+#define SCM_LPICR_ENBSTOP (0x80)
+#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
+#define SCM_LPICR_XLPM_IPL_ANY (0x00)
+#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
+#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
+#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
+#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
+#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
+#define SCM_LPICR_XLPM_IPL_L7 (0x70)
+
+/* Bit definitions and macros for SCM_DMAREQC */
+#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
+#define SCM_DMAREQC_EXT_ETPU (0x00080000)
+#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
+#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
+#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
+#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
+#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
+#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
+#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
+#define SCM_DMAREQC_DMACn_DTMR0 (0x04)
+#define SCM_DMAREQC_DMACn_DTMR1 (0x05)
+#define SCM_DMAREQC_DMACn_DTMR2 (0x06)
+#define SCM_DMAREQC_DMACn_DTMR3 (0x07)
+#define SCM_DMAREQC_DMACn_UART0RX (0x08)
+#define SCM_DMAREQC_DMACn_UART1RX (0x09)
+#define SCM_DMAREQC_DMACn_UART2RX (0x0A)
+#define SCM_DMAREQC_DMACn_UART0TX (0x0C)
+#define SCM_DMAREQC_DMACn_UART1TX (0x0D)
+#define SCM_DMAREQC_DMACn_UART3TX (0x0E)
+
+/* Bit definitions and macros for SCM_MPARK */
+#define SCM_MPARK_M2_P_EN (0x02000000)
+#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
+#define SCM_MPARK_M3_PRTY_4TH (0x00000000)
+#define SCM_MPARK_M3_PRTY_3RD (0x00400000)
+#define SCM_MPARK_M3_PRTY_2ND (0x00800000)
+#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
+#define SCM_MPARK_M2_PRTY_MSK (0x00300000)
+#define SCM_MPARK_M2_PRTY_4TH (0x00000000)
+#define SCM_MPARK_M2_PRTY_3RD (0x00100000)
+#define SCM_MPARK_M2_PRTY_2ND (0x00200000)
+#define SCM_MPARK_M2_PRTY_1ST (0x00300000)
+#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
+#define SCM_MPARK_M0_PRTY_4TH (0x00000000)
+#define SCM_MPARK_M0_PRTY_3RD (0x00040000)
+#define SCM_MPARK_M0_PRTY_2ND (0x00080000)
+#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
+#define SCM_MPARK_FIXED (0x00004000)
+#define SCM_MPARK_TIMEOUT (0x00002000)
+#define SCM_MPARK_PRKLAST (0x00001000)
+#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
+
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPR3 (0x08)
+#define SCM_MPR_MPR2 (0x04)
+#define SCM_MPR_MPR1 (0x02)
+#define SCM_MPR_MPR0 (0x01)
+
+/* Bit definitions and macros for SCM_PACRn */
+#define SCM_PACRn_LOCK1 (0x80)
+#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
+#define SCM_PACRn_LOCK0 (0x08)
+#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
+
+/* Bit definitions and macros for SCM_GPACR */
+#define SCM_PACRn_LOCK (0x80)
+#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_DCR */
+#define SDRAMC_DCR_NAM (0x2000)
+#define SDRAMC_DCR_COC (0x1000)
+#define SDRAMC_DCR_IS (0x0800)
+#define SDRAMC_DCR_RTIM_MASK (0x0C00)
+#define SDRAMC_DCR_RTIM_3CLKS (0x0000)
+#define SDRAMC_DCR_RTIM_6CLKS (0x0200)
+#define SDRAMC_DCR_RTIM_9CLKS (0x0400)
+#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for SDRAMC_DARCn */
+#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)
+#define SDRAMC_DARCn_RE (0x00008000)
+#define SDRAMC_DARCn_CASL_MASK (0x00003000)
+#define SDRAMC_DARCn_CASL_C0 (0x00000000)
+#define SDRAMC_DARCn_CASL_C1 (0x00001000)
+#define SDRAMC_DARCn_CASL_C2 (0x00002000)
+#define SDRAMC_DARCn_CASL_C3 (0x00003000)
+#define SDRAMC_DARCn_CBM_MASK (0x00000700)
+#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
+#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
+#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
+#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
+#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
+#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
+#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
+#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
+#define SDRAMC_DARCn_IMRS (0x00000040)
+#define SDRAMC_DARCn_PS_MASK (0x00000030)
+#define SDRAMC_DARCn_PS_32 (0x00000000)
+#define SDRAMC_DARCn_PS_16 (0x00000010)
+#define SDRAMC_DARCn_PS_8 (0x00000020)
+#define SDRAMC_DARCn_IP (0x00000008)
+
+/* Bit definitions and macros for SDRAMC_DMRn */
+#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
+#define SDRAMC_DMRn_WP (0x00000100)
+#define SDRAMC_DMRn_V (0x00000001)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+/* Bit definitions and macros for FBCS_CSMR */
+#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
+#define FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define FBCS_CSMR_BAM_128M (0x07FF0000)
+#define FBCS_CSMR_BAM_64M (0x03FF0000)
+#define FBCS_CSMR_BAM_32M (0x01FF0000)
+#define FBCS_CSMR_BAM_16M (0x00FF0000)
+#define FBCS_CSMR_BAM_8M (0x007F0000)
+#define FBCS_CSMR_BAM_4M (0x003F0000)
+#define FBCS_CSMR_BAM_2M (0x001F0000)
+#define FBCS_CSMR_BAM_1M (0x000F0000)
+#define FBCS_CSMR_BAM_1024K (0x000F0000)
+#define FBCS_CSMR_BAM_512K (0x00070000)
+#define FBCS_CSMR_BAM_256K (0x00030000)
+#define FBCS_CSMR_BAM_128K (0x00010000)
+#define FBCS_CSMR_BAM_64K (0x00000000)
+#define FBCS_CSMR_WP (0x00000100)
+#define FBCS_CSMR_V (0x00000001)
+
+/* Bit definitions and macros for FBCS_CSCR */
+#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
+#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
+#define FBCS_CSCR_AA (0x0100)
+#define FBCS_CSCR_PS_MASK (0x00C0)
+#define FBCS_CSCR_PS_32 (0x0000)
+#define FBCS_CSCR_PS_16 (0x0080)
+#define FBCS_CSCR_PS_8 (0x0040)
+#define FBCS_CSCR_BEM (0x0020)
+#define FBCS_CSCR_BSTR (0x0010)
+#define FBCS_CSCR_BSTW (0x0008)
+#define FBCS_CSCR_SWWS(x) ((x)&0x07)
+
+/*********************************************************************
+* Queued Serial Peripheral Interface (QSPI)
+*********************************************************************/
+/* Bit definitions and macros for QSPI_QMR */
+#define QSPI_QMR_MSTR (0x8000)
+#define QSPI_QMR_DOHIE (0x4000)
+#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
+#define QSPI_QMR_CPOL (0x0200)
+#define QSPI_QMR_CPHA (0x0100)
+#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QDLYR */
+#define QSPI_QDLYR_SPE (0x8000)
+#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
+#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QWR */
+#define QSPI_QWR_HALT (0x8000)
+#define QSPI_QWR_WREN (0x4000)
+#define QSPI_QWR_WRTO (0x2000)
+#define QSPI_QWR_CSIV (0x1000)
+#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
+#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
+
+/* Bit definitions and macros for QSPI_QIR */
+#define QSPI_QIR_WCEFB (0x8000)
+#define QSPI_QIR_ABRTB (0x4000)
+#define QSPI_QIR_ABRTL (0x1000)
+#define QSPI_QIR_WCEFE (0x0800)
+#define QSPI_QIR_ABRTE (0x0400)
+#define QSPI_QIR_SPIFE (0x0100)
+#define QSPI_QIR_WCEF (0x0008)
+#define QSPI_QIR_ABRT (0x0004)
+#define QSPI_QIR_SPIF (0x0001)
+
+/* Bit definitions and macros for QSPI_QAR */
+#define QSPI_QAR_ADDR(x) ((x)&0x003F)
+
+/* Bit definitions and macros for QSPI_QDR */
+#define QSPI_QDR_CONT (0x8000)
+#define QSPI_QDR_BITSE (0x4000)
+#define QSPI_QDR_DT (0x2000)
+#define QSPI_QDR_DSCK (0x1000)
+#define QSPI_QDR_QSPI_CS3 (0x0800)
+#define QSPI_QDR_QSPI_CS2 (0x0400)
+#define QSPI_QDR_QSPI_CS1 (0x0200)
+#define QSPI_QDR_QSPI_CS0 (0x0100)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_CAN1_BUF0I (43)
+#define INT0_HI_CAN1_BUF1I (44)
+#define INT0_HI_CAN1_BUF2I (45)
+#define INT0_HI_CAN1_BUF3I (46)
+#define INT0_HI_CAN1_BUF4I (47)
+#define INT0_HI_CAN1_BUF5I (48)
+#define INT0_HI_CAN1_BUF6I (49)
+#define INT0_HI_CAN1_BUF7I (50)
+#define INT0_HI_CAN1_BUF8I (51)
+#define INT0_HI_CAN1_BUF9I (52)
+#define INT0_HI_CAN1_BUF10I (53)
+#define INT0_HI_CAN1_BUF11I (54)
+#define INT0_HI_CAN1_BUF12I (55)
+#define INT0_HI_CAN1_BUF13I (56)
+#define INT0_HI_CAN1_BUF14I (57)
+#define INT0_HI_CAN1_BUF15I (58)
+#define INT0_HI_CAN1_ERRINT (59)
+#define INT0_HI_CAN1_BOFFINT (60)
+/* 60-63 Reserved */
+
+/* 0 - 7 Reserved */
+#define INT1_LO_CAN1_BUF0I (8)
+#define INT1_LO_CAN1_BUF1I (9)
+#define INT1_LO_CAN1_BUF2I (10)
+#define INT1_LO_CAN1_BUF3I (11)
+#define INT1_LO_CAN1_BUF4I (12)
+#define INT1_LO_CAN1_BUF5I (13)
+#define INT1_LO_CAN1_BUF6I (14)
+#define INT1_LO_CAN1_BUF7I (15)
+#define INT1_LO_CAN1_BUF8I (16)
+#define INT1_LO_CAN1_BUF9I (17)
+#define INT1_LO_CAN1_BUF10I (18)
+#define INT1_LO_CAN1_BUF11I (19)
+#define INT1_LO_CAN1_BUF12I (20)
+#define INT1_LO_CAN1_BUF13I (21)
+#define INT1_LO_CAN1_BUF14I (22)
+#define INT1_LO_CAN1_BUF15I (23)
+#define INT1_LO_CAN1_ERRINT (24)
+#define INT1_LO_CAN1_BOFFINT (25)
+/* 26 Reserved */
+#define INT1_LO_ETPU_TC0F (27)
+#define INT1_LO_ETPU_TC1F (28)
+#define INT1_LO_ETPU_TC2F (29)
+#define INT1_LO_ETPU_TC3F (30)
+#define INT1_LO_ETPU_TC4F (31)
+#define INT1_HI_ETPU_TC5F (32)
+#define INT1_HI_ETPU_TC6F (33)
+#define INT1_HI_ETPU_TC7F (34)
+#define INT1_HI_ETPU_TC8F (35)
+#define INT1_HI_ETPU_TC9F (36)
+#define INT1_HI_ETPU_TC10F (37)
+#define INT1_HI_ETPU_TC11F (38)
+#define INT1_HI_ETPU_TC12F (39)
+#define INT1_HI_ETPU_TC13F (40)
+#define INT1_HI_ETPU_TC14F (41)
+#define INT1_HI_ETPU_TC15F (42)
+#define INT1_HI_ETPU_TC16F (43)
+#define INT1_HI_ETPU_TC17F (44)
+#define INT1_HI_ETPU_TC18F (45)
+#define INT1_HI_ETPU_TC19F (46)
+#define INT1_HI_ETPU_TC20F (47)
+#define INT1_HI_ETPU_TC21F (48)
+#define INT1_HI_ETPU_TC22F (49)
+#define INT1_HI_ETPU_TC23F (50)
+#define INT1_HI_ETPU_TC24F (51)
+#define INT1_HI_ETPU_TC25F (52)
+#define INT1_HI_ETPU_TC26F (53)
+#define INT1_HI_ETPU_TC27F (54)
+#define INT1_HI_ETPU_TC28F (55)
+#define INT1_HI_ETPU_TC29F (56)
+#define INT1_HI_ETPU_TC30F (57)
+#define INT1_HI_ETPU_TC31F (58)
+#define INT1_HI_ETPU_TGIF (59)
+
+/* Bit definitions and macros for INTC_IPRH */
+#define INTC_IPRH_INT63 (0x80000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT32 (0x00000001)
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for INTC_IRLR */
+#define INTC_IRLRn(x) (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for INTC_IACKLPRn */
+#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
+#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_ICRnx */
+#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
+#define INTC_ICRnx_IP(x) ((x)&0x07)
+
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR */
+#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
+#define GPIO_PODR_ADDR_MASK (0xE0)
+#define GPIO_PODR_BS(x) ((x)&0x0F)
+#define GPIO_PODR_BS_MASK (0x0F)
+#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
+#define GPIO_PODR_CS_MASK (0xFE)
+#define GPIO_PODR_SDRAM(X) ((x)&0x3F)
+#define GPIO_PODR_SDRAM_MASK (0x3F)
+#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
+#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
+#define GPIO_PODR_UARTH(x) ((x)&0x03)
+#define GPIO_PODR_UARTH_MASK (0x03)
+#define GPIO_PODR_QSPI(x) ((x)&0x1F)
+#define GPIO_PODR_QSPI_MASK (0x1F)
+#define GPIO_PODR_ETPU(x) ((x)&0x07)
+#define GPIO_PODR_ETPU_MASK (0x07)
+
+/* Bit definitions and macros for GPIO_PDDR */
+#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
+#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
+#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
+#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
+#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
+#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
+#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
+#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
+#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
+#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
+#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
+#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
+#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
+#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
+#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
+#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PPDSDR */
+#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
+#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
+#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
+#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
+#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
+#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
+#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
+#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
+#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
+#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
+#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
+#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
+#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
+#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
+#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
+#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PCLRR */
+#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
+#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
+#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
+#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
+#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
+#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
+#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
+#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
+#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
+#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
+#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
+#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
+#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
+#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
+#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
+#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PAR */
+#define GPIO_PAR_AD_ADDR23 (0x80)
+#define GPIO_PAR_AD_ADDR22 (0x40)
+#define GPIO_PAR_AD_ADDR21 (0x20)
+#define GPIO_PAR_AD_DATAL (0x01)
+#define GPIO_PAR_BUSCTL_OE (0x4000)
+#define GPIO_PAR_BUSCTL_TA (0x1000)
+#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
+#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
+#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
+#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
+#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
+#define GPIO_PAR_BUSCTL_RWB (0x0100)
+#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
+#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
+#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
+#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
+#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
+#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
+#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
+#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
+#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
+#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
+#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
+#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
+#define GPIO_PAR_BS(x) ((x)&0x0F)
+#define GPIO_PAR_BS_MASK (0x0F)
+#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
+#define GPIO_PAR_CS_MASK (0xFE)
+#define GPIO_PAR_CS_CS7 (0x80)
+#define GPIO_PAR_CS_CS6 (0x40)
+#define GPIO_PAR_CS_CS5 (0x20)
+#define GPIO_PAR_CS_CS4 (0x10)
+#define GPIO_PAR_CS_CS3 (0x08)
+#define GPIO_PAR_CS_CS2 (0x04)
+#define GPIO_PAR_CS_CS1 (0x02)
+#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
+#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
+#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
+#define GPIO_PAR_SDRAM_SDWE (0x20)
+#define GPIO_PAR_SDRAM_SCAS (0x10)
+#define GPIO_PAR_SDRAM_SRAS (0x08)
+#define GPIO_PAR_SDRAM_SCKE (0x04)
+#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
+#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
+#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
+#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
+#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
+#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
+#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
+#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
+#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
+#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
+#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
+#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
+#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
+#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
+#define GPIO_PAR_FECI2C_SDA_MASK (0x03)
+#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
+#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
+#define GPIO_PAR_UART_DREQ2 (0x8000)
+#define GPIO_PAR_UART_CAN1EN (0x4000)
+#define GPIO_PAR_UART_U2RXD (0x2000)
+#define GPIO_PAR_UART_U2TXD (0x1000)
+#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
+#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
+#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
+#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
+#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
+#define GPIO_PAR_UART_U1TXD_MASK (0x0300)
+#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
+#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
+#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
+#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
+#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
+#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART_U1RTS_MASK (0x0030)
+#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
+#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
+#define GPIO_PAR_UART_U0RXD (0x0008)
+#define GPIO_PAR_UART_U0TXD (0x0004)
+#define GPIO_PAR_UART_U0CTS (0x0002)
+#define GPIO_PAR_UART_U0RTS (0x0001)
+#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
+#define GPIO_PAR_QSPI_CS1_MASK (0xC0)
+#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
+#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
+#define GPIO_PAR_QSPI_CS0 (0x20)
+#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
+#define GPIO_PAR_QSPI_DIN_MASK (0x18)
+#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
+#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
+#define GPIO_PAR_QSPI_DOUT (0x04)
+#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
+#define GPIO_PAR_QSPI_SCK_MASK (0x03)
+#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
+#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
+#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
+#define GPIO_PAR_DT3IN_MASK (0xC000)
+#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
+#define GPIO_PAR_DT3IN_U2CTS (0x8000)
+#define GPIO_PAR_DT3IN_DT3IN (0xC000)
+#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
+#define GPIO_PAR_DT2IN_MASK (0x3000)
+#define GPIO_PAR_DT2IN_DT2OUT (0x1000)
+#define GPIO_PAR_DT2IN_DREQ2 (0x2000)
+#define GPIO_PAR_DT2IN_DT2IN (0x3000)
+#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
+#define GPIO_PAR_DT1IN_MASK (0x0C00)
+#define GPIO_PAR_DT1IN_DT1OUT (0x0400)
+#define GPIO_PAR_DT1IN_DREQ1 (0x0800)
+#define GPIO_PAR_DT1IN_DT1IN (0x0C00)
+#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
+#define GPIO_PAR_DT0IN_MASK (0x0300)
+#define GPIO_PAR_DT0IN_DREQ0 (0x0200)
+#define GPIO_PAR_DT0IN_DT0IN (0x0300)
+#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DT3OUT_MASK (0x00C0)
+#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
+#define GPIO_PAR_DT3OUT_U2RTS (0x0080)
+#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
+#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DT2OUT_MASK (0x0030)
+#define GPIO_PAR_DT2OUT_DACK2 (0x0020)
+#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
+#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DT1OUT_MASK (0x000C)
+#define GPIO_PAR_DT1OUT_DACK1 (0x0008)
+#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
+#define GPIO_PAR_DT0OUT(x) ((x)&0x03)
+#define GPIO_PAR_DT0OUT_MASK (0x0003)
+#define GPIO_PAR_DT0OUT_DACK0 (0x0002)
+#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
+#define GPIO_PAR_ETPU_TCRCLK (0x04)
+#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
+#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
+
+/* Bit definitions and macros for GPIO_DSCR */
+#define GPIO_DSCR_EIM_EIM1 (0x10)
+#define GPIO_DSCR_EIM_EIM0 (0x01)
+#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
+#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
+#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
+#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
+#define GPIO_DSCR_FECI2C_FEC (0x10)
+#define GPIO_DSCR_FECI2C_I2C (0x01)
+#define GPIO_DSCR_UART_IRQ (0x40)
+#define GPIO_DSCR_UART_UART2 (0x10)
+#define GPIO_DSCR_UART_UART1 (0x04)
+#define GPIO_DSCR_UART_UART0 (0x01)
+#define GPIO_DSCR_QSPI_QSPI (0x01)
+#define GPIO_DSCR_TIMER (0x01)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_RCR */
+#define CCM_RCR_SOFTRST (0x80)
+#define CCM_RCR_FRCRSTOUT (0x40)
+
+/* Bit definitions and macros for CCM_RSR */
+#define CCM_RSR_SOFT (0x20)
+#define CCM_RSR_WDR (0x10)
+#define CCM_RSR_POR (0x08)
+#define CCM_RSR_EXT (0x04)
+#define CCM_RSR_LOC (0x02)
+#define CCM_RSR_LOL (0x01)
+
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_LOAD (0x8000)
+#define CCM_CCR_SZEN (0x0040)
+#define CCM_CCR_PSTEN (0x0020)
+#define CCM_CCR_BME (0x0008)
+#define CCM_CCR_BMT(x) ((x)&0x07)
+#define CCM_CCR_BMT_MASK (0x0007)
+#define CCM_CCR_BMT_64K (0x0000)
+#define CCM_CCR_BMT_32K (0x0001)
+#define CCM_CCR_BMT_16K (0x0002)
+#define CCM_CCR_BMT_8K (0x0003)
+#define CCM_CCR_BMT_4K (0x0004)
+#define CCM_CCR_BMT_2K (0x0005)
+#define CCM_CCR_BMT_1K (0x0006)
+#define CCM_CCR_BMT_512 (0x0007)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
+#define CCM_RCON_RLOAD (0x0020)
+#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
+#define CCM_RCON_BOOTPS_MASK (0x0018)
+#define CCM_RCON_BOOTPS_32 (0x0018)
+#define CCM_RCON_BOOTPS_16 (0x0008)
+#define CCM_RCON_BOOTPS_8 (0x0010)
+#define CCM_RCON_MODE (0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
+#define CCM_CIR_PRN(x) ((x)&0x003F)
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
+#define PLL_SYNCR_MFD_MASK (0x07000000)
+#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
+#define PLL_SYNCR_RFC_MASK (0x00380000)
+#define PLL_SYNCR_LOCEN (0x00040000)
+#define PLL_SYNCR_LOLRE (0x00020000)
+#define PLL_SYNCR_LOCRE (0x00010000)
+#define PLL_SYNCR_DISCLK (0x00008000)
+#define PLL_SYNCR_LOLIRQ (0x00004000)
+#define PLL_SYNCR_LOCIRQ (0x00002000)
+#define PLL_SYNCR_RATE (0x00001000)
+#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
+#define PLL_SYNCR_EXP(x) ((x)&0x03FF)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_LOLF (0x00000200)
+#define PLL_SYNSR_LOC (0x00000100)
+#define PLL_SYNSR_MODE (0x00000080)
+#define PLL_SYNSR_PLLSEL (0x00000040)
+#define PLL_SYNSR_PLLREF (0x00000020)
+#define PLL_SYNSR_LOCKS (0x00000010)
+#define PLL_SYNSR_LOCK (0x00000008)
+#define PLL_SYNSR_LOCF (0x00000004)
+#define PLL_SYNSR_CALDONE (0x00000002)
+#define PLL_SYNSR_CALPASS (0x00000001)
+
+/*********************************************************************
+ * Edge Port
+*********************************************************************/
+#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
+#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
+#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
+#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
+#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
+#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
+#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
+
+#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
+#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
+#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
+#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
+#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
+#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
+#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
+
+#define EPORT_EPIER_EPIE7 (0x80)
+#define EPORT_EPIER_EPIE6 (0x40)
+#define EPORT_EPIER_EPIE5 (0x20)
+#define EPORT_EPIER_EPIE4 (0x10)
+#define EPORT_EPIER_EPIE3 (0x08)
+#define EPORT_EPIER_EPIE2 (0x04)
+#define EPORT_EPIER_EPIE1 (0x02)
+
+#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
+#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
+#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
+#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
+#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
+#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
+#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
+
+#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
+#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
+#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
+#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
+#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
+#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
+#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT (0x0008)
+#define WTM_WCR_DOZE (0x0004)
+#define WTM_WCR_HALTED (0x0002)
+#define WTM_WCR_EN (0x0001)
+
+/*********************************************************************
+* FlexCAN Module (CAN)
+*********************************************************************/
+/* Bit definitions and macros for CAN_CANMCR */
+#define CANMCR_MDIS (0x80000000)
+#define CANMCR_FRZ (0x40000000)
+#define CANMCR_HALT (0x10000000)
+#define CANMCR_NORDY (0x08000000)
+#define CANMCR_SOFTRST (0x02000000)
+#define CANMCR_FRZACK (0x01000000)
+#define CANMCR_SUPV (0x00800000)
+#define CANMCR_LPMACK (0x00100000)
+#define CANMCR_MAXMB(x) (((x)&0x0F))
+
+/* Bit definitions and macros for CAN_CANCTRL */
+#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
+#define CANCTRL_RJW(x) (((x)&0x03)<<22)
+#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
+#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
+#define CANCTRL_BOFFMSK (0x00008000)
+#define CANCTRL_ERRMSK (0x00004000)
+#define CANCTRL_CLKSRC (0x00002000)
+#define CANCTRL_LPB (0x00001000)
+#define CANCTRL_SMP (0x00000080)
+#define CANCTRL_BOFFREC (0x00000040)
+#define CANCTRL_TSYNC (0x00000020)
+#define CANCTRL_LBUF (0x00000010)
+#define CANCTRL_LOM (0x00000008)
+#define CANCTRL_PROPSEG(x) (((x)&0x07))
+
+/* Bit definitions and macros for CAN_TIMER */
+#define TIMER_TIMER(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for CAN_RXGMASK */
+#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
+
+/* Bit definitions and macros for CAN_ERRCNT */
+#define ERRCNT_TXECTR(x) (((x)&0xFF))
+#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for CAN_ERRSTAT */
+#define ERRSTAT_BITERR1 (0x00008000)
+#define ERRSTAT_BITERR0 (0x00004000)
+#define ERRSTAT_ACKERR (0x00002000)
+#define ERRSTAT_CRCERR (0x00001000)
+#define ERRSTAT_FRMERR (0x00000800)
+#define ERRSTAT_STFERR (0x00000400)
+#define ERRSTAT_TXWRN (0x00000200)
+#define ERRSTAT_RXWRN (0x00000100)
+#define ERRSTAT_IDLE (0x00000080)
+#define ERRSTAT_TXRX (0x00000040)
+#define ERRSTAT_FLT_BUSOFF (0x00000020)
+#define ERRSTAT_FLT_PASSIVE (0x00000010)
+#define ERRSTAT_FLT_ACTIVE (0x00000000)
+#define ERRSTAT_BOFFINT (0x00000004)
+#define ERRSTAT_ERRINT (0x00000002)
+
+/* Bit definitions and macros for CAN_IMASK */
+#define IMASK_BUF15M (0x00008000)
+#define IMASK_BUF14M (0x00004000)
+#define IMASK_BUF13M (0x00002000)
+#define IMASK_BUF12M (0x00001000)
+#define IMASK_BUF11M (0x00000800)
+#define IMASK_BUF10M (0x00000400)
+#define IMASK_BUF9M (0x00000200)
+#define IMASK_BUF8M (0x00000100)
+#define IMASK_BUF7M (0x00000080)
+#define IMASK_BUF6M (0x00000040)
+#define IMASK_BUF5M (0x00000020)
+#define IMASK_BUF4M (0x00000010)
+#define IMASK_BUF3M (0x00000008)
+#define IMASK_BUF2M (0x00000004)
+#define IMASK_BUF1M (0x00000002)
+#define IMASK_BUF0M (0x00000001)
+
+/* Bit definitions and macros for CAN_IFLAG */
+#define IFLAG_BUF15I (0x00008000)
+#define IFLAG_BUF14I (0x00004000)
+#define IFLAG_BUF13I (0x00002000)
+#define IFLAG_BUF12I (0x00001000)
+#define IFLAG_BUF11I (0x00000800)
+#define IFLAG_BUF10I (0x00000400)
+#define IFLAG_BUF9I (0x00000200)
+#define IFLAG_BUF8I (0x00000100)
+#define IFLAG_BUF7I (0x00000080)
+#define IFLAG_BUF6I (0x00000040)
+#define IFLAG_BUF5I (0x00000020)
+#define IFLAG_BUF4I (0x00000010)
+#define IFLAG_BUF3I (0x00000008)
+#define IFLAG_BUF2I (0x00000004)
+#define IFLAG_BUF1I (0x00000002)
+#define IFLAG_BUF0I (0x00000001)
+
+#endif /* mcf5235_h */
* MA 02111-1307 USA
*/
-
#ifndef mcf5249_h
#define mcf5249_h
/****************************************************************************/
/*
* useful definitions for reading/writing MBAR offset memory
*/
-#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
-#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
-#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
-#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
-#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
-#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
-
+#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
+#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
+#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
/*
* Size of internal RAM
*/
-#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
-#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
+#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
+#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
/*
* Define the 5249 SIM register set addresses.
/*****************
***** MBAR1 *****
*****************/
-#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
-
-#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
-#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
-
-#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
-
-#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
-
-/** UART Bases **/
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
+#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
+#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
+
+#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
+#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
+
+#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
+
+#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/*****************
***** MBAR2 *****
/* GPIO Addresses
* Note: These are offset from MBAR2!
*/
-#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
-#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/
-#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/
-#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
-#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
-#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
-#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
-#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
-
-#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
-#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
-#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
-
-#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
-#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
-#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
-
-#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
-#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
-#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
-#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
-#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
-#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
-#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
-#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
-
-#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
-#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
-
-#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
-#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
-
-#define MCFSIM_PLLCR 0x180 /* PLL Control register */
+#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
+#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */
+#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */
+#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
+#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
+#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
+#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
+#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
+
+#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
+#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
+#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
+
+#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
+#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
+#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
+
+#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
+#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
+#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
+#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
+#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
+#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
+#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
+#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
+
+#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
+#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
+
+#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
+#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
+
+#define MCFSIM_PLLCR 0x180 /* PLL Control register */
/*
* Some symbol defines for the above...
/*
* Bit definitions for the ICR family of registers.
*/
-#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
-#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
-#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
-#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
-#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
-#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
-#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
-#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
-#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
-
-#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
-#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
-#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
-#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
-
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
/*
* Macros to read/set IMR register. It is 32 bits on the 5249.
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-#endif /* mcf5249_h */
+#endif /* mcf5249_h */
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef m5253_h
+#define m5253_h
+/****************************************************************************/
+
+/*
+* PLL Module (PLL)
+*/
+
+/* Register read/write macros */
+#define PLL_PLLCR (0x000180)
+
+#define SIM_RSR (0x000000)
+#define SIM_SYPCR (0x000001)
+#define SIM_SWIVR (0x000002)
+#define SIM_SWSR (0x000003)
+#define SIM_MPARK (0x00000C)
+
+/* Bit definitions and macros for RSR */
+#define SIM_RSR_SWTR (0x20)
+#define SIM_RSR_HRST (0x80)
+
+/* Register read/write macros */
+#define CIM_MISCCR (0x000500)
+#define CIM_ATA_DADDR (0x000504)
+#define CIM_ATA_DCOUNT (0x000508)
+#define CIM_RTC_TIME (0x00050C)
+#define CIM_USB_CANCLK (0x000510)
+
+/* Bit definitions and macros for MISCCR */
+#define CIM_MISCCR_ADTA (0x00000001)
+#define CIM_MISCCR_ADTD (0x00000002)
+#define CIM_MISCCR_ADIE (0x00000004)
+#define CIM_MISCCR_ADIC (0x00000008)
+#define CIM_MISCCR_ADIP (0x00000010)
+#define CIM_MISCCR_CPUEND (0x00000020)
+#define CIM_MISCCR_DMAEND (0x00000040)
+#define CIM_MISCCR_RTCCLR (0x00000080)
+#define CIM_MISCCR_RTCPL (0x00000100)
+#define CIM_MISCCR_URIE (0x00000800)
+#define CIM_MISCCR_URIC (0x00001000)
+#define CIM_MISCCR_URIP (0x00002000)
+
+/* Bit definitions and macros for ATA_DADDR */
+#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
+#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for ATA_DCOUNT */
+#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF))
+
+#endif /* m5253_h */
* MA 02111-1307 USA
*/
-
#ifndef _MCF5271_H_
#define _MCF5271_H_
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
-#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040
#define MCF_SDRAMC_DACR0 0x000048
#define MCFSIM_ICR1 0x000C41
-#endif /* _MCF5271_H_ */
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_CAN1_BUF0I (43)
+#define INT0_HI_CAN1_BUF1I (44)
+#define INT0_HI_CAN1_BUF2I (45)
+#define INT0_HI_CAN1_BUF3I (46)
+#define INT0_HI_CAN1_BUF4I (47)
+#define INT0_HI_CAN1_BUF5I (48)
+#define INT0_HI_CAN1_BUF6I (49)
+#define INT0_HI_CAN1_BUF7I (50)
+#define INT0_HI_CAN1_BUF8I (51)
+#define INT0_HI_CAN1_BUF9I (52)
+#define INT0_HI_CAN1_BUF10I (53)
+#define INT0_HI_CAN1_BUF11I (54)
+#define INT0_HI_CAN1_BUF12I (55)
+#define INT0_HI_CAN1_BUF13I (56)
+#define INT0_HI_CAN1_BUF14I (57)
+#define INT0_HI_CAN1_BUF15I (58)
+#define INT0_HI_CAN1_ERRINT (59)
+#define INT0_HI_CAN1_BOFFINT (60)
+/* 60-63 Reserved */
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+#endif /* _MCF5271_H_ */
* MA 02111-1307 USA
*/
-
#ifndef mcf5272_h
#define mcf5272_h
/****************************************************************************/
#define INT_RAM_SIZE 4096
+#define GPIO_PACNT_PA15MSK (0xC0000000)
+#define GPIO_PACNT_DGNT1 (0x40000000)
+#define GPIO_PACNT_PA14MSK (0x30000000)
+#define GPIO_PACNT_DREQ1 (0x10000000)
+#define GPIO_PACNT_PA13MSK (0x0C000000)
+#define GPIO_PACNT_DFSC3 (0x04000000)
+#define GPIO_PACNT_PA12MSK (0x03000000)
+#define GPIO_PACNT_DFSC2 (0x01000000)
+#define GPIO_PACNT_PA11MSK (0x00C00000)
+#define GPIO_PACNT_QSPI_CS1 (0x00800000)
+#define GPIO_PACNT_PA10MSK (0x00300000)
+#define GPIO_PACNT_DREQ0 (0x00100000)
+#define GPIO_PACNT_PA9MSK (0x000C0000)
+#define GPIO_PACNT_DGNT0 (0x00040000)
+#define GPIO_PACNT_PA8MSK (0x00030000)
+#define GPIO_PACNT_FSC0 (0x00010000)
+#define GPIO_PACNT_FSR0 (0x00010000)
+#define GPIO_PACNT_PA7MSK (0x0000C000)
+#define GPIO_PACNT_DOUT3 (0x00008000)
+#define GPIO_PACNT_QSPI_CS3 (0x00004000)
+#define GPIO_PACNT_PA6MSK (0x00003000)
+#define GPIO_PACNT_USB_RXD (0x00001000)
+#define GPIO_PACNT_PA5MSK (0x00000C00)
+#define GPIO_PACNT_USB_TXEN (0x00000400)
+#define GPIO_PACNT_PA4MSK (0x00000300)
+#define GPIO_PACNT_USB_SUSP (0x00000100)
+#define GPIO_PACNT_PA3MSK (0x000000C0)
+#define GPIO_PACNT_USB_TN (0x00000040)
+#define GPIO_PACNT_PA2MSK (0x00000030)
+#define GPIO_PACNT_USB_RN (0x00000010)
+#define GPIO_PACNT_PA1MSK (0x0000000C)
+#define GPIO_PACNT_USB_RP (0x00000004)
+#define GPIO_PACNT_PA0MSK (0x00000003)
+#define GPIO_PACNT_USB_TP (0x00000001)
-/*
- * Define the 5272 SIM register set addresses.
- */
-#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
-#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
-#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
-#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
-#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
-
-#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
-#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
-#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
+#define GPIO_PBCNT_PB15MSK (0xC0000000)
+#define GPIO_PBCNT_E_MDC (0x40000000)
+#define GPIO_PBCNT_PB14MSK (0x30000000)
+#define GPIO_PBCNT_E_RXER (0x10000000)
+#define GPIO_PBCNT_PB13MSK (0x0C000000)
+#define GPIO_PBCNT_E_RXD1 (0x04000000)
+#define GPIO_PBCNT_PB12MSK (0x03000000)
+#define GPIO_PBCNT_E_RXD2 (0x01000000)
+#define GPIO_PBCNT_PB11MSK (0x00C00000)
+#define GPIO_PBCNT_E_RXD3 (0x00400000)
+#define GPIO_PBCNT_PB10MSK (0x00300000)
+#define GPIO_PBCNT_E_TXD1 (0x00100000)
+#define GPIO_PBCNT_PB9MSK (0x000C0000)
+#define GPIO_PBCNT_E_TXD2 (0x00040000)
+#define GPIO_PBCNT_PB8MSK (0x00030000)
+#define GPIO_PBCNT_E_TXD3 (0x00010000)
+#define GPIO_PBCNT_PB7MSK (0x0000C000)
+#define GPIO_PBCNT_TOUT0 (0x00004000)
+#define GPIO_PBCNT_PB6MSK (0x00003000)
+#define GPIO_PBCNT_TA (0x00001000)
+#define GPIO_PBCNT_PB4MSK (0x00000300)
+#define GPIO_PBCNT_URT0_CLK (0x00000100)
+#define GPIO_PBCNT_PB3MSK (0x000000C0)
+#define GPIO_PBCNT_URT0_RTS (0x00000040)
+#define GPIO_PBCNT_PB2MSK (0x00000030)
+#define GPIO_PBCNT_URT0_CTS (0x00000010)
+#define GPIO_PBCNT_PB1MSK (0x0000000C)
+#define GPIO_PBCNT_URT0_RXD (0x00000004)
+#define GPIO_PBCNT_URT0_TIN2 (0x00000004)
+#define GPIO_PBCNT_PB0MSK (0x00000003)
+#define GPIO_PBCNT_URT0_TXD (0x00000001)
-#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
-#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
-#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
-#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
+#define GPIO_PDCNT_PD7MSK (0x0000C000)
+#define GPIO_PDCNT_TIN1 (0x00008000)
+#define GPIO_PDCNT_PWM_OUT2 (0x00004000)
+#define GPIO_PDCNT_PD6MSK (0x00003000)
+#define GPIO_PDCNT_TOUT1 (0x00002000)
+#define GPIO_PDCNT_PWM_OUT1 (0x00001000)
+#define GPIO_PDCNT_PD5MSK (0x00000C00)
+#define GPIO_PDCNT_INT4 (0x00000C00)
+#define GPIO_PDCNT_DIN3 (0x00000800)
+#define GPIO_PDCNT_PD4MSK (0x00000300)
+#define GPIO_PDCNT_URT1_TXD (0x00000200)
+#define GPIO_PDCNT_DOUT0 (0x00000100)
+#define GPIO_PDCNT_PD3MSK (0x000000C0)
+#define GPIO_PDCNT_INT5 (0x000000C0)
+#define GPIO_PDCNT_URT1_RTS (0x00000080)
+#define GPIO_PDCNT_PD2MSK (0x00000030)
+#define GPIO_PDCNT_QSPI_CS2 (0x00000030)
+#define GPIO_PDCNT_URT1_CTS (0x00000020)
+#define GPIO_PDCNT_PD1MSK (0x0000000C)
+#define GPIO_PDCNT_URT1_RXD (0x00000008)
+#define GPIO_PDCNT_URT1_TIN3 (0x00000008)
+#define GPIO_PDCNT_DIN0 (0x00000004)
+#define GPIO_PDCNT_PD0MSK (0x00000003)
+#define GPIO_PDCNT_URT1_CLK (0x00000002)
+#define GPIO_PDCNT_DCL0 (0x00000001)
-#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
-#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
-#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
-#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
-#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
-#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
-#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
-#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
-#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
-#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
-#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
-#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
-#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
-#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
-#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
-#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
+#define INT_RSVD0 (0)
+#define INT_INT1 (1)
+#define INT_INT2 (2)
+#define INT_INT3 (3)
+#define INT_INT4 (4)
+#define INT_TMR0 (5)
+#define INT_TMR1 (6)
+#define INT_TMR2 (7)
+#define INT_TMR3 (8)
+#define INT_UART1 (9)
+#define INT_UART2 (10)
+#define INT_PLIP (11)
+#define INT_PLIA (12)
+#define INT_USB0 (13)
+#define INT_USB1 (14)
+#define INT_USB2 (15)
+#define INT_USB3 (16)
+#define INT_USB4 (17)
+#define INT_USB5 (18)
+#define INT_USB6 (19)
+#define INT_USB7 (20)
+#define INT_DMA (21)
+#define INT_ERX (22)
+#define INT_ETX (23)
+#define INT_ENTC (24)
+#define INT_QSPI (25)
+#define INT_INT5 (26)
+#define INT_INT6 (27)
+#define INT_SWTO (28)
-#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
-#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
-#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
+#define INT_ICR1_TMR0MASK (0x000F000)
+#define INT_ICR1_TMR0PI (0x0008000)
+#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12)
+#define INT_ICR1_TMR1MASK (0x0000F00)
+#define INT_ICR1_TMR1PI (0x0000800)
+#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8)
+#define INT_ICR1_TMR2MASK (0x00000F0)
+#define INT_ICR1_TMR2PI (0x0000080)
+#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4)
+#define INT_ICR1_TMR3MASK (0x000000F)
+#define INT_ICR1_TMR3PI (0x0000008)
+#define INT_ICR1_TMR3IPL(x) (((x)&0x7))
-#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
-#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
-#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
-#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
-#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
-#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
-#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
-#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
-#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
+#define INT_ISR_INT31 (0x80000000)
+#define INT_ISR_INT30 (0x40000000)
+#define INT_ISR_INT29 (0x20000000)
+#define INT_ISR_INT28 (0x10000000)
+#define INT_ISR_INT27 (0x08000000)
+#define INT_ISR_INT26 (0x04000000)
+#define INT_ISR_INT25 (0x02000000)
+#define INT_ISR_INT24 (0x01000000)
+#define INT_ISR_INT23 (0x00800000)
+#define INT_ISR_INT22 (0x00400000)
+#define INT_ISR_INT21 (0x00200000)
+#define INT_ISR_INT20 (0x00100000)
+#define INT_ISR_INT19 (0x00080000)
+#define INT_ISR_INT18 (0x00040000)
+#define INT_ISR_INT17 (0x00020000)
+#define INT_ISR_INT16 (0x00010000)
+#define INT_ISR_INT15 (0x00008000)
+#define INT_ISR_INT14 (0x00004000)
+#define INT_ISR_INT13 (0x00002000)
+#define INT_ISR_INT12 (0x00001000)
+#define INT_ISR_INT11 (0x00000800)
+#define INT_ISR_INT10 (0x00000400)
+#define INT_ISR_INT9 (0x00000200)
+#define INT_ISR_INT8 (0x00000100)
+#define INT_ISR_INT7 (0x00000080)
+#define INT_ISR_INT6 (0x00000040)
+#define INT_ISR_INT5 (0x00000020)
+#define INT_ISR_INT4 (0x00000010)
+#define INT_ISR_INT3 (0x00000008)
+#define INT_ISR_INT2 (0x00000004)
+#define INT_ISR_INT1 (0x00000002)
+#define INT_ISR_INT0 (0x00000001)
-#endif /* mcf5272_h */
+#endif /* mcf5272_h */
/****************************************************************************/
#ifndef m5282_h
#define m5282_h
-/****************************************************************************/
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_LOLRE (0x8000)
+#define PLL_SYNCR_MFD2 (0x4000)
+#define PLL_SYNCR_MFD1 (0x2000)
+#define PLL_SYNCR_MFD0 (0x1000)
+#define PLL_SYNCR_LOCRE (0x0800)
+#define PLL_SYNCR_RFC2 (0x0400)
+#define PLL_SYNCR_RFC1 (0x0200)
+#define PLL_SYNCR_RFC0 (0x0100)
+#define PLL_SYNCR_LOCEN (0x0080)
+#define PLL_SYNCR_DISCLK (0x0040)
+#define PLL_SYNCR_FWKUP (0x0020)
+#define PLL_SYNCR_STPMD1 (0x0008)
+#define PLL_SYNCR_STPMD0 (0x0004)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_MODE (0x0080)
+#define PLL_SYNSR_PLLSEL (0x0040)
+#define PLL_SYNSR_PLLREF (0x0020)
+#define PLL_SYNSR_LOCKS (0x0010)
+#define PLL_SYNSR_LOCK (0x0008)
+#define PLL_SYNSR_LOCS (0x0004)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM_SWT1 (8)
+#define INT0_LO_DMA_00 (9)
+#define INT0_LO_DMA_01 (10)
+#define INT0_LO_DMA_02 (11)
+#define INT0_LO_DMA_03 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PMM_LVDF (36)
+#define INT0_HI_QADC_CF1 (37)
+#define INT0_HI_QADC_CF2 (38)
+#define INT0_HI_QADC_PF1 (39)
+#define INT0_HI_QADC_PF2 (40)
+#define INT0_HI_GPTA_TOF (41)
+#define INT0_HI_GPTA_PAIF (42)
+#define INT0_HI_GPTA_PAOVF (43)
+#define INT0_HI_GPTA_C0F (44)
+#define INT0_HI_GPTA_C1F (45)
+#define INT0_HI_GPTA_C2F (46)
+#define INT0_HI_GPTA_C3F (47)
+#define INT0_HI_GPTB_TOF (48)
+#define INT0_HI_GPTB_PAIF (49)
+#define INT0_HI_GPTB_PAOVF (50)
+#define INT0_HI_GPTB_C0F (51)
+#define INT0_HI_GPTB_C1F (52)
+#define INT0_HI_GPTB_C2F (53)
+#define INT0_HI_GPTB_C3F (54)
+#define INT0_HI_PIT0 (55)
+#define INT0_HI_PIT1 (56)
+#define INT0_HI_PIT2 (57)
+#define INT0_HI_PIT3 (58)
+#define INT0_HI_CFM_CBEIF (59)
+#define INT0_HI_CFM_CCIF (60)
+#define INT0_HI_CFM_PVIF (61)
+#define INT0_HI_CFM_AEIF (62)
/*
* Size of internal RAM
#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
-#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
-#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
-#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
-#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
-#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
-#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
-#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
-#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
-#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
-#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
-#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
-#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
-
-#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
-#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
-#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
-#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
-#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
-#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
-#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
-#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
-#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
-#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
-#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
-#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
-#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
-#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
-#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
-#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
-#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
-#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
-
-#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
-#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
-#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
-#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
-#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
-#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
-#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
-#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
+#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
+#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
+#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
+#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
+#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
+#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
+#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
+#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
+#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
+#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
+#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
+#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
+#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
+#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
+#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
+#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
+#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
+#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
+#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
+#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
+#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
+#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
+#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
+#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
+#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
-
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
/* System Conrol Module SCM */
-#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
+#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
-
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
-#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
-#define MCFSCM_RAMBAR_BDE (0x00000200)
+#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
+#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
-#define MCFRESET_RCR_SOFTRST (0x80)
-#define MCFRESET_RCR_FRCRSTOUT (0x40)
-#define MCFRESET_RCR_LVDF (0x10)
-#define MCFRESET_RCR_LVDIE (0x08)
-#define MCFRESET_RCR_LVDRE (0x04)
-#define MCFRESET_RCR_LVDE (0x01)
-
-#define MCFRESET_RSR_LVD (0x40)
-#define MCFRESET_RSR_SOFT (0x20)
-#define MCFRESET_RSR_WDR (0x10)
-#define MCFRESET_RSR_POR (0x08)
-#define MCFRESET_RSR_EXT (0x04)
-#define MCFRESET_RSR_LOC (0x02)
-#define MCFRESET_RSR_LOL (0x01)
-#define MCFRESET_RSR_ALL (0x7F)
-#define MCFRESET_RCR_SOFTRST (0x80)
-#define MCFRESET_RCR_FRCRSTOUT (0x40)
+#define MCFRESET_RCR_SOFTRST (0x80)
+#define MCFRESET_RCR_FRCRSTOUT (0x40)
+#define MCFRESET_RCR_LVDF (0x10)
+#define MCFRESET_RCR_LVDIE (0x08)
+#define MCFRESET_RCR_LVDRE (0x04)
+#define MCFRESET_RCR_LVDE (0x01)
+
+#define MCFRESET_RSR_LVD (0x40)
+#define MCFRESET_RSR_SOFT (0x20)
+#define MCFRESET_RSR_WDR (0x10)
+#define MCFRESET_RSR_POR (0x08)
+#define MCFRESET_RSR_EXT (0x04)
+#define MCFRESET_RSR_LOC (0x02)
+#define MCFRESET_RSR_LOL (0x01)
+#define MCFRESET_RSR_ALL (0x7F)
+#define MCFRESET_RCR_SOFTRST (0x80)
+#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
-
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
-#define MCFCCM_CCR_SZEN (0x0040)
-#define MCFCCM_CCR_PSTEN (0x0020)
+#define MCFCCM_CCR_SZEN (0x0040)
+#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
-#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
+#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
-#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
-#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
+#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
+#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
-#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
-#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
-#define MCFCLOCK_SYNSR_LOCK 0x08
+#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
+#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
+#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
-#define MCFSDRAMC_DMR_WP (0x00000100)
-#define MCFSDRAMC_DMR_CI (0x00000040)
-#define MCFSDRAMC_DMR_AM (0x00000020)
-#define MCFSDRAMC_DMR_SC (0x00000010)
-#define MCFSDRAMC_DMR_SD (0x00000008)
-#define MCFSDRAMC_DMR_UC (0x00000004)
-#define MCFSDRAMC_DMR_UD (0x00000002)
-#define MCFSDRAMC_DMR_V (0x00000001)
-
-#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
-#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
-#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
-#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
+#define MCFSDRAMC_DMR_WP (0x00000100)
+#define MCFSDRAMC_DMR_CI (0x00000040)
+#define MCFSDRAMC_DMR_AM (0x00000020)
+#define MCFSDRAMC_DMR_SC (0x00000010)
+#define MCFSDRAMC_DMR_SD (0x00000008)
+#define MCFSDRAMC_DMR_UC (0x00000004)
+#define MCFSDRAMC_DMR_UD (0x00000002)
+#define MCFSDRAMC_DMR_V (0x00000001)
+
+#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
+#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
+#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
+#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
-*
* General Purpose Timer (GPT) Module
-*
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
-
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
-#endif /* m5282_h */
+#endif /* m5282_h */
--- /dev/null
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5329_h
+#define mcf5329_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28)
+#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24)
+#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20)
+#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12)
+#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8)
+#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4)
+#define MPROT_MTR 4
+#define MPROT_MTW 2
+#define MPROT_MPL 1
+
+/* Bit definitions and macros for SCM_BMT */
+#define BMT_BME (0x08)
+#define BMT_8 (0x07)
+#define BMT_16 (0x06)
+#define BMT_32 (0x05)
+#define BMT_64 (0x04)
+#define BMT_128 (0x03)
+#define BMT_256 (0x02)
+#define BMT_512 (0x01)
+#define BMT_1024 (0x00)
+
+/* Bit definitions and macros for SCM_PACRA */
+#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28)
+#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24)
+#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20)
+#define PACR_SP 4
+#define PACR_WP 2
+#define PACR_TP 1
+
+/* Bit definitions and macros for SCM_PACRB */
+#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28)
+#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12)
+
+/* Bit definitions and macros for SCM_PACRC */
+#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28)
+#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24)
+#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20)
+#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16)
+#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8)
+#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4)
+#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRD */
+#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28)
+#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24)
+#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20)
+#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12)
+#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8)
+#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4)
+#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRE */
+#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28)
+#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24)
+#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20)
+#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16)
+#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12)
+#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8)
+#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4)
+
+/* Bit definitions and macros for SCM_PACRF */
+#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28)
+#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24)
+#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20)
+#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16)
+#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12)
+#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8)
+#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4)
+#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRG */
+#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28)
+
+/* Bit definitions and macros for SCM_PACRH */
+#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28)
+#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24)
+#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20)
+
+/* PACRn Assignments */
+#define PACR0(x) SCM_PACRA_PACR0(x)
+#define PACR1(x) SCM_PACRA_PACR1(x)
+#define PACR2(x) SCM_PACRA_PACR2(x)
+#define PACR8(x) SCM_PACRB_PACR8(x)
+#define PACR12(x) SCM_PACRB_PACR12(x)
+#define PACR16(x) SCM_PACRC_PACR16(x)
+#define PACR17(x) SCM_PACRC_PACR17(x)
+#define PACR18(x) SCM_PACRC_PACR18(x)
+#define PACR19(x) SCM_PACRC_PACR19(x)
+#define PACR21(x) SCM_PACRC_PACR21(x)
+#define PACR22(x) SCM_PACRC_PACR22(x)
+#define PACR23(x) SCM_PACRC_PACR23(x)
+#define PACR24(x) SCM_PACRD_PACR24(x)
+#define PACR25(x) SCM_PACRD_PACR25(x)
+#define PACR26(x) SCM_PACRD_PACR26(x)
+#define PACR28(x) SCM_PACRD_PACR28(x)
+#define PACR29(x) SCM_PACRD_PACR29(x)
+#define PACR30(x) SCM_PACRD_PACR30(x)
+#define PACR31(x) SCM_PACRD_PACR31(x)
+#define PACR32(x) SCM_PACRE_PACR32(x)
+#define PACR33(x) SCM_PACRE_PACR33(x)
+#define PACR34(x) SCM_PACRE_PACR34(x)
+#define PACR35(x) SCM_PACRE_PACR35(x)
+#define PACR36(x) SCM_PACRE_PACR36(x)
+#define PACR37(x) SCM_PACRE_PACR37(x)
+#define PACR38(x) SCM_PACRE_PACR38(x)
+#define PACR40(x) SCM_PACRF_PACR40(x)
+#define PACR41(x) SCM_PACRF_PACR41(x)
+#define PACR42(x) SCM_PACRF_PACR42(x)
+#define PACR43(x) SCM_PACRF_PACR43(x)
+#define PACR44(x) SCM_PACRF_PACR44(x)
+#define PACR45(x) SCM_PACRF_PACR45(x)
+#define PACR46(x) SCM_PACRF_PACR46(x)
+#define PACR47(x) SCM_PACRF_PACR47(x)
+#define PACR48(x) SCM_PACRG_PACR48(x)
+#define PACR56(x) SCM_PACRH_PACR56(x)
+#define PACR57(x) SCM_PACRH_PACR57(x)
+#define PACR58(x) SCM_PACRH_PACR58(x)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define CWCR_RO (0x8000)
+#define CWCR_CWR_WH (0x0100)
+#define CWCR_CWE (0x0080)
+#define CWRI_WINDOW (0x0060)
+#define CWRI_RESET (0x0040)
+#define CWRI_INT_RESET (0x0020)
+#define CWRI_INT (0x0000)
+#define CWCR_CWT(x) (((x)&0x001F))
+
+/* Bit definitions and macros for SCM_ISR */
+#define SCMISR_CFEI (0x02)
+#define SCMISR_CWIC (0x01)
+
+/* Bit definitions and macros for SCM_BCR */
+#define BCR_GBR (0x00000200)
+#define BCR_GBW (0x00000100)
+#define BCR_S7 (0x00000080)
+#define BCR_S6 (0x00000040)
+#define BCR_S4 (0x00000010)
+#define BCR_S1 (0x00000002)
+
+/* Bit definitions and macros for SCM_CFIER */
+#define CFIER_ECFEI (0x01)
+
+/* Bit definitions and macros for SCM_CFLOC */
+#define CFLOC_LOC (0x80)
+
+/* Bit definitions and macros for SCM_CFATR */
+#define CFATR_WRITE (0x80)
+#define CFATR_SZ32 (0x20)
+#define CFATR_SZ16 (0x10)
+#define CFATR_SZ08 (0x00)
+#define CFATR_CACHE (0x08)
+#define CFATR_MODE (0x02)
+#define CFATR_TYPE (0x01)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+/* Bit definitions and macros for FBCS_CSAR */
+#define CSAR_BA(x) (((x)&0xFFFF)<<16)
+
+/* Bit definitions and macros for FBCS_CSMR */
+#define CSMR_BAM(x) (((x)&0xFFFF)<<16)
+#define CSMR_BAM_4G (0xFFFF0000)
+#define CSMR_BAM_2G (0x7FFF0000)
+#define CSMR_BAM_1G (0x3FFF0000)
+#define CSMR_BAM_1024M (0x3FFF0000)
+#define CSMR_BAM_512M (0x1FFF0000)
+#define CSMR_BAM_256M (0x0FFF0000)
+#define CSMR_BAM_128M (0x07FF0000)
+#define CSMR_BAM_64M (0x03FF0000)
+#define CSMR_BAM_32M (0x01FF0000)
+#define CSMR_BAM_16M (0x00FF0000)
+#define CSMR_BAM_8M (0x007F0000)
+#define CSMR_BAM_4M (0x003F0000)
+#define CSMR_BAM_2M (0x001F0000)
+#define CSMR_BAM_1M (0x000F0000)
+#define CSMR_BAM_1024K (0x000F0000)
+#define CSMR_BAM_512K (0x00070000)
+#define CSMR_BAM_256K (0x00030000)
+#define CSMR_BAM_128K (0x00010000)
+#define CSMR_BAM_64K (0x00000000)
+#define CSMR_WP (0x00000100)
+#define CSMR_V (0x00000001)
+
+/* Bit definitions and macros for FBCS_CSCR */
+#define CSCR_SWS(x) (((x)&0x3F)<<26)
+#define CSCR_ASET(x) (((x)&0x03)<<20)
+#define CSCR_SWSEN (0x00800000)
+#define CSCR_ASET_4CLK (0x00300000)
+#define CSCR_ASET_3CLK (0x00200000)
+#define CSCR_ASET_2CLK (0x00100000)
+#define CSCR_ASET_1CLK (0x00000000)
+#define CSCR_RDAH(x) (((x)&0x03)<<18)
+#define CSCR_RDAH_4CYC (0x000C0000)
+#define CSCR_RDAH_3CYC (0x00080000)
+#define CSCR_RDAH_2CYC (0x00040000)
+#define CSCR_RDAH_1CYC (0x00000000)
+#define CSCR_WRAH(x) (((x)&0x03)<<16)
+#define CSCR_WDAH_4CYC (0x00003000)
+#define CSCR_WDAH_3CYC (0x00002000)
+#define CSCR_WDAH_2CYC (0x00001000)
+#define CSCR_WDAH_1CYC (0x00000000)
+#define CSCR_WS(x) (((x)&0x3F)<<10)
+#define CSCR_SBM (0x00000200)
+#define CSCR_AA (0x00000100)
+#define CSCR_PS_MASK (0x000000C0)
+#define CSCR_PS_32 (0x00000000)
+#define CSCR_PS_16 (0x00000080)
+#define CSCR_PS_8 (0x00000040)
+#define CSCR_BEM (0x00000020)
+#define CSCR_BSTR (0x00000010)
+#define CSCR_BSTW (0x00000008)
+
+/*********************************************************************
+* FlexCAN Module (CAN)
+*********************************************************************/
+/* Bit definitions and macros for CAN_CANMCR */
+#define CANMCR_MDIS (0x80000000)
+#define CANMCR_FRZ (0x40000000)
+#define CANMCR_HALT (0x10000000)
+#define CANMCR_NORDY (0x08000000)
+#define CANMCR_SOFTRST (0x02000000)
+#define CANMCR_FRZACK (0x01000000)
+#define CANMCR_SUPV (0x00800000)
+#define CANMCR_LPMACK (0x00100000)
+#define CANMCR_MAXMB(x) (((x)&0x0F))
+
+/* Bit definitions and macros for CAN_CANCTRL */
+#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
+#define CANCTRL_RJW(x) (((x)&0x03)<<22)
+#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
+#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
+#define CANCTRL_BOFFMSK (0x00008000)
+#define CANCTRL_ERRMSK (0x00004000)
+#define CANCTRL_CLKSRC (0x00002000)
+#define CANCTRL_LPB (0x00001000)
+#define CANCTRL_SMP (0x00000080)
+#define CANCTRL_BOFFREC (0x00000040)
+#define CANCTRL_TSYNC (0x00000020)
+#define CANCTRL_LBUF (0x00000010)
+#define CANCTRL_LOM (0x00000008)
+#define CANCTRL_PROPSEG(x) (((x)&0x07))
+
+/* Bit definitions and macros for CAN_TIMER */
+#define TIMER_TIMER(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for CAN_RXGMASK */
+#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
+
+/* Bit definitions and macros for CAN_ERRCNT */
+#define ERRCNT_TXECTR(x) (((x)&0xFF))
+#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for CAN_ERRSTAT */
+#define ERRSTAT_BITERR1 (0x00008000)
+#define ERRSTAT_BITERR0 (0x00004000)
+#define ERRSTAT_ACKERR (0x00002000)
+#define ERRSTAT_CRCERR (0x00001000)
+#define ERRSTAT_FRMERR (0x00000800)
+#define ERRSTAT_STFERR (0x00000400)
+#define ERRSTAT_TXWRN (0x00000200)
+#define ERRSTAT_RXWRN (0x00000100)
+#define ERRSTAT_IDLE (0x00000080)
+#define ERRSTAT_TXRX (0x00000040)
+#define ERRSTAT_FLT_BUSOFF (0x00000020)
+#define ERRSTAT_FLT_PASSIVE (0x00000010)
+#define ERRSTAT_FLT_ACTIVE (0x00000000)
+#define ERRSTAT_BOFFINT (0x00000004)
+#define ERRSTAT_ERRINT (0x00000002)
+#define ERRSTAT_WAKINT (0x00000001)
+
+/* Bit definitions and macros for CAN_IMASK */
+#define IMASK_BUF15M (0x00008000)
+#define IMASK_BUF14M (0x00004000)
+#define IMASK_BUF13M (0x00002000)
+#define IMASK_BUF12M (0x00001000)
+#define IMASK_BUF11M (0x00000800)
+#define IMASK_BUF10M (0x00000400)
+#define IMASK_BUF9M (0x00000200)
+#define IMASK_BUF8M (0x00000100)
+#define IMASK_BUF7M (0x00000080)
+#define IMASK_BUF6M (0x00000040)
+#define IMASK_BUF5M (0x00000020)
+#define IMASK_BUF4M (0x00000010)
+#define IMASK_BUF3M (0x00000008)
+#define IMASK_BUF2M (0x00000004)
+#define IMASK_BUF1M (0x00000002)
+#define IMASK_BUF0M (0x00000001)
+
+/* Bit definitions and macros for CAN_IFLAG */
+#define IFLAG_BUF15I (0x00008000)
+#define IFLAG_BUF14I (0x00004000)
+#define IFLAG_BUF13I (0x00002000)
+#define IFLAG_BUF12I (0x00001000)
+#define IFLAG_BUF11I (0x00000800)
+#define IFLAG_BUF10I (0x00000400)
+#define IFLAG_BUF9I (0x00000200)
+#define IFLAG_BUF8I (0x00000100)
+#define IFLAG_BUF7I (0x00000080)
+#define IFLAG_BUF6I (0x00000040)
+#define IFLAG_BUF5I (0x00000020)
+#define IFLAG_BUF4I (0x00000010)
+#define IFLAG_BUF3I (0x00000008)
+#define IFLAG_BUF2I (0x00000004)
+#define IFLAG_BUF1I (0x00000002)
+#define IFLAG_BUF0I (0x00000001)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INTC0_EPORT INTC_IPRL_INT1
+
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_RSVD1 (29)
+#define INT0_LO_I2C (30)
+#define INT0_LO_QSPI (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_FEC_TXF (36)
+#define INT0_HI_FEC_TXB (37)
+#define INT0_HI_FEC_UN (38)
+#define INT0_HI_FEC_RL (39)
+#define INT0_HI_FEC_RXF (40)
+#define INT0_HI_FEC_RXB (41)
+#define INT0_HI_FEC_MII (42)
+#define INT0_HI_FEC_LC (43)
+#define INT0_HI_FEC_HBERR (44)
+#define INT0_HI_FEC_GRA (45)
+#define INT0_HI_FEC_EBERR (46)
+#define INT0_HI_FEC_BABT (47)
+#define INT0_HI_FEC_BABR (48)
+/* 49 - 61 Reserved */
+#define INT0_HI_SCM (62)
+
+/* Bit definitions and macros for INTC_IPRH */
+#define INTC_IPRH_INT63 (0x80000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT32 (0x00000001)
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for INTC_ICONFIG */
+#define INTC_ICFG_ELVLPRI7 (0x8000)
+#define INTC_ICFG_ELVLPRI6 (0x4000)
+#define INTC_ICFG_ELVLPRI5 (0x2000)
+#define INTC_ICFG_ELVLPRI4 (0x1000)
+#define INTC_ICFG_ELVLPRI3 (0x0800)
+#define INTC_ICFG_ELVLPRI2 (0x0400)
+#define INTC_ICFG_ELVLPRI1 (0x0200)
+#define INTC_ICFG_EMASK (0x0020)
+
+/* Bit definitions and macros for INTC_SIMR */
+#define INTC_SIMR_SALL (0x40)
+#define INTC_SIMR_SIMR(x) ((x)&0x3F)
+
+/* Bit definitions and macros for INTC_CIMR */
+#define INTC_CIMR_CALL (0x40)
+#define INTC_CIMR_CIMR(x) ((x)&0x3F)
+
+/* Bit definitions and macros for INTC_CLMASK */
+#define INTC_CLMASK_CLMASK(x) ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_SLMASK */
+#define INTC_SLMASK_SLMASK(x) ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_ICR */
+#define INTC_ICR_IL(x) ((x)&0x07)
+
+/*********************************************************************
+* Queued Serial Peripheral Interface (QSPI)
+*********************************************************************/
+/* Bit definitions and macros for QSPI_QMR */
+#define QSPI_QMR_MSTR (0x8000)
+#define QSPI_QMR_DOHIE (0x4000)
+#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
+#define QSPI_QMR_CPOL (0x0200)
+#define QSPI_QMR_CPHA (0x0100)
+#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QDLYR */
+#define QSPI_QDLYR_SPE (0x8000)
+#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
+#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QWR */
+#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
+#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
+#define QSPI_QWR_CSIV (0x1000)
+#define QSPI_QWR_WRTO (0x2000)
+#define QSPI_QWR_WREN (0x4000)
+#define QSPI_QWR_HALT (0x8000)
+
+/* Bit definitions and macros for QSPI_QIR */
+#define QSPI_QIR_WCEFB (0x8000)
+#define QSPI_QIR_ABRTB (0x4000)
+#define QSPI_QIR_ABRTL (0x1000)
+#define QSPI_QIR_WCEFE (0x0800)
+#define QSPI_QIR_ABRTE (0x0400)
+#define QSPI_QIR_SPIFE (0x0100)
+#define QSPI_QIR_WCEF (0x0008)
+#define QSPI_QIR_ABRT (0x0004)
+#define QSPI_QIR_SPIF (0x0001)
+
+/* Bit definitions and macros for QSPI_QAR */
+#define QSPI_QAR_ADDR(x) ((x)&0x003F)
+#define QSPI_QAR_TRANS (0x0000)
+#define QSPI_QAR_RECV (0x0010)
+#define QSPI_QAR_CMD (0x0020)
+
+/* Bit definitions and macros for QSPI_QDR */
+#define QSPI_QDR_CONT (0x8000)
+#define QSPI_QDR_BITSE (0x4000)
+#define QSPI_QDR_DT (0x2000)
+#define QSPI_QDR_DSCK (0x1000)
+#define QSPI_QDR_QSPI_CS3 (0x0800)
+#define QSPI_QDR_QSPI_CS2 (0x0400)
+#define QSPI_QDR_QSPI_CS1 (0x0200)
+#define QSPI_QDR_QSPI_CS0 (0x0100)
+
+/*********************************************************************
+* Pulse Width Modulation (PWM)
+*********************************************************************/
+/* Bit definitions and macros for PWM_E */
+#define PWM_EN_PWME7 (0x80)
+#define PWM_EN_PWME5 (0x20)
+#define PWM_EN_PWME3 (0x08)
+#define PWM_EN_PWME1 (0x02)
+
+/* Bit definitions and macros for PWM_POL */
+#define PWM_POL_PPOL7 (0x80)
+#define PWM_POL_PPOL5 (0x20)
+#define PWM_POL_PPOL3 (0x08)
+#define PWM_POL_PPOL1 (0x02)
+
+/* Bit definitions and macros for PWM_CLK */
+#define PWM_CLK_PCLK7 (0x80)
+#define PWM_CLK_PCLK5 (0x20)
+#define PWM_CLK_PCLK3 (0x08)
+#define PWM_CLK_PCLK1 (0x02)
+
+/* Bit definitions and macros for PWM_PRCLK */
+#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
+#define PWM_PRCLK_PCKA(x) ((x)&0x07)
+
+/* Bit definitions and macros for PWM_CAE */
+#define PWM_CAE_CAE7 (0x80)
+#define PWM_CAE_CAE5 (0x20)
+#define PWM_CAE_CAE3 (0x08)
+#define PWM_CAE_CAE1 (0x02)
+
+/* Bit definitions and macros for PWM_CTL */
+#define PWM_CTL_CON67 (0x80)
+#define PWM_CTL_CON45 (0x40)
+#define PWM_CTL_CON23 (0x20)
+#define PWM_CTL_CON01 (0x10)
+#define PWM_CTL_PSWAR (0x08)
+#define PWM_CTL_PFRZ (0x04)
+
+/* Bit definitions and macros for PWM_SDN */
+#define PWM_SDN_IF (0x80)
+#define PWM_SDN_IE (0x40)
+#define PWM_SDN_RESTART (0x20)
+#define PWM_SDN_LVL (0x10)
+#define PWM_SDN_PWM7IN (0x04)
+#define PWM_SDN_PWM7IL (0x02)
+#define PWM_SDN_SDNEN (0x01)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT (0x0008)
+#define WTM_WCR_DOZE (0x0004)
+#define WTM_WCR_HALTED (0x0002)
+#define WTM_WCR_EN (0x0001)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
+#define CCM_CCR_LIMP (0x0041)
+#define CCM_CCR_LOAD (0x0021)
+#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define CCM_CCR_OSC_MODE (0x0005)
+#define CCM_CCR_PLL_MODE (0x0003)
+#define CCM_CCR_RESERVED (0x0001)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
+#define CCM_RCON_LIMP (0x0041)
+#define CCM_RCON_LOAD (0x0021)
+#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define CCM_RCON_OSC_MODE (0x0005)
+#define CCM_RCON_PLL_MODE (0x0003)
+#define CCM_RCON_RESERVED (0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
+#define CCM_CIR_PRN(x) ((x)&0x003F)
+
+/* Bit definitions and macros for CCM_MISCCR */
+#define CCM_MISCCR_PLL_LOCK (0x2000)
+#define CCM_MISCCR_LIMP (0x1000)
+#define CCM_MISCCR_LCD_CHEN (0x0100)
+#define CCM_MISCCR_SSI_PUE (0x0080)
+#define CCM_MISCCR_SSI_PUS (0x0040)
+#define CCM_MISCCR_TIM_DMA (0x0020)
+#define CCM_MISCCR_SSI_SRC (0x0010)
+#define CCM_MISCCR_USBDIV (0x0002)
+#define CCM_MISCCR_USBSRC (0x0001)
+
+/* Bit definitions and macros for CCM_CDR */
+#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
+#define CCM_CDR_SSIDIV(x) ((x)&0x000F)
+
+/* Bit definitions and macros for CCM_UHCSR */
+#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
+#define CCM_UHCSR_WKUP (0x0004)
+#define CCM_UHCSR_UHMIE (0x0002)
+#define CCM_UHCSR_XPDE (0x0001)
+
+/* Bit definitions and macros for CCM_UOCSR */
+#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
+#define CCM_UOCSR_DPPD (0x2000)
+#define CCM_UOCSR_DMPD (0x1000)
+#define CCM_UOCSR_DRV_VBUS (0x0800)
+#define CCM_UOCSR_CRG_VBUS (0x0400)
+#define CCM_UOCSR_DCR_VBUS (0x0200)
+#define CCM_UOCSR_DPPU (0x0100)
+#define CCM_UOCSR_AVLD (0x0080)
+#define CCM_UOCSR_BVLD (0x0040)
+#define CCM_UOCSR_VVLD (0x0020)
+#define CCM_UOCSR_SEND (0x0010)
+#define CCM_UOCSR_PWRFLT (0x0008)
+#define CCM_UOCSR_WKUP (0x0004)
+#define CCM_UOCSR_UOMIE (0x0002)
+#define CCM_UOCSR_XPDE (0x0001)
+
+/* not done yet */
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR_FECH_L */
+#define GPIO_PODR_FECH_L7 (0x80)
+#define GPIO_PODR_FECH_L6 (0x40)
+#define GPIO_PODR_FECH_L5 (0x20)
+#define GPIO_PODR_FECH_L4 (0x10)
+#define GPIO_PODR_FECH_L3 (0x08)
+#define GPIO_PODR_FECH_L2 (0x04)
+#define GPIO_PODR_FECH_L1 (0x02)
+#define GPIO_PODR_FECH_L0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_SSI */
+#define GPIO_PODR_SSI_4 (0x10)
+#define GPIO_PODR_SSI_3 (0x08)
+#define GPIO_PODR_SSI_2 (0x04)
+#define GPIO_PODR_SSI_1 (0x02)
+#define GPIO_PODR_SSI_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BUSCTL */
+#define GPIO_PODR_BUSCTL_3 (0x08)
+#define GPIO_PODR_BUSCTL_2 (0x04)
+#define GPIO_PODR_BUSCTL_1 (0x02)
+#define GPIO_PODR_BUSCTL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BE */
+#define GPIO_PODR_BE_3 (0x08)
+#define GPIO_PODR_BE_2 (0x04)
+#define GPIO_PODR_BE_1 (0x02)
+#define GPIO_PODR_BE_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_CS */
+#define GPIO_PODR_CS_5 (0x20)
+#define GPIO_PODR_CS_4 (0x10)
+#define GPIO_PODR_CS_3 (0x08)
+#define GPIO_PODR_CS_2 (0x04)
+#define GPIO_PODR_CS_1 (0x02)
+
+/* Bit definitions and macros for GPIO_PODR_PWM */
+#define GPIO_PODR_PWM_5 (0x20)
+#define GPIO_PODR_PWM_4 (0x10)
+#define GPIO_PODR_PWM_3 (0x08)
+#define GPIO_PODR_PWM_2 (0x04)
+
+/* Bit definitions and macros for GPIO_PODR_FECI2C */
+#define GPIO_PODR_FECI2C_3 (0x08)
+#define GPIO_PODR_FECI2C_2 (0x04)
+#define GPIO_PODR_FECI2C_1 (0x02)
+#define GPIO_PODR_FECI2C_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_UART */
+#define GPIO_PODR_UART_7 (0x80)
+#define GPIO_PODR_UART_6 (0x40)
+#define GPIO_PODR_UART_5 (0x20)
+#define GPIO_PODR_UART_4 (0x10)
+#define GPIO_PODR_UART_3 (0x08)
+#define GPIO_PODR_UART_2 (0x04)
+#define GPIO_PODR_UART_1 (0x02)
+#define GPIO_PODR_UART_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_QSPI */
+#define GPIO_PODR_QSPI_5 (0x20)
+#define GPIO_PODR_QSPI_4 (0x10)
+#define GPIO_PODR_QSPI_3 (0x08)
+#define GPIO_PODR_QSPI_2 (0x04)
+#define GPIO_PODR_QSPI_1 (0x02)
+#define GPIO_PODR_QSPI_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_TIMER */
+#define GPIO_PODR_TIMER_3 (0x08)
+#define GPIO_PODR_TIMER_2 (0x04)
+#define GPIO_PODR_TIMER_1 (0x02)
+#define GPIO_PODR_TIMER_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAH */
+#define GPIO_PODR_LCDDATAH_1 (0x02)
+#define GPIO_PODR_LCDDATAH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAM */
+#define GPIO_PODR_LCDDATAM_7 (0x80)
+#define GPIO_PODR_LCDDATAM_6 (0x40)
+#define GPIO_PODR_LCDDATAM_5 (0x20)
+#define GPIO_PODR_LCDDATAM_4 (0x10)
+#define GPIO_PODR_LCDDATAM_3 (0x08)
+#define GPIO_PODR_LCDDATAM_2 (0x04)
+#define GPIO_PODR_LCDDATAM_1 (0x02)
+#define GPIO_PODR_LCDDATAM_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAL */
+#define GPIO_PODR_LCDDATAL_7 (0x80)
+#define GPIO_PODR_LCDDATAL_6 (0x40)
+#define GPIO_PODR_LCDDATAL_5 (0x20)
+#define GPIO_PODR_LCDDATAL_4 (0x10)
+#define GPIO_PODR_LCDDATAL_3 (0x08)
+#define GPIO_PODR_LCDDATAL_2 (0x04)
+#define GPIO_PODR_LCDDATAL_1 (0x02)
+#define GPIO_PODR_LCDDATAL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLH */
+#define GPIO_PODR_LCDCTLH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLL */
+#define GPIO_PODR_LCDCTLL_7 (0x80)
+#define GPIO_PODR_LCDCTLL_6 (0x40)
+#define GPIO_PODR_LCDCTLL_5 (0x20)
+#define GPIO_PODR_LCDCTLL_4 (0x10)
+#define GPIO_PODR_LCDCTLL_3 (0x08)
+#define GPIO_PODR_LCDCTLL_2 (0x04)
+#define GPIO_PODR_LCDCTLL_1 (0x02)
+#define GPIO_PODR_LCDCTLL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_FECH */
+#define GPIO_PDDR_FECH_L7 (0x80)
+#define GPIO_PDDR_FECH_L6 (0x40)
+#define GPIO_PDDR_FECH_L5 (0x20)
+#define GPIO_PDDR_FECH_L4 (0x10)
+#define GPIO_PDDR_FECH_L3 (0x08)
+#define GPIO_PDDR_FECH_L2 (0x04)
+#define GPIO_PDDR_FECH_L1 (0x02)
+#define GPIO_PDDR_FECH_L0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_SSI */
+#define GPIO_PDDR_SSI_4 (0x10)
+#define GPIO_PDDR_SSI_3 (0x08)
+#define GPIO_PDDR_SSI_2 (0x04)
+#define GPIO_PDDR_SSI_1 (0x02)
+#define GPIO_PDDR_SSI_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BUSCTL */
+#define GPIO_PDDR_BUSCTL_3 (0x08)
+#define GPIO_PDDR_BUSCTL_2 (0x04)
+#define GPIO_PDDR_BUSCTL_1 (0x02)
+#define GPIO_PDDR_BUSCTL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BE */
+#define GPIO_PDDR_BE_3 (0x08)
+#define GPIO_PDDR_BE_2 (0x04)
+#define GPIO_PDDR_BE_1 (0x02)
+#define GPIO_PDDR_BE_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_CS */
+#define GPIO_PDDR_CS_1 (0x02)
+#define GPIO_PDDR_CS_2 (0x04)
+#define GPIO_PDDR_CS_3 (0x08)
+#define GPIO_PDDR_CS_4 (0x10)
+#define GPIO_PDDR_CS_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_PWM */
+#define GPIO_PDDR_PWM_2 (0x04)
+#define GPIO_PDDR_PWM_3 (0x08)
+#define GPIO_PDDR_PWM_4 (0x10)
+#define GPIO_PDDR_PWM_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_FECI2C */
+#define GPIO_PDDR_FECI2C_0 (0x01)
+#define GPIO_PDDR_FECI2C_1 (0x02)
+#define GPIO_PDDR_FECI2C_2 (0x04)
+#define GPIO_PDDR_FECI2C_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_UART */
+#define GPIO_PDDR_UART_0 (0x01)
+#define GPIO_PDDR_UART_1 (0x02)
+#define GPIO_PDDR_UART_2 (0x04)
+#define GPIO_PDDR_UART_3 (0x08)
+#define GPIO_PDDR_UART_4 (0x10)
+#define GPIO_PDDR_UART_5 (0x20)
+#define GPIO_PDDR_UART_6 (0x40)
+#define GPIO_PDDR_UART_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_QSPI */
+#define GPIO_PDDR_QSPI_0 (0x01)
+#define GPIO_PDDR_QSPI_1 (0x02)
+#define GPIO_PDDR_QSPI_2 (0x04)
+#define GPIO_PDDR_QSPI_3 (0x08)
+#define GPIO_PDDR_QSPI_4 (0x10)
+#define GPIO_PDDR_QSPI_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_TIMER */
+#define GPIO_PDDR_TIMER_0 (0x01)
+#define GPIO_PDDR_TIMER_1 (0x02)
+#define GPIO_PDDR_TIMER_2 (0x04)
+#define GPIO_PDDR_TIMER_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */
+#define GPIO_PDDR_LCDDATAH_0 (0x01)
+#define GPIO_PDDR_LCDDATAH_1 (0x02)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */
+#define GPIO_PDDR_LCDDATAM_0 (0x01)
+#define GPIO_PDDR_LCDDATAM_1 (0x02)
+#define GPIO_PDDR_LCDDATAM_2 (0x04)
+#define GPIO_PDDR_LCDDATAM_3 (0x08)
+#define GPIO_PDDR_LCDDATAM_4 (0x10)
+#define GPIO_PDDR_LCDDATAM_5 (0x20)
+#define GPIO_PDDR_LCDDATAM_6 (0x40)
+#define GPIO_PDDR_LCDDATAM_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */
+#define GPIO_PDDR_LCDDATAL_0 (0x01)
+#define GPIO_PDDR_LCDDATAL_1 (0x02)
+#define GPIO_PDDR_LCDDATAL_2 (0x04)
+#define GPIO_PDDR_LCDDATAL_3 (0x08)
+#define GPIO_PDDR_LCDDATAL_4 (0x10)
+#define GPIO_PDDR_LCDDATAL_5 (0x20)
+#define GPIO_PDDR_LCDDATAL_6 (0x40)
+#define GPIO_PDDR_LCDDATAL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */
+#define GPIO_PDDR_LCDCTLH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */
+#define GPIO_PDDR_LCDCTLL_0 (0x01)
+#define GPIO_PDDR_LCDCTLL_1 (0x02)
+#define GPIO_PDDR_LCDCTLL_2 (0x04)
+#define GPIO_PDDR_LCDCTLL_3 (0x08)
+#define GPIO_PDDR_LCDCTLL_4 (0x10)
+#define GPIO_PDDR_LCDCTLL_5 (0x20)
+#define GPIO_PDDR_LCDCTLL_6 (0x40)
+#define GPIO_PDDR_LCDCTLL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECH */
+#define GPIO_PPDSDR_FECH_L0 (0x01)
+#define GPIO_PPDSDR_FECH_L1 (0x02)
+#define GPIO_PPDSDR_FECH_L2 (0x04)
+#define GPIO_PPDSDR_FECH_L3 (0x08)
+#define GPIO_PPDSDR_FECH_L4 (0x10)
+#define GPIO_PPDSDR_FECH_L5 (0x20)
+#define GPIO_PPDSDR_FECH_L6 (0x40)
+#define GPIO_PPDSDR_FECH_L7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_SSI */
+#define GPIO_PPDSDR_SSI_0 (0x01)
+#define GPIO_PPDSDR_SSI_1 (0x02)
+#define GPIO_PPDSDR_SSI_2 (0x04)
+#define GPIO_PPDSDR_SSI_3 (0x08)
+#define GPIO_PPDSDR_SSI_4 (0x10)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */
+#define GPIO_PPDSDR_BUSCTL_0 (0x01)
+#define GPIO_PPDSDR_BUSCTL_1 (0x02)
+#define GPIO_PPDSDR_BUSCTL_2 (0x04)
+#define GPIO_PPDSDR_BUSCTL_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BE */
+#define GPIO_PPDSDR_BE_0 (0x01)
+#define GPIO_PPDSDR_BE_1 (0x02)
+#define GPIO_PPDSDR_BE_2 (0x04)
+#define GPIO_PPDSDR_BE_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_CS */
+#define GPIO_PPDSDR_CS_1 (0x02)
+#define GPIO_PPDSDR_CS_2 (0x04)
+#define GPIO_PPDSDR_CS_3 (0x08)
+#define GPIO_PPDSDR_CS_4 (0x10)
+#define GPIO_PPDSDR_CS_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_PWM */
+#define GPIO_PPDSDR_PWM_2 (0x04)
+#define GPIO_PPDSDR_PWM_3 (0x08)
+#define GPIO_PPDSDR_PWM_4 (0x10)
+#define GPIO_PPDSDR_PWM_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */
+#define GPIO_PPDSDR_FECI2C_0 (0x01)
+#define GPIO_PPDSDR_FECI2C_1 (0x02)
+#define GPIO_PPDSDR_FECI2C_2 (0x04)
+#define GPIO_PPDSDR_FECI2C_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_UART */
+#define GPIO_PPDSDR_UART_0 (0x01)
+#define GPIO_PPDSDR_UART_1 (0x02)
+#define GPIO_PPDSDR_UART_2 (0x04)
+#define GPIO_PPDSDR_UART_3 (0x08)
+#define GPIO_PPDSDR_UART_4 (0x10)
+#define GPIO_PPDSDR_UART_5 (0x20)
+#define GPIO_PPDSDR_UART_6 (0x40)
+#define GPIO_PPDSDR_UART_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_QSPI */
+#define GPIO_PPDSDR_QSPI_0 (0x01)
+#define GPIO_PPDSDR_QSPI_1 (0x02)
+#define GPIO_PPDSDR_QSPI_2 (0x04)
+#define GPIO_PPDSDR_QSPI_3 (0x08)
+#define GPIO_PPDSDR_QSPI_4 (0x10)
+#define GPIO_PPDSDR_QSPI_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_TIMER */
+#define GPIO_PPDSDR_TIMER_0 (0x01)
+#define GPIO_PPDSDR_TIMER_1 (0x02)
+#define GPIO_PPDSDR_TIMER_2 (0x04)
+#define GPIO_PPDSDR_TIMER_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */
+#define GPIO_PPDSDR_LCDDATAH_0 (0x01)
+#define GPIO_PPDSDR_LCDDATAH_1 (0x02)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */
+#define GPIO_PPDSDR_LCDDATAM_0 (0x01)
+#define GPIO_PPDSDR_LCDDATAM_1 (0x02)
+#define GPIO_PPDSDR_LCDDATAM_2 (0x04)
+#define GPIO_PPDSDR_LCDDATAM_3 (0x08)
+#define GPIO_PPDSDR_LCDDATAM_4 (0x10)
+#define GPIO_PPDSDR_LCDDATAM_5 (0x20)
+#define GPIO_PPDSDR_LCDDATAM_6 (0x40)
+#define GPIO_PPDSDR_LCDDATAM_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */
+#define GPIO_PPDSDR_LCDDATAL_0 (0x01)
+#define GPIO_PPDSDR_LCDDATAL_1 (0x02)
+#define GPIO_PPDSDR_LCDDATAL_2 (0x04)
+#define GPIO_PPDSDR_LCDDATAL_3 (0x08)
+#define GPIO_PPDSDR_LCDDATAL_4 (0x10)
+#define GPIO_PPDSDR_LCDDATAL_5 (0x20)
+#define GPIO_PPDSDR_LCDDATAL_6 (0x40)
+#define GPIO_PPDSDR_LCDDATAL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */
+#define GPIO_PPDSDR_LCDCTLH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */
+#define GPIO_PPDSDR_LCDCTLL_0 (0x01)
+#define GPIO_PPDSDR_LCDCTLL_1 (0x02)
+#define GPIO_PPDSDR_LCDCTLL_2 (0x04)
+#define GPIO_PPDSDR_LCDCTLL_3 (0x08)
+#define GPIO_PPDSDR_LCDCTLL_4 (0x10)
+#define GPIO_PPDSDR_LCDCTLL_5 (0x20)
+#define GPIO_PPDSDR_LCDCTLL_6 (0x40)
+#define GPIO_PPDSDR_LCDCTLL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECH */
+#define GPIO_PCLRR_FECH_L0 (0x01)
+#define GPIO_PCLRR_FECH_L1 (0x02)
+#define GPIO_PCLRR_FECH_L2 (0x04)
+#define GPIO_PCLRR_FECH_L3 (0x08)
+#define GPIO_PCLRR_FECH_L4 (0x10)
+#define GPIO_PCLRR_FECH_L5 (0x20)
+#define GPIO_PCLRR_FECH_L6 (0x40)
+#define GPIO_PCLRR_FECH_L7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_SSI */
+#define GPIO_PCLRR_SSI_0 (0x01)
+#define GPIO_PCLRR_SSI_1 (0x02)
+#define GPIO_PCLRR_SSI_2 (0x04)
+#define GPIO_PCLRR_SSI_3 (0x08)
+#define GPIO_PCLRR_SSI_4 (0x10)
+
+/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */
+#define GPIO_PCLRR_BUSCTL_L0 (0x01)
+#define GPIO_PCLRR_BUSCTL_L1 (0x02)
+#define GPIO_PCLRR_BUSCTL_L2 (0x04)
+#define GPIO_PCLRR_BUSCTL_L3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_BE */
+#define GPIO_PCLRR_BE_0 (0x01)
+#define GPIO_PCLRR_BE_1 (0x02)
+#define GPIO_PCLRR_BE_2 (0x04)
+#define GPIO_PCLRR_BE_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_CS */
+#define GPIO_PCLRR_CS_1 (0x02)
+#define GPIO_PCLRR_CS_2 (0x04)
+#define GPIO_PCLRR_CS_3 (0x08)
+#define GPIO_PCLRR_CS_4 (0x10)
+#define GPIO_PCLRR_CS_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_PWM */
+#define GPIO_PCLRR_PWM_2 (0x04)
+#define GPIO_PCLRR_PWM_3 (0x08)
+#define GPIO_PCLRR_PWM_4 (0x10)
+#define GPIO_PCLRR_PWM_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECI2C */
+#define GPIO_PCLRR_FECI2C_0 (0x01)
+#define GPIO_PCLRR_FECI2C_1 (0x02)
+#define GPIO_PCLRR_FECI2C_2 (0x04)
+#define GPIO_PCLRR_FECI2C_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_UART */
+#define GPIO_PCLRR_UART0 (0x01)
+#define GPIO_PCLRR_UART1 (0x02)
+#define GPIO_PCLRR_UART2 (0x04)
+#define GPIO_PCLRR_UART3 (0x08)
+#define GPIO_PCLRR_UART4 (0x10)
+#define GPIO_PCLRR_UART5 (0x20)
+#define GPIO_PCLRR_UART6 (0x40)
+#define GPIO_PCLRR_UART7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_QSPI */
+#define GPIO_PCLRR_QSPI0 (0x01)
+#define GPIO_PCLRR_QSPI1 (0x02)
+#define GPIO_PCLRR_QSPI2 (0x04)
+#define GPIO_PCLRR_QSPI3 (0x08)
+#define GPIO_PCLRR_QSPI4 (0x10)
+#define GPIO_PCLRR_QSPI5 (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_TIMER */
+#define GPIO_PCLRR_TIMER0 (0x01)
+#define GPIO_PCLRR_TIMER1 (0x02)
+#define GPIO_PCLRR_TIMER2 (0x04)
+#define GPIO_PCLRR_TIMER3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */
+#define GPIO_PCLRR_LCDDATAH0 (0x01)
+#define GPIO_PCLRR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */
+#define GPIO_PCLRR_LCDDATAM0 (0x01)
+#define GPIO_PCLRR_LCDDATAM1 (0x02)
+#define GPIO_PCLRR_LCDDATAM2 (0x04)
+#define GPIO_PCLRR_LCDDATAM3 (0x08)
+#define GPIO_PCLRR_LCDDATAM4 (0x10)
+#define GPIO_PCLRR_LCDDATAM5 (0x20)
+#define GPIO_PCLRR_LCDDATAM6 (0x40)
+#define GPIO_PCLRR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */
+#define GPIO_PCLRR_LCDDATAL0 (0x01)
+#define GPIO_PCLRR_LCDDATAL1 (0x02)
+#define GPIO_PCLRR_LCDDATAL2 (0x04)
+#define GPIO_PCLRR_LCDDATAL3 (0x08)
+#define GPIO_PCLRR_LCDDATAL4 (0x10)
+#define GPIO_PCLRR_LCDDATAL5 (0x20)
+#define GPIO_PCLRR_LCDDATAL6 (0x40)
+#define GPIO_PCLRR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */
+#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */
+#define GPIO_PCLRR_LCDCTLL0 (0x01)
+#define GPIO_PCLRR_LCDCTLL1 (0x02)
+#define GPIO_PCLRR_LCDCTLL2 (0x04)
+#define GPIO_PCLRR_LCDCTLL3 (0x08)
+#define GPIO_PCLRR_LCDCTLL4 (0x10)
+#define GPIO_PCLRR_LCDCTLL5 (0x20)
+#define GPIO_PCLRR_LCDCTLL6 (0x40)
+#define GPIO_PCLRR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for GPIO_PAR_FEC */
+#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
+#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
+#define GPIO_PAR_FEC_7W_GPIO (0x00)
+#define GPIO_PAR_FEC_7W_URTS1 (0x04)
+#define GPIO_PAR_FEC_7W_FEC (0x0C)
+#define GPIO_PAR_FEC_MII_GPIO (0x00)
+#define GPIO_PAR_FEC_MII_UART (0x01)
+#define GPIO_PAR_FEC_MII_FEC (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_PWM */
+#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
+#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2)
+#define GPIO_PAR_PWM5 (0x10)
+#define GPIO_PAR_PWM7 (0x20)
+
+/* Bit definitions and macros for GPIO_PAR_BUSCTL */
+#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3)
+#define GPIO_PAR_BUSCTL_RWB (0x20)
+#define GPIO_PAR_BUSCTL_TA (0x40)
+#define GPIO_PAR_BUSCTL_OE (0x80)
+#define GPIO_PAR_BUSCTL_OE_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_OE_OE (0x80)
+#define GPIO_PAR_BUSCTL_TA_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_TA_TA (0x40)
+#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_RWB_RWB (0x20)
+#define GPIO_PAR_BUSCTL_TS_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10)
+#define GPIO_PAR_BUSCTL_TS_TS (0x18)
+
+/* Bit definitions and macros for GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0)
+#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_MDC_GPIO (0x00)
+#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40)
+#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
+#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0)
+#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00)
+#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10)
+#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
+#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30)
+#define GPIO_PAR_FECI2C_SCL_GPIO (0x00)
+#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04)
+#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
+#define GPIO_PAR_FECI2C_SDA_GPIO (0x00)
+#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02)
+#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_BE */
+#define GPIO_PAR_BE0 (0x01)
+#define GPIO_PAR_BE1 (0x02)
+#define GPIO_PAR_BE2 (0x04)
+#define GPIO_PAR_BE3 (0x08)
+
+/* Bit definitions and macros for GPIO_PAR_CS */
+#define GPIO_PAR_CS1 (0x02)
+#define GPIO_PAR_CS2 (0x04)
+#define GPIO_PAR_CS3 (0x08)
+#define GPIO_PAR_CS4 (0x10)
+#define GPIO_PAR_CS5 (0x20)
+#define GPIO_PAR_CS1_GPIO (0x00)
+#define GPIO_PAR_CS1_SDCS1 (0x01)
+#define GPIO_PAR_CS1_CS1 (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_SSI */
+#define GPIO_PAR_SSI_MCLK (0x0080)
+#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12)
+#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_UART */
+#define GPIO_PAR_UART_TXD0 (0x0001)
+#define GPIO_PAR_UART_RXD0 (0x0002)
+#define GPIO_PAR_UART_RTS0 (0x0004)
+#define GPIO_PAR_UART_CTS0 (0x0008)
+#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_UART_CTS1_GPIO (0x0000)
+#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800)
+#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400)
+#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00)
+#define GPIO_PAR_UART_RTS1_GPIO (0x0000)
+#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200)
+#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100)
+#define GPIO_PAR_UART_RTS1_URTS1 (0x0300)
+#define GPIO_PAR_UART_RXD1_GPIO (0x0000)
+#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080)
+#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040)
+#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0)
+#define GPIO_PAR_UART_TXD1_GPIO (0x0000)
+#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020)
+#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010)
+#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030)
+
+/* Bit definitions and macros for GPIO_PAR_QSPI */
+#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12)
+#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_TIMER */
+#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0)
+#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIN3_GPIO (0x00)
+#define GPIO_PAR_TIN3_TOUT3 (0x80)
+#define GPIO_PAR_TIN3_URXD2 (0x40)
+#define GPIO_PAR_TIN3_TIN3 (0xC0)
+#define GPIO_PAR_TIN2_GPIO (0x00)
+#define GPIO_PAR_TIN2_TOUT2 (0x20)
+#define GPIO_PAR_TIN2_UTXD2 (0x10)
+#define GPIO_PAR_TIN2_TIN2 (0x30)
+#define GPIO_PAR_TIN1_GPIO (0x00)
+#define GPIO_PAR_TIN1_TOUT1 (0x08)
+#define GPIO_PAR_TIN1_DACK1 (0x04)
+#define GPIO_PAR_TIN1_TIN1 (0x0C)
+#define GPIO_PAR_TIN0_GPIO (0x00)
+#define GPIO_PAR_TIN0_TOUT0 (0x02)
+#define GPIO_PAR_TIN0_DREQ0 (0x01)
+#define GPIO_PAR_TIN0_TIN0 (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_LCDDATA */
+#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03)
+#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2)
+#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4)
+#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6)
+
+/* Bit definitions and macros for GPIO_PAR_LCDCTL */
+#define GPIO_PAR_LCDCTL_CLS (0x0001)
+#define GPIO_PAR_LCDCTL_PS (0x0002)
+#define GPIO_PAR_LCDCTL_REV (0x0004)
+#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008)
+#define GPIO_PAR_LCDCTL_CONTRAST (0x0010)
+#define GPIO_PAR_LCDCTL_LSCLK (0x0020)
+#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040)
+#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080)
+#define GPIO_PAR_LCDCTL_ACD_OE (0x0100)
+
+/* Bit definitions and macros for GPIO_PAR_IRQ */
+#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12)
+
+/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */
+#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03)
+#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2)
+#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03)
+#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_DSCR_I2C */
+#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_PWM */
+#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_FEC */
+#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_UART */
+#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03)
+#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2)
+
+/* Bit definitions and macros for GPIO_DSCR_QSPI */
+#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_TIMER */
+#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_SSI */
+#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_LCD */
+#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_CLKRST */
+#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_IRQ */
+#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)
+
+/* not done yet */
+/*********************************************************************
+* LCD Controller (LCDC)
+*********************************************************************/
+/* Bit definitions and macros for LCDC_LSSAR */
+#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LSR */
+#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
+#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
+
+/* Bit definitions and macros for LCDC_LVPWR */
+#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
+
+/* Bit definitions and macros for LCDC_LCPR */
+#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
+#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
+#define LCDC_LCPR_OP (0x10000000)
+#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
+#define LCDC_LCPR_CC_TRANSPARENT (0x00000000)
+#define LCDC_LCPR_CC_OR (0x40000000)
+#define LCDC_LCPR_CC_XOR (0x80000000)
+#define LCDC_LCPR_CC_AND (0xC0000000)
+#define LCDC_LCPR_OP_ON (0x10000000)
+#define LCDC_LCPR_OP_OFF (0x00000000)
+
+/* Bit definitions and macros for LCDC_LCWHBR */
+#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
+#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
+#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
+#define LCDC_LCWHBR_BK_EN (0x80000000)
+#define LCDC_LCWHBR_BK_EN_ON (0x80000000)
+#define LCDC_LCWHBR_BK_EN_OFF (0x00000000)
+
+/* Bit definitions and macros for LCDC_LCCMR */
+#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
+#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
+#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
+
+/* Bit definitions and macros for LCDC_LPCR */
+#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
+#define LCDC_LPCR_SHARP (0x00000040)
+#define LCDC_LPCR_SCLKSEL (0x00000080)
+#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
+#define LCDC_LPCR_ACDSEL (0x00008000)
+#define LCDC_LPCR_REV_VS (0x00010000)
+#define LCDC_LPCR_SWAP_SEL (0x00020000)
+#define LCDC_LPCR_ENDSEL (0x00040000)
+#define LCDC_LPCR_SCLKIDLE (0x00080000)
+#define LCDC_LPCR_OEPOL (0x00100000)
+#define LCDC_LPCR_CLKPOL (0x00200000)
+#define LCDC_LPCR_LPPOL (0x00400000)
+#define LCDC_LPCR_FLM (0x00800000)
+#define LCDC_LPCR_PIXPOL (0x01000000)
+#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
+#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
+#define LCDC_LPCR_COLOR (0x40000000)
+#define LCDC_LPCR_TFT (0x80000000)
+#define LCDC_LPCR_MODE_MONOCHROME (0x00000000)
+#define LCDC_LPCR_MODE_CSTN (0x40000000)
+#define LCDC_LPCR_MODE_TFT (0xC0000000)
+#define LCDC_LPCR_PBSIZ_1 (0x00000000)
+#define LCDC_LPCR_PBSIZ_2 (0x10000000)
+#define LCDC_LPCR_PBSIZ_4 (0x20000000)
+#define LCDC_LPCR_PBSIZ_8 (0x30000000)
+#define LCDC_LPCR_BPIX_1bpp (0x00000000)
+#define LCDC_LPCR_BPIX_2bpp (0x02000000)
+#define LCDC_LPCR_BPIX_4bpp (0x04000000)
+#define LCDC_LPCR_BPIX_8bpp (0x06000000)
+#define LCDC_LPCR_BPIX_12bpp (0x08000000)
+#define LCDC_LPCR_BPIX_16bpp (0x0A000000)
+#define LCDC_LPCR_BPIX_18bpp (0x0C000000)
+
+#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
+
+/* Bit definitions and macros for LCDC_LHCR */
+#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
+#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
+#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for LCDC_LVCR */
+#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
+#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
+#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for LCDC_LPOR */
+#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
+
+/* Bit definitions and macros for LCDC_LPCCR */
+#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
+#define LCDC_LPCCR_CC_EN (0x00000100)
+#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
+#define LCDC_LPCCR_LDMSK (0x00008000)
+#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
+#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
+#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
+#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
+
+/* Bit definitions and macros for LCDC_LDCR */
+#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
+#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
+#define LCDC_LDCR_BURST (0x80000000)
+
+/* Bit definitions and macros for LCDC_LRMCR */
+#define LCDC_LRMCR_SEL_REF (0x00000001)
+
+/* Bit definitions and macros for LCDC_LICR */
+#define LCDC_LICR_INTCON (0x00000001)
+#define LCDC_LICR_INTSYN (0x00000004)
+#define LCDC_LICR_GW_INT_CON (0x00000010)
+
+/* Bit definitions and macros for LCDC_LIER */
+#define LCDC_LIER_BOF_EN (0x00000001)
+#define LCDC_LIER_EOF_EN (0x00000002)
+#define LCDC_LIER_ERR_RES_EN (0x00000004)
+#define LCDC_LIER_UDR_ERR_EN (0x00000008)
+#define LCDC_LIER_GW_BOF_EN (0x00000010)
+#define LCDC_LIER_GW_EOF_EN (0x00000020)
+#define LCDC_LIER_GW_ERR_RES_EN (0x00000040)
+#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
+
+/* Bit definitions and macros for LCDC_LISR */
+#define LCDC_LISR_BOF (0x00000001)
+#define LCDC_LISR_EOF (0x00000002)
+#define LCDC_LISR_ERR_RES (0x00000004)
+#define LCDC_LISR_UDR_ERR (0x00000008)
+#define LCDC_LISR_GW_BOF (0x00000010)
+#define LCDC_LISR_GW_EOF (0x00000020)
+#define LCDC_LISR_GW_ERR_RES (0x00000040)
+#define LCDC_LISR_GW_UDR_ERR (0x00000080)
+
+/* Bit definitions and macros for LCDC_LGWSAR */
+#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LGWSR */
+#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
+#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
+
+/* Bit definitions and macros for LCDC_LGWVPWR */
+#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
+
+/* Bit definitions and macros for LCDC_LGWPOR */
+#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
+
+/* Bit definitions and macros for LCDC_LGWPR */
+#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
+#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
+
+/* Bit definitions and macros for LCDC_LGWCR */
+#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
+#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
+#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
+#define LCDC_LGWCR_GW_RVS (0x00200000)
+#define LCDC_LGWCR_GWE (0x00400000)
+#define LCDC_LGWCR_GWCKE (0x00800000)
+#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for LCDC_LGWDCR */
+#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
+#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
+#define LCDC_LGWDCR_GWBT (0x80000000)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_SDMR */
+#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
+#define SDRAMC_SDMR_BNKAD_LMR (0x00000000)
+#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
+#define SDRAMC_SDMR_CMD (0x00010000)
+
+/* Bit definitions and macros for SDRAMC_SDCR */
+#define SDRAMC_SDCR_MODE_EN (0x80000000)
+#define SDRAMC_SDCR_CKE (0x40000000)
+#define SDRAMC_SDCR_DDR (0x20000000)
+#define SDRAMC_SDCR_REF (0x10000000)
+#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
+#define SDRAMC_SDCR_OE_RULE (0x00400000)
+#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
+#define SDRAMC_SDCR_PS_32 (0x00000000)
+#define SDRAMC_SDCR_PS_16 (0x00002000)
+#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
+#define SDRAMC_SDCR_IREF (0x00000004)
+#define SDRAMC_SDCR_IPALL (0x00000002)
+
+/* Bit definitions and macros for SDRAMC_SDCFG1 */
+#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
+#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
+
+/* Bit definitions and macros for SDRAMC_SDCFG2 */
+#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
+#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+
+/* Bit definitions and macros for SDRAMC_SDDS */
+#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
+#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
+#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
+#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
+#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003)
+
+/* Bit definitions and macros for SDRAMC_SDCS */
+#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
+#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F)
+#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
+#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
+#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
+#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
+#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
+#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
+#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
+#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
+#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
+#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
+#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
+#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
+#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
+#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+/* Bit definitions and macros for SSI_CR */
+#define SSI_CR_CIS (0x00000200)
+#define SSI_CR_TCH (0x00000100)
+#define SSI_CR_MCE (0x00000080)
+#define SSI_CR_I2S_SLAVE (0x00000040)
+#define SSI_CR_I2S_MASTER (0x00000020)
+#define SSI_CR_I2S_NORMAL (0x00000000)
+#define SSI_CR_SYN (0x00000010)
+#define SSI_CR_NET (0x00000008)
+#define SSI_CR_RE (0x00000004)
+#define SSI_CR_TE (0x00000002)
+#define SSI_CR_SSI_EN (0x00000001)
+
+/* Bit definitions and macros for SSI_ISR */
+#define SSI_ISR_CMDAU (0x00040000)
+#define SSI_ISR_CMDDU (0x00020000)
+#define SSI_ISR_RXT (0x00010000)
+#define SSI_ISR_RDR1 (0x00008000)
+#define SSI_ISR_RDR0 (0x00004000)
+#define SSI_ISR_TDE1 (0x00002000)
+#define SSI_ISR_TDE0 (0x00001000)
+#define SSI_ISR_ROE1 (0x00000800)
+#define SSI_ISR_ROE0 (0x00000400)
+#define SSI_ISR_TUE1 (0x00000200)
+#define SSI_ISR_TUE0 (0x00000100)
+#define SSI_ISR_TFS (0x00000080)
+#define SSI_ISR_RFS (0x00000040)
+#define SSI_ISR_TLS (0x00000020)
+#define SSI_ISR_RLS (0x00000010)
+#define SSI_ISR_RFF1 (0x00000008)
+#define SSI_ISR_RFF0 (0x00000004)
+#define SSI_ISR_TFE1 (0x00000002)
+#define SSI_ISR_TFE0 (0x00000001)
+
+/* Bit definitions and macros for SSI_IER */
+#define SSI_IER_RDMAE (0x00400000)
+#define SSI_IER_RIE (0x00200000)
+#define SSI_IER_TDMAE (0x00100000)
+#define SSI_IER_TIE (0x00080000)
+#define SSI_IER_CMDAU (0x00040000)
+#define SSI_IER_CMDU (0x00020000)
+#define SSI_IER_RXT (0x00010000)
+#define SSI_IER_RDR1 (0x00008000)
+#define SSI_IER_RDR0 (0x00004000)
+#define SSI_IER_TDE1 (0x00002000)
+#define SSI_IER_TDE0 (0x00001000)
+#define SSI_IER_ROE1 (0x00000800)
+#define SSI_IER_ROE0 (0x00000400)
+#define SSI_IER_TUE1 (0x00000200)
+#define SSI_IER_TUE0 (0x00000100)
+#define SSI_IER_TFS (0x00000080)
+#define SSI_IER_RFS (0x00000040)
+#define SSI_IER_TLS (0x00000020)
+#define SSI_IER_RLS (0x00000010)
+#define SSI_IER_RFF1 (0x00000008)
+#define SSI_IER_RFF0 (0x00000004)
+#define SSI_IER_TFE1 (0x00000002)
+#define SSI_IER_TFE0 (0x00000001)
+
+/* Bit definitions and macros for SSI_TCR */
+#define SSI_TCR_TXBIT0 (0x00000200)
+#define SSI_TCR_TFEN1 (0x00000100)
+#define SSI_TCR_TFEN0 (0x00000080)
+#define SSI_TCR_TFDIR (0x00000040)
+#define SSI_TCR_TXDIR (0x00000020)
+#define SSI_TCR_TSHFD (0x00000010)
+#define SSI_TCR_TSCKP (0x00000008)
+#define SSI_TCR_TFSI (0x00000004)
+#define SSI_TCR_TFSL (0x00000002)
+#define SSI_TCR_TEFS (0x00000001)
+
+/* Bit definitions and macros for SSI_RCR */
+#define SSI_RCR_RXEXT (0x00000400)
+#define SSI_RCR_RXBIT0 (0x00000200)
+#define SSI_RCR_RFEN1 (0x00000100)
+#define SSI_RCR_RFEN0 (0x00000080)
+#define SSI_RCR_RSHFD (0x00000010)
+#define SSI_RCR_RSCKP (0x00000008)
+#define SSI_RCR_RFSI (0x00000004)
+#define SSI_RCR_RFSL (0x00000002)
+#define SSI_RCR_REFS (0x00000001)
+
+/* Bit definitions and macros for SSI_CCR */
+#define SSI_CCR_DIV2 (0x00040000)
+#define SSI_CCR_PSR (0x00020000)
+#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
+#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
+#define SSI_CCR_PM(x) ((x)&0x000000FF)
+
+/* Bit definitions and macros for SSI_FCSR */
+#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
+#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
+#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
+#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
+#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
+#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
+#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
+#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
+
+/* Bit definitions and macros for SSI_ACR */
+#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
+#define SSI_ACR_WR (0x00000010)
+#define SSI_ACR_RD (0x00000008)
+#define SSI_ACR_TIF (0x00000004)
+#define SSI_ACR_FV (0x00000002)
+#define SSI_ACR_AC97EN (0x00000001)
+
+/* Bit definitions and macros for SSI_ACADD */
+#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ACDAT */
+#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ATAG */
+#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+/* Bit definitions and macros for PLL_PODR */
+#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
+#define PLL_PODR_BUSDIV(x) ((x)&0x0F)
+
+/* Bit definitions and macros for PLL_PLLCR */
+#define PLL_PLLCR_DITHEN (0x80)
+#define PLL_PLLCR_DITHDEV(x) ((x)&0x07)
+
+#endif /* mcf5329_h */
--- /dev/null
+/*
+ * MCF5445x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5445X__
+#define __MCF5445X__
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
+#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
+#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
+#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
+#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
+#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
+#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
+#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
+#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
+#define XBS_CRS_RO (0x80000000) /* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD (0)
+#define XBS_CRS_PCTL_PARK_ON_LAST (1)
+#define XBS_CRS_PCTL_PARK_NONE (2)
+#define XBS_CRS_PCTL_PARK_CORE (0)
+#define XBS_CRS_PCTL_PARK_EDMA (1)
+#define XBS_CRS_PCTL_PARK_FEC0 (2)
+#define XBS_CRS_PCTL_PARK_FEC1 (3)
+#define XBS_CRS_PCTL_PARK_PCI (5)
+#define XBS_CRS_PCTL_PARK_USB (6)
+#define XBS_CRS_PCTL_PARK_SBF (7)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+
+/* Bit definitions and macros for CSAR group */
+#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSMR group */
+#define FBCS_CSMR_V (0x00000001) /* Valid bit */
+#define FBCS_CSMR_WP (0x00000100) /* Write protect */
+#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
+#define FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define FBCS_CSMR_BAM_128M (0x07FF0000)
+#define FBCS_CSMR_BAM_64M (0x03FF0000)
+#define FBCS_CSMR_BAM_32M (0x01FF0000)
+#define FBCS_CSMR_BAM_16M (0x00FF0000)
+#define FBCS_CSMR_BAM_8M (0x007F0000)
+#define FBCS_CSMR_BAM_4M (0x003F0000)
+#define FBCS_CSMR_BAM_2M (0x001F0000)
+#define FBCS_CSMR_BAM_1M (0x000F0000)
+#define FBCS_CSMR_BAM_1024K (0x000F0000)
+#define FBCS_CSMR_BAM_512K (0x00070000)
+#define FBCS_CSMR_BAM_256K (0x00030000)
+#define FBCS_CSMR_BAM_128K (0x00010000)
+#define FBCS_CSMR_BAM_64K (0x00000000)
+
+/* Bit definitions and macros for CSCR group */
+#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
+#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
+#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
+#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
+#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
+#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
+#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
+#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
+
+#define FBCS_CSCR_PS_8 (0x00000040)
+#define FBCS_CSCR_PS_16 (0x00000080)
+#define FBCS_CSCR_PS_32 (0x00000000)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_RSVD1 (29)
+#define INT0_LO_I2C (30)
+#define INT0_LO_QSPI (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_FEC0_TXF (36)
+#define INT0_HI_FEC0_TXB (37)
+#define INT0_HI_FEC0_UN (38)
+#define INT0_HI_FEC0_RL (39)
+#define INT0_HI_FEC0_RXF (40)
+#define INT0_HI_FEC0_RXB (41)
+#define INT0_HI_FEC0_MII (42)
+#define INT0_HI_FEC0_LC (43)
+#define INT0_HI_FEC0_HBERR (44)
+#define INT0_HI_FEC0_GRA (45)
+#define INT0_HI_FEC0_EBERR (46)
+#define INT0_HI_FEC0_BABT (47)
+#define INT0_HI_FEC0_BABR (48)
+#define INT0_HI_FEC1_TXF (49)
+#define INT0_HI_FEC1_TXB (50)
+#define INT0_HI_FEC1_UN (51)
+#define INT0_HI_FEC1_RL (52)
+#define INT0_HI_FEC1_RXF (53)
+#define INT0_HI_FEC1_RXB (54)
+#define INT0_HI_FEC1_MII (55)
+#define INT0_HI_FEC1_LC (56)
+#define INT0_HI_FEC1_HBERR (57)
+#define INT0_HI_FEC1_GRA (58)
+#define INT0_HI_FEC1_EBERR (59)
+#define INT0_HI_FEC1_BABT (60)
+#define INT0_HI_FEC1_BABR (61)
+#define INT0_HI_SCMIR (62)
+#define INT0_HI_RTC_ISR (63)
+
+#define INT1_HI_DSPI_EOQF (33)
+#define INT1_HI_DSPI_TFFF (34)
+#define INT1_HI_DSPI_TCF (35)
+#define INT1_HI_DSPI_TFUF (36)
+#define INT1_HI_DSPI_RFDF (37)
+#define INT1_HI_DSPI_RFOF (38)
+#define INT1_HI_DSPI_RFOF_TFUF (39)
+#define INT1_HI_RNG_EI (40)
+#define INT1_HI_PIT0_PIF (43)
+#define INT1_HI_PIT1_PIF (44)
+#define INT1_HI_PIT2_PIF (45)
+#define INT1_HI_PIT3_PIF (46)
+#define INT1_HI_USBOTG_USBSTS (47)
+#define INT1_HI_SSI_ISR (49)
+#define INT1_HI_CCM_UOCSR (53)
+#define INT1_HI_ATA_ISR (54)
+#define INT1_HI_PCI_SCR (55)
+#define INT1_HI_PCI_ASR (56)
+#define INT1_HI_PLL_LOCKS (57)
+
+/* Bit definitions and macros for IPRH */
+#define INTC_IPRH_INT32 (0x00000001)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT63 (0x80000000)
+
+/* Bit definitions and macros for IPRL */
+#define INTC_IPRL_INT0 (0x00000001)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT31 (0x80000000)
+
+/* Bit definitions and macros for IMRH */
+#define INTC_IMRH_INT_MASK32 (0x00000001)
+#define INTC_IMRH_INT_MASK33 (0x00000002)
+#define INTC_IMRH_INT_MASK34 (0x00000004)
+#define INTC_IMRH_INT_MASK35 (0x00000008)
+#define INTC_IMRH_INT_MASK36 (0x00000010)
+#define INTC_IMRH_INT_MASK37 (0x00000020)
+#define INTC_IMRH_INT_MASK38 (0x00000040)
+#define INTC_IMRH_INT_MASK39 (0x00000080)
+#define INTC_IMRH_INT_MASK40 (0x00000100)
+#define INTC_IMRH_INT_MASK41 (0x00000200)
+#define INTC_IMRH_INT_MASK42 (0x00000400)
+#define INTC_IMRH_INT_MASK43 (0x00000800)
+#define INTC_IMRH_INT_MASK44 (0x00001000)
+#define INTC_IMRH_INT_MASK45 (0x00002000)
+#define INTC_IMRH_INT_MASK46 (0x00004000)
+#define INTC_IMRH_INT_MASK47 (0x00008000)
+#define INTC_IMRH_INT_MASK48 (0x00010000)
+#define INTC_IMRH_INT_MASK49 (0x00020000)
+#define INTC_IMRH_INT_MASK50 (0x00040000)
+#define INTC_IMRH_INT_MASK51 (0x00080000)
+#define INTC_IMRH_INT_MASK52 (0x00100000)
+#define INTC_IMRH_INT_MASK53 (0x00200000)
+#define INTC_IMRH_INT_MASK54 (0x00400000)
+#define INTC_IMRH_INT_MASK55 (0x00800000)
+#define INTC_IMRH_INT_MASK56 (0x01000000)
+#define INTC_IMRH_INT_MASK57 (0x02000000)
+#define INTC_IMRH_INT_MASK58 (0x04000000)
+#define INTC_IMRH_INT_MASK59 (0x08000000)
+#define INTC_IMRH_INT_MASK60 (0x10000000)
+#define INTC_IMRH_INT_MASK61 (0x20000000)
+#define INTC_IMRH_INT_MASK62 (0x40000000)
+#define INTC_IMRH_INT_MASK63 (0x80000000)
+
+/* Bit definitions and macros for IMRL */
+#define INTC_IMRL_INT_MASK0 (0x00000001)
+#define INTC_IMRL_INT_MASK1 (0x00000002)
+#define INTC_IMRL_INT_MASK2 (0x00000004)
+#define INTC_IMRL_INT_MASK3 (0x00000008)
+#define INTC_IMRL_INT_MASK4 (0x00000010)
+#define INTC_IMRL_INT_MASK5 (0x00000020)
+#define INTC_IMRL_INT_MASK6 (0x00000040)
+#define INTC_IMRL_INT_MASK7 (0x00000080)
+#define INTC_IMRL_INT_MASK8 (0x00000100)
+#define INTC_IMRL_INT_MASK9 (0x00000200)
+#define INTC_IMRL_INT_MASK10 (0x00000400)
+#define INTC_IMRL_INT_MASK11 (0x00000800)
+#define INTC_IMRL_INT_MASK12 (0x00001000)
+#define INTC_IMRL_INT_MASK13 (0x00002000)
+#define INTC_IMRL_INT_MASK14 (0x00004000)
+#define INTC_IMRL_INT_MASK15 (0x00008000)
+#define INTC_IMRL_INT_MASK16 (0x00010000)
+#define INTC_IMRL_INT_MASK17 (0x00020000)
+#define INTC_IMRL_INT_MASK18 (0x00040000)
+#define INTC_IMRL_INT_MASK19 (0x00080000)
+#define INTC_IMRL_INT_MASK20 (0x00100000)
+#define INTC_IMRL_INT_MASK21 (0x00200000)
+#define INTC_IMRL_INT_MASK22 (0x00400000)
+#define INTC_IMRL_INT_MASK23 (0x00800000)
+#define INTC_IMRL_INT_MASK24 (0x01000000)
+#define INTC_IMRL_INT_MASK25 (0x02000000)
+#define INTC_IMRL_INT_MASK26 (0x04000000)
+#define INTC_IMRL_INT_MASK27 (0x08000000)
+#define INTC_IMRL_INT_MASK28 (0x10000000)
+#define INTC_IMRL_INT_MASK29 (0x20000000)
+#define INTC_IMRL_INT_MASK30 (0x40000000)
+#define INTC_IMRL_INT_MASK31 (0x80000000)
+
+/* Bit definitions and macros for INTFRCH */
+#define INTC_INTFRCH_INTFRC32 (0x00000001)
+#define INTC_INTFRCH_INTFRC33 (0x00000002)
+#define INTC_INTFRCH_INTFRC34 (0x00000004)
+#define INTC_INTFRCH_INTFRC35 (0x00000008)
+#define INTC_INTFRCH_INTFRC36 (0x00000010)
+#define INTC_INTFRCH_INTFRC37 (0x00000020)
+#define INTC_INTFRCH_INTFRC38 (0x00000040)
+#define INTC_INTFRCH_INTFRC39 (0x00000080)
+#define INTC_INTFRCH_INTFRC40 (0x00000100)
+#define INTC_INTFRCH_INTFRC41 (0x00000200)
+#define INTC_INTFRCH_INTFRC42 (0x00000400)
+#define INTC_INTFRCH_INTFRC43 (0x00000800)
+#define INTC_INTFRCH_INTFRC44 (0x00001000)
+#define INTC_INTFRCH_INTFRC45 (0x00002000)
+#define INTC_INTFRCH_INTFRC46 (0x00004000)
+#define INTC_INTFRCH_INTFRC47 (0x00008000)
+#define INTC_INTFRCH_INTFRC48 (0x00010000)
+#define INTC_INTFRCH_INTFRC49 (0x00020000)
+#define INTC_INTFRCH_INTFRC50 (0x00040000)
+#define INTC_INTFRCH_INTFRC51 (0x00080000)
+#define INTC_INTFRCH_INTFRC52 (0x00100000)
+#define INTC_INTFRCH_INTFRC53 (0x00200000)
+#define INTC_INTFRCH_INTFRC54 (0x00400000)
+#define INTC_INTFRCH_INTFRC55 (0x00800000)
+#define INTC_INTFRCH_INTFRC56 (0x01000000)
+#define INTC_INTFRCH_INTFRC57 (0x02000000)
+#define INTC_INTFRCH_INTFRC58 (0x04000000)
+#define INTC_INTFRCH_INTFRC59 (0x08000000)
+#define INTC_INTFRCH_INTFRC60 (0x10000000)
+#define INTC_INTFRCH_INTFRC61 (0x20000000)
+#define INTC_INTFRCH_INTFRC62 (0x40000000)
+#define INTC_INTFRCH_INTFRC63 (0x80000000)
+
+/* Bit definitions and macros for INTFRCL */
+#define INTC_INTFRCL_INTFRC0 (0x00000001)
+#define INTC_INTFRCL_INTFRC1 (0x00000002)
+#define INTC_INTFRCL_INTFRC2 (0x00000004)
+#define INTC_INTFRCL_INTFRC3 (0x00000008)
+#define INTC_INTFRCL_INTFRC4 (0x00000010)
+#define INTC_INTFRCL_INTFRC5 (0x00000020)
+#define INTC_INTFRCL_INTFRC6 (0x00000040)
+#define INTC_INTFRCL_INTFRC7 (0x00000080)
+#define INTC_INTFRCL_INTFRC8 (0x00000100)
+#define INTC_INTFRCL_INTFRC9 (0x00000200)
+#define INTC_INTFRCL_INTFRC10 (0x00000400)
+#define INTC_INTFRCL_INTFRC11 (0x00000800)
+#define INTC_INTFRCL_INTFRC12 (0x00001000)
+#define INTC_INTFRCL_INTFRC13 (0x00002000)
+#define INTC_INTFRCL_INTFRC14 (0x00004000)
+#define INTC_INTFRCL_INTFRC15 (0x00008000)
+#define INTC_INTFRCL_INTFRC16 (0x00010000)
+#define INTC_INTFRCL_INTFRC17 (0x00020000)
+#define INTC_INTFRCL_INTFRC18 (0x00040000)
+#define INTC_INTFRCL_INTFRC19 (0x00080000)
+#define INTC_INTFRCL_INTFRC20 (0x00100000)
+#define INTC_INTFRCL_INTFRC21 (0x00200000)
+#define INTC_INTFRCL_INTFRC22 (0x00400000)
+#define INTC_INTFRCL_INTFRC23 (0x00800000)
+#define INTC_INTFRCL_INTFRC24 (0x01000000)
+#define INTC_INTFRCL_INTFRC25 (0x02000000)
+#define INTC_INTFRCL_INTFRC26 (0x04000000)
+#define INTC_INTFRCL_INTFRC27 (0x08000000)
+#define INTC_INTFRCL_INTFRC28 (0x10000000)
+#define INTC_INTFRCL_INTFRC29 (0x20000000)
+#define INTC_INTFRCL_INTFRC30 (0x40000000)
+#define INTC_INTFRCL_INTFRC31 (0x80000000)
+
+/* Bit definitions and macros for ICONFIG */
+#define INTC_ICONFIG_EMASK (0x0020)
+#define INTC_ICONFIG_ELVLPRI1 (0x0200)
+#define INTC_ICONFIG_ELVLPRI2 (0x0400)
+#define INTC_ICONFIG_ELVLPRI3 (0x0800)
+#define INTC_ICONFIG_ELVLPRI4 (0x1000)
+#define INTC_ICONFIG_ELVLPRI5 (0x2000)
+#define INTC_ICONFIG_ELVLPRI6 (0x4000)
+#define INTC_ICONFIG_ELVLPRI7 (0x8000)
+
+/* Bit definitions and macros for SIMR */
+#define INTC_SIMR_SIMR(x) (((x)&0x7F))
+
+/* Bit definitions and macros for CIMR */
+#define INTC_CIMR_CIMR(x) (((x)&0x7F))
+
+/* Bit definitions and macros for CLMASK */
+#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
+
+/* Bit definitions and macros for SLMASK */
+#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
+
+/* Bit definitions and macros for ICR group */
+#define INTC_ICR_IL(x) (((x)&0x07))
+
+/*********************************************************************
+* DMA Serial Peripheral Interface (DSPI)
+*********************************************************************/
+
+/* Bit definitions and macros for DMCR */
+#define DSPI_DMCR_HALT (0x00000001)
+#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
+#define DSPI_DMCR_CRXF (0x00000400)
+#define DSPI_DMCR_CTXF (0x00000800)
+#define DSPI_DMCR_DRXF (0x00001000)
+#define DSPI_DMCR_DTXF (0x00002000)
+#define DSPI_DMCR_CSIS0 (0x00010000)
+#define DSPI_DMCR_CSIS2 (0x00040000)
+#define DSPI_DMCR_CSIS3 (0x00080000)
+#define DSPI_DMCR_CSIS5 (0x00200000)
+#define DSPI_DMCR_ROOE (0x01000000)
+#define DSPI_DMCR_PCSSE (0x02000000)
+#define DSPI_DMCR_MTFE (0x04000000)
+#define DSPI_DMCR_FRZ (0x08000000)
+#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
+#define DSPI_DMCR_CSCK (0x40000000)
+#define DSPI_DMCR_MSTR (0x80000000)
+
+/* Bit definitions and macros for DTCR */
+#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DCTAR group */
+#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
+#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
+#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
+#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
+#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
+#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
+#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
+#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
+#define DSPI_DCTAR_LSBFE (0x01000000)
+#define DSPI_DCTAR_CPHA (0x02000000)
+#define DSPI_DCTAR_CPOL (0x04000000)
+#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
+#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
+#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
+#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
+#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
+#define DSPI_DCTAR_PASC_1CLK (0x00000000)
+#define DSPI_DCTAR_PASC_3CLK (0x00100000)
+#define DSPI_DCTAR_PASC_5CLK (0x00200000)
+#define DSPI_DCTAR_PASC_7CLK (0x00300000)
+#define DSPI_DCTAR_PDT_1CLK (0x00000000)
+#define DSPI_DCTAR_PDT_3CLK (0x00040000)
+#define DSPI_DCTAR_PDT_5CLK (0x00080000)
+#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
+#define DSPI_DCTAR_PBR_1CLK (0x00000000)
+#define DSPI_DCTAR_PBR_3CLK (0x00010000)
+#define DSPI_DCTAR_PBR_5CLK (0x00020000)
+#define DSPI_DCTAR_PBR_7CLK (0x00030000)
+
+/* Bit definitions and macros for DSR */
+#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
+#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
+#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
+#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
+#define DSPI_DSR_RFDF (0x00020000)
+#define DSPI_DSR_RFOF (0x00080000)
+#define DSPI_DSR_TFFF (0x02000000)
+#define DSPI_DSR_TFUF (0x08000000)
+#define DSPI_DSR_EOQF (0x10000000)
+#define DSPI_DSR_TXRXS (0x40000000)
+#define DSPI_DSR_TCF (0x80000000)
+
+/* Bit definitions and macros for DIRSR */
+#define DSPI_DIRSR_RFDFS (0x00010000)
+#define DSPI_DIRSR_RFDFE (0x00020000)
+#define DSPI_DIRSR_RFOFE (0x00080000)
+#define DSPI_DIRSR_TFFFS (0x01000000)
+#define DSPI_DIRSR_TFFFE (0x02000000)
+#define DSPI_DIRSR_TFUFE (0x08000000)
+#define DSPI_DIRSR_EOQFE (0x10000000)
+#define DSPI_DIRSR_TCFE (0x80000000)
+
+/* Bit definitions and macros for DTFR */
+#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_DTFR_CS0 (0x00010000)
+#define DSPI_DTFR_CS2 (0x00040000)
+#define DSPI_DTFR_CS3 (0x00080000)
+#define DSPI_DTFR_CS5 (0x00200000)
+#define DSPI_DTFR_CTCNT (0x04000000)
+#define DSPI_DTFR_EOQ (0x08000000)
+#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
+#define DSPI_DTFR_CONT (0x80000000)
+
+/* Bit definitions and macros for DRFR */
+#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DTFDR group */
+#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DRFDR group */
+#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
+
+/*********************************************************************
+* Edge Port Module (EPORT)
+*********************************************************************/
+
+/* Bit definitions and macros for EPPAR */
+#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
+#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
+#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
+#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
+#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
+#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
+#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
+#define EPORT_EPPAR_LEVEL (0)
+#define EPORT_EPPAR_RISING (1)
+#define EPORT_EPPAR_FALLING (2)
+#define EPORT_EPPAR_BOTH (3)
+#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA7_RISING (0x4000)
+#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
+#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
+#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA6_RISING (0x1000)
+#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
+#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
+#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA5_RISING (0x0400)
+#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
+#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
+#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA4_RISING (0x0100)
+#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
+#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
+#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA3_RISING (0x0040)
+#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
+#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
+#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA2_RISING (0x0010)
+#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
+#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
+#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA1_RISING (0x0004)
+#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
+#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
+
+/* Bit definitions and macros for EPDDR */
+#define EPORT_EPDDR_EPDD1 (0x02)
+#define EPORT_EPDDR_EPDD2 (0x04)
+#define EPORT_EPDDR_EPDD3 (0x08)
+#define EPORT_EPDDR_EPDD4 (0x10)
+#define EPORT_EPDDR_EPDD5 (0x20)
+#define EPORT_EPDDR_EPDD6 (0x40)
+#define EPORT_EPDDR_EPDD7 (0x80)
+
+/* Bit definitions and macros for EPIER */
+#define EPORT_EPIER_EPIE1 (0x02)
+#define EPORT_EPIER_EPIE2 (0x04)
+#define EPORT_EPIER_EPIE3 (0x08)
+#define EPORT_EPIER_EPIE4 (0x10)
+#define EPORT_EPIER_EPIE5 (0x20)
+#define EPORT_EPIER_EPIE6 (0x40)
+#define EPORT_EPIER_EPIE7 (0x80)
+
+/* Bit definitions and macros for EPDR */
+#define EPORT_EPDR_EPD1 (0x02)
+#define EPORT_EPDR_EPD2 (0x04)
+#define EPORT_EPDR_EPD3 (0x08)
+#define EPORT_EPDR_EPD4 (0x10)
+#define EPORT_EPDR_EPD5 (0x20)
+#define EPORT_EPDR_EPD6 (0x40)
+#define EPORT_EPDR_EPD7 (0x80)
+
+/* Bit definitions and macros for EPPDR */
+#define EPORT_EPPDR_EPPD1 (0x02)
+#define EPORT_EPPDR_EPPD2 (0x04)
+#define EPORT_EPPDR_EPPD3 (0x08)
+#define EPORT_EPPDR_EPPD4 (0x10)
+#define EPORT_EPPDR_EPPD5 (0x20)
+#define EPORT_EPPDR_EPPD6 (0x40)
+#define EPORT_EPPDR_EPPD7 (0x80)
+
+/* Bit definitions and macros for EPFR */
+#define EPORT_EPFR_EPF1 (0x02)
+#define EPORT_EPFR_EPF2 (0x04)
+#define EPORT_EPFR_EPF3 (0x08)
+#define EPORT_EPFR_EPF4 (0x10)
+#define EPORT_EPFR_EPF5 (0x20)
+#define EPORT_EPFR_EPF6 (0x40)
+#define EPORT_EPFR_EPF7 (0x80)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+
+/* Bit definitions and macros for WCR */
+#define WTM_WCR_EN (0x0001)
+#define WTM_WCR_HALTED (0x0002)
+#define WTM_WCR_DOZE (0x0004)
+#define WTM_WCR_WAIT (0x0008)
+
+/*********************************************************************
+* Serial Boot Facility (SBF)
+*********************************************************************/
+
+/* Bit definitions and macros for SBFCR */
+#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
+#define SBF_SBFCR_FR (0x0010) /* Fast read */
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT (0x40)
+#define RCM_RCR_SOFTRST (0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL (0x01)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_SOFT (0x20)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+/* Bit definitions and macros for CCR_360 */
+#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
+#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
+#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
+#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
+#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
+#define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
+#define CCM_CCR_360_PLLMULT2_MASK (0x0003)
+#define CCM_CCR_360_PLLMULT3_MASK (0x0007)
+#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
+#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
+#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
+#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
+#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
+#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
+#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
+#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
+#define CCM_CCR_360_PLLMULT2_12X (0x0000)
+#define CCM_CCR_360_PLLMULT2_6X (0x0001)
+#define CCM_CCR_360_PLLMULT2_16X (0x0002)
+#define CCM_CCR_360_PLLMULT2_8X (0x0003)
+#define CCM_CCR_360_PLLMULT3_20X (0x0000)
+#define CCM_CCR_360_PLLMULT3_10X (0x0001)
+#define CCM_CCR_360_PLLMULT3_24X (0x0002)
+#define CCM_CCR_360_PLLMULT3_18X (0x0003)
+#define CCM_CCR_360_PLLMULT3_12X (0x0004)
+#define CCM_CCR_360_PLLMULT3_6X (0x0005)
+#define CCM_CCR_360_PLLMULT3_16X (0x0006)
+#define CCM_CCR_360_PLLMULT3_8X (0x0007)
+
+/* Bit definitions and macros for CCR_256 */
+#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
+#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
+#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+#define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
+#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
+#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
+#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
+#define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
+#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
+#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
+#define CCM_CCR_256_PLLMULT3_MASK (0x0007)
+#define CCM_CCR_256_PLLMULT3_20X (0x0000)
+#define CCM_CCR_256_PLLMULT3_10X (0x0001)
+#define CCM_CCR_256_PLLMULT3_24X (0x0002)
+#define CCM_CCR_256_PLLMULT3_18X (0x0003)
+#define CCM_CCR_256_PLLMULT3_12X (0x0004)
+#define CCM_CCR_256_PLLMULT3_6X (0x0005)
+#define CCM_CCR_256_PLLMULT3_16X (0x0006)
+#define CCM_CCR_256_PLLMULT3_8X (0x0007)
+
+/* Bit definitions and macros for RCON_360 */
+#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
+#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
+#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
+#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for RCON_256 */
+#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
+#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
+#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for CIR */
+#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
+#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
+#define CCM_CIR_PIN_MASK (0xFFC0)
+#define CCM_CIR_PRN_MASK (0x003F)
+#define CCM_CIR_PIN_MCF54450 (0x4F<<6)
+#define CCM_CIR_PIN_MCF54451 (0x4D<<6)
+#define CCM_CIR_PIN_MCF54452 (0x4B<<6)
+#define CCM_CIR_PIN_MCF54453 (0x49<<6)
+#define CCM_CIR_PIN_MCF54454 (0x4A<<6)
+#define CCM_CIR_PIN_MCF54455 (0x48<<6)
+
+/* Bit definitions and macros for MISCCR */
+#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
+#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
+#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
+#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
+#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
+#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
+#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
+#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
+#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
+#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
+#define CCM_MISCCR_BMT_65536 (0)
+#define CCM_MISCCR_BMT_32768 (1)
+#define CCM_MISCCR_BMT_16384 (2)
+#define CCM_MISCCR_BMT_8192 (3)
+#define CCM_MISCCR_BMT_4096 (4)
+#define CCM_MISCCR_BMT_2048 (5)
+#define CCM_MISCCR_BMT_1024 (6)
+#define CCM_MISCCR_BMT_512 (7)
+#define CCM_MISCCR_SSIPUS_UP (1)
+#define CCM_MISCCR_SSIPUS_DOWN (0)
+#define CCM_MISCCR_TIMDMA_TIM (1)
+#define CCM_MISCCR_TIMDMA_SSI (0)
+#define CCM_MISCCR_SSISRC_CLKIN (0)
+#define CCM_MISCCR_SSISRC_PLL (1)
+#define CCM_MISCCR_USBOC_ACTHI (0)
+#define CCM_MISCCR_USBOV_ACTLO (1)
+#define CCM_MISCCR_USBSRC_CLKIN (0)
+#define CCM_MISCCR_USBSRC_PLL (1)
+
+/* Bit definitions and macros for CDR */
+#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
+#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
+
+/* Bit definitions and macros for UOCSR */
+#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
+#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
+#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
+#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
+#define CCM_UOCSR_SEND (0x0010) /* Session end */
+#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
+#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
+#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
+#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
+#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
+#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
+#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
+#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+
+/* Bit definitions and macros for PAR_FEC */
+#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
+#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
+#define GPIO_PAR_FEC_FEC1_MASK (0x8F)
+#define GPIO_PAR_FEC_FEC1_MII (0x70)
+#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
+#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
+#define GPIO_PAR_FEC_FEC1_ATA (0x10)
+#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
+#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
+#define GPIO_PAR_FEC_FEC0_MII (0x07)
+#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
+#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02)
+#define GPIO_PAR_FEC_FEC0_ATA (0x01)
+#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_DMA */
+#define GPIO_PAR_DMA_DREQ0 (0x01)
+#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DMA_DACK1_MASK (0x3F)
+#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
+#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
+#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
+#define GPIO_PAR_DMA_DREQ1_MASK (0xCF)
+#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
+#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
+#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
+#define GPIO_PAR_DMA_DACK0_MASK (0xF3)
+#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
+#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
+#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
+#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
+#define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_FBCTL */
+#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
+#define GPIO_PAR_FBCTL_RW (0x20)
+#define GPIO_PAR_FBCTL_TA (0x40)
+#define GPIO_PAR_FBCTL_OE (0x80)
+#define GPIO_PAR_FBCTL_OE_OE (0x80)
+#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_TA_TA (0x40)
+#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
+#define GPIO_PAR_FBCTL_RW_RW (0x20)
+#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
+#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
+#define GPIO_PAR_FBCTL_TS_TS (0x18)
+#define GPIO_PAR_FBCTL_TS_ALE (0x10)
+#define GPIO_PAR_FBCTL_TS_TBST (0x08)
+#define GPIO_PAR_FBCTL_TS_GPIO (0x80)
+
+/* Bit definitions and macros for PAR_DSPI */
+#define GPIO_PAR_DSPI_SCK (0x01)
+#define GPIO_PAR_DSPI_SOUT (0x02)
+#define GPIO_PAR_DSPI_SIN (0x04)
+#define GPIO_PAR_DSPI_PCS0 (0x08)
+#define GPIO_PAR_DSPI_PCS1 (0x10)
+#define GPIO_PAR_DSPI_PCS2 (0x20)
+#define GPIO_PAR_DSPI_PCS5 (0x40)
+#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
+#define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
+#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
+#define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
+#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
+#define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
+#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
+#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
+#define GPIO_PAR_DSPI_SIN_SIN (0x04)
+#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
+#define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
+#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
+#define GPIO_PAR_DSPI_SCK_SCK (0x01)
+#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_BE */
+#define GPIO_PAR_BE_BS0 (0x01)
+#define GPIO_PAR_BE_BS1 (0x04)
+#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK (0x3F)
+#define GPIO_PAR_BE_BE3_BE3 (0xC0)
+#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
+#define GPIO_PAR_BE_BE3_GPIO (0x00)
+#define GPIO_PAR_BE_BE2_MASK (0xCF)
+#define GPIO_PAR_BE_BE2_BE2 (0x30)
+#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
+#define GPIO_PAR_BE_BE2_GPIO (0x00)
+#define GPIO_PAR_BE_BE1_BE1 (0x04)
+#define GPIO_PAR_BE_BE1_GPIO (0x00)
+#define GPIO_PAR_BE_BE0_BE0 (0x01)
+#define GPIO_PAR_BE_BE0_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_CS */
+#define GPIO_PAR_CS_CS1 (0x02)
+#define GPIO_PAR_CS_CS2 (0x04)
+#define GPIO_PAR_CS_CS3 (0x08)
+#define GPIO_PAR_CS_CS3_CS3 (0x08)
+#define GPIO_PAR_CS_CS3_GPIO (0x00)
+#define GPIO_PAR_CS_CS2_CS2 (0x04)
+#define GPIO_PAR_CS_CS2_GPIO (0x00)
+#define GPIO_PAR_CS_CS1_CS1 (0x02)
+#define GPIO_PAR_CS_CS1_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_TIMER */
+#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
+#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
+#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
+#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
+#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
+#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_USB */
+#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
+#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_USB_VBUSEN_MASK (0xF3)
+#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
+#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
+#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
+#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
+#define GPIO_PAR_USB_VBUSOC_MASK (0xFC)
+#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
+#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
+#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_UART */
+#define GPIO_PAR_UART_U0TXD (0x01)
+#define GPIO_PAR_UART_U0RXD (0x02)
+#define GPIO_PAR_UART_U0RTS (0x04)
+#define GPIO_PAR_UART_U0CTS (0x08)
+#define GPIO_PAR_UART_U1TXD (0x10)
+#define GPIO_PAR_UART_U1RXD (0x20)
+#define GPIO_PAR_UART_U1RTS (0x40)
+#define GPIO_PAR_UART_U1CTS (0x80)
+#define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
+#define GPIO_PAR_UART_U1CTS_GPIO (0x00)
+#define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
+#define GPIO_PAR_UART_U1RTS_GPIO (0x00)
+#define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
+#define GPIO_PAR_UART_U1RXD_GPIO (0x00)
+#define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
+#define GPIO_PAR_UART_U1TXD_GPIO (0x00)
+#define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
+#define GPIO_PAR_UART_U0CTS_GPIO (0x00)
+#define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
+#define GPIO_PAR_UART_U0RTS_GPIO (0x00)
+#define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
+#define GPIO_PAR_UART_U0RXD_GPIO (0x00)
+#define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
+#define GPIO_PAR_UART_U0TXD_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
+#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
+#define GPIO_PAR_FECI2C_MDIO0 (0x0010)
+#define GPIO_PAR_FECI2C_MDC0 (0x0040)
+#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
+#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
+#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
+#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
+#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
+#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
+#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
+#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
+#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
+#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
+#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
+#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
+#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
+#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
+#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
+
+/* Bit definitions and macros for PAR_SSI */
+#define GPIO_PAR_SSI_MCLK (0x0001)
+#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
+#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
+#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
+#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
+#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
+#define GPIO_PAR_SSI_FS_MASK (0xFF3F)
+#define GPIO_PAR_SSI_FS_FS (0x00C0)
+#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
+#define GPIO_PAR_SSI_FS_GPIO (0x0000)
+#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
+#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
+#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
+#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
+#define GPIO_PAR_SSI_STXD_MASK (0xFFF3)
+#define GPIO_PAR_SSI_STXD_STXD (0x000C)
+#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
+#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
+#define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
+#define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
+
+/* Bit definitions and macros for PAR_ATA */
+#define GPIO_PAR_ATA_IORDY (0x0001)
+#define GPIO_PAR_ATA_DMARQ (0x0002)
+#define GPIO_PAR_ATA_RESET (0x0004)
+#define GPIO_PAR_ATA_DA0 (0x0020)
+#define GPIO_PAR_ATA_DA1 (0x0040)
+#define GPIO_PAR_ATA_DA2 (0x0080)
+#define GPIO_PAR_ATA_CS0 (0x0100)
+#define GPIO_PAR_ATA_CS1 (0x0200)
+#define GPIO_PAR_ATA_BUFEN (0x0400)
+#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
+#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
+#define GPIO_PAR_ATA_CS1_CS1 (0x0200)
+#define GPIO_PAR_ATA_CS1_GPIO (0x0000)
+#define GPIO_PAR_ATA_CS0_CS0 (0x0100)
+#define GPIO_PAR_ATA_CS0_GPIO (0x0000)
+#define GPIO_PAR_ATA_DA2_DA2 (0x0080)
+#define GPIO_PAR_ATA_DA2_GPIO (0x0000)
+#define GPIO_PAR_ATA_DA1_DA1 (0x0040)
+#define GPIO_PAR_ATA_DA1_GPIO (0x0000)
+#define GPIO_PAR_ATA_DA0_DA0 (0x0020)
+#define GPIO_PAR_ATA_DA0_GPIO (0x0000)
+#define GPIO_PAR_ATA_RESET_RESET (0x0004)
+#define GPIO_PAR_ATA_RESET_GPIO (0x0000)
+#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
+#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
+#define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
+#define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
+
+/* Bit definitions and macros for PAR_IRQ */
+#define GPIO_PAR_IRQ_IRQ1 (0x02)
+#define GPIO_PAR_IRQ_IRQ4 (0x10)
+#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
+#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
+#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
+#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_PCI */
+#define GPIO_PAR_PCI_REQ0 (0x0001)
+#define GPIO_PAR_PCI_REQ1 (0x0004)
+#define GPIO_PAR_PCI_REQ2 (0x0010)
+#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_PCI_GNT0 (0x0100)
+#define GPIO_PAR_PCI_GNT1 (0x0400)
+#define GPIO_PAR_PCI_GNT2 (0x1000)
+#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
+#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
+#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
+#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
+#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
+#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
+#define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
+#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
+#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
+#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
+#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
+#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
+#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
+#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
+#define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
+#define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
+#define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
+
+/* Bit definitions and macros for MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
+#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
+#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
+#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
+#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
+#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
+#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
+#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
+#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
+#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
+#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
+#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
+#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
+#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
+#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
+#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
+#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
+#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
+#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
+#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
+#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
+
+/* Bit definitions and macros for MSCR_PCI */
+#define GPIO_MSCR_PCI_PCI (0x01)
+#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
+#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
+
+/* Bit definitions and macros for DSCR_I2C */
+#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
+#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
+#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
+#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
+#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_FLEXBUS */
+#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
+#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
+#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
+#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_FEC */
+#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
+#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
+#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
+#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
+#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
+#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
+#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
+#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
+#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
+#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_UART */
+#define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
+#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
+#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
+#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
+#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
+#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
+#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
+#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
+#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
+#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DSPI */
+#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
+#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_TIMER */
+#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
+#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_SSI */
+#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
+#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
+#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
+#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
+#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DMA */
+#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
+#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
+#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
+#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
+#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_RESET */
+#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
+#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
+#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
+#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
+#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_IRQ */
+#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
+#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_USB */
+#define GPIO_DSCR_USB_USB(x) (((x)&0x03))
+#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
+#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
+#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
+#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_ATA */
+#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
+#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
+#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
+#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
+#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
+
+/*********************************************************************
+* Random Number Generator (RNG)
+*********************************************************************/
+
+/* Bit definitions and macros for RNGCR */
+#define RNG_RNGCR_GO (0x00000001)
+#define RNG_RNGCR_HA (0x00000002)
+#define RNG_RNGCR_IM (0x00000004)
+#define RNG_RNGCR_CI (0x00000008)
+
+/* Bit definitions and macros for RNGSR */
+#define RNG_RNGSR_SV (0x00000001)
+#define RNG_RNGSR_LRS (0x00000002)
+#define RNG_RNGSR_FUF (0x00000004)
+#define RNG_RNGSR_EI (0x00000008)
+#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
+#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+/* Bit definitions and macros for SDMR */
+#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
+#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
+#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
+#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
+#define SDRAMC_SDMR_BK_LMR (0x00000000)
+#define SDRAMC_SDMR_BK_LEMR (0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
+#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
+#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
+#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
+#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
+#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
+#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
+#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
+#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
+#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
+#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
+#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
+#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
+#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
+
+/* Bit definitions and macros for SDCFG1 */
+#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
+#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
+#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
+#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
+#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
+#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
+#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
+
+/* Bit definitions and macros for SDCFG2 */
+#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
+#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
+#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
+#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
+
+/* Bit definitions and macros for SDCS group */
+#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
+#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
+#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
+#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
+#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
+#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
+#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
+#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
+#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
+#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
+#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
+#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
+#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
+#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
+#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
+#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
+#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+
+/* Bit definitions and macros for CR */
+#define SSI_CR_SSI_EN (0x00000001)
+#define SSI_CR_TE (0x00000002)
+#define SSI_CR_RE (0x00000004)
+#define SSI_CR_NET (0x00000008)
+#define SSI_CR_SYN (0x00000010)
+#define SSI_CR_I2S(x) (((x)&0x00000003)<<5)
+#define SSI_CR_MCE (0x00000080)
+#define SSI_CR_TCH (0x00000100)
+#define SSI_CR_CIS (0x00000200)
+#define SSI_CR_I2S_NORMAL (0x00000000)
+#define SSI_CR_I2S_MASTER (0x00000020)
+#define SSI_CR_I2S_SLAVE (0x00000040)
+
+/* Bit definitions and macros for ISR */
+#define SSI_ISR_TFE0 (0x00000001)
+#define SSI_ISR_TFE1 (0x00000002)
+#define SSI_ISR_RFF0 (0x00000004)
+#define SSI_ISR_RFF1 (0x00000008)
+#define SSI_ISR_RLS (0x00000010)
+#define SSI_ISR_TLS (0x00000020)
+#define SSI_ISR_RFS (0x00000040)
+#define SSI_ISR_TFS (0x00000080)
+#define SSI_ISR_TUE0 (0x00000100)
+#define SSI_ISR_TUE1 (0x00000200)
+#define SSI_ISR_ROE0 (0x00000400)
+#define SSI_ISR_ROE1 (0x00000800)
+#define SSI_ISR_TDE0 (0x00001000)
+#define SSI_ISR_TDE1 (0x00002000)
+#define SSI_ISR_RDR0 (0x00004000)
+#define SSI_ISR_RDR1 (0x00008000)
+#define SSI_ISR_RXT (0x00010000)
+#define SSI_ISR_CMDDU (0x00020000)
+#define SSI_ISR_CMDAU (0x00040000)
+
+/* Bit definitions and macros for IER */
+#define SSI_IER_TFE0 (0x00000001)
+#define SSI_IER_TFE1 (0x00000002)
+#define SSI_IER_RFF0 (0x00000004)
+#define SSI_IER_RFF1 (0x00000008)
+#define SSI_IER_RLS (0x00000010)
+#define SSI_IER_TLS (0x00000020)
+#define SSI_IER_RFS (0x00000040)
+#define SSI_IER_TFS (0x00000080)
+#define SSI_IER_TUE0 (0x00000100)
+#define SSI_IER_TUE1 (0x00000200)
+#define SSI_IER_ROE0 (0x00000400)
+#define SSI_IER_ROE1 (0x00000800)
+#define SSI_IER_TDE0 (0x00001000)
+#define SSI_IER_TDE1 (0x00002000)
+#define SSI_IER_RDR0 (0x00004000)
+#define SSI_IER_RDR1 (0x00008000)
+#define SSI_IER_RXT (0x00010000)
+#define SSI_IER_CMDU (0x00020000)
+#define SSI_IER_CMDAU (0x00040000)
+#define SSI_IER_TIE (0x00080000)
+#define SSI_IER_TDMAE (0x00100000)
+#define SSI_IER_RIE (0x00200000)
+#define SSI_IER_RDMAE (0x00400000)
+
+/* Bit definitions and macros for TCR */
+#define SSI_TCR_TEFS (0x00000001)
+#define SSI_TCR_TFSL (0x00000002)
+#define SSI_TCR_TFSI (0x00000004)
+#define SSI_TCR_TSCKP (0x00000008)
+#define SSI_TCR_TSHFD (0x00000010)
+#define SSI_TCR_TXDIR (0x00000020)
+#define SSI_TCR_TFDIR (0x00000040)
+#define SSI_TCR_TFEN0 (0x00000080)
+#define SSI_TCR_TFEN1 (0x00000100)
+#define SSI_TCR_TXBIT0 (0x00000200)
+
+/* Bit definitions and macros for RCR */
+#define SSI_RCR_REFS (0x00000001)
+#define SSI_RCR_RFSL (0x00000002)
+#define SSI_RCR_RFSI (0x00000004)
+#define SSI_RCR_RSCKP (0x00000008)
+#define SSI_RCR_RSHFD (0x00000010)
+#define SSI_RCR_RFEN0 (0x00000080)
+#define SSI_RCR_RFEN1 (0x00000100)
+#define SSI_RCR_RXBIT0 (0x00000200)
+#define SSI_RCR_RXEXT (0x00000400)
+
+/* Bit definitions and macros for CCR */
+#define SSI_CCR_PM(x) (((x)&0x000000FF))
+#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
+#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
+#define SSI_CCR_PSR (0x00020000)
+#define SSI_CCR_DIV2 (0x00040000)
+
+/* Bit definitions and macros for FCSR */
+#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
+#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
+#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
+#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
+#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
+#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
+#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
+#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for ACR */
+#define SSI_ACR_AC97EN (0x00000001)
+#define SSI_ACR_FV (0x00000002)
+#define SSI_ACR_TIF (0x00000004)
+#define SSI_ACR_RD (0x00000008)
+#define SSI_ACR_WR (0x00000010)
+#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
+
+/* Bit definitions and macros for ACADD */
+#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
+
+/* Bit definitions and macros for ACDAT */
+#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
+
+/* Bit definitions and macros for ATAG */
+#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+/* Bit definitions and macros for PCR */
+#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
+#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
+#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
+#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
+#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
+#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
+#define PLL_PCR_PFDR_MASK (0x000F0000)
+#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
+#define PLL_PCR_OUTDIV4_MASK (0x0000F000)
+#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
+#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
+#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
+
+/* Bit definitions and macros for PSR */
+#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
+#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
+#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
+#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
+
+/*********************************************************************
+* PCI
+*********************************************************************/
+
+/* Bit definitions and macros for SCR */
+#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
+#define PCI_SCR_SE (0x40000000) /* System error signalled */
+#define PCI_SCR_MA (0x20000000) /* Master aboart received */
+#define PCI_SCR_TR (0x10000000) /* Target abort received */
+#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
+#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
+#define PCI_SCR_DP (0x01000000) /* Master data parity err */
+#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
+#define PCI_SCR_R (0x00400000) /* Reserved */
+#define PCI_SCR_66M (0x00200000) /* 66Mhz */
+#define PCI_SCR_C (0x00100000) /* Capabilities list */
+#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
+#define PCI_SCR_S (0x00000100) /* SERR enable */
+#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
+#define PCI_SCR_PER (0x00000040) /* Parity error response */
+#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
+#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
+#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
+#define PCI_SCR_B (0x00000004) /* Bus master enable */
+#define PCI_SCR_M (0x00000002) /* Memory access control */
+#define PCI_SCR_IO (0x00000001) /* I/O access control */
+
+#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
+#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
+#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
+#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
+
+#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
+#define PCI_BAR_BAR1(x) (x & 0xFFF00000)
+#define PCI_BAR_BAR2(x) (x & 0xFFC00000)
+#define PCI_BAR_BAR3(x) (x & 0xFF000000)
+#define PCI_BAR_BAR4(x) (x & 0xF8000000)
+#define PCI_BAR_BAR5(x) (x & 0xE0000000)
+#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
+#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
+#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
+
+#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
+#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
+#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
+#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
+
+#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
+#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
+#define PCI_GSCR_SE (0x10000000) /* SERR detected */
+#define PCI_GSCR_ER (0x08000000) /* Error response detected */
+#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
+#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
+#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
+#define PCI_GSCR_PR (0x00000001) /* PCI reset */
+
+#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
+#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
+#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
+#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
+
+#define PCI_TCR1_B5E (0x00002000) /* */
+#define PCI_TCR1_B4E (0x00001000) /* */
+#define PCI_TCR1_B3E (0x00000800) /* */
+#define PCI_TCR1_B2E (0x00000400) /* */
+#define PCI_TCR1_B1E (0x00000200) /* */
+#define PCI_TCR1_B0E (0x00000100) /* */
+#define PCI_TCR1_CR (0x00000001) /* */
+
+#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
+#define PCI_TBATR_EN (0x00000001) /* Enable */
+
+#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
+#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
+#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
+#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
+#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
+#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
+#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
+#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
+#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
+
+#define PCI_ICR_REE (0x04000000) /* Retry error enable */
+#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
+#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
+
+#define PCI_IDR_DEVID (
+
+/********************************************************************/
+
+#endif /* __MCF5445X__ */
+++ /dev/null
-/*
- * mcftimer.h -- ColdFire internal TIMER support defines.
- *
- * Based on mcftimer.h of uCLinux distribution:
- * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
- * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************/
-#ifndef mcftimer_h
-#define mcftimer_h
-/****************************************************************************/
-
-#include <linux/config.h>
-
-/*
- * Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
-#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
-#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
-#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
-#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
-#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
-#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
-#endif
-
-/*
- * Define the TIMER register set addresses.
- */
-#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
-#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
-#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
-#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
-#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
-
-
-/*
- * Define the TIMER register set addresses for 5282.
- */
-#define MCFTIMER_PCSR 0
-#define MCFTIMER_PMR 1
-#define MCFTIMER_PCNTR 2
-
-/*
- * Bit definitions for the Timer Mode Register (TMR).
- * Register bit flags are common accross ColdFires.
- */
-#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
-#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
-#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
-#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
-#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
-#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
-#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
-#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
-#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
-#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
-#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
-#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
-#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
-#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
-#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
-#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
-#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
-
-/*
- * Bit definitions for the Timer Event Registers (TER).
- */
-#define MCFTIMER_TER_CAP 0x01 /* Capture event */
-#define MCFTIMER_TER_REF 0x02 /* Refernece event */
-
-/*
- * Bit definitions for the 5282 PIT Control and Status Register (PCSR).
- */
-#define MCFTIMER_PCSR_EN 0x0001
-#define MCFTIMER_PCSR_RLD 0x0002
-#define MCFTIMER_PCSR_PIF 0x0004
-#define MCFTIMER_PCSR_PIE 0x0008
-#define MCFTIMER_PCSR_OVW 0x0010
-#define MCFTIMER_PCSR_HALTED 0x0020
-#define MCFTIMER_PCSR_DOZE 0x0040
-
-
-/****************************************************************************/
-#endif /* mcftimer_h */
+++ /dev/null
-/*
- * mcfuart.h -- ColdFire internal UART support defines.
- *
- * File copied from mcfuart.h of uCLinux distribution:
- * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************/
-#ifndef mcfuart_h
-#define mcfuart_h
-/****************************************************************************/
-
-#include <linux/config.h>
-
-/*
- * Define the base address of the UARTS within the MBAR address
- * space.
- */
-#if defined(CONFIG_M5272)
-#define MCFUART_BASE1 0x100 /* Base address of UART1 */
-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
-#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#if defined(CONFIG_NETtel)
-#define MCFUART_BASE1 0x180 /* Base address of UART1 */
-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
-#else
-#define MCFUART_BASE1 0x140 /* Base address of UART1 */
-#define MCFUART_BASE2 0x180 /* Base address of UART2 */
-#endif
-#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x240 /* Base address of UART2 */
-#define MCFUART_BASE3 0x280 /* Base address of UART3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
-#else
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
-#endif
-#endif
-
-
-/*
- * Define the ColdFire UART register set addresses.
- */
-#define MCFUART_UMR 0x00 /* Mode register (r/w) */
-#define MCFUART_USR 0x04 /* Status register (r) */
-#define MCFUART_UCSR 0x04 /* Clock Select (w) */
-#define MCFUART_UCR 0x08 /* Command register (w) */
-#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
-#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
-#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
-#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
-#define MCFUART_UISR 0x14 /* Interrup Status (r) */
-#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
-#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
-#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
-#ifdef CONFIG_M5272
-#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
-#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
-#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
-#else
-#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
-#endif
-#define MCFUART_UIPR 0x34 /* Input Port (r) */
-#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
-#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
-
-#ifdef CONFIG_M5249
-/* Note: This isn't in the 5249 docs */
-#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
-#endif
-
-/*
- * Define bit flags in Mode Register 1 (MR1).
- */
-#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
-#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
-#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
-#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
-#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
-
-#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
-#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
-#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
-#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
-#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
-
-#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
-#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
-#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
-#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
-
-/*
- * Define bit flags in Mode Register 2 (MR2).
- */
-#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
-#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
-#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
-#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
-#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
-
-#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
-#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
-#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
-
-/*
- * Define bit flags in Status Register (USR).
- */
-#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
-#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
-#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
-#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
-#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
-#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
-#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
-#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
-
-#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
- MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
-
-/*
- * Define bit flags in Clock Select Register (UCSR).
- */
-#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
-#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
-#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
-
-#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
-#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
-#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
-
-/*
- * Define bit flags in Command Register (UCR).
- */
-#define MCFUART_UCR_CMDNULL 0x00 /* No command */
-#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
-#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
-#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
-#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
-#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
-#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
-#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
-
-#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
-#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
-#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
-#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
-#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
-#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
-
-/*
- * Define bit flags in Input Port Change Register (UIPCR).
- */
-#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
-#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
-
-/*
- * Define bit flags in Input Port Register (UIP).
- */
-#define MCFUART_UIPR_CTS 0x01 /* CTS value */
-
-/*
- * Define bit flags in Output Port Registers (UOP).
- * Clear bit by writing to UOP0, set by writing to UOP1.
- */
-#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
-
-/*
- * Define bit flags in the Auxiliary Control Register (UACR).
- */
-#define MCFUART_UACR_IEC 0x01 /* Input enable control */
-
-/*
- * Define bit flags in Interrupt Status Register (UISR).
- * These same bits are used for the Interrupt Mask Register (UIMR).
- */
-#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
-#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
-#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
-#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
-
-#ifdef CONFIG_M5272
-/*
- * Define bit flags in the Transmitter FIFO Register (UTF).
- */
-#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
-#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
-#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
-
-/*
- * Define bit flags in the Receiver FIFO Register (URF).
- */
-#define MCFUART_URF_RXB 0x1f /* receiver data level */
-#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
-#define MCFUART_URF_RXS 0xc0 /* receiver status */
-#endif
-
-/****************************************************************************/
-#endif /* mcfuart_h */
#ifndef __ASSEMBLY__
struct pt_regs {
- ulong d0;
- ulong d1;
- ulong d2;
- ulong d3;
- ulong d4;
- ulong d5;
- ulong d6;
- ulong d7;
- ulong a0;
- ulong a1;
- ulong a2;
- ulong a3;
- ulong a4;
- ulong a5;
- ulong a6;
-#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
- unsigned format : 4; /* frame format specifier */
- unsigned vector : 12; /* vector offset */
+ ulong d0;
+ ulong d1;
+ ulong d2;
+ ulong d3;
+ ulong d4;
+ ulong d5;
+ ulong d6;
+ ulong d7;
+ ulong a0;
+ ulong a1;
+ ulong a2;
+ ulong a3;
+ ulong a4;
+ ulong a5;
+ ulong a6;
+#if defined(__M68K__)
+ unsigned format:4; /* frame format specifier */
+ unsigned vector:12; /* vector offset */
unsigned short sr;
- unsigned long pc;
+ unsigned long pc;
#else
unsigned short sr;
- unsigned long pc;
+ unsigned long pc;
#endif
};
-#endif /* #ifndef __ASSEMBLY__ */
+#endif /* #ifndef __ASSEMBLY__ */
-#endif /* #ifndef _M68K_PTRACE_H */
+#endif /* #ifndef _M68K_PTRACE_H */
--- /dev/null
+/*
+ * RealTime Clock
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCFRTC_H__
+#define __MCFRTC_H__
+
+/* Real time Clock */
+typedef struct rtc_ctrl {
+ u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
+ u32 seconds; /* 0x04 Seconds Counter Register */
+ u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
+ u32 alrm_sec; /* 0x0C Seconds Alarm Register */
+ u32 cr; /* 0x10 Control Register */
+ u32 isr; /* 0x14 Interrupt Status Register */
+ u32 ier; /* 0x18 Interrupt Enable Register */
+ u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
+ u32 days; /* 0x20 Days Counter Register */
+ u32 alrm_day; /* 0x24 Days Alarm Register */
+ void *extended;
+} rtc_t;
+
+/* Bit definitions and macros for HOURMIN */
+#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F))
+#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for SECONDS */
+#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F))
+
+/* Bit definitions and macros for ALRM_HM */
+#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F))
+#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for ALRM_SEC */
+#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F))
+
+/* Bit definitions and macros for CR */
+#define RTC_CR_SWR (0x00000001)
+#define RTC_CR_XTL(x) (((x)&0x00000003)<<5)
+#define RTC_CR_EN (0x00000080)
+#define RTC_CR_32768 (0x0)
+#define RTC_CR_32000 (0x1)
+#define RTC_CR_38400 (0x2)
+
+/* Bit definitions and macros for ISR */
+#define RTC_ISR_SW (0x00000001)
+#define RTC_ISR_MIN (0x00000002)
+#define RTC_ISR_ALM (0x00000004)
+#define RTC_ISR_DAY (0x00000008)
+#define RTC_ISR_1HZ (0x00000010)
+#define RTC_ISR_HR (0x00000020)
+#define RTC_ISR_2HZ (0x00000080)
+#define RTC_ISR_SAM0 (0x00000100)
+#define RTC_ISR_SAM1 (0x00000200)
+#define RTC_ISR_SAM2 (0x00000400)
+#define RTC_ISR_SAM3 (0x00000800)
+#define RTC_ISR_SAM4 (0x00001000)
+#define RTC_ISR_SAM5 (0x00002000)
+#define RTC_ISR_SAM6 (0x00004000)
+#define RTC_ISR_SAM7 (0x00008000)
+
+/* Bit definitions and macros for IER */
+#define RTC_IER_SW (0x00000001)
+#define RTC_IER_MIN (0x00000002)
+#define RTC_IER_ALM (0x00000004)
+#define RTC_IER_DAY (0x00000008)
+#define RTC_IER_1HZ (0x00000010)
+#define RTC_IER_HR (0x00000020)
+#define RTC_IER_2HZ (0x00000080)
+#define RTC_IER_SAM0 (0x00000100)
+#define RTC_IER_SAM1 (0x00000200)
+#define RTC_IER_SAM2 (0x00000400)
+#define RTC_IER_SAM3 (0x00000800)
+#define RTC_IER_SAM4 (0x00001000)
+#define RTC_IER_SAM5 (0x00002000)
+#define RTC_IER_SAM6 (0x00004000)
+#define RTC_IER_SAM7 (0x00008000)
+
+/* Bit definitions and macros for STPWCH */
+#define RTC_STPWCH_CNT(x) (((x)&0x0000003F))
+
+/* Bit definitions and macros for DAYS */
+#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for ALRM_DAY */
+#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF))
+
+#endif /* __MCFRTC_H__ */
--- /dev/null
+/*
+ * timer.h -- ColdFire internal TIMER support defines.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef timer_h
+#define timer_h
+/****************************************************************************/
+
+/****************************************************************************/
+/* Timer structure */
+/****************************************************************************/
+/* DMA Timer module registers */
+typedef struct dtimer_ctrl {
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+ u16 tmr; /* 0x00 Mode register */
+ u16 res1; /* 0x02 */
+ u16 trr; /* 0x04 Reference register */
+ u16 res2; /* 0x06 */
+ u16 tcr; /* 0x08 Capture register */
+ u16 res3; /* 0x0A */
+ u16 tcn; /* 0x0C Counter register */
+ u16 res4; /* 0x0E */
+ u8 res6; /* 0x10 */
+ u8 ter; /* 0x11 Event register */
+ u16 res7; /* 0x12 */
+#else
+ u16 tmr; /* 0x00 Mode register */
+ u8 txmr; /* 0x02 Extended Mode register */
+ u8 ter; /* 0x03 Event register */
+ u32 trr; /* 0x04 Reference register */
+ u32 tcr; /* 0x08 Capture register */
+ u32 tcn; /* 0x0C Counter register */
+#endif
+} dtmr_t;
+
+/*Programmable Interrupt Timer */
+typedef struct pit_ctrl {
+ u16 pcsr; /* 0x00 Control and Status Register */
+ u16 pmr; /* 0x02 Modulus Register */
+ u16 pcntr; /* 0x04 Count Register */
+} pit_t;
+
+/*********************************************************************
+* DMA Timers (DTIM)
+*********************************************************************/
+/* Bit definitions and macros for DTMR */
+#define DTIM_DTMR_RST (0x0001) /* Reset */
+#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
+#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
+#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
+#define DTIM_DTMR_OM (0x0020) /* Output Mode */
+#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
+#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
+#define DTIM_DTMR_RST_EN (0x0001)
+#define DTIM_DTMR_RST_RST (0x0000)
+#define DTIM_DTMR_CE_ANY (0x00C0)
+#define DTIM_DTMR_CE_FALL (0x0080)
+#define DTIM_DTMR_CE_RISE (0x0040)
+#define DTIM_DTMR_CE_NONE (0x0000)
+#define DTIM_DTMR_CLK_DTIN (0x0006)
+#define DTIM_DTMR_CLK_DIV16 (0x0004)
+#define DTIM_DTMR_CLK_DIV1 (0x0002)
+#define DTIM_DTMR_CLK_STOP (0x0000)
+
+/* Bit definitions and macros for DTXMR */
+#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
+#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
+
+/* Bit definitions and macros for DTER */
+#define DTIM_DTER_CAP (0x01) /* Capture event */
+#define DTIM_DTER_REF (0x02) /* Output reference event */
+
+/*********************************************************************
+*
+* Programmable Interrupt Timer Modules (PIT)
+*
+*********************************************************************/
+
+/* Bit definitions and macros for PCSR */
+#define PIT_PCSR_EN (0x0001)
+#define PIT_PCSR_RLD (0x0002)
+#define PIT_PCSR_PIF (0x0004)
+#define PIT_PCSR_PIE (0x0008)
+#define PIT_PCSR_OVW (0x0010)
+#define PIT_PCSR_HALTED (0x0020)
+#define PIT_PCSR_DOZE (0x0040)
+#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
+
+/* Bit definitions and macros for PMR */
+#define PIT_PMR_PM(x) (x)
+
+/* Bit definitions and macros for PCNTR */
+#define PIT_PCNTR_PC(x) (x)
+
+/****************************************************************************/
+#endif /* timer_h */
#ifndef __ASSEMBLY__
typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- unsigned long bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_mbar_base; /* base of internal registers */
- unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* Ethernet adress */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+ unsigned long bi_sramstart; /* start of SRAM memory */
+ unsigned long bi_sramsize; /* size of SRAM memory */
+ unsigned long bi_mbar_base; /* base of internal registers */
+ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
+ unsigned long bi_boot_params; /* where this board expects params */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
+ unsigned long bi_intfreq; /* Internal Freq, in MHz */
+ unsigned long bi_busfreq; /* Bus Freq, in MHz */
+#ifdef CONFIG_PCI
+ unsigned long bi_pcifreq; /* pci Freq in MHz */
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
+ unsigned long bi_baudrate; /* Console Baudrate */
+
+#ifdef CONFIG_HAS_ETH1
+ /* second onboard ethernet port */
+ unsigned char bi_enet1addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH2
+ /* third onboard ethernet port */
+ unsigned char bi_enet2addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH3
+ unsigned char bi_enet3addr[6];
+#endif
} bd_t;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLY__ */
-#endif /* __U_BOOT_H__ */
+#endif /* __U_BOOT_H__ */
--- /dev/null
+/*
+ * uart.h -- ColdFire internal UART support defines.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef uart_h
+#define uart_h
+/****************************************************************************/
+
+/* UART module registers */
+/* Register read/write struct */
+typedef struct uart {
+ u8 umr; /* 0x00 Mode Register */
+ u8 resv0[0x3];
+ union {
+ u8 usr; /* 0x04 Status Register */
+ u8 ucsr; /* 0x04 Clock Select Register */
+ };
+ u8 resv1[0x3];
+ u8 ucr; /* 0x08 Command Register */
+ u8 resv2[0x3];
+ union {
+ u8 utb; /* 0x0c Transmit Buffer */
+ u8 urb; /* 0x0c Receive Buffer */
+ };
+ u8 resv3[0x3];
+ union {
+ u8 uipcr; /* 0x10 Input Port Change Register */
+ u8 uacr; /* 0x10 Auxiliary Control reg */
+ };
+ u8 resv4[0x3];
+ union {
+ u8 uimr; /* 0x14 Interrupt Mask reg */
+ u8 uisr; /* 0x14 Interrupt Status reg */
+ };
+ u8 resv5[0x3];
+ u8 ubg1; /* 0x18 Counter Timer Upper Register */
+ u8 resv6[0x3];
+ u8 ubg2; /* 0x1c Counter Timer Lower Register */
+ u8 resv7[0x17];
+ u8 uip; /* 0x34 Input Port Register */
+ u8 resv8[0x3];
+ u8 uop1; /* 0x38 Output Port Set Register */
+ u8 resv9[0x3];
+ u8 uop0; /* 0x3c Output Port Reset Register */
+} uart_t;
+
+/*********************************************************************
+* Universal Asynchronous Receiver Transmitter (UART)
+*********************************************************************/
+/* Bit definitions and macros for UMR */
+#define UART_UMR_BC(x) (((x)&0x03))
+#define UART_UMR_PT (0x04)
+#define UART_UMR_PM(x) (((x)&0x03)<<3)
+#define UART_UMR_ERR (0x20)
+#define UART_UMR_RXIRQ (0x40)
+#define UART_UMR_RXRTS (0x80)
+#define UART_UMR_SB(x) (((x)&0x0F))
+#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
+#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
+#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
+#define UART_UMR_PM_MULTI_ADDR (0x1C)
+#define UART_UMR_PM_MULTI_DATA (0x18)
+#define UART_UMR_PM_NONE (0x10)
+#define UART_UMR_PM_FORCE_HI (0x0C)
+#define UART_UMR_PM_FORCE_LO (0x08)
+#define UART_UMR_PM_ODD (0x04)
+#define UART_UMR_PM_EVEN (0x00)
+#define UART_UMR_BC_5 (0x00)
+#define UART_UMR_BC_6 (0x01)
+#define UART_UMR_BC_7 (0x02)
+#define UART_UMR_BC_8 (0x03)
+#define UART_UMR_CM_NORMAL (0x00)
+#define UART_UMR_CM_ECH (0x40)
+#define UART_UMR_CM_LOCAL_LOOP (0x80)
+#define UART_UMR_CM_REMOTE_LOOP (0xC0)
+#define UART_UMR_SB_STOP_BITS_1 (0x07)
+#define UART_UMR_SB_STOP_BITS_15 (0x08)
+#define UART_UMR_SB_STOP_BITS_2 (0x0F)
+
+/* Bit definitions and macros for USR */
+#define UART_USR_RXRDY (0x01)
+#define UART_USR_FFULL (0x02)
+#define UART_USR_TXRDY (0x04)
+#define UART_USR_TXEMP (0x08)
+#define UART_USR_OE (0x10)
+#define UART_USR_PE (0x20)
+#define UART_USR_FE (0x40)
+#define UART_USR_RB (0x80)
+
+/* Bit definitions and macros for UCSR */
+#define UART_UCSR_TCS(x) (((x)&0x0F))
+#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
+#define UART_UCSR_RCS_SYS_CLK (0xD0)
+#define UART_UCSR_RCS_CTM16 (0xE0)
+#define UART_UCSR_RCS_CTM (0xF0)
+#define UART_UCSR_TCS_SYS_CLK (0x0D)
+#define UART_UCSR_TCS_CTM16 (0x0E)
+#define UART_UCSR_TCS_CTM (0x0F)
+
+/* Bit definitions and macros for UCR */
+#define UART_UCR_RXC(x) (((x)&0x03))
+#define UART_UCR_TXC(x) (((x)&0x03)<<2)
+#define UART_UCR_MISC(x) (((x)&0x07)<<4)
+#define UART_UCR_NONE (0x00)
+#define UART_UCR_STOP_BREAK (0x70)
+#define UART_UCR_START_BREAK (0x60)
+#define UART_UCR_BKCHGINT (0x50)
+#define UART_UCR_RESET_ERROR (0x40)
+#define UART_UCR_RESET_TX (0x30)
+#define UART_UCR_RESET_RX (0x20)
+#define UART_UCR_RESET_MR (0x10)
+#define UART_UCR_TX_DISABLED (0x08)
+#define UART_UCR_TX_ENABLED (0x04)
+#define UART_UCR_RX_DISABLED (0x02)
+#define UART_UCR_RX_ENABLED (0x01)
+
+/* Bit definitions and macros for UIPCR */
+#define UART_UIPCR_CTS (0x01)
+#define UART_UIPCR_COS (0x10)
+
+/* Bit definitions and macros for UACR */
+#define UART_UACR_IEC (0x01)
+
+/* Bit definitions and macros for UIMR */
+#define UART_UIMR_TXRDY (0x01)
+#define UART_UIMR_RXRDY_FU (0x02)
+#define UART_UIMR_DB (0x04)
+#define UART_UIMR_COS (0x80)
+
+/* Bit definitions and macros for UISR */
+#define UART_UISR_TXRDY (0x01)
+#define UART_UISR_RXRDY_FU (0x02)
+#define UART_UISR_DB (0x04)
+#define UART_UISR_RXFTO (0x08)
+#define UART_UISR_TXFIFO (0x10)
+#define UART_UISR_RXFIFO (0x20)
+#define UART_UISR_COS (0x80)
+
+/* Bit definitions and macros for UIP */
+#define UART_UIP_CTS (0x01)
+
+/* Bit definitions and macros for UOP1 */
+#define UART_UOP1_RTS (0x01)
+
+/* Bit definitions and macros for UOP0 */
+#define UART_UOP0_RTS (0x01)
+
+/****************************************************************************/
+#endif /* mcfuart_h */
-/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
*/
-#ifndef __ASM_MIPS_STRING_H
-#define __ASM_MIPS_STRING_H
-
-#include <linux/config.h>
-
-#define __HAVE_ARCH_STRCPY
-extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
-{
- char *__xdest = __dest;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "addiu\t%1,1\n\t"
- "sb\t$1,(%0)\n\t"
- "bnez\t$1,1b\n\t"
- "addiu\t%0,1\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__dest), "=r" (__src)
- : "0" (__dest), "1" (__src)
- : "$1","memory");
-
- return __xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
-{
- char *__xdest = __dest;
-
- if (__n == 0)
- return __xdest;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "subu\t%2,1\n\t"
- "sb\t$1,(%0)\n\t"
- "beqz\t$1,2f\n\t"
- "addiu\t%0,1\n\t"
- "bnez\t%2,1b\n\t"
- "addiu\t%1,1\n"
- "2:\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__dest), "=r" (__src), "=r" (__n)
- : "0" (__dest), "1" (__src), "2" (__n)
- : "$1","memory");
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
- return __dest;
-}
-
-#define __HAVE_ARCH_STRCMP
-extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
-{
- int __res;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "lbu\t%2,(%0)\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "addiu\t%0,1\n\t"
- "bne\t$1,%2,2f\n\t"
- "addiu\t%1,1\n\t"
- "bnez\t%2,1b\n\t"
- "lbu\t%2,(%0)\n\t"
-#if defined(CONFIG_CPU_R3000)
- "nop\n\t"
-#endif
- "move\t%2,$1\n"
- "2:\tsubu\t%2,$1\n"
- "3:\t.set\tat\n\t"
- ".set\treorder"
- : "=r" (__cs), "=r" (__ct), "=r" (__res)
- : "0" (__cs), "1" (__ct)
- : "$1");
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
- return __res;
-}
+#undef __HAVE_ARCH_STRCPY
+extern char *strcpy(char *__dest, __const__ char *__src);
-#define __HAVE_ARCH_STRNCMP
-extern __inline__ int
-strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
-{
- int __res;
+#undef __HAVE_ARCH_STRNCPY
+extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t%3,(%0)\n\t"
- "beqz\t%2,2f\n\t"
- "lbu\t$1,(%1)\n\t"
- "subu\t%2,1\n\t"
- "bne\t$1,%3,3f\n\t"
- "addiu\t%0,1\n\t"
- "bnez\t%3,1b\n\t"
- "addiu\t%1,1\n"
- "2:\n\t"
-#if defined(CONFIG_CPU_R3000)
- "nop\n\t"
-#endif
- "move\t%3,$1\n"
- "3:\tsubu\t%3,$1\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
- : "0" (__cs), "1" (__ct), "2" (__count)
- : "$1");
+#undef __HAVE_ARCH_STRCMP
+extern int strcmp(__const__ char *__cs, __const__ char *__ct);
- return __res;
-}
+#undef __HAVE_ARCH_STRNCMP
+extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-/* Don't build bcopy at all ... */
-#define __HAVE_ARCH_BCOPY
-
-#define __HAVE_ARCH_MEMSCAN
-extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
-{
- char *__end = (char *)__addr + __size;
-
- __asm__(".set\tpush\n\t"
- ".set\tnoat\n\t"
- ".set\treorder\n\t"
- "1:\tbeq\t%0,%1,2f\n\t"
- "addiu\t%0,1\n\t"
- "lb\t$1,-1(%0)\n\t"
- "bne\t$1,%4,1b\n"
- "2:\t.set\tpop"
- : "=r" (__addr), "=r" (__end)
- : "0" (__addr), "1" (__end), "r" (__c)
- : "$1");
-
- return __addr;
-}
-
-#endif /* __ASM_MIPS_STRING_H */
+#endif /* _ASM_STRING_H */
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
+#if defined(CONFIG_MPC8360)
+ u32 ddr_sec_clk;
+#endif /* CONFIG_MPC8360 */
+#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
-#if defined (CONFIG_MPC8360)
- u32 ddr_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
unsigned long do_mdm_init;
unsigned long be_quiet;
#endif
-#ifdef CONFIG_LWMON
+#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
void **jt; /* jump table */
/*
* MPC85xx Internal Memory Map
*
+ * Copyright 2007 Freescale Semiconductor.
+ *
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
char res58[60176];
} ccsr_rio_t;
+/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
+typedef struct par_io {
+ uint cpodr; /* 0x100 */
+ uint cpdat; /* 0x104 */
+ uint cpdir1; /* 0x108 */
+ uint cpdir2; /* 0x10c */
+ uint cppar1; /* 0x110 */
+ uint cppar2; /* 0x114 */
+ char res[8];
+}par_io_t;
+
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
+#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
+#define MPC85xx_DEVDISR_PCI1 0x80000000
+#define MPC85xx_DEVDISR_PCI2 0x40000000
+#define MPC85xx_DEVDISR_PCIE 0x20000000
+#define MPC85xx_DEVDISR_LBC 0x08000000
+#define MPC85xx_DEVDISR_PCIE2 0x04000000
+#define MPC85xx_DEVDISR_PCIE3 0x02000000
+#define MPC85xx_DEVDISR_SEC 0x01000000
+#define MPC85xx_DEVDISR_SRIO 0x00080000
+#define MPC85xx_DEVDISR_RMSG 0x00040000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_DMA 0x00000400
+#define MPC85xx_DEVDISR_TSEC1 0x00000080
+#define MPC85xx_DEVDISR_TSEC2 0x00000040
+#define MPC85xx_DEVDISR_TSEC3 0x00000020
+#define MPC85xx_DEVDISR_TSEC4 0x00000010
+#define MPC85xx_DEVDISR_I2C 0x00000004
+#define MPC85xx_DEVDISR_DUART 0x00000002
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
+#ifdef CONFIG_MPC8568
+ char res10b[76];
+ par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
+ char res10c[3136];
+#else
char res10b[3404];
+#endif
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
uint res14; /* 0xe0f28 */
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
- char res15[61651];
+ char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA 0x00060000
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
-#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
+#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
-#define MPC86xx_DEVDISR_PCIEX1 0x80000000
-#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCI1 0x80000000
+#define MPC86xx_DEVDISR_PCIE1 0x40000000
+#define MPC86xx_DEVDISR_PCIE2 0x20000000
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
- char res10[3416];
+ char res10a[1880];
+ uint clkdvdr; /* 0xe0800 - Clock Divide register */
+ char res10b[1532];
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
+typedef struct ucc_mii_mng {
+ u32 miimcfg; /* MII management configuration reg */
+ u32 miimcom; /* MII management command reg */
+ u32 miimadd; /* MII management address reg */
+ u32 miimcon; /* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind; /* MII management indication reg */
+ u32 ifctl; /* interface control reg */
+ u32 ifstat; /* interface statux reg */
+} __attribute__ ((packed))uec_mii_t;
+
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
+#if defined(CONFIG_MPC8568)
+ u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
+ u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
+#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
+#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC8568)
+#define QE_MURAM_SIZE 0x10000UL
+#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void remove_tlb(u32 vaddr, u32 size);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */
#define HID0_DPM (1<<20)
#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
+#define HID0_TBEN (1<<14) /* Time Base Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI
#define HID0_SPD (1<<9) /* Speculative disable */
+#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
#define HID0_SGE (1<<7) /* Store Gathering Enable */
#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
+#define SPRN_MCAR 0x23d /* Machine Check Address register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCRO 0x3f6
+#define SPRN_MSSCR0 0x3f6
+#define SPRN_MSSSR0 0x3f7
#endif
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCRO
+#define MSSCR0 SPRN_MSSCR0
#endif
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR
--- /dev/null
+
+#ifndef _AT45_H_
+#define _AT45_H_
+#ifdef DATAFLASH_MMC_SELECT
+extern void AT91F_SelectMMC(void);
+extern void AT91F_SelectSPI(void);
+extern int AT91F_GetMuxStatus(void);
+#endif
+extern void AT91F_SpiInit(void);
+extern void AT91F_SpiEnable(int cs);
+extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
+extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress);
+extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
+ AT91PS_DataflashDesc pDesc);
+extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
+ AT91PS_DataflashDesc pDataFlashDesc,
+ unsigned int timeout);
+extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead );
+extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite);
+extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int page);
+extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite );
+extern AT91S_DataFlashStatus AT91F_PageErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page);
+extern AT91S_DataFlashStatus AT91F_BlockErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block);
+extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest );
+extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size);
+extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest,
+ int size );
+extern int AT91F_DataFlashRead(
+ AT91PS_DataFlash pDataFlash,
+ unsigned long addr,
+ unsigned long size,
+ char *buffer);
+extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
+
+#endif
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
- void pcie_setup_hoses(void);
+ void pcie_setup_hoses(int busno);
#endif
#endif
void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void);
void reset_cpu (ulong addr);
+#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+void ft_cpu_setup(void *blob, bd_t *bd);
+#ifdef CONFIG_PCI
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+#endif
+
/* $(CPU)/serial.c */
int serial_init (void);
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_VFD /* VFD support (TRAB) */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */
#endif /* _CONFIG_CMD_ALL_H */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
#define CONFIG_CMD_EEPROM
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
#define CONFIG_SUPPORT_VFAT
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_SUPPORT_VFAT
-#define CFG_NAND_LEGACY
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_MISC_INIT_R
-#define FEC_ENET
-#define CONFIG_ETHADDR 00:CF:52:82:EB:01
-
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#include <config_cmd_default.h>
#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:CF:52:82:EB:01
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "\nEV123 U-Boot> "
*/
#define CFG_MBAR 0x40000000
-#define CFG_DISCOVER_PHY
-/* #define CFG_ENET_BD_BASE 0x380000 */
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_INT_FLASH_BASE 0xF0000000
+#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 19200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
+
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
-#define CFG_NAND_LEGACY
-
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif /* CONFIG_MPC5200 */
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
--- /dev/null
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5235EVB_H
+#define _M5235EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF523x /* define processor family */
+#define CONFIG_M5235 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE "u-boot.bin"
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_KGDB)
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
+
+#define CFG_HZ 1000
+#define CFG_CLK 75000000
+#define CFG_CPU_CLK CFG_CLK * 2
+
+#define CFG_MBAR 0x40000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x21
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+#ifdef NORFLASH_PS32BIT
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#else
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#endif
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+#ifdef NORFLASH_PS32BIT
+# define CFG_ENV_OFFSET (0x8000)
+# define CFG_ENV_SIZE 0x4000
+# define CFG_ENV_SECT_SIZE 0x4000
+#else
+# define CFG_ENV_OFFSET (0x4000)
+# define CFG_ENV_SIZE 0x2000
+# define CFG_ENV_SECT_SIZE 0x2000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ * CS6 - Available
+ * CS7 - Available
+ */
+#ifdef NORFLASH_PS32BIT
+# define CFG_CS0_BASE 0xFFC0
+# define CFG_CS0_MASK 0x003f0001
+# define CFG_CS0_CTRL 0x1D00
+#else
+# define CFG_CS0_BASE 0xFFE0
+# define CFG_CS0_MASK 0x001f0001
+# define CFG_CS0_CTRL 0x1D80
+#endif
+
+#endif /* _M5329EVB_H */
--- /dev/null
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5249EVB_H
+#define _M5249EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5249 /* define processor type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+
+#define CFG_PROMPT "=> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CFG_LOAD_ADDR 0x200000 /* default load address */
+
+#define CFG_MEMTEST_START 0x400
+#define CFG_MEMTEST_END 0x380000
+
+#define CFG_HZ 1000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */
+#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_MBAR2 0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_FLASH_BASE (CFG_CSAR0 << 16)
+
+#if 0 /* test-only */
+#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+
+#define CFG_MONITOR_LEN 0x20000
+#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
+#define CFG_BOOTPARAMS_LEN 64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CFG_CSAR0 0xffe0
+#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define CFG_CSAR1 0xe000
+#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
+#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_GPIO1_LED 0x00400000 /* user led */
+
+#endif /* M5249 */
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253EVBE_H
+#define _M5253EVBE_H
+
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5253 /* define processor type */
+#define CONFIG_M5253EVBE /* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG /* disable watchdog */
+
+#define CONFIG_BOOTDELAY 5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#else
+#define CFG_ENV_ADDR 0xffe04000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#endif
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+/* ATA */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_IDE_RESET 1
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 2
+
+#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800)
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+#define _IO_BASE 0
+
+#define CFG_PROMPT "=> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_MEMTEST_START 0x400
+#define CFG_MEMTEST_END 0x380000
+
+#define CFG_HZ 1000
+
+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+# define CFG_PLLCR 0x1243E054
+# define CFG_CLK 140000000
+#else
+# define CFG_PLLCR 0x135a4140
+# define CFG_CLK 70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE 0x20000
+#else
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN 0x40000
+#define CFG_MALLOC_LEN (256 << 10)
+#define CFG_BOOTPARAMS_LEN (64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE 0xffe00000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 1000
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_SIZE 0x200000
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE 16
+
+/* Port configuration */
+#define CFG_FECI2C 0xF0
+
+#define CFG_CSAR0 0xFFE0
+#define CFG_CSMR0 0x001F0021
+#define CFG_CSCR0 0x1D80
+
+#define CFG_CSAR1 0
+#define CFG_CSMR1 0
+#define CFG_CSCR1 0
+
+#define CFG_CSAR2 0
+#define CFG_CSMR2 0
+#define CFG_CSCR2 0
+
+#define CFG_CSAR3 0
+#define CFG_CSMR3 0
+#define CFG_CSCR3 0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_GPIO1_LED 0x00400000 /* user led */
+
+#endif /* _M5253EVB_H */
#ifndef _M5271EVB_H
#define _M5271EVB_H
-#define DEBUG
#undef DEBUG
/*
#define CONFIG_M5271 /* define processor type */
#define CONFIG_M5271EVB /* define board type */
-#define CONFIG_IPADDR 192.168.30.1
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
-#define CONFIG_BOOTDELAY 5
-
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
-#define CFG_ENV_SECT_SIZE 0x2000
-#define CFG_ENV_IS_IN_FLASH 1
#else
#define CFG_ENV_ADDR 0xffe04000
+#endif
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
-#endif
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*
* BOOTP options
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PING
#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE "u-boot.bin"
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_RETRY_COUNT 5
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe2ffff;" \
+ "era ffe00000 ffe2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
#define CFG_PROMPT "=> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
-/* Enable FEC ethernet */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-#define CFG_ENET_BD_BASE 0x480000
-
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
/* Port configuration */
#define CFG_FECI2C 0xF0
-#endif /* _M5271EVB_H */
+#endif /* _M5271EVB_H */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5272 /* define processor type */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5272 /* define processor type */
-#define FEC_ENET
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_WATCHDOG
+#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
-#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
#define CFG_ENV_IS_IN_FLASH 1
#endif
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
-
#define CONFIG_BOOTDELAY 5
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
-
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
-
#define CFG_HZ 1000
#define CFG_CLK 66000000
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
-
#define CFG_SCR 0x0003;
#define CFG_SPR 0xffff;
-#define CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE 0x380000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
/*-----------------------------------------------------------------------
*/
#define CFG_BR0_PRELIM 0xFFE00201
#define CFG_OR0_PRELIM 0xFFE00014
-
#define CFG_BR1_PRELIM 0
#define CFG_OR1_PRELIM 0
-
#define CFG_BR2_PRELIM 0x30000001
#define CFG_OR2_PRELIM 0xFFF80000
-
#define CFG_BR3_PRELIM 0
#define CFG_OR3_PRELIM 0
-
#define CFG_BR4_PRELIM 0
#define CFG_OR4_PRELIM 0
-
#define CFG_BR5_PRELIM 0
#define CFG_OR5_PRELIM 0
-
#define CFG_BR6_PRELIM 0
#define CFG_OR6_PRELIM 0
-
#define CFG_BR7_PRELIM 0x00000701
#define CFG_OR7_PRELIM 0xFFC0007C
#define CFG_PACNT 0x00000000
#define CFG_PADDR 0x0000
#define CFG_PADAT 0x0000
-#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
+#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_PBDDR 0x0000
#define CFG_PBDAT 0x0000
#define CFG_PDCNT 0x00000000
-
-#endif /* _M5272C3_H */
+#endif /* _M5272C3_H */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5282 /* define processor type */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5282 /* define processor type */
-#define FEC_ENET
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
#define CONFIG_BOOTDELAY 5
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
#define CFG_HZ 1000000
#define CFG_CLK 64000000
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
*/
#define CFG_MBAR 0x40000000
-#undef CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE 0x380000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
+#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
-/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */
-#define CFG_MONITOR_BASE 0x20000
+#if (TEXT_BASE != CFG_INT_FLASH_BASE)
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#else
+#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_SECT 35
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_FLASH_ERASE_TOUT 10000000
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
-
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-
-
+#define CFG_CS0_BASE CFG_FLASH_BASE
+#define CFG_CS0_SIZE 2*1024*1024
+#define CFG_CS0_WIDTH 16
+#define CFG_CS0_RO 0
+#define CFG_CS0_WS 6
+/*
+#define CFG_CS3_BASE 0xE0000000
+#define CFG_CS3_SIZE 1*1024*1024
+#define CFG_CS3_WIDTH 16
+#define CFG_CS3_RO 0
+#define CFG_CS3_WS 6
+*/
/*-----------------------------------------------------------------------
* Port configuration
*/
+#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_PADDR 0x0000000
+#define CFG_PADAT 0x0000000
+
+#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_PBDDR 0x0000000
+#define CFG_PBDAT 0x0000000
+
+#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
+#define CFG_PCDDR 0x0000000
+#define CFG_PCDAT 0x0000000
+
+#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_PCDDR 0x0000000
+#define CFG_PCDAT 0x0000000
+#define CFG_PEHLPAR 0xC0
+#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CFG_DDRUA 0x05
+#define CFG_PJPAR 0xFF;
-#endif /* _CONFIG_M5282EVB_H */
+#endif /* _CONFIG_M5282EVB_H */
--- /dev/null
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5329EVB_H
+#define _M5329EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x /* define processor family */
+#define CONFIG_M5329 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef NANDFLASH_SIZE
+# define CONFIG_CMD_NAND
+#endif
+
+#define CFG_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5329EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x40010000
+
+#define CFG_HZ 1000
+#define CFG_CLK 80000000
+#define CFG_CPU_CLK CFG_CLK * 3
+
+#define CFG_MBAR 0xFC000000
+
+#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x53722730
+#define CFG_SDRAM_CFG2 0x56670000
+#define CFG_SDRAM_CTRL 0xE1092000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x018D0000
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef NANDFLASH_SIZE
+# define CFG_MAX_NAND_DEVICE 1
+# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
+# define CFG_NAND_SIZE 1
+# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+# define NAND_MAX_CHIPS 1
+# define NAND_ALLOW_ERASE_ALL 1
+# define CONFIG_JFFS2_NAND 1
+# define CONFIG_JFFS2_DEV "nand0"
+# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
+# define CONFIG_JFFS2_PART_OFFSET 0x00000000
+#endif
+
+#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x007f0001
+#define CFG_CS0_CTRL 0x00001fa0
+
+#define CFG_CS1_BASE 0x1000
+#define CFG_CS1_MASK 0x001f0001
+#define CFG_CS1_CTRL 0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE 0x2000
+#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
+#define CFG_CS2_CTRL 0x00001f60
+#endif
+
+#endif /* _M5329EVB_H */
--- /dev/null
+/*
+ * Configuation settings for the Freescale MCF54455 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _JAMICA54455_H
+#define _JAMICA54455_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5445x /* define processor family */
+#define CONFIG_M54455 /* define processor type */
+#define CONFIG_M54455EVB /* M54455EVB board */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_CF_DOMII
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC1_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+# define CONFIG_HAS_ETH1
+
+# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_ETHPRIME "FEC0"
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME M54455EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+/* ATA configuration */
+#define CONFIG_ISO_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_IDE_RESET 1
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 2
+
+#define CFG_ATA_BASE_ADDR 0x90000000
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+#define _IO_BASE 0
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+/* PCI */
+#define CONFIG_PCI 1
+
+#define CFG_PCI_MEM_BUS 0xA0000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#define CFG_PCI_IO_BUS 0xB1000000
+#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE 0x01000000
+
+#define CFG_PCI_CFG_BUS 0xB0000000
+#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE 0x01000000
+
+/* FPGA - Spartan 2 */
+/* experiment
+#define CONFIG_FPGA CFG_SPARTAN3
+#define CONFIG_FPGA_COUNT 1
+#define CFG_FPGA_PROG_FEEDBACK
+#define CFG_FPGA_CHECK_CTRLC
+*/
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM 512 /* 512 KB */
+
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
+
+#define CFG_HZ 1000
+
+#define CFG_MBAR 0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_BASE1 0x48000000
+#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x65311610
+#define CFG_SDRAM_CFG2 0x59670000
+#define CFG_SDRAM_CTRL 0xEA0B2000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x00010033
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OVERWRITE 1
+#undef CFG_ENV_IS_EMBEDDED
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CFG_ATMEL_BOOT
+# define CFG_FLASH_BASE 0
+# define CFG_FLASH0_BASE CFG_CS0_BASE
+# define CFG_FLASH1_BASE CFG_CS1_BASE
+#else
+# define CFG_FLASH_BASE CFG_FLASH0_BASE
+# define CFG_FLASH0_BASE CFG_CS1_BASE
+# define CFG_FLASH1_BASE CFG_CS0_BASE
+#endif
+
+/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
+/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
+ keep reset. */
+#undef CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
+
+#else
+
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+# define CFG_ATMEL_REGION 4
+# define CFG_ATMEL_TOTALSECT 11
+# define CFG_ATMEL_SECT {1, 2, 1, 7}
+# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
+# define CFG_INTEL_SECT 137
+
+/* max number of sectors on one chip */
+# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
+# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
+# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CFG_ATMEL_BOOT
+# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_PART_SIZE 0x01000000
+# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
+#else
+# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
+# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - CPLD
+ * CS3 - FPGA
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#ifdef CFG_ATMEL_BOOT
+ /* Atmel Flash */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x00070001
+#define CFG_CS0_CTRL 0x00001140
+/* Intel Flash */
+#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_MASK 0x01FF0001
+#define CFG_CS1_CTRL 0x003F3D60
+
+#define CFG_ATMEL_BASE CFG_CS0_BASE
+#else
+/* Intel Flash */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x01FF0001
+#define CFG_CS0_CTRL 0x003F3D60
+ /* Atmel Flash */
+#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_MASK 0x00070001
+#define CFG_CS1_CTRL 0x00001140
+
+#define CFG_ATMEL_BASE CFG_CS1_BASE
+#endif
+
+/* CPLD */
+#define CFG_CS2_BASE 0x08000000
+#define CFG_CS2_MASK 0x00070001
+#define CFG_CS2_CTRL 0x003f1140
+
+/* FPGA */
+#define CFG_CS3_BASE 0x09000000
+#define CFG_CS3_MASK 0x00070001
+#define CFG_CS3_CTRL 0x00000020
+
+#endif /* _JAMICA54455_H */
/* 0x03200064 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32 )
#else
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#endif
#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8313@0"
#define OF_SOC "soc8313@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0x1c
#define TSEC2_PHY_ADDR 4
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
#define CFG_SICRL 0x00000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8323@0"
#define OF_SOC "soc8323@e0000000"
#define OF_QE "qe@e0100000"
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:04:9f:ef:23:33
#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
#endif
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
+#define TSEC2_FLAGS TSEC_GIGABIT
#endif
#define CONFIG_ETHPRIME "Freescale TSEC"
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
#define CFG_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
/*
* CS4 on Local Bus, to PIB
*/
-#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
+#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
-#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
+#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
#define CONFIG_OF_HAS_BD_T 1
#define CONFIG_OF_HAS_UBOOT_ENV 1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8360@0"
#define OF_SOC "soc8360@e0000000"
#define OF_QE "qe@e0100000"
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8540@0"
#define OF_SOC "soc8540@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
#endif
/* Options are: TSEC[0-1], FEC */
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
+#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
+#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_HAS_ETH2
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define FEC_FLAGS 0
+
/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8541@0"
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
-#undef CONFIG_PCI /* Enable PCI/PCIE */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
-#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
-#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* When initializing flash, if we cannot find the manufacturer ID,
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8544@0"
#define OF_SOC "soc8544@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe1000000
-#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE2_IO_BASE 0x00000000
-#define CFG_PCIE2_IO_PHYS 0xe2000000
-#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE2_IO_PHYS 0xe1010000
+#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
-#define CFG_PCIE1_MEM_BASE2 0xa8000000
-#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
-#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
-#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
-#define CFG_PCIE1_IO_PHYS 0xaf000000
-#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe1020000
+#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE 0xb0000000
#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
#define CFG_PCIE3_IO_BASE 0x00000000
-#define CFG_PCIE3_IO_PHYS 0xe3000000
+#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE3_MEM_BASE2 0xb0200000
+#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
+#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
-#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
-#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
#endif /* CONFIG_TSEC_ENET */
/*
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_CMD_PCI
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
+ #define CONFIG_CMD_SCSI
+ #define CONFIG_CMD_EXT2
#endif
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
+#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
#define CONFIG_HOSTNAME 8544ds_unknown
#define CONFIG_ROOTPATH /nfs/mpc85xx
-#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
+#define CONFIG_BOOTFILE 8544ds/uImage.uboot
+#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcie3regs=setenv a e000b; run pciereg\0" \
- "pcieerr=md ${a}020 1; md ${a}e00;" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1err=setenv a e000a; run pcieerr\0" \
- "pcie2err=setenv a e0009; run pcieerr\0" \
- "pcie3err=setenv a e000b; run pcieerr\0" \
- "pcie1errc=setenv a e000a; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; run pcieerrc\0" \
- "pcie3errc=setenv a e000b; run pcieerrc\0"
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie2regs=setenv a e0009; run pciereg\0" \
+ "pcie3regs=setenv a e000b; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie2cfg=setenv b 5; run pciecfg\0" \
+ "pcie3cfg=setenv b 0; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
+ "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
+ "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
+ "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
+ "echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
- "pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; run pcierr\0" \
- "pci1errc=setenv a e0008; run pcierrc\0"
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
+ "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
#define ENET_ENV ""
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
- "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
+ "ramdiskfile=8544ds/ramdisk.uboot\0" \
+ "dtbaddr=c00000\0" \
+ "dtbfile=8544ds/mpc8544ds.dtb\0" \
+ "bdev=sda3\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- PCIE_ENV \
- PCI_ENV \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
ENET_ENV
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/sda3 rw " \
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
#endif /* __CONFIG_H */
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI /* enable any pci type devices */
+#define CONFIG_PCI1 /* PCI controller 1 */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#undef CONFIG_RIO
+#undef CONFIG_PCI2
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
/*
* DDR Setup
*/
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
*
* OR0, OR1:
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
* TRLX = use relaxed timing = ORx[29] = 1
* EAD = use external address latch delay = OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
+#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff801001
#define CFG_BR1_PRELIM 0xff001001
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
/*
* SDRAM on the Local Bus
*/
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+#define CFG_LBC_CACHE_SIZE 64
+#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
+#define CFG_LBC_NONCACHE_SIZE 64
+
+#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
-#define CFG_BR2_PRELIM 0xf0001861
+#define CFG_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
+ * 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
+ * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
* port-size = 8-bits = BR[19:20] = 01
* no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
+ * GPMC for MSEL = BR[24:26] = 000
+ * Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
*
* For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
+ * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
+ * CSNT OR[20] = 1
+ * ACS OR[21:22] = 11
+ * XACS OR[23] = 1
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
+ * SETA OR[28] = 0
+ * TRLX OR[29] = 1
+ * EHTR OR[30] = 1
+ * EAD extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM 0xf8000801
-#define CFG_OR3_PRELIM 0xfff00ff7
+#define CFG_BR3_PRELIM 0xf8000801
+#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
+#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
-#define CFG_BAUDRATE_TABLE \
+#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8548@0"
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CFG_PCI2_MEM_BASE 0x90000000
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2800000
-#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
-#define CFG_PEX_MEM_BASE 0xa0000000
-#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PEX_IO_BASE 0x00000000
-#define CFG_PEX_IO_PHYS 0xe3000000
-#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xC0000000
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_85XX_PCI2
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
-#undef CONFIG_TSEC4
+#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
-
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
-#define CONFIG_IPADDR 192.168.1.253
+#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH /nfsroot
-#define CONFIG_BOOTFILE your.uImage
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE 8548cds/uImage.uboot
+#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
-#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0"
+#if defined(CONFIG_PCIE1)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
+ "pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
+ "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
+#else
+#define PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+ "echo e;md ${a}e00 9\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
+#else
+#define PCI_ENV ""
+#endif
+#if defined(CONFIG_PCI1)
+#define PCI_ENV1 \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
+#else
+#define PCI_ENV1 ""
+#endif
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
+#if defined(CONFIG_PCI2)
+#define PCI_ENV2 \
+ "pci2regs=setenv a e0009; run pcireg\0" \
+ "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
+ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
+#else
+#define PCI_ENV2 ""
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+ "md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+ "echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet2regs=setenv a e0025; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0" \
+ "enet4regs=setenv a e0027; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS1\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=mpc8548cds.dtb\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ PCI_ENV1 \
+ PCI_ENV2 \
+ ENET_ENV
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8555@0"
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8560@0"
#define OF_SOC "soc8560@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-#undef CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
+#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR 0x52
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
/*
* General PCI
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME "FSL UEC0"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS 0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
+#define CFG_UEC1_RX_CLK QE_CLK_NONE
+#define CFG_UEC1_TX_CLK QE_CLK16
+#define CFG_UEC1_ETH_TYPE GIGA_ETH
+#define CFG_UEC1_PHY_ADDR 7
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2 /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
+#define CFG_UEC2_RX_CLK QE_CLK_NONE
+#define CFG_UEC2_TX_CLK QE_CLK16
+#define CFG_UEC2_ETH_TYPE GIGA_ETH
+#define CFG_UEC2_PHY_ADDR 1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+#endif /* CONFIG_QE */
+
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
+#if defined(CONFIG_TSEC_ENET)
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
-#undef CONFIG_TSEC3
-#undef CONFIG_TSEC4
-#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-/* Options are: eTSEC[0-3] */
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */
*/
/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
+#define CONFIG_HAS_ETH0 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
#undef CONFIG_WATCHDOG /* watchdog disabled */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
-#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 242 /* NVRAM size */
-
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#if 1 /* test-only */
+
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#endif /* CONFIG_TSEC_ENET */
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:40:42:01:00:00
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:40:42:01:00:01
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#endif /* ENVIRONMENT_IN_EEPROM */
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
* Open firmware flat tree support
*-----------------------------------------------------------------------
*/
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
*/
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
+ "bootfile="CFG_BOOTFILE_PATH"\0" \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91C_USE_RMII
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 2
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START \
- ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+ ({ gd->bd->bi_dram[0].start; })
#define CFG_MEMTEST_END \
({ \
- DECLARE_GLOBAL_DATA_PTR; \
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
})
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
+#define CONFIG_PROG_SDRAM_TLB
+#undef CFG_DRAM_TEST
/*-----------------------------------------------------------------------
* I2C
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_CM5200 1 /* ... on CM5200 platform */
-
/*
* Supported commands
*/
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
-
/*
* Ethernet configuration
*/
#define CONFIG_MISC_INIT_R 1
#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
-
/*
* POST support
*/
/* List of I2C addresses to be verified by POST */
#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
-
/* display image timestamps */
#define CONFIG_TIMESTAMP 1
-
/*
* Autobooting
*/
""
#define CONFIG_BOOTCOMMAND "run flash_flash"
-
/*
* Low level configuration
*/
-
/*
* Clock configuration
*/
#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
-
/*
* Memory map
*/
*/
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#define CFG_FLASH_BASE 0xfc000000
+#define CFG_FLASH_BASE 0xfc000000
/* we need these despite using CFI */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x00000001
-
/*
* SDRAM configuration
* settings for k4s561632E-xx75, assuming XLB = 132 MHz
#define SDRAM_CONFIG1 0xE2333900
#define SDRAM_CONFIG2 0x8EE70000
-
-
/*
* MTD configuration
*/
"2m(kernel),27904k(rootfs)," \
"-(config)"
-
/*
* I2C configuration
*/
#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */
-
/*
* RTC configuration
*/
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
-
/*
* USB configuration
*/
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
-
/*
* Pin multiplexing configuration
*/
*/
#define CFG_GPS_PORT_CONFIG 0x10559C44
-
/*
* Miscellaneous configurable options
*/
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Various low-level settings
*/
#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */
-
/*
* Cache Configuration
*/
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
/*
* Flat Device Tree support
*/
*/
#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
+
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_REGINFO
#define CFG_ENV_IS_IN_FLASH 1
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
-#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif
/*-----------------------------------------------------------------------
* Enable use of Ethernet
* ---
*/
+#define CONFIG_MCFFEC
-#define FEC_ENET
+/* Enable Dma Timer */
+#define CONFIG_MCFTMR
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
* ---
*/
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_MII
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/*
*-----------------------------------------------------------------------------
--- /dev/null
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU4 1 /* Board is HCU4 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */
+#define CONFIG_405GP 1
+#define CONFIG_4xx 1
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+*----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/* ... with on-chip memory here (4KBytes) */
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
+/* Do not set up locked dcache as init ram. */
+#undef CFG_INIT_DCACHE_CS
+
+/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CFG_TEMP_STACK_OCM 1
+
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE 9600
+
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM configuration */
+#define PROM_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the first internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 0
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu4
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/home/diagnose/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/hcu4/uImage\0" \
+ "load=tftp 100000 hcu4/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu4_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/* SPD EEPROM (sdram speed config) disabled */
+#define CONFIG_SPD_EEPROM 1
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB1AP 0x03041200
+#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB2AP 0x02054500
+#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB3AP 0x01840300
+#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB4AP 0x01800300
+#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU5 1 /* Board is HCU5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xfff00000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CONFIG_BAUDRATE 9600
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO, but
+ CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM and bootstrap configuration */
+#define PROM_SIZE 2048
+#define CFG_BOOSTRAP_OPTION_OFFSET 512
+#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
+#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the second internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 1
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu5
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "bootfile=hcu5/uImage\0" \
+ "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
+ "load=tftp 100000 hcu5/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_CS_1 0xC8000000 /* CAN */
+#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
+#define CFG_CPLD CFG_CS_2
+#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ * Memory Bank 0 (BOOT-FLASH) initialization
+ */
+#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Memory Bank 1 CAN-Chips initialization */
+#define CFG_EBC_PB1AP 0x02054500
+#define CFG_EBC_PB1CR 0xC8018000
+
+/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
+#define CFG_EBC_PB2AP 0x01840300
+#define CFG_EBC_PB2CR 0xCC0BA000
+
+/* Memory Bank 3 IMC-Bus fast mode initialization */
+#define CFG_EBC_PB3AP 0x01800300
+#define CFG_EBC_PB3CR 0xCE0BA000
+
+/* Memory Bank 4 (not used) initialization */
+#undef CFG_EBC_PB4AP
+#undef CFG_EBC_PB4CR
+
+/* Memory Bank 5 (not used) initialization */
+#undef CFG_EBC_PB5AP
+#undef CFG_EBC_PB5CR
+
+#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
+#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+ #define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_ETHADDR 00:06:3b:01:41:55
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \
"filesystem over NFS; echo"
+#define CONFIG_MCFTMR
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
#define CFG_ENV_IS_IN_FLASH
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
/*
* Ethernet
*/
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-#define CFG_ENET_BD_BASE 0x480000
-#define CFG_DISCOVER_PHY 1
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
#define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/*
* Definitions for initial stack pointer and data area (in DPRAM)
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
"-(user)";
#if defined(CONFIG_CMD_MII)
-#error MII commands don't work on iDMR board and sholud not be enabled.
+#error "MII commands don't work on iDMR board and should not be enabled."
#endif
#endif /* _IDMR_H */
#if 0
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
#undef CONFIG_SHOW_BOOT_PROGRESS
/*-----------------------------------------------------------------------
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
#define CONFIG_DDR_ECC 1 /* with ECC support */
-#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */
/*-----------------------------------------------------------------------
* I2C
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_LIME_BASE_0 0xc0000000
#define CFG_LIME_BASE_1 0xc1000000
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH0 0xFC000000
+#define CFG_FLASH1 0xF8000000
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
+#define CFG_POST_ECC_ON CFG_POST_ECC
+#else
+#define CFG_POST_ECC_ON 0
#endif
+/* POST support */
+#define CONFIG_POST (CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ECC_ON | \
+ CFG_POST_ETHER | \
+ CFG_POST_FPU | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_RTC | \
+ CFG_POST_SPR | \
+ CFG_POST_UART)
+
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CONFIG_LOGBUFFER
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
+ /* 64 byte page write mode using*/
+ /* last 6 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
+#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+
+#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
+#if 0
+#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
+#endif
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
+#define CONFIG_PREBOOT "setenv bootdelay 15"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=lwmon5\0" \
"netdev=eth0\0" \
+ "unlock=yes\0" \
+ "logversion=2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
+ "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
+ "flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/lwmon5/uImage\0" \
"kernel_addr=FC000000\0" \
"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
"cp.b 200000 FFF80000 80000\0" \
"upd=run load;run update\0" \
+ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
+ "autoscr 200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 300
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_USB
#endif
-
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#if 0
+/*
+ * ToDo: Watchdog is not test fully, so exclude it for now
+ */
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+#endif
/*
* For booting Linux, the board info and command line data
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03050200
-#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000)
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
/* Memory Bank 1 (Lime) initialization */
#define CFG_EBC_PB1AP 0x01004380
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
/* SDRAM Clock frequency adjustment register */
-#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
-/* Lime Clock frequency is to set 133MHz */
+#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
+/* Lime Clock frequency is to set 100MHz */
+#define CFG_LIME_CLOCK_100MHZ 0x00000
+#if 0
+/* Lime Clock frequency for 133MHz */
#define CFG_LIME_CLOCK_133MHZ 0x10000
+#endif
/* SDRAM Parameter register */
#define CFG_LIME_MMR 0xC1FCFFFC
-/* SDRAM parameter value */
+/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ and pixel flare on display when 133MHz was configured. According to
+ SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+#ifdef CFG_LIME_CLOCK_133MHZ
+#define CFG_LIME_MMR_VALUE 0x414FB7F3
+#else
#define CFG_LIME_MMR_VALUE 0x414FB7F2
+#endif
/*-----------------------------------------------------------------------
* GPIO Setup
#define CFG_GPIO_PHY1_RST 12
#define CFG_GPIO_FLASH_WP 14
#define CFG_GPIO_PHY0_RST 22
-#define CFG_GPIO_WATCHDOG 58
+#define CFG_GPIO_EEPROM_EXT_WP 55
+#define CFG_GPIO_EEPROM_INT_WP 57
#define CFG_GPIO_LIME_S 59
#define CFG_GPIO_LIME_RST 60
+#define CFG_GPIO_WATCHDOG 63
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
#define CFG_RESET_ADDRESS 0xfff00100
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,7448@0"
#define OF_TSI "tsi108@c0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
-
#define CONFIG_SUPPORT_VFAT
/*
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x0000)
-/* These addresses need to be shifted one place to the left
- * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
- * These values are shifted
- */
-#define CFG_ATA_PORT_ADDR(port) ((port) << 1)
-
#endif /* __CONFIG_H */
#define CONFIG_M5271 /* define processor type */
#define CONFIG_R5200 /* define board type */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_IPADDR 192.168.0.172
-#define CONFIG_SERVERIP 192.168.0.148
-#define CONFIG_ETHADDR 00:06:3b:00:44:55
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/* Note: We only copy one sectors worth of application code from location
* 10200000 for speed purposes. Increase the size if necessary */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e
--- /dev/null
+/*
+ * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman <joe.hamman@embeddedspecialties.com>
+ *
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SBC8641D board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx 1 /* MPC86xx */
+#define CONFIG_MPC8641 1 /* MPC8641 specific */
+#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR 0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS 0xfff00100
+
+#define CONFIG_PCI 1 /* Enable PCIE */
+#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CACHE_LINE_INTERLEAVING 0x20000000
+#define PAGE_INTERLEAVING 0x21000000
+#define BANK_INTERLEAVING 0x22000000
+#define SUPER_BANK_INTERLEAVING 0x23000000
+
+
+#define CONFIG_ALTIVEC 1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT 0
+#define L2_ENABLE (L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR1 & DDR2 parameters
+ */
+
+ #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
+
+ #define CFG_DDR_CS0_BNDS 0x0000000F
+ #define CFG_DDR_CS1_BNDS 0x00000000
+ #define CFG_DDR_CS2_BNDS 0x00000000
+ #define CFG_DDR_CS3_BNDS 0x00000000
+ #define CFG_DDR_CS0_CONFIG 0x80010102
+ #define CFG_DDR_CS1_CONFIG 0x00000000
+ #define CFG_DDR_CS2_CONFIG 0x00000000
+ #define CFG_DDR_CS3_CONFIG 0x00000000
+ #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_0 0x00220802
+ #define CFG_DDR_TIMING_1 0x38377322
+ #define CFG_DDR_TIMING_2 0x002040c7
+ #define CFG_DDR_CFG_1A 0x43008008
+ #define CFG_DDR_CFG_2 0x24401000
+ #define CFG_DDR_MODE_1 0x23c00542
+ #define CFG_DDR_MODE_2 0x00000000
+ #define CFG_DDR_MODE_CTL 0x00000000
+ #define CFG_DDR_INTERVAL 0x05080100
+ #define CFG_DDR_DATA_INIT 0x00000000
+ #define CFG_DDR_CLK_CTRL 0x03800000
+ #define CFG_DDR_CFG_1B 0xC3008008
+
+ #define CFG_DDR2_CS0_BNDS 0x0010001F
+ #define CFG_DDR2_CS1_BNDS 0x00000000
+ #define CFG_DDR2_CS2_BNDS 0x00000000
+ #define CFG_DDR2_CS3_BNDS 0x00000000
+ #define CFG_DDR2_CS0_CONFIG 0x80010102
+ #define CFG_DDR2_CS1_CONFIG 0x00000000
+ #define CFG_DDR2_CS2_CONFIG 0x00000000
+ #define CFG_DDR2_CS3_CONFIG 0x00000000
+ #define CFG_DDR2_EXT_REFRESH 0x00000000
+ #define CFG_DDR2_TIMING_0 0x00220802
+ #define CFG_DDR2_TIMING_1 0x38377322
+ #define CFG_DDR2_TIMING_2 0x002040c7
+ #define CFG_DDR2_CFG_1A 0x43008008
+ #define CFG_DDR2_CFG_2 0x24401000
+ #define CFG_DDR2_MODE_1 0x23c00542
+ #define CFG_DDR2_MODE_2 0x00000000
+ #define CFG_DDR2_MODE_CTL 0x00000000
+ #define CFG_DDR2_INTERVAL 0x05080100
+ #define CFG_DDR2_DATA_INIT 0x00000000
+ #define CFG_DDR2_CLK_CTRL 0x03800000
+ #define CFG_DDR2_CFG_1B 0xC3008008
+
+
+#endif
+
+/* #define CFG_ID_EEPROM 1
+#define ID_EEPROM_ADDR 0x57 */
+
+/*
+ * The SBC8641D contains 16MB flash space at ff000000.
+ */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+
+/* Flash */
+#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
+
+/* 64KB EEPROM */
+#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */
+#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
+
+/* EPLD - User switches, board id, LEDs */
+#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */
+#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
+
+/* Local bus SDRAM 128MB */
+#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */
+#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
+#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */
+#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
+
+/* Disk on Chip (DOC) 128MB */
+#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */
+#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
+
+/* LCD */
+#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */
+#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
+
+/* Control logic & misc peripherals */
+#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */
+#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 131 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_WRITE_SWAPPED_DATA
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECTION
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8641@0"
+#define OF_SOC "soc@f8000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0xe3000000
+#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#undef CFG_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#undef CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/* #define CONFIG_MII 1 */ /* MII PHY management */
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
+
+#define TSEC1_PHY_ADDR 0x1F
+#define TSEC2_PHY_ADDR 0x00
+#define TSEC3_PHY_ADDR 0x01
+#define TSEC4_PHY_ADDR 0x02
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC4_FLAGS TSEC_GIGABIT
+
+#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
+ */
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U CFG_DBAT0U
+
+/*
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 512M PCI-Express 1 Memory
+ * 0xa000_0000 512M PCI-Express 2 Memory
+ * Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U CFG_DBAT1U
+
+/*
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M RapidIO Memory
+ */
+#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U CFG_DBAT2U
+
+/*
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xf800_0000 4M CCSR
+ */
+#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U CFG_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
+ * Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U CFG_DBAT4U
+
+/*
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L CFG_DBAT5L
+#define CFG_IBAT5U CFG_DBAT5U
+
+/*
+ * BAT6 32M Cache-inhibited, guarded
+ * 0xfe00_0000 32M FLASH
+ */
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U CFG_DBAT6U
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 02:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH0 1
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_HAS_ETH2 1
+#define CONFIG_HAS_ETH3 1
+
+#define CONFIG_IPADDR 192.168.0.50
+
+#define CONFIG_HOSTNAME sbc8641d
+#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK 255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=uRamdisk\0" \
+ "dtbaddr=400000\0" \
+ "dtbfile=sbc8641d.dtb\0" \
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=1"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_FLASHBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "bootm ffd00000 ffb00000 ffa00000"
+
+#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CONFIG_CMD_USB
#endif
+#ifndef CONFIG_RAINIER
+#define CFG_POST_FPU_ON CFG_POST_FPU
+#else
+#define CFG_POST_FPU_ON 0
+#endif
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
- CFG_POST_FPU | \
+ CFG_POST_FPU_ON | \
CFG_POST_ETHER | \
CFG_POST_SPR)
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MII
-/* #define MII_DEBUG */
-/* #define CONFIG_FEC_ENET */
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
-/* #define CONFIG_FEC2_PHY_NORXERR */
-/* #define CFG_DISCOVER_PHY */
-/* #define CONFIG_PHY_ADDR 0x1 */
#define CONFIG_FEC2_PHY 1
#define CONFIG_BAUDRATE 19200
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
-#undef CONFIG_CMD_NET
-
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
-
+#define CONFIG_MPC85XX_PCI2 1
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
#define CONFIG_OF_HAS_BD_T 1
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_TAIHU 1 /* on a taihu board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
+#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootfile=/tftpboot/taihu/uImage\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
+ "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
+ "cp.b 200000 FFFC0000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x14 /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SPI
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
+#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
+#define CFG_SDRAM_BANKS 2
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_UART1_CONSOLE 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+#define CONFIG_SOFT_SPI
+#define SPI_SCL spi_scl
+#define SPI_SDA spi_sda
+#define SPI_READ spi_read()
+#define SPI_DELAY udelay(2)
+#ifndef __ASSEMBLY__
+void spi_scl(int);
+void spi_sda(int);
+unsigned char spi_read(void);
+#endif
+
+/* standard dtt sensor configuration */
+#define CONFIG_DTT_DS1775 1
+#define CONFIG_DTT_SENSORS { 0 }
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CONFIG_EEPRO100 1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFE00000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PPC405 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
+} \
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization */
+#define CFG_EBC_PB0AP 0x03815600
+#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CFG_EBC_PB1AP 0x05815600
+#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (USB device) initialization */
+#define CFG_EBC_PB2AP 0x03016600
+#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (LCM and D-flip-flop) initialization */
+#define CFG_EBC_PB3AP 0x158FF600
+#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (not install) initialization */
+#define CFG_EBC_PB4AP 0x158FF600
+#define CFG_EBC_PB4CR 0x5021A000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
+#define CFG_GPIO0_OSRL 0x00000110
+#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
+#define CFG_GPIO0_ISR1L 0x15545440
+#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
+#define CFG_GPIO0_ODR 0x00000000 /* open drain */
+
+#define GPIO0 0 /* GPIO controller 0 */
+
+/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
+
+#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
+#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
+#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
+#define GPIO_IS2(x) (x+GPIOx_IS1L)
+#define GPIO_IS3(x) (x+GPIOx_IS1L)
+
+#define CPLD_REG0_ADDR 0x50100000
+#define CPLD_REG1_ADDR 0x50100001
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/* Initial value of the on-board touch screen brightness */
#define CFG_BRIGHTNESS 0x20
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
+
+#define CONFIG_MMC 1
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
+#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
+#define CONFIG_STUART 1 /* we use STUART on Conxs */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_SERVERIP 192.168.1.99
+#define CONFIG_BOOTCOMMAND "run boot_flash"
+#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
+ " rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "program_boot_mmc=" \
+ "mw.b 0xa0010000 0xff 0x20000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 u-boot.bin; " \
+ "then " \
+ "protect off 0x0 0x1ffff; " \
+ "erase 0x0 0x1ffff; " \
+ "cp.b 0xa0010000 0x0 0x20000; " \
+ "fi\0" \
+ "program_uzImage_mmc=" \
+ "mw.b 0xa0010000 0xff 0x180000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 uzImage; " \
+ "then " \
+ "protect off 0x40000 0x1bffff; " \
+ "erase 0x40000 0x1bffff; " \
+ "cp.b 0xa0010000 0x40000 0x180000; " \
+ "fi\0" \
+ "program_ramdisk_mmc=" \
+ "mw.b 0xa0010000 0xff 0x500000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 ramdisk.gz; " \
+ "then " \
+ "protect off 0x1c0000 0x6bffff; " \
+ "erase 0x1c0000 0x6bffff; " \
+ "cp.b 0xa0010000 0x1c0000 0x500000; " \
+ "fi\0" \
+ "boot_mmc=" \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0030000 uzImage && " \
+ "fatload mmc 0 0xa0800000 ramdisk.gz; " \
+ "then " \
+ "bootm 0xa0030000; " \
+ "fi\0" \
+ "boot_flash=" \
+ "cp.b 0x1c0000 0xa0800000 0x500000; " \
+ "bootm 0x40000\0" \
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+/* #define CONFIG_INITRD_TAG 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE 0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00018000
+#define CFG_GPSR1_VAL 0x00000000
+#define CFG_GPSR2_VAL 0x400dc000
+#define CFG_GPSR3_VAL 0x00000000
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPCR3_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x00018000
+#define CFG_GPDR1_VAL 0x00028801
+#define CFG_GPDR2_VAL 0x520dc000
+#define CFG_GPDR3_VAL 0x0001E000
+#define CFG_GAFR0_L_VAL 0x801c0000
+#define CFG_GAFR0_U_VAL 0x00000013
+#define CFG_GAFR1_L_VAL 0x6990100A
+#define CFG_GAFR1_U_VAL 0x00000008
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x010900F2
+#define CFG_GAFR3_L_VAL 0x54000003
+#define CFG_GAFR3_U_VAL 0x00002401
+#define CFG_GRER0_VAL 0x00000000
+#define CFG_GRER1_VAL 0x00000000
+#define CFG_GRER2_VAL 0x00000000
+#define CFG_GRER3_VAL 0x00000000
+#define CFG_GFER0_VAL 0x00000000
+#define CFG_GFER1_VAL 0x00000000
+#define CFG_GFER2_VAL 0x00000000
+#define CFG_GFER3_VAL 0x00000020
+
+
+#define CFG_PSSR_VAL 0x20 /* CHECK */
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN 0x01FFFFFF /* CHECK */
+#define CFG_CCCR 0x02000290 /* 520Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL 0x4df84df0
+#define CFG_MSC1_VAL 0x7ff87ff4
+#define CFG_MSC2_VAL 0xa26936d4
+#define CFG_MDCNFG_VAL 0x880009C9
+#define CFG_MDREFR_VAL 0x20ca201e
+#define CFG_MDMRS_VAL 0x00220022
+
+#define CFG_FLYCNFG_VAL 0x00000000
+#define CFG_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000001
+#define CFG_MCMEM0_VAL 0x00004204
+#define CFG_MCMEM1_VAL 0x00010204
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00008407
+#define CFG_MCIO1_VAL 0x0000c108
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
+/* #define CONFIG_DM9000_USE_8BIT */
+/* #define CONFIG_DM9000_USE_16BIT */
+#define CONFIG_DM9000_USE_32BIT
+
+#define CONFIG_USB_OHCI_NEW 1
+#define CFG_USB_OHCI_BOARD_INIT 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
+#define CFG_USB_OHCI_REGS_BASE 0x4C000000
+#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
+#define CONFIG_USB_STORAGE 1
+#define CFG_USB_OHCI_CPU_INIT 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_MONITOR_BASE 0
+#define CFG_MONITOR_LEN 0x40000
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#endif /* __CONFIG_H */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
-/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define EXTCLK_83 83333333
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
#undef CONFIG_SHOW_BOOT_PROGRESS
#undef CONFIG_STRESS
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * zeus.h - configuration for Zeus board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ZEUS 1 /* Board is Zeus */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EP 1 /* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x01 /* PHY address */
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_CACHE | \
+ CFG_POST_UART | \
+ CFG_POST_ETHER)
+
+#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CFG_POST_UART_TABLE {UART0_BASE}
+
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
+#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * The layout of the I2C EEPROM, used for bootstrap setup and for board-
+ * specific values, like ethaddr... that can be restored via the sw-reset
+ * button
+ */
+#define FACTORY_RESET_I2C_EEPROM 0x50
+#define FACTORY_RESET_ENV_OFFS 0x80
+#define FACTORY_RESET_ENV_SIZE 0x80
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+/* extra data in OCM */
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
+#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash 16M) initialization */
+#define CFG_EBC_PB0AP 0x05815600
+#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
+#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
+#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
+#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
+#define CFG_GPIO0_TSRH 0x00000000
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
+#define CFG_GPIO0_ODR 0x00000000
+
+#define CFG_GPIO_SW_RESET 1
+#define CFG_GPIO_ZEUS_PE 12
+#define CFG_GPIO_LED_RED 22
+#define CFG_GPIO_LED_GREEN 23
+
+/* Time in milli-seconds */
+#define CFG_TIME_POST 5000
+#define CFG_TIME_FACTORY_RESET 10000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
+#define CONFIG_IPADDR 192.168.1.10
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_GATEWAYIP 192.168.1.100
+#define CONFIG_ETHADDR 50:00:00:00:06:00
+#define CONFIG_ETH1ADDR 50:00:00:00:06:01
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "logversion=2\0" \
+ "hostname=zeus\0" \
+ "netdev=eth0\0" \
+ "ethact=ppc_4xx_eth0\0" \
+ "netmask=255.255.255.0\0" \
+ "ramdisk_size=50000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw" \
+ " nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw" \
+ " ramdisk=${ramdisk_size}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0," \
+ "${baudrate}\0" \
+ "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "run nfsargs addip addtty;bootm\0" \
+ "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "tftp ${ramdisk_mem_addr} ${file_fs};" \
+ "run ramargs addip addtty;" \
+ "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
+ "rootpath=/target_fs/zeus\0" \
+ "kernel_fl_addr=ff000000\0" \
+ "kernel_mem_addr=200000\0" \
+ "ramdisk_fl_addr=ff300000\0" \
+ "ramdisk_mem_addr=4000000\0" \
+ "uboot_fl_addr=fffc0000\0" \
+ "uboot_mem_addr=100000\0" \
+ "file_uboot=/zeus/u-boot.bin\0" \
+ "tftp_uboot=tftp 100000 ${file_uboot}\0" \
+ "update_uboot=protect off fffc0000 ffffffff;" \
+ "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
+ "protect on fffc0000 ffffffff\0" \
+ "upd_uboot=run tftp_uboot;run update_uboot\0" \
+ "file_kernel=/zeus/uImage_ba\0" \
+ "tftp_kernel=tftp 100000 ${file_kernel}\0" \
+ "update_kernel=protect off ff000000 ff17ffff;" \
+ "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
+ "upd_kernel=run tftp_kernel;run update_kernel\0" \
+ "file_fs=/zeus/rootfs_ba.img\0" \
+ "tftp_fs=tftp 100000 ${file_fs}\0" \
+ "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
+ "cp.b 100000 ff300000 580000\0" \
+ "upd_fs=run tftp_fs;run update_fs\0" \
+ "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
+ ""
+
+#endif /* __CONFIG_H */
#include "config.h"
/*number of protected area*/
-#define NB_DATAFLASH_AREA 4
+#ifdef CONFIG_NEW_PARTITION
+# define NB_DATAFLASH_AREA 6
+#else
+# define NB_DATAFLASH_AREA 4
+#endif
+
+#ifdef CFG_NO_FLASH
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+# define ERR_OK 0
+# define ERR_TIMOUT 1
+# define ERR_NOT_ERASED 2
+# define ERR_PROTECTED 4
+# define ERR_INVAL 8
+# define ERR_ALIGN 16
+# define ERR_UNKNOWN_FLASH_VENDOR 32
+# define ERR_UNKNOWN_FLASH_TYPE 64
+# define ERR_PROG_ERROR 128
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+# define FLAG_PROTECT_SET 0x01
+# define FLAG_PROTECT_CLEAR 0x02
+# define FLAG_PROTECT_INVALID 0x03
+
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+# define FLAG_SETENV 0x80
+#endif /* CFG_NO_FLASH */
/*define the area structure*/
typedef struct {
unsigned long start;
unsigned long end;
unsigned char protected;
+ unsigned char setenv;
+ unsigned char label[20];
} dataflash_protect_t;
typedef unsigned int AT91S_DataFlashStatus;
AT91S_DataflashDesc Desc;
AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */
unsigned long logical_address;
+ unsigned long end_address;
unsigned int id; /* device id */
} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;
#define AT45DB321 0x34
#define AT45DB642 0x3c
#define AT45DB128 0x10
+#define PAGES_PER_BLOCK 8
#define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */
extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size);
extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr);
+extern int addr2ram(ulong addr);
extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr);
extern int addr_dataflash (unsigned long addr);
extern int read_dataflash (unsigned long addr, unsigned long size, char *result);
extern void dataflash_print_info (void);
extern void dataflash_perror (int err);
+#ifdef CONFIG_NEW_DF_PARTITION
+extern int AT91F_DataflashSetEnv (void); #endif
+#endif
+
#endif
#define DM9161_COLLISION_TEST (1 << 7)
/*--Bit definitions: DM9161_BMSR */
-#define DM9161_100BASE_T4 (1 << 15)
+#define DM9161_100BASE_TX (1 << 15)
#define DM9161_100BASE_TX_FD (1 << 14)
-#define DM9161_100BASE_T4_HD (1 << 13)
+#define DM9161_100BASE_TX_HD (1 << 13)
#define DM9161_10BASE_T_FD (1 << 12)
#define DM9161_10BASE_T_HD (1 << 11)
#define DM9161_MF_PREAMB_SUPPR (1 << 6)
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
defined(CONFIG_DTT_LM81) || \
defined(CONFIG_DTT_ADM1021)
#define DTT_CONFIG 0xAC
#endif
+#if defined(CONFIG_DTT_DS1775)
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_OS 0x3
+#endif
+
#if defined(CONFIG_DTT_ADM1021)
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
+#define FLAG_PROTECT_INVALID 0x03
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+#define FLAG_SETENV 0x80
/*-----------------------------------------------------------------------
* Device IDs
#define IDE_BUS(dev) (dev >> 1)
+#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+
#ifdef CONFIG_IDE_LED
/*
#define IH_CPU_NIOS2 15 /* Nios-II */
#define IH_CPU_BLACKFIN 16 /* Blackfin */
#define IH_CPU_AVR32 17 /* AVR32 */
+#define IH_CPU_ST200 18 /* STMicroelectronics ST200 */
/*
* Image Types
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LED_H
+#define __LED_H
+
+#ifndef __ASSEMBLY__
+extern void LED_init (void);
+extern void red_LED_on(void);
+extern void red_LED_off(void);
+extern void green_LED_on(void);
+extern void green_LED_off(void);
+extern void yellow_LED_on(void);
+extern void yellow_LED_off(void);
+#else
+ .extern LED_init
+ .extern red_LED_on
+ .extern red_LED_off
+ .extern yellow_LED_on
+ .extern yellow_LED_off
+ .extern green_LED_on
+ .extern green_LED_off
+#endif
+#endif
})
#define fdt_setprop_string(fdt, nodeoffset, name, str) \
fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create);
int fdt_delprop(void *fdt, int nodeoffset, const char *name);
int fdt_add_subnode_namelen(void *fdt, int parentoffset,
const char *name, int namelen);
#define NAND_MFR_NATIONAL 0x8f
#define NAND_MFR_RENESAS 0x07
#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_MICRON 0x2c
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_32_BE 0x00080000
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright(c) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
*/
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define _START_OFFSET EXC_OFF_SYS_RESET
+/* define for common ppc_asm.tmpl */
+#define EXC_OFF_SYS_RESET 0x100 /* System reset */
+#define _START_OFFSET 0
#if defined(CONFIG_E500)
#include <e500.h>
extern int nand_curr_device;
extern nand_info_t nand_info[];
+extern void nand_init(void);
static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
int state;
int (*init) (struct eth_device*, bd_t*);
- int (*send) (struct eth_device*, volatile void* pachet, int length);
+ int (*send) (struct eth_device*, volatile void* packet, int length);
int (*recv) (struct eth_device*);
void (*halt) (struct eth_device*);
-
+#ifdef CONFIG_MCAST_TFTP
+ int (*mcast) (struct eth_device*, u32 ip, u8 set);
+#endif
struct eth_device *next;
void *priv;
};
extern void eth_halt(void); /* stop SCC */
extern char *eth_get_name(void); /* get name of current device */
+#ifdef CONFIG_MCAST_TFTP
+int eth_mcast_join( IPaddr_t mcast_addr, u8 join);
+u32 ether_crc (size_t len, unsigned char const *p);
+#endif
+
/**********************************************************************/
/*
memcpy((void*)to, (void*)from, sizeof(ulong));
}
+/**
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ether_addr(const u8 *addr)
+{
+ return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 *addr)
+{
+ return (0x01 & addr[0]);
+}
+
/* Convert an IP address to a string */
extern void ip_to_string (IPaddr_t x, char *s);
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#define CFG_POST_FPU 0x00004000
+#define CFG_POST_ECC 0x00008000
#endif /* CONFIG_POST */
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
/*
* PLL Voltage Controlled Oscillator (VCO) definitions
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
+#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
+
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
+#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
#ifndef __ASSEMBLY__
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
+static inline u32 get_mcsr(void)
+{
+ u32 val;
+
+ asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+ return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+ asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
.long hdlr - _start + _START_OFFSET; \
.long crit_return - _start + _START_OFFSET
-#ifdef CONFIG_440
#define MCK_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
.L_ ## label : \
.long hdlr - _start + _START_OFFSET; \
.long mck_return - _start + _START_OFFSET
-#endif /* CONFIG_440 */
#endif /* __PPC_ASM_TMPL__ */
#include <s3c24x0.h>
-static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
{
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
}
-static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
{
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
}
-static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
{
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
}
-static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
{
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
}
-static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
{
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
}
-static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
{
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
}
-static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
+static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
{
return (S3C2410_NAND * const)S3C2410_NAND_BASE;
}
-static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
{
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
}
-static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
{
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
}
-static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
{
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
}
-static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
{
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
}
-static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
{
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
}
-static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
{
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
}
-static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
{
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
}
-static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
{
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
}
-static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
+static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
{
return (S3C2410_ADC * const)S3C2410_ADC_BASE;
}
-static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
{
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
}
-static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
+static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
{
return (S3C2410_SDI * const)S3C2410_SDI_BASE;
}
#endif
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
extern void serial_initialize(void);
extern void serial_devices_init(void);
extern int serial_assign(char * name);
drv_vfd_init();
#endif /* CONFIG_VFD */
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
+
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
int post_flag;
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CFG_NO_FLASH
extern flash_info_t flash_info[];
#endif
static int init_baudrate(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
char tmp[64];
int i = getenv_r("baudrate", tmp, sizeof(tmp));
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
#ifdef DEBUG
static void display_global_data(void)
{
- DECLARE_GLOBAL_DATA_PTR;
bd_t *bd;
bd = gd->bd;
printf("--flags:%x\n", gd->flags);
void board_init_f(ulong bootflag)
{
- DECLARE_GLOBAL_DATA_PTR;
ulong addr;
bd_t *bd;
int i;
void board_init_r(gd_t * id, ulong dest_addr)
{
- DECLARE_GLOBAL_DATA_PTR;
ulong size;
extern void malloc_bin_reloc(void);
char *s, *e;
#ifdef CONFIG_POST
+DECLARE_GLOBAL_DATA_PTR;
+
#define POST_MAX_NUMBER 32
#define BOOTMODE_MAGIC 0xDEAD0000
int post_init_f(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int res = 0;
unsigned int i;
void post_bootmode_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
int bootmode = post_bootmode_get(0);
int newword;
/* POST tests run before relocation only mark status bits .... */
static void post_log_mark_start(unsigned long testid)
{
- DECLARE_GLOBAL_DATA_PTR;
gd->post_log_word |= (testid) << 16;
}
static void post_log_mark_succ(unsigned long testid)
{
- DECLARE_GLOBAL_DATA_PTR;
gd->post_log_word |= testid;
}
/* ... and the messages are output once we are relocated */
void post_output_backlog(void)
{
- DECLARE_GLOBAL_DATA_PTR;
int j;
for (j = 0; j < post_list_size; j++) {
void post_reloc(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned int i;
/*
SOBJS =
-COBJS = cache.o traps.o time.o board.o m68k_linux.o
+COBJS = cache.o traps.o time.o interrupts.o board.o m68k_linux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#include <malloc.h>
#include <devices.h>
-#ifdef CONFIG_M5272
-#include <asm/immap_5272.h>
-#endif
+#include <asm/immap.h>
#if defined(CONFIG_CMD_IDE)
#include <ide.h>
char *strmhz(char *buf, long hz)
{
- long l, n;
- long m;
+ long l, n;
+ long m;
- n = hz / 1000000L;
+ n = hz / 1000000L;
- l = sprintf (buf, "%ld", n);
+ l = sprintf (buf, "%ld", n);
- m = (hz % 1000000L) / 1000L;
+ m = (hz % 1000000L) / 1000L;
- if (m != 0)
- sprintf (buf+l, ".%03ld", m);
+ if (m != 0)
+ sprintf (buf+l, ".%03ld", m);
- return (buf);
+ return (buf);
}
/*
typedef int (init_fnc_t) (void);
/************************************************************************
- * Init Utilities *
+ * Init Utilities
************************************************************************
* Some of this code should be moved into the core functions,
* but let's get it working (again) first...
*/
init_fnc_t *init_sequence[] = {
+ get_clocks,
env_init,
init_baudrate,
serial_init,
*/
bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
+#ifdef CFG_INIT_RAM_ADDR
+ bd->bi_sramstart = CFG_INIT_RAM_ADDR; /* start of SRAM memory */
+ bd->bi_sramsize = CFG_INIT_RAM_END; /* size of SRAM memory */
+#endif
bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
+#ifdef CONFIG_PCI
+ bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+ bd->bi_inpfreq = gd->inp_clk; /* input Freq in Hz */
+ bd->bi_vcofreq = gd->vco_clk; /* vco Freq in Hz */
+ bd->bi_flbfreq = gd->flb_clk; /* flexbus Freq in Hz */
+#endif
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CFG_EXTBDINFO
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
+
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
WATCHDOG_RESET ();
/*
* Setup trap handlers
*/
- trap_init (0);
+ trap_init (CFG_SDRAM_BASE);
#if !defined(CFG_NO_FLASH)
puts ("FLASH: ");
if (s)
s = (*e) ? e + 1 : e;
}
+#ifdef CONFIG_HAS_ETH1
+ /* handle the 2nd ethernet address */
+
+ s = getenv ("eth1addr");
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+#endif
+#ifdef CONFIG_HAS_ETH2
+ /* handle the 3rd ethernet address */
+
+ s = getenv ("eth2addr");
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH3
+ /* handle 4th ethernet address */
+ s = getenv("eth3addr");
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+#endif
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
WATCHDOG_RESET ();
+#if defined(CONFIG_PCI)
+ /*
+ * Do pci configuration
+ */
+ pci_init ();
+#endif
/** leave this here (after malloc(), environment and PCI are working) **/
/* Initialize devices */
nand_init(); /* go init the NAND */
#endif
-#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
+#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
+#if defined(FEC_ENET)
eth_init(bd);
#endif
+#if defined(CONFIG_NET_MULTI)
+ puts ("Net: ");
+ eth_initialize (bd);
+#endif
+#endif
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
#endif
+#if defined(CONFIG_CMD_PCMCIA) \
+ && !defined(CONFIG_CMD_IDE)
+ WATCHDOG_RESET ();
+ puts ("PCMCIA:");
+ pcmcia_init ();
+#endif
+
+#if defined(CONFIG_CMD_IDE)
+ WATCHDOG_RESET ();
+ puts ("IDE: ");
+ ide_init ();
+#endif
+
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET ();
/*
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007 Freescale Semiconductor Inc
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+#define NR_IRQS (CFG_NUM_IRQS)
+
+/*
+ * Interrupt vector functions.
+ */
+struct interrupt_action {
+ interrupt_handler_t *handler;
+ void *arg;
+};
+
+static struct interrupt_action irq_vecs[NR_IRQS];
+
+static __inline__ unsigned short get_sr (void)
+{
+ unsigned short sr;
+
+ asm volatile ("move.w %%sr,%0":"=r" (sr):);
+
+ return sr;
+}
+
+static __inline__ void set_sr (unsigned short sr)
+{
+ asm volatile ("move.w %0,%%sr"::"r" (sr));
+}
+
+/************************************************************************/
+/*
+ * Install and free an interrupt handler
+ */
+void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
+{
+ if ((vec < 0) || (vec > NR_IRQS)) {
+ printf ("irq_install_handler: wrong interrupt vector %d\n",
+ vec);
+ return;
+ }
+
+ irq_vecs[vec].handler = handler;
+ irq_vecs[vec].arg = arg;
+}
+
+void irq_free_handler (int vec)
+{
+ if ((vec < 0) || (vec > NR_IRQS)) {
+ return;
+ }
+
+ irq_vecs[vec].handler = NULL;
+ irq_vecs[vec].arg = NULL;
+}
+
+void enable_interrupts (void)
+{
+ unsigned short sr;
+
+ sr = get_sr ();
+ set_sr (sr & ~0x0700);
+}
+
+int disable_interrupts (void)
+{
+ unsigned short sr;
+
+ sr = get_sr ();
+ set_sr (sr | 0x0700);
+
+ return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */
+}
+
+void int_handler (struct pt_regs *fp)
+{
+ int vec;
+
+ vec = (fp->vector >> 2) & 0xff;
+ if (vec > 0x40)
+ vec -= 0x40;
+
+ if (irq_vecs[vec].handler != NULL) {
+ irq_vecs[vec].handler (irq_vecs[vec].arg);
+ } else {
+ printf ("\nBogus External Interrupt Vector %d\n", vec);
+ }
+}
#include <command.h>
#include <image.h>
#include <zlib.h>
+#include <bzlib.h>
+#include <environment.h>
#include <asm/byteorder.h>
DECLARE_GLOBAL_DATA_PTR;
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
-extern image_header_t header; /* from cmd_bootm.c */
-
-extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-
-static int linux_argc;
-static char **linux_argv;
-
-static char **linux_env;
-static char *linux_env_p;
-static int linux_env_idx;
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
-static void linux_params_init (ulong start, char *commandline);
-static void linux_env_set (char *env_name, char *env_val);
+extern image_header_t header;
-void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
- ulong addr, ulong * len_ptr, int verify)
+void do_bootm_linux(cmd_tbl_t * cmdtp, int flag,
+ int argc, char *argv[],
+ ulong addr, ulong * len_ptr, int verify)
{
- ulong len = 0, checksum;
+ ulong sp;
+ ulong len, checksum;
ulong initrd_start, initrd_end;
+ ulong cmd_start, cmd_end;
+ ulong initrd_high;
ulong data;
- void (*theKernel) (int, char **, char **, int *);
+ int initrd_copy_to_ram = 1;
+ char *cmdline;
+ char *s;
+ bd_t *kbd;
+ void (*kernel) (bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
- char *commandline = getenv ("bootargs");
- char env_buf[12];
- theKernel =
- (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep);
+ if ((s = getenv("initrd_high")) != NULL) {
+ /* a value of "no" or a similar string will act like 0,
+ * turning the "load high" feature off. This is intentional.
+ */
+ initrd_high = simple_strtoul(s, NULL, 16);
+ if (initrd_high == ~0)
+ initrd_copy_to_ram = 0;
+ } else { /* not set, no restrictions to load high */
+ initrd_high = ~0;
+ }
+
+#ifdef CONFIG_LOGBUFFER
+ kbd = gd->bd;
+ /* Prevent initrd from overwriting logbuffer */
+ if (initrd_high < (kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD))
+ initrd_high = kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD;
+ debug("## Logbuffer at 0x%08lX ", kbd->bi_memsize - LOGBUFF_LEN);
+#endif
+
+ /*
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CFG_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
+ */
+ asm("movel %%a7, %%d0\n"
+ "movel %%d0, %0\n": "=d"(sp): :"%d0");
+
+ debug("## Current stack ends at 0x%08lX ", sp);
+
+ sp -= 2048; /* just to be sure */
+ if (sp > CFG_BOOTMAPSZ)
+ sp = CFG_BOOTMAPSZ;
+ sp &= ~0xF;
+
+ debug("=> set upper limit to 0x%08lX\n", sp);
+
+ cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF);
+ kbd = (bd_t *) (((ulong) cmdline - sizeof(bd_t)) & ~0xF);
+
+ if ((s = getenv("bootargs")) == NULL)
+ s = "";
+
+ strcpy(cmdline, s);
+
+ cmd_start = (ulong) & cmdline[0];
+ cmd_end = cmd_start + strlen(cmdline);
+
+ *kbd = *(gd->bd);
+
+#ifdef DEBUG
+ printf("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end);
+
+ do_bdinfo(NULL, 0, 0, NULL);
+#endif
+
+ if ((s = getenv("clocks_in_mhz")) != NULL) {
+ /* convert all clock information to MHz */
+ kbd->bi_intfreq /= 1000000L;
+ kbd->bi_busfreq /= 1000000L;
+ }
+
+ kernel =
+ (void (*)(bd_t *, ulong, ulong, ulong, ulong))ntohl(hdr->ih_ep);
/*
* Check if there is an initrd image
*/
+
if (argc >= 3) {
- show_boot_progress (9);
+ debug("Not skipping initrd\n");
+ SHOW_BOOT_PROGRESS(9);
- addr = simple_strtoul (argv[2], NULL, 16);
+ addr = simple_strtoul(argv[2], NULL, 16);
- printf ("## Loading Ramdisk Image at %08lx ...\n", addr);
+ printf("## Loading RAMDisk Image at %08lx ...\n", addr);
/* Copy header so we can blank CRC field for re-calculation */
- memcpy (&header, (char *) addr, sizeof (image_header_t));
+ memmove(&header, (char *)addr, sizeof(image_header_t));
- if (ntohl (hdr->ih_magic) != IH_MAGIC) {
- printf ("Bad Magic Number\n");
- show_boot_progress (-10);
- do_reset (cmdtp, flag, argc, argv);
+ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+ puts("Bad Magic Number\n");
+ SHOW_BOOT_PROGRESS(-10);
+ do_reset(cmdtp, flag, argc, argv);
}
data = (ulong) & header;
- len = sizeof (image_header_t);
+ len = sizeof(image_header_t);
- checksum = ntohl (hdr->ih_hcrc);
+ checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *) data, len) != checksum) {
- printf ("Bad Header Checksum\n");
- show_boot_progress (-11);
- do_reset (cmdtp, flag, argc, argv);
+ if (crc32(0, (uchar *) data, len) != checksum) {
+ puts("Bad Header Checksum\n");
+ SHOW_BOOT_PROGRESS(-11);
+ do_reset(cmdtp, flag, argc, argv);
}
- show_boot_progress (10);
+ SHOW_BOOT_PROGRESS(10);
- print_image_hdr (hdr);
+ print_image_hdr(hdr);
- data = addr + sizeof (image_header_t);
- len = ntohl (hdr->ih_size);
+ data = addr + sizeof(image_header_t);
+ len = ntohl(hdr->ih_size);
if (verify) {
ulong csum = 0;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ ulong cdata = data, edata = cdata + len;
+#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
- printf (" Verifying Checksum ... ");
- csum = crc32 (0, (char *) data, len);
- if (csum != ntohl (hdr->ih_dcrc)) {
- printf ("Bad Data CRC\n");
- show_boot_progress (-12);
- do_reset (cmdtp, flag, argc, argv);
+ puts(" Verifying Checksum ... ");
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+
+ while (cdata < edata) {
+ ulong chunk = edata - cdata;
+
+ if (chunk > CHUNKSZ)
+ chunk = CHUNKSZ;
+ csum = crc32(csum, (uchar *) cdata, chunk);
+ cdata += chunk;
+
+ WATCHDOG_RESET();
}
- printf ("OK\n");
+#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+ csum = crc32(0, (uchar *) data, len);
+#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+
+ if (csum != ntohl(hdr->ih_dcrc)) {
+ puts("Bad Data CRC\n");
+ SHOW_BOOT_PROGRESS(-12);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+ puts("OK\n");
}
- show_boot_progress (11);
+ SHOW_BOOT_PROGRESS(11);
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_M68K) ||
(hdr->ih_type != IH_TYPE_RAMDISK)) {
- printf ("No Linux M68K Ramdisk Image\n");
- show_boot_progress (-13);
- do_reset (cmdtp, flag, argc, argv);
+ puts("No Linux ColdFire Ramdisk Image\n");
+ SHOW_BOOT_PROGRESS(-13);
+ do_reset(cmdtp, flag, argc, argv);
}
/*
* Now check if we have a multifile image
*/
} else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
- ulong tail = ntohl (len_ptr[0]) % 4;
+ u_long tail = ntohl(len_ptr[0]) % 4;
int i;
- show_boot_progress (13);
+ SHOW_BOOT_PROGRESS(13);
/* skip kernel length and terminator */
data = (ulong) (&len_ptr[2]);
for (i = 1; len_ptr[i]; ++i)
data += 4;
/* add kernel length, and align */
- data += ntohl (len_ptr[0]);
+ data += ntohl(len_ptr[0]);
if (tail) {
data += 4 - tail;
}
- len = ntohl (len_ptr[1]);
+ len = ntohl(len_ptr[1]);
} else {
/*
* no initrd image
*/
- show_boot_progress (14);
+ SHOW_BOOT_PROGRESS(14);
- data = 0;
+ len = data = 0;
}
-#ifdef DEBUG
if (!data) {
- printf ("No initrd\n");
+ debug("No initrd\n");
}
-#endif
if (data) {
- initrd_start = data;
- initrd_end = initrd_start + len;
- } else {
- initrd_start = 0;
- initrd_end = 0;
- }
-
- show_boot_progress (15);
-
-#ifdef DEBUG
- printf ("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) theKernel);
-#endif
-
- linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline);
-
- sprintf (env_buf, "%lu", gd->ram_size >> 20);
- linux_env_set ("memsize", env_buf);
-
- sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start));
- linux_env_set ("initrd_start", env_buf);
-
- sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start));
- linux_env_set ("initrd_size", env_buf);
-
- sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
- linux_env_set ("flash_start", env_buf);
-
- sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
- linux_env_set ("flash_size", env_buf);
-
- /* we assume that the kernel is in place */
- printf ("\nStarting kernel ...\n\n");
-
- theKernel (linux_argc, linux_argv, linux_env, 0);
-}
-
-static void linux_params_init (ulong start, char *line)
-{
- char *next, *quote, *argp;
-
- linux_argc = 1;
- linux_argv = (char **) start;
- linux_argv[0] = 0;
- argp = (char *) (linux_argv + LINUX_MAX_ARGS);
-
- next = line;
-
- while (line && *line && linux_argc < LINUX_MAX_ARGS) {
- quote = strchr (line, '"');
- next = strchr (line, ' ');
-
- while (next != NULL && quote != NULL && quote < next) {
- /* we found a left quote before the next blank
- * now we have to find the matching right quote
- */
- next = strchr (quote + 1, '"');
- if (next != NULL) {
- quote = strchr (next + 1, '"');
- next = strchr (next + 1, ' ');
+ if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
+ initrd_start = data;
+ initrd_end = initrd_start + len;
+ } else {
+ initrd_start = (ulong) kbd - len;
+ initrd_start &= ~(4096 - 1); /* align on page */
+
+ if (initrd_high) {
+ ulong nsp;
+
+ /*
+ * the inital ramdisk does not need to be within
+ * CFG_BOOTMAPSZ as it is not accessed until after
+ * the mm system is initialised.
+ *
+ * do the stack bottom calculation again and see if
+ * the initrd will fit just below the monitor stack
+ * bottom without overwriting the area allocated
+ * above for command line args and board info.
+ */
+ asm("movel %%a7, %%d0\n"
+ "movel %%d0, %0\n": "=d"(nsp): :"%d0");
+
+ nsp -= 2048; /* just to be sure */
+ nsp &= ~0xF;
+
+ if (nsp > initrd_high) /* limit as specified */
+ nsp = initrd_high;
+
+ nsp -= len;
+ nsp &= ~(4096 - 1); /* align on page */
+
+ if (nsp >= sp)
+ initrd_start = nsp;
}
- }
- if (next == NULL) {
- next = line + strlen (line);
+ SHOW_BOOT_PROGRESS(12);
+
+ debug
+ ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
+ data, data + len - 1, len, len);
+
+ initrd_end = initrd_start + len;
+ printf(" Loading Ramdisk to %08lx, end %08lx ... ",
+ initrd_start, initrd_end);
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ {
+ size_t l = len;
+ void *to = (void *)initrd_start;
+ void *from = (void *)data;
+
+ while (l > 0) {
+ size_t tail =
+ (l > CHUNKSZ) ? CHUNKSZ : l;
+ WATCHDOG_RESET();
+ memmove(to, from, tail);
+ to += tail;
+ from += tail;
+ l -= tail;
+ }
+ }
+#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+ memmove((void *)initrd_start, (void *)data, len);
+#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+ puts("OK\n");
}
-
- linux_argv[linux_argc] = argp;
- memcpy (argp, line, next - line);
- argp[next - line] = 0;
-
- argp += next - line + 1;
- linux_argc++;
-
- if (*next)
- next++;
-
- line = next;
+ } else {
+ initrd_start = 0;
+ initrd_end = 0;
}
- linux_env = (char **) (((ulong) argp + 15) & ~15);
- linux_env[0] = 0;
- linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS);
- linux_env_idx = 0;
-}
-
-static void linux_env_set (char *env_name, char *env_val)
-{
- if (linux_env_idx < LINUX_MAX_ENVS - 1) {
- linux_env[linux_env_idx] = linux_env_p;
-
- strcpy (linux_env_p, env_name);
- linux_env_p += strlen (env_name);
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel);
- strcpy (linux_env_p, "=");
- linux_env_p += 1;
+ SHOW_BOOT_PROGRESS(15);
- strcpy (linux_env_p, env_val);
- linux_env_p += strlen (env_val);
-
- linux_env_p++;
- linux_env[++linux_env_idx] = 0;
- }
+ /*
+ * Linux Kernel Parameters (passing board info data):
+ * r3: ptr to board info data
+ * r4: initrd_start or 0 if no initrd
+ * r5: initrd_end - unused if r4 is 0
+ * r6: Start of command line string
+ * r7: End of command line string
+ */
+ (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+ /* does not return */
}
#include <common.h>
-#include <asm/mcftimer.h>
+#include <asm/timer.h>
+#include <asm/immap.h>
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-#endif
+DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
-#endif
+static ulong timestamp;
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
+#if defined(CONFIG_MCFTMR)
+#ifndef CFG_UDELAY_BASE
+# error "uDelay base not defined!"
#endif
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#include <asm/immap_5249.h>
+#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
+# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
#endif
+extern void dtimer_intr_setup(void);
-
-static ulong timestamp;
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
-static unsigned short lastinc;
-#endif
-
-
-#if defined(CONFIG_M5272)
-/*
- * We use timer 3 which is running with a period of 1 us
- */
void udelay(unsigned long usec)
{
- volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
+ volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE);
uint start, now, tmp;
while (usec > 0) {
usec = usec - tmp;
/* Set up TIMER 3 as timebase clock */
- timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
- timerp->timer_tcn = 0;
+ timerp->tmr = DTIM_DTMR_RST_RST;
+ timerp->tcn = 0;
/* set period to 1 us */
- timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
- MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
+ timerp->tmr =
+ CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
+ DTIM_DTMR_RST_EN;
- start = now = timerp->timer_tcn;
+ start = now = timerp->tcn;
while (now < start + tmp)
- now = timerp->timer_tcn;
+ now = timerp->tcn;
}
}
-void mcf_timer_interrupt (void * not_used){
- volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
- volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
+void dtimer_interrupt(void *not_used)
+{
+ volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
- /* check for timer 4 interrupts */
- if ((intp->int_isr & 0x01000000) != 0) {
+ /* check for timer interrupt asserted */
+ if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) {
+ timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
+ timestamp++;
return;
}
-
- /* reset timer */
- timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
- timestamp ++;
}
-void timer_init (void) {
- volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
- volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
+void timer_init(void)
+{
+ volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
timestamp = 0;
+ timerp->tcn = 0;
+ timerp->trr = 0;
+
/* Set up TIMER 4 as clock */
- timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
+ timerp->tmr = DTIM_DTMR_RST_RST;
+
+ /* initialize and enable timer interrupt */
+ irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
- /* initialize and enable timer 4 interrupt */
- irq_install_handler (72, mcf_timer_interrupt, 0);
- intp->int_icr1 |= 0x0000000d;
+ timerp->tcn = 0;
+ timerp->trr = 1000; /* Interrupt every ms */
+
+ dtimer_intr_setup();
- timerp->timer_tcn = 0;
- timerp->timer_trr = 1000; /* Interrupt every ms */
/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
- timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
- MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
+ timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
+ DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
}
-void reset_timer (void)
+void reset_timer(void)
{
timestamp = 0;
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
return (timestamp - base);
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
+#endif /* CONFIG_MCFTMR */
+
+#if defined(CONFIG_MCFPIT)
+#if !defined(CFG_PIT_BASE)
+# error "CFG_PIT_BASE not defined!"
#endif
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+static unsigned short lastinc;
void udelay(unsigned long usec)
{
- volatile unsigned short *timerp;
+ volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE);
uint tmp;
- timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
-
while (usec > 0) {
if (usec > 65000)
tmp = 65000;
usec = usec - tmp;
/* Set up TIMER 3 as timebase clock */
- timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
- timerp[MCFTIMER_PMR] = 0;
+ timerp->pcsr = PIT_PCSR_OVW;
+ timerp->pmr = 0;
/* set period to 1 us */
- timerp[MCFTIMER_PCSR] =
-#ifdef CONFIG_M5271
- (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
-#else /* !CONFIG_M5271 */
- (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
-#endif /* CONFIG_M5271 */
-
- timerp[MCFTIMER_PMR] = tmp;
- while (timerp[MCFTIMER_PCNTR] > 0);
+ timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
+
+ timerp->pmr = tmp;
+ while (timerp->pcntr > 0) ;
}
}
-void timer_init (void)
+void timer_init(void)
{
- volatile unsigned short *timerp;
-
- timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
+ volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
timestamp = 0;
/* Set up TIMER 4 as poll clock */
- timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
- timerp[MCFTIMER_PMR] = lastinc = 0;
- timerp[MCFTIMER_PCSR] =
-#ifdef CONFIG_M5271
- (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
-#else /* !CONFIG_M5271 */
- (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
-#endif /* CONFIG_M5271 */
+ timerp->pcsr = PIT_PCSR_OVW;
+ timerp->pmr = lastinc = 0;
+ timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
- volatile unsigned short *timerp;
+ volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
- timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
timestamp = 0;
- timerp[MCFTIMER_PMR] = lastinc = 0;
+ timerp->pmr = lastinc = 0;
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
unsigned short now, diff;
- volatile unsigned short *timerp;
+ volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
- timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
- now = timerp[MCFTIMER_PCNTR];
+ now = timerp->pcntr;
diff = -(now - lastinc);
timestamp += diff;
return timestamp - base;
}
-void wait_ticks (unsigned long ticks)
+void wait_ticks(unsigned long ticks)
{
- set_timer (0);
- while (get_timer (0) < ticks);
+ set_timer(0);
+ while (get_timer(0) < ticks) ;
}
-#endif
-
-
-#if defined(CONFIG_M5249)
-/*
- * We use timer 1 which is running with a period of 1 us
- */
-void udelay(unsigned long usec)
-{
- volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
- uint start, now, tmp;
-
- while (usec > 0) {
- if (usec > 65000)
- tmp = 65000;
- else
- tmp = usec;
- usec = usec - tmp;
-
- /* Set up TIMER 1 as timebase clock */
- timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
- timerp->timer_tcn = 0;
- /* set period to 1 us */
- /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
- timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
- MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
-
- start = now = timerp->timer_tcn;
- while (now < start + tmp)
- now = timerp->timer_tcn;
- }
-}
-
-void mcf_timer_interrupt (void * not_used){
- volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
-
- /* check for timer 2 interrupts */
- if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
- return;
- }
-
- /* reset timer */
- timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
- timestamp ++;
-}
-
-void timer_init (void) {
- volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
-
- timestamp = 0;
-
- /* Set up TIMER 2 as clock */
- timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
-
- /* initialize and enable timer 2 interrupt */
- irq_install_handler (31, mcf_timer_interrupt, 0);
- mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
- mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);
-
- timerp->timer_tcn = 0;
- timerp->timer_trr = 1000; /* Interrupt every ms */
- /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
- /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
- timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
- MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
-}
-
-void reset_timer (void)
-{
- timestamp = 0;
-}
-
-ulong get_timer (ulong base)
-{
- return (timestamp - base);
-}
-
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-#endif
-
+#endif /* CONFIG_MCFPIT */
/*
* This function is derived from PowerPC code (read timebase as long long).
* This function is derived from PowerPC code (timebase clock frequency).
* On M68K it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
/***********************************************************************/
-#ifdef CONFIG_ADD_RAM_INFO
-void board_add_ram_info(int);
-#endif
+void __board_add_ram_info(int use_default)
+{
+ /* please define platform specific board_add_ram_info() */
+}
+void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
+
static int init_func_ram (void)
{
if ((gd->ram_size = initdram (board_type)) > 0) {
print_size (gd->ram_size, "");
-#ifdef CONFIG_ADD_RAM_INFO
board_add_ram_info(0);
-#endif
putc('\n');
return (0);
}
/* if the serial port does not hang in exception, printf can be used */
#if !defined(CFG_SERIAL_HANG_IN_EXCEPTION)
if (ex_tab_message)
- printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
+ debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
#endif
if (ret) return ret;
}
#endif /* CONFIG_OF_LIBFDT */
-
return 0;
}
+/**
+ * fdt_find_and_setprop: Find a node and set it's property
+ *
+ * @fdt: ptr to device tree
+ * @node: path of node
+ * @prop: property name
+ * @val: ptr to new value
+ * @len: length of new property value
+ * @create: flag to create the property if it doesn't exist
+ *
+ * Convenience function to directly set a property given the path to the node.
+ */
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create)
+{
+ int nodeoff = fdt_find_node_by_path(fdt, node);
+
+ if (nodeoff < 0)
+ return nodeoff;
+
+ if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL))
+ return 0; /* create flag not set; so exit quietly */
+
+ return fdt_setprop(fdt, nodeoff, prop, val, len);
+}
+
int fdt_delprop(void *fdt, int nodeoffset, const char *name)
{
struct fdt_property *prop;
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)sdram.c:
+ @rm -f $(obj)sdram.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
+endif
+
#########################################################################
$(obj)%.o: $(obj)%.S
IPaddr_t tmp_ip;
NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
+#if !defined(CONFIG_BOOTP_SERVERIP)
NetCopyIP(&tmp_ip, &bp->bp_siaddr);
if (tmp_ip != 0)
NetCopyIP(&NetServerIP, &bp->bp_siaddr);
memcpy (NetServerEther, ((Ethernet_t *)NetRxPkt)->et_src, 6);
+#endif
if (strlen(bp->bp_file) > 0)
copy_filename (BootFile, bp->bp_file, sizeof(BootFile));
break;
#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET)
case 2: /* Time offset */
- NetCopyLong (&NetTimeOffset, (ulong *) (popt + 2));
+ NetCopyLong ((ulong *)&NetTimeOffset, (ulong *) (popt + 2));
NetTimeOffset = ntohl (NetTimeOffset);
break;
#endif
extern int uec_initialize(int);
extern int bfin_EMAC_initialize(bd_t *);
extern int atstk1000_eth_initialize(bd_t *);
+extern int mcffec_initialize(bd_t*);
static struct eth_device *eth_devices, *eth_current;
#if defined(CONFIG_ATSTK1000)
atstk1000_eth_initialize(bis);
#endif
+#if defined(CONFIG_MCFFEC)
+ mcffec_initialize(bis);
+#endif
if (!eth_devices) {
puts ("No ethernet found.\n");
memcpy(dev->enetaddr, enetaddr, 6);
}
+#ifdef CONFIG_MCAST_TFTP
+/* Multicast.
+ * mcast_addr: multicast ipaddr from which multicast Mac is made
+ * join: 1=join, 0=leave.
+ */
+int eth_mcast_join( IPaddr_t mcast_ip, u8 join)
+{
+ u8 mcast_mac[6];
+ if (!eth_current || !eth_current->mcast)
+ return -1;
+ mcast_mac[5] = htonl(mcast_ip) & 0xff;
+ mcast_mac[4] = (htonl(mcast_ip)>>8) & 0xff;
+ mcast_mac[3] = (htonl(mcast_ip)>>16) & 0x7f;
+ mcast_mac[2] = 0x5e;
+ mcast_mac[1] = 0x0;
+ mcast_mac[0] = 0x1;
+ return eth_current->mcast(eth_current, mcast_mac, join);
+}
+
+/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
+ * and this is the ethernet-crc method needed for TSEC -- and perhaps
+ * some other adapter -- hash tables
+ */
+#define CRCPOLY_LE 0xedb88320
+u32 ether_crc (size_t len, unsigned char const *p)
+{
+ int i;
+ u32 crc;
+ crc = ~0;
+ while (len--) {
+ crc ^= *p++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
+ }
+ /* an reverse the bits, cuz of way they arrive -- last-first */
+ crc = (crc >> 16) | (crc << 16);
+ crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
+ crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
+ crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
+ crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
+ return crc;
+}
+
+#endif
+
int eth_init(bd_t *bis)
{
char NetOurRootPath[64]={0,}; /* Our bootpath */
ushort NetBootFileSize=0; /* Our bootfile size in blocks */
+#ifdef CONFIG_MCAST_TFTP /* Multicast TFTP */
+IPaddr_t Mcast_addr;
+#endif
+
/** END OF BOOTP EXTENTIONS **/
ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */
case NETLOOP_SUCCESS:
if (NetBootFileXferSize > 0) {
- char buf[10];
+ char buf[20];
printf("Bytes transferred = %ld (%lx hex)\n",
NetBootFileXferSize,
NetBootFileXferSize);
- sprintf(buf, "%lx", NetBootFileXferSize);
+ sprintf(buf, "%lX", NetBootFileXferSize);
setenv("filesize", buf);
sprintf(buf, "%lX", (unsigned long)load_addr);
}
tmp = NetReadIP(&ip->ip_dst);
if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) {
+#ifdef CONFIG_MCAST_TFTP
+ if (Mcast_addr != tmp)
+#endif
return;
}
/*
}
#endif
+
#ifdef CONFIG_NETCONSOLE
nc_input_packet((uchar *)ip +IP_HDR_SIZE,
ntohs(ip->udp_dst),
extern flash_info_t flash_info[];
#endif
+/* 512 is poor choice for ethernet, MTU is typically 1500.
+ * Minus eth.hdrs thats 1468. Can get 2x better throughput with
+ * almost-MTU block sizes. At least try... fall back to 512 if need be.
+ */
+#define TFTP_MTU_BLOCKSIZE 1468
+static unsigned short TftpBlkSize=TFTP_BLOCK_SIZE;
+static unsigned short TftpBlkSizeOption=TFTP_MTU_BLOCKSIZE;
+
+#ifdef CONFIG_MCAST_TFTP
+#include <malloc.h>
+#define MTFTP_BITMAPSIZE 0x1000
+static unsigned *Bitmap;
+static int PrevBitmapHole,Mapsize=MTFTP_BITMAPSIZE;
+static uchar ProhibitMcast=0, MasterClient=0;
+static uchar Multicast=0;
+extern IPaddr_t Mcast_addr;
+static int Mcast_port;
+static ulong TftpEndingBlock; /* can get 'last' block before done..*/
+
+static void parse_multicast_oack(char *pkt,int len);
+
+static void
+mcast_cleanup(void)
+{
+ if (Mcast_addr) eth_mcast_join(Mcast_addr, 0);
+ if (Bitmap) free(Bitmap);
+ Bitmap=NULL;
+ Mcast_addr = Multicast = Mcast_port = 0;
+ TftpEndingBlock = -1;
+}
+
+#endif /* CONFIG_MCAST_TFTP */
+
static __inline__ void
store_block (unsigned block, uchar * src, unsigned len)
{
- ulong offset = block * TFTP_BLOCK_SIZE + TftpBlockWrapOffset;
+ ulong offset = block * TftpBlkSize + TftpBlockWrapOffset;
ulong newsize = offset + len;
#ifdef CFG_DIRECT_FLASH_TFTP
int i, rc = 0;
{
(void)memcpy((void *)(load_addr + offset), src, len);
}
+#ifdef CONFIG_MCAST_TFTP
+ if (Multicast)
+ ext2_set_bit(block, Bitmap);
+#endif
if (NetBootFileXferSize < newsize)
NetBootFileXferSize = newsize;
int len = 0;
volatile ushort *s;
+#ifdef CONFIG_MCAST_TFTP
+ /* Multicast TFTP.. non-MasterClients do not ACK data. */
+ if (Multicast
+ && (TftpState == STATE_DATA)
+ && (MasterClient == 0))
+ return;
+#endif
/*
* We will always be sending some sort of packet, so
* cobble together the packet headers now.
printf("send option \"timeout %s\"\n", (char *)pkt);
#endif
pkt += strlen((char *)pkt) + 1;
+ /* try for more effic. blk size */
+ pkt += sprintf((char *)pkt,"blksize%c%d%c",
+ 0,TftpBlkSizeOption,0);
+#ifdef CONFIG_MCAST_TFTP
+ /* Check all preconditions before even trying the option */
+ if (!ProhibitMcast
+ && (Bitmap=malloc(Mapsize))
+ && eth_get_dev()->mcast) {
+ free(Bitmap);
+ Bitmap=NULL;
+ pkt += sprintf((char *)pkt,"multicast%c%c",0,0);
+ }
+#endif /* CONFIG_MCAST_TFTP */
len = pkt - xp;
break;
- case STATE_DATA:
case STATE_OACK:
+#ifdef CONFIG_MCAST_TFTP
+ /* My turn! Start at where I need blocks I missed.*/
+ if (Multicast)
+ TftpBlock=ext2_find_next_zero_bit(Bitmap,(Mapsize*8),0);
+ /*..falling..*/
+#endif
+ case STATE_DATA:
xp = pkt;
s = (ushort *)pkt;
*s++ = htons(TFTP_ACK);
{
ushort proto;
ushort *s;
+ int i;
if (dest != TftpOurPort) {
+#ifdef CONFIG_MCAST_TFTP
+ if (Multicast
+ && (!Mcast_port || (dest != Mcast_port)))
+#endif
return;
}
if (TftpState != STATE_RRQ && src != TftpServerPort) {
#endif
TftpState = STATE_OACK;
TftpServerPort = src;
+ /*
+ * Check for 'blksize' option.
+ * Careful: "i" is signed, "len" is unsigned, thus
+ * something like "len-8" may give a *huge* number
+ */
+ for (i=0; i+8<len; i++) {
+ if (strcmp ((char*)pkt+i,"blksize") == 0) {
+ TftpBlkSize = (unsigned short)
+ simple_strtoul((char*)pkt+i+8,NULL,10);
+#ifdef ET_DEBUG
+ printf ("Blocksize ack: %s, %d\n",
+ (char*)pkt+i+8,TftpBlkSize);
+#endif
+ break;
+ }
+ }
+#ifdef CONFIG_MCAST_TFTP
+ parse_multicast_oack((char *)pkt,len-1);
+ if ((Multicast) && (!MasterClient))
+ TftpState = STATE_DATA; /* passive.. */
+ else
+#endif
TftpSend (); /* Send ACK */
break;
case TFTP_DATA:
*/
if (TftpBlock == 0) {
TftpBlockWrap++;
- TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
+ TftpBlockWrapOffset += TftpBlkSize * TFTP_SEQUENCE_SIZE;
printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20);
} else {
if (((TftpBlock - 1) % 10) == 0) {
TftpBlockWrap = 0;
TftpBlockWrapOffset = 0;
+#ifdef CONFIG_MCAST_TFTP
+ if (Multicast) { /* start!=1 common if mcast */
+ TftpLastBlock = TftpBlock - 1;
+ } else
+#endif
if (TftpBlock != 1) { /* Assertion */
printf ("\nTFTP error: "
"First block is not block 1 (%ld)\n"
* Acknoledge the block just received, which will prompt
* the server for the next one.
*/
+#ifdef CONFIG_MCAST_TFTP
+ /* if I am the MasterClient, actively calculate what my next
+ * needed block is; else I'm passive; not ACKING
+ */
+ if (Multicast) {
+ if (len < TftpBlkSize) {
+ TftpEndingBlock = TftpBlock;
+ } else if (MasterClient) {
+ TftpBlock = PrevBitmapHole =
+ ext2_find_next_zero_bit(
+ Bitmap,
+ (Mapsize*8),
+ PrevBitmapHole);
+ if (TftpBlock > ((Mapsize*8) - 1)) {
+ printf ("tftpfile too big\n");
+ /* try to double it and retry */
+ Mapsize<<=1;
+ mcast_cleanup();
+ NetStartAgain ();
+ return;
+ }
+ TftpLastBlock = TftpBlock;
+ }
+ }
+#endif
TftpSend ();
- if (len < TFTP_BLOCK_SIZE) {
+#ifdef CONFIG_MCAST_TFTP
+ if (Multicast) {
+ if (MasterClient && (TftpBlock >= TftpEndingBlock)) {
+ puts ("\nMulticast tftp done\n");
+ mcast_cleanup();
+ NetState = NETLOOP_SUCCESS;
+ }
+ }
+ else
+#endif
+ if (len < TftpBlkSize) {
/*
* We received the whole thing. Try to
* run it.
printf ("\nTFTP error: '%s' (%d)\n",
pkt + 2, ntohs(*(ushort *)pkt));
puts ("Starting again\n\n");
+#ifdef CONFIG_MCAST_TFTP
+ mcast_cleanup();
+#endif
NetStartAgain ();
break;
}
{
if (++TftpTimeoutCount > TIMEOUT_COUNT) {
puts ("\nRetry count exceeded; starting again\n");
+#ifdef CONFIG_MCAST_TFTP
+ mcast_cleanup();
+#endif
NetStartAgain ();
} else {
puts ("T ");
TftpState = STATE_RRQ;
/* Use a pseudo-random port unless a specific port is set */
TftpOurPort = 1024 + (get_timer(0) % 3072);
+
#ifdef CONFIG_TFTP_PORT
if ((ep = getenv("tftpdstp")) != NULL) {
TftpServerPort = simple_strtol(ep, NULL, 10);
/* zero out server ether in case the server ip has changed */
memset(NetServerEther, 0, 6);
+ /* Revert TftpBlkSize to dflt */
+ TftpBlkSize = TFTP_BLOCK_SIZE;
+#ifdef CONFIG_MCAST_TFTP
+ mcast_cleanup();
+#endif
TftpSend ();
}
+#ifdef CONFIG_MCAST_TFTP
+/* Credits: atftp project.
+ */
+
+/* pick up BcastAddr, Port, and whether I am [now] the master-client. *
+ * Frame:
+ * +-------+-----------+---+-------~~-------+---+
+ * | opc | multicast | 0 | addr, port, mc | 0 |
+ * +-------+-----------+---+-------~~-------+---+
+ * The multicast addr/port becomes what I listen to, and if 'mc' is '1' then
+ * I am the new master-client so must send ACKs to DataBlocks. If I am not
+ * master-client, I'm a passive client, gathering what DataBlocks I may and
+ * making note of which ones I got in my bitmask.
+ * In theory, I never go from master->passive..
+ * .. this comes in with pkt already pointing just past opc
+ */
+static void parse_multicast_oack(char *pkt, int len)
+{
+ int i;
+ IPaddr_t addr;
+ char *mc_adr, *port, *mc;
+
+ mc_adr=port=mc=NULL;
+ /* march along looking for 'multicast\0', which has to start at least
+ * 14 bytes back from the end.
+ */
+ for (i=0;i<len-14;i++)
+ if (strcmp (pkt+i,"multicast") == 0)
+ break;
+ if (i >= (len-14)) /* non-Multicast OACK, ign. */
+ return;
+
+ i+=10; /* strlen multicast */
+ mc_adr = pkt+i;
+ for (;i<len;i++) {
+ if (*(pkt+i) == ',') {
+ *(pkt+i) = '\0';
+ if (port) {
+ mc = pkt+i+1;
+ break;
+ } else {
+ port = pkt+i+1;
+ }
+ }
+ }
+ if (!port || !mc_adr || !mc ) return;
+ if (Multicast && MasterClient) {
+ printf ("I got a OACK as master Client, WRONG!\n");
+ return;
+ }
+ /* ..I now accept packets destined for this MCAST addr, port */
+ if (!Multicast) {
+ if (Bitmap) {
+ printf ("Internal failure! no mcast.\n");
+ free(Bitmap);
+ Bitmap=NULL;
+ ProhibitMcast=1;
+ return ;
+ }
+ /* I malloc instead of pre-declare; so that if the file ends
+ * up being too big for this bitmap I can retry
+ */
+ if (!(Bitmap = malloc (Mapsize))) {
+ printf ("No Bitmap, no multicast. Sorry.\n");
+ ProhibitMcast=1;
+ return;
+ }
+ memset (Bitmap,0,Mapsize);
+ PrevBitmapHole = 0;
+ Multicast = 1;
+ }
+ addr = string_to_ip(mc_adr);
+ if (Mcast_addr != addr) {
+ if (Mcast_addr)
+ eth_mcast_join(Mcast_addr, 0);
+ if (eth_mcast_join(Mcast_addr=addr, 1)) {
+ printf ("Fail to set mcast, revert to TFTP\n");
+ ProhibitMcast=1;
+ mcast_cleanup();
+ NetStartAgain();
+ }
+ }
+ MasterClient = (unsigned char)simple_strtoul((char *)mc,NULL,10);
+ Mcast_port = (unsigned short)simple_strtoul(port,NULL,10);
+ printf ("Multicast: %s:%d [%d]\n", mc_adr, Mcast_port, MasterClient);
+ return;
+}
+
+#endif /* Multicast TFTP */
+
#endif
--- /dev/null
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+LIB = libpostlwmon5.a
+
+COBJS = ecc.o
+
+include $(TOPDIR)/post/rules.mk
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Developed for DENX Software Engineering GmbH.
+ *
+ * Author: Pavel Kolesnikov <concord@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_ECC
+
+/*
+ * MEMORY ECC test
+ *
+ * This test performs the checks ECC facility of memory.
+ */
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <ppc440.h>
+
+#include "../../../board/lwmon5/sdram.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const static unsigned char syndrome_codes[] = {
+ 0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
+ 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
+ 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
+ 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
+ 0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
+ 0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
+ 0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
+ 0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
+ 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
+};
+
+#define ECC_START_ADDR 0x10
+#define ECC_STOP_ADDR 0x2000
+#define ECC_PATTERN 0x0101010101010101ull
+#define ECC_PATTERN_CORR 0x0101010101010100ull
+#define ECC_PATTERN_UNCORR 0x010101010101010Full
+
+static int test_ecc_error(void)
+{
+ unsigned long value;
+ unsigned long hdata, ldata, haddr, laddr;
+ unsigned int bit;
+
+ int ret = 0;
+
+ mfsdram(DDR0_23, value);
+
+ for (bit = 0; bit < sizeof(syndrome_codes); bit++)
+ if (syndrome_codes[bit] == ((value >> 16) & 0xff))
+ break;
+
+ mfsdram(DDR0_00, value);
+
+ if (value & DDR0_00_INT_STATUS_BIT0) {
+ debug("Bit0. A single access outside the defined PHYSICAL"
+ " memory space detected\n");
+ mfsdram(DDR0_32, laddr);
+ mfsdram(DDR0_33, haddr);
+ debug(" addr = 0x%08x%08x\n", haddr, laddr);
+ ret = 1;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT1) {
+ debug("Bit1. Multiple accesses outside the defined PHYSICAL"
+ " memory space detected\n");
+ ret = 2;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT2) {
+ debug("Bit2. Single correctable ECC event detected\n");
+ mfsdram(DDR0_38, laddr);
+ mfsdram(DDR0_39, haddr);
+ mfsdram(DDR0_40, ldata);
+ mfsdram(DDR0_41, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 3;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT3) {
+ debug("Bit3. Multiple correctable ECC events detected\n");
+ mfsdram(DDR0_38, laddr);
+ mfsdram(DDR0_39, haddr);
+ mfsdram(DDR0_40, ldata);
+ mfsdram(DDR0_41, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 4;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT4) {
+ debug("Bit4. Single uncorrectable ECC event detected\n");
+ mfsdram(DDR0_34, laddr);
+ mfsdram(DDR0_35, haddr);
+ mfsdram(DDR0_36, ldata);
+ mfsdram(DDR0_37, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 5;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT5) {
+ debug("Bit5. Multiple uncorrectable ECC events detected\n");
+ mfsdram(DDR0_34, laddr);
+ mfsdram(DDR0_35, haddr);
+ mfsdram(DDR0_36, ldata);
+ mfsdram(DDR0_37, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 6;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT6) {
+ debug("Bit6. DRAM initialization complete\n");
+ ret = 7;
+ }
+
+ /* error status cleared */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ return ret;
+}
+
+static int test_ecc(unsigned long ecc_addr)
+{
+ volatile unsigned long long *ecc_mem;
+ unsigned long value;
+ unsigned long ecc_data;
+ volatile unsigned long *lecc_mem;
+ int pret, ret = 0;
+
+ sync();
+ eieio();
+ WATCHDOG_RESET();
+
+ ecc_mem = (unsigned long long *)ecc_addr;
+ lecc_mem = (ulong *)ecc_addr;
+ *ecc_mem = ECC_PATTERN;
+ pret = test_ecc_error();
+ if (pret != 0)
+ ret = 1;
+
+ /* disconnect ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_DISABLE);
+
+ /* injecting error */
+ *ecc_mem = ECC_PATTERN_CORR;
+
+ /* enable ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+
+ ecc_data = *lecc_mem;
+ pret = test_ecc_error();
+ /* if read data ok, 1 correctable error must be fixed */
+ if (pret != 3)
+ ret = 1;
+
+ /* test for uncorrectable error */
+ /* disconnect from ecc storage */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_NO_ECC_RAM);
+
+ /* injecting multiply bit error */
+
+ *ecc_mem = ECC_PATTERN_UNCORR;
+
+ /* enable ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+
+ ecc_data = *lecc_mem;
+ /* what the data should be read? */
+
+ pret = test_ecc_error();
+ /* info about uncorrectable error must appear */
+ if (pret != 5)
+ ret = 1;
+
+ sync();
+ eieio();
+
+ return ret;
+}
+
+int ecc_post_test (int flags)
+{
+ int ret = 0;
+ unsigned long value;
+ unsigned long iaddr;
+
+#if CONFIG_DDR_ECC
+ sync();
+ eieio();
+
+ /* mask all int */
+ mfsdram(DDR0_01, value);
+ mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
+ | DDR0_01_INT_MASK_ALL_OFF);
+
+ /* clear error status */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ /* enable full support of ECC */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+
+ for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) {
+ ret = test_ecc(iaddr);
+ if (ret)
+ break;
+ }
+
+ /* clear error status */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ /*
+ * Clear possible errors resulting from ECC testing.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+#endif
+
+ return ret;
+
+}
+
+#endif /* CONFIG_POST & CFG_POST_ECC */
+#endif /* CONFIG_POST */
static int tlb = -1; /* index to the victim TLB entry */
+#ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
+#endif
int cache_post_test (int flags)
{
void* virt = (void*)CFG_POST_CACHE_ADDR;
- int ints, i, res = 0;
- u32 word0;
+ int ints;
+ int res = 0;
+
+ /*
+ * All 44x variants deal with cache management differently
+ * because they have the address translation always enabled.
+ * The 40x ppc's don't use address translation in U-Boot at all,
+ * so we have to distinguish here between 40x and 44x.
+ */
+#ifdef CONFIG_440
+ int word0, i;
if (tlb < 0) {
/*
}
}
}
+#endif
ints = disable_interrupts ();
WATCHDOG_RESET ();
.text
+ /*
+ * All 44x variants deal with cache management differently
+ * because they have the address translation always enabled.
+ * The 40x ppc's don't use address translation in U-Boot at all,
+ * so we have to distinguish here between 40x and 44x.
+ */
+#ifdef CONFIG_440
/* void cache_post_disable (int tlb)
*/
cache_post_disable:
sync
isync
blr
+#else
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+ lis r0, 0x0000
+ ori r0, r0, 0x0000
+ mtdccr r0
+ sync
+ isync
+ blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+ lis r0, 0x8000
+ ori r0, r0, 0x0000
+ mtdccr r0
+ lis r0, 0x8000
+ ori r0, r0, 0x0000
+ mtdcwr r0
+ sync
+ isync
+ blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+ lis r0, 0x8000
+ ori r0, r0, 0x0000
+ mtdccr r0
+ lis r0, 0x0000
+ ori r0, r0, 0x0000
+ mtdcwr r0
+ sync
+ isync
+ blr
+#endif
/* void cache_post_dinvalidate (void *p, int size)
*/
static void ether_post_init (int devnum, int hw_addr)
{
int i;
- unsigned mode_reg;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ unsigned mode_reg;
sys_info_t sysinfo;
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
/* set internal loopback mode */
+#ifdef CFG_POST_ETHER_EXT_LOOPBACK
+ out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+ in32 (EMAC_M1));
+#else
out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
EMAC_M1_MF_100MBPS | EMAC_M1_IST |
in32 (EMAC_M1));
+#endif
/* set transmit enable & receive enable */
out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
#if defined(CONFIG_440EP) || \
defined(CONFIG_440EPX)
-#include <ppc4xx.h>
#include <asm/processor.h>
+#include <ppc4xx.h>
int fpu_status(void)
#if CONFIG_POST & CFG_POST_UART
+/*
+ * This table defines the UART's that should be tested and can
+ * be overridden in the board config file
+ */
+#ifndef CFG_POST_UART_TABLE
+#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
+#endif
+
#include <asm/processor.h>
#include <serial.h>
+#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#else
+#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
+#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+#if defined(CONFIG_440GP)
+#define CR0_MASK 0x3fff0000
+#define CR0_EXTCLK_ENA 0x00600000
+#define CR0_UDIV_POS 16
+#define UDIV_SUBTRACT 1
+#define UART0_SDR cntrl0
+#define MFREG(a, d) d = mfdcr(a)
+#define MTREG(a, d) mtdcr(a, d)
+#else /* #if defined(CONFIG_440GP) */
+/* all other 440 PPC's access clock divider via sdr register */
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPe)
#define UART2_SDR sdr_uart2
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx)
#define UART3_SDR sdr_uart3
+#endif
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
+#endif /* #if defined(CONFIG_440GP) */
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define UCR0_MASK 0x0000007f
+#define UCR1_MASK 0x00007f00
+#define UCR0_UDIV_POS 0
+#define UCR1_UDIV_POS 8
+#define UDIV_MAX 127
+#else /* CONFIG_405GP || CONFIG_405CR */
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define CR0_MASK 0x00001fff
+#define CR0_EXTCLK_ENA 0x000000c0
+#define CR0_UDIV_POS 1
+#define UDIV_MAX 32
+#endif
#define UART_RBR 0x00
#define UART_THR 0x00
#define UART_DLM 0x01
/*
- Line Status Register.
-*/
+ * Line Status Register.
+ */
#define asyncLSRDataReady1 0x01
#define asyncLSROverrunError1 0x02
#define asyncLSRParityError1 0x04
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_440)
+#if !defined(CFG_EXT_SERIAL_CLOCK)
+static void serial_divs (int baudrate, unsigned long *pudiv,
+ unsigned short *pbdiv)
+{
+ sys_info_t sysinfo;
+ unsigned long div; /* total divisor udiv * bdiv */
+ unsigned long umin; /* minimum udiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
+ unsigned long i;
+ unsigned long est; /* current estimate */
+
+ get_sys_info(&sysinfo);
+
+ udiv = 32; /* Assume lowest possible serial clk */
+ div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
+ umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
+ diff = 32; /* highest possible */
+
+ /* i is the test udiv value -- start with the largest
+ * possible (32) to minimize serial clock and constrain
+ * search to umin.
+ */
+ for (i = 32; i > umin; i--) {
+ ibdiv = div / i;
+ est = i * ibdiv;
+ idiff = (est > div) ? (est-div) : (div-est);
+ if (idiff == 0) {
+ udiv = i;
+ break; /* can't do better */
+ } else if (idiff < diff) {
+ udiv = i; /* best so far */
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pudiv = udiv;
+ *pbdiv = div / udiv;
+}
+#endif
+
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg;
return 0;
}
+#else /* CONFIG_440 */
+
+static int uart_post_init (unsigned long dev_base)
+{
+ unsigned long reg;
+ unsigned long tmp;
+ unsigned long clk;
+ unsigned long udiv;
+ unsigned short bdiv;
+ volatile char val;
+ int i;
+
+ for (i = 0; i < 3500; i++) {
+ if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
+ break;
+ udelay (100);
+ }
+
+#if defined(CONFIG_405EZ)
+ serial_divs(gd->baudrate, &udiv, &bdiv);
+ clk = tmp = reg = 0;
+#else
+#ifdef CONFIG_405EP
+ reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
+ clk = gd->cpu_clk;
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
+ udiv = UDIV_MAX;
+ reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
+ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
+ mtdcr (cpc0_ucr, reg);
+#else /* CONFIG_405EP */
+ reg = mfdcr(cntrl0) & ~CR0_MASK;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ clk = CFG_EXT_SERIAL_CLOCK;
+ udiv = 1;
+ reg |= CR0_EXTCLK_ENA;
+#else
+ clk = gd->cpu_clk;
+#ifdef CFG_405_UART_ERRATA_59
+ udiv = 31; /* Errata 59: stuck at 31 */
+#else
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
+ udiv = UDIV_MAX;
+#endif
+#endif
+ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
+ mtdcr (cntrl0, reg);
+#endif /* CONFIG_405EP */
+ tmp = gd->baudrate * udiv * 16;
+ bdiv = (clk + tmp / 2) / tmp;
+#endif /* CONFIG_405EZ */
+
+ out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
+ out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
+ out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+ out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
+ out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
+ val = in8(dev_base + UART_LSR); /* clear line status */
+ val = in8(dev_base + UART_RBR); /* read receive buffer */
+ out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
+ out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
+
+ return (0);
+}
+#endif /* CONFIG_440 */
+
static void uart_post_putc (unsigned long dev_base, char c)
{
int i;
int uart_post_test (int flags)
{
int i, res = 0;
- static unsigned long base[] = {
- UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
- };
+ static unsigned long base[] = CFG_POST_UART_TABLE;
for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
if (test_ctlr (base[i], i))
unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
256 << 20 : bd->bi_memsize) - (1 << 20);
+ /* Limit area to be tested with the board info struct */
+ if (CFG_SDRAM_BASE + memsize > (ulong)bd)
+ memsize = (ulong)bd - CFG_SDRAM_BASE;
if (flags & POST_SLOWTEST) {
ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
extern int sysmon_post_test (int flags);
extern int dsp_post_test (int flags);
extern int codec_post_test (int flags);
+extern int ecc_post_test (int flags);
extern int sysmon_init_f (void);
CFG_POST_CODEC
},
#endif
+#if CONFIG_POST & CFG_POST_ECC
+ {
+ "ECC test",
+ "ecc",
+ "This test checks ECC facility of memory.",
+ POST_ROM | POST_ALWAYS,
+ &ecc_post_test,
+ NULL,
+ NULL,
+ CFG_POST_ECC
+ },
+#endif
};
unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
- mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
+ mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o \
+ mcfrtc.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE)
+
+#include <command.h>
+#include <rtc.h>
+#include <asm/immap.h>
+#include <asm/rtc.h>
+
+#undef RTC_DEBUG
+
+#ifndef CFG_MCFRTC_BASE
+#error RTC_BASE is not defined!
+#endif
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+#define STARTOFTIME 1970
+
+void rtc_get(struct rtc_time *tmp)
+{
+ volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
+
+ int rtc_days, rtc_hrs, rtc_mins;
+ int tim;
+
+ rtc_days = rtc->days;
+ rtc_hrs = rtc->hourmin >> 8;
+ rtc_mins = RTC_HOURMIN_MINUTES(rtc->hourmin);
+
+ tim = (rtc_days * 24) + rtc_hrs;
+ tim = (tim * 60) + rtc_mins;
+ tim = (tim * 60) + rtc->seconds;
+
+ to_tm(tim, tmp);
+
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+
+#ifdef RTC_DEBUG
+ printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+}
+
+void rtc_set(struct rtc_time *tmp)
+{
+ volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
+
+ static int month_days[12] = {
+ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+ };
+ int days, i, months;
+
+ if (tmp->tm_year > 2037) {
+ printf("Unable to handle. Exceeding integer limitation!\n");
+ tmp->tm_year = 2027;
+ }
+#ifdef RTC_DEBUG
+ printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+ /* calculate days by years */
+ for (i = STARTOFTIME, days = 0; i < tmp->tm_year; i++) {
+ days += 365 + isleap(i);
+ }
+
+ /* calculate days by months */
+ months = tmp->tm_mon - 1;
+ for (i = 0; i < months; i++) {
+ days += month_days[i];
+
+ if (i == 1)
+ days += isleap(i);
+ }
+
+ days += tmp->tm_mday - 1;
+
+ rtc->days = days;
+ rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min;
+ rtc->seconds = tmp->tm_sec;
+}
+
+void rtc_reset(void)
+{
+ volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
+
+ if ((rtc->cr & RTC_CR_EN) == 0) {
+ printf("real-time-clock was stopped. Now starting...\n");
+ rtc->cr |= RTC_CR_EN;
+ }
+
+ rtc->cr |= RTC_CR_SWR;
+}
+
+#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */
projects / people / ms / u-boot.git / commitdiff
