config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+
+config HAS_FSL_XHCI_USB
+ bool
+ default y if ARCH_LS1043A || ARCH_LS1046A
+ help
+ For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
+ pins, select it when the pins are assigned to USB.
unsigned int el = current_el();
void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
+ u32 *loadable_l, *loadable_h;
int ret;
#ifdef CONFIG_CHAIN_OF_TRUST
PPA_KEY_HASH,
&ppa_img_addr);
if (ret != 0)
- printf("PPA validation failed\n");
+ printf("SEC firmware(s) validation failed\n");
else
- printf("PPA validation Successful\n");
+ printf("SEC firmware(s) validation Successful\n");
}
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
+
+ /* Assign addresses to loadable ptrs */
+ loadable_l = &gur->scratchrw[4];
+ loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
+
+ /* Assign addresses to loadable ptrs */
+ loadable_l = &scfg->scratchrw[2];
+ loadable_h = &scfg->scratchrw[3];
#endif
debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
boot_loc_ptr_l, boot_loc_ptr_h);
- ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
+ ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
+ loadable_l, loadable_h);
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
return 0;
}
+/*
+ * SEC Firmware FIT image parser to check if any loadable is
+ * present. If present, verify integrity of the loadable and
+ * copy loadable to address provided in (loadable_h, loadable_l).
+ *
+ * Returns 0 on success and a negative errno on error task fail.
+ */
+static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
+ u32 *loadable_l, u32 *loadable_h)
+{
+ phys_addr_t sec_firmware_loadable_addr = 0;
+ int conf_node_off, ld_node_off;
+ char *conf_node_name = NULL;
+ const void *data;
+ size_t size;
+ ulong load;
+
+ conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
+
+ conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
+ if (conf_node_off < 0) {
+ printf("SEC Firmware: %s: no such config\n", conf_node_name);
+ return -ENOENT;
+ }
+
+ ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
+ FIT_LOADABLE_PROP);
+ if (ld_node_off >= 0) {
+ printf("SEC Firmware: '%s' present in config\n",
+ FIT_LOADABLE_PROP);
+
+ /* Verify secure firmware image */
+ if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
+ printf("SEC Loadable: Bad loadable image (bad CRC)\n");
+ return -EINVAL;
+ }
+
+ if (fit_image_get_data(sec_firmware_img, ld_node_off,
+ &data, &size)) {
+ printf("SEC Loadable: Can't get subimage data/size");
+ return -ENOENT;
+ }
+
+ /* Get load address, treated as load offset to secure memory */
+ if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) {
+ printf("SEC Loadable: Can't get subimage load");
+ return -ENOENT;
+ }
+
+ /* Compute load address for loadable in secure memory */
+ sec_firmware_loadable_addr = (sec_firmware_addr -
+ gd->arch.tlb_size) + load;
+
+ /* Copy loadable to secure memory and flush dcache */
+ debug("%s copied to address 0x%p\n",
+ FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr);
+ memcpy((void *)sec_firmware_loadable_addr, data, size);
+ flush_dcache_range(sec_firmware_loadable_addr,
+ sec_firmware_loadable_addr + size);
+ }
+
+ /* Populate address ptrs for loadable image with loadbale addr */
+ out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
+ out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
+
+ return 0;
+}
+
static int sec_firmware_copy_image(const char *title,
u64 image_addr, u32 image_size, u64 sec_firmware)
{
/*
* This function will parse the SEC Firmware image, and then load it
- * to secure memory.
+ * to secure memory. Also load any loadable if present along with SEC
+ * Firmware image.
*/
-static int sec_firmware_load_image(const void *sec_firmware_img)
+static int sec_firmware_load_image(const void *sec_firmware_img,
+ u32 *loadable_l, u32 *loadable_h)
{
const void *raw_image_addr;
size_t raw_image_size = 0;
if (ret)
goto out;
+ /*
+ * Check if any loadable are present along with firmware image, if
+ * present load them.
+ */
+ ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l,
+ loadable_h);
+ if (ret)
+ goto out;
+
sec_firmware_addr |= SEC_FIRMWARE_LOADED;
debug("SEC Firmware: Entry point: 0x%llx\n",
sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
* @sec_firmware_img: the SEC Firmware image address
* @eret_hold_l: the address to hold exception return address low
* @eret_hold_h: the address to hold exception return address high
+ * @loadable_l: the address to hold loadable address low
+ * @loadable_h: the address to hold loadable address high
*/
int sec_firmware_init(const void *sec_firmware_img,
u32 *eret_hold_l,
- u32 *eret_hold_h)
+ u32 *eret_hold_h,
+ u32 *loadable_l,
+ u32 *loadable_h)
{
int ret;
if (!sec_firmware_is_valid(sec_firmware_img))
return -EINVAL;
- ret = sec_firmware_load_image(sec_firmware_img);
+ ret = sec_firmware_load_image(sec_firmware_img, loadable_l,
+ loadable_h);
if (ret) {
printf("SEC Firmware: Failed to load image\n");
return ret;
num-cs = <4>;
};
+ usb0: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
* Reserve secure memory
* To be aligned with MMU block size
*/
-#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
+#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define PSCI_INVALID_VER 0xffffffff
#define SEC_JR3_OFFSET 0x40000
+#define WORD_MASK 0xffffffff
+#define WORD_SHIFT 32
-int sec_firmware_init(const void *, u32 *, u32 *);
+int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
bool sec_firmware_support_hwrng(void);
mtspr SPRN_PIR,r4 /* write to PIR register */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+ mfspr r8, L1CSR2
+ clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
+ mtspr L1CSR2, r8
+#else
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
slwi r8,r4,1
addi r8,r8,32
mtspr L1CSR2,r8
#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
ls1088a_handle_phy_interface_rgmii(i);
break;
case PHY_INTERFACE_MODE_QSGMII:
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
* Initialize the global default MC portal
* And check that the MC firmware is responding portal commands:
*/
- root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
if (!root_mc_io) {
- printf(" No memory: malloc() failed\n");
+ printf(" No memory: calloc() failed\n");
return -ENOMEM;
}
struct dpio_cfg dpio_cfg;
int err = 0;
- dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
+ dflt_dpio = (struct fsl_dpio_obj *)calloc(
+ sizeof(struct fsl_dpio_obj), 1);
if (!dflt_dpio) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_create:
free(dflt_dpio);
-err_malloc:
+err_calloc:
return err;
}
goto err_create;
}
- dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
if (!dflt_mc_io) {
err = -ENOMEM;
- printf(" No memory: malloc() failed\n");
- goto err_malloc;
+ printf(" No memory: calloc() failed\n");
+ goto err_calloc;
}
child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
return 0;
err_child_open:
free(dflt_mc_io);
-err_malloc:
+err_calloc:
dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
root_dprc_handle, child_dprc_id);
err_create:
struct dpbp_attr dpbp_attr;
struct dpbp_cfg dpbp_cfg;
- dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
+ dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
+ sizeof(struct fsl_dpbp_obj), 1);
if (!dflt_dpbp) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
dpbp_cfg.options = 512;
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
err_create:
-err_malloc:
+err_calloc:
return err;
}
struct dpni_extended_cfg dpni_extended_cfg;
struct dpni_cfg dpni_cfg;
- dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
+ dflt_dpni = (struct fsl_dpni_obj *)calloc(
+ sizeof(struct fsl_dpni_obj), 1);
if (!dflt_dpni) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
err_create:
err_prepare_extended_cfg:
free(dflt_dpni);
-err_malloc:
+err_calloc:
return err;
}
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
if (!ec)
- wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+ wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
#endif
#ifdef CONFIG_SYS_FSL_EC2
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
if (!ec)
- wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+ wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
#endif
}
#endif
Select the DRA7XX xHCI USB index.
Current supported values: 0, 1.
+config USB_XHCI_FSL
+ bool "Support for NXP Layerscape on-chip xHCI USB controller"
+ default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
+ depends on !SPL_NO_USB
+ help
+ Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
endif # USB_XHCI_HCD
config USB_EHCI_HCD
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS
"kernel_load=0x96000000\0" \
"kernel_size=0x2800000\0"
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-/*XHCI Support - enabled by default*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
/*
* I2C IO expander
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-/* XHCI Support - enabled by default */
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-/*XHCI Support - enabled by default*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
/*
* Video
*/
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-/* XHCI Support - enabled by default */
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#endif
#endif
-/* USB */
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-
/*
* Miscellaneous configurable options
*/
#endif
#endif
-/* USB */
-#ifndef SPL_NO_USB
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-#endif
-
/* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_LIBATA
#define CFG_LPUART_EN 0x2
#endif
-/* USB */
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#endif
#endif
-/* USB */
-#ifndef SPL_NO_USB
-#define CONFIG_HAS_FSL_XHCI_USB
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#endif
-#endif
-
/* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_LIBATA
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_DISPLAY_BOARDINFO_LATE
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS2_QDS_H */
#define CONFIG_MISC_INIT_R
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
CONFIG_HAS_FEC
CONFIG_HAS_FSL_DR_USB
CONFIG_HAS_FSL_MPH_USB
-CONFIG_HAS_FSL_XHCI_USB
CONFIG_HAS_POST
CONFIG_HCLK_FREQ
CONFIG_HDBOOT
CONFIG_USB_TUSB_OMAP_DMA
CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
-CONFIG_USB_XHCI_FSL
CONFIG_USB_XHCI_KEYSTONE
CONFIG_USB_XHCI_OMAP
CONFIG_USER_LOWLEVEL_INIT