.text
.global _start
_start:
+ /*
+ * reserve registers:
+ * r10: Stores little/big endian offset for vectors
+ * r2: Stores imm opcode
+ * r3: Stores brai opcode
+ */
+
mts rmsr, r0 /* disable cache */
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
*/
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
- swi r6, r0, 0
- lbui r10, r0, 0
- swi r6, r0, 0x40
- swi r10, r0, 0x50
-
- /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
- addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
- swi r6, r0, 0x0 /* reset address */
- swi r6, r0, 0x8 /* user vector exception */
- swi r6, r0, 0x10 /* interrupt */
- swi r6, r0, 0x20 /* hardware exception */
-
- addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
- swi r6, r0, 0x4 /* reset address */
- swi r6, r0, 0xC /* user vector exception */
- swi r6, r0, 0x14 /* interrupt */
- swi r6, r0, 0x24 /* hardware exception */
+ lwi r7, r0, 0x28
+ swi r6, r0, 0x28 /* used first unused MB vector */
+ lbui r10, r0, 0x28 /* used first unused MB vector */
+ swi r7, r0, 0x28
+
+ /* add opcode instruction for 32bit jump - 2 instruction imm & brai */
+ addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
+ addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
#ifdef CONFIG_SYS_RESET_ADDRESS
/* reset address */
+ swi r2, r0, 0x0 /* reset address - imm opcode */
+ swi r3, r0, 0x4 /* reset address - brai opcode */
+
addik r6, r0, CONFIG_SYS_RESET_ADDRESS
sw r6, r1, r0
- lhu r7, r1, r0
- shi r7, r0, 0x2
- shi r6, r0, 0x6
-/*
- * Copy U-Boot code to CONFIG_SYS_TEXT_BASE
- * solve problem with sbrk_base
- */
-#if (CONFIG_SYS_RESET_ADDRESS != CONFIG_SYS_TEXT_BASE)
- addi r4, r0, __end
- addi r5, r0, __text_start
- rsub r4, r5, r4 /* size = __end - __text_start */
- addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */
- addi r7, r0, 0 /* counter */
-4:
- lw r8, r6, r7
- sw r8, r5, r7
- addi r7, r7, 0x4
- cmp r8, r4, r7
- blti r8, 4b
-#endif
+ lhu r7, r1, r10
+ rsubi r8, r10, 0x2
+ sh r7, r0, r8
+ rsubi r8, r10, 0x6
+ sh r6, r0, r8
#endif
#ifdef CONFIG_SYS_USR_EXCEP
/* user_vector_exception */
+ swi r2, r0, 0x8 /* user vector exception - imm opcode */
+ swi r3, r0, 0xC /* user vector exception - brai opcode */
+
addik r6, r0, _exception_handler
sw r6, r1, r0
/*
#ifdef CONFIG_SYS_INTC_0
/* interrupt_handler */
+ swi r2, r0, 0x10 /* interrupt - imm opcode */
+ swi r3, r0, 0x14 /* interrupt - brai opcode */
+
addik r6, r0, _interrupt_handler
sw r6, r1, r0
lhu r7, r1, r10
#endif
/* hardware exception */
+ swi r2, r0, 0x20 /* hardware exception - imm opcode */
+ swi r3, r0, 0x24 /* hardware exception - brai opcode */
+
addik r6, r0, _hw_exception_handler
sw r6, r1, r0
lhu r7, r1, r10
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
-typedef struct {
- u32 baseaddress; /* Base address for device (IPIF) */
+struct xemaclite {
u32 nexttxbuffertouse; /* Next TX buffer to write to */
u32 nextrxbuffertouse; /* Next RX buffer to read from */
- uchar deviceid; /* Unique ID of device - for future */
-} xemaclite;
-
-static xemaclite emaclite;
+};
static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
debug ("EmacLite Initialization Started\n");
- memset (&emaclite, 0, sizeof (xemaclite));
- emaclite.baseaddress = dev->iobase;
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
+ out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
/* Copy MAC address */
xemaclite_alignedwrite (dev->enetaddr,
- emaclite.baseaddress, ENET_ADDR_LENGTH);
+ dev->iobase, ENET_ADDR_LENGTH);
/* Set the length */
- out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
/* Update the MAC address in the EMAC Lite */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
+ out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
/* Wait for EMAC Lite to finish with the MAC address update */
- while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
- XEL_TSR_PROG_MAC_ADDR) != 0) ;
+ while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
+ XEL_TSR_PROG_MAC_ADDR) != 0)
+ ;
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
/* The same operation with PONG TX */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
- xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress +
+ out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
+ xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
- out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
+ out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_TSR_PROG_MAC_ADDR);
- while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
- XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
+ while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
+ XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
+ ;
#endif
/*
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
- out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
+ out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
+ out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_RSR_RECV_IE_MASK);
#endif
return 0;
}
-static int xemaclite_txbufferavailable (xemaclite *instanceptr)
+static int xemaclite_txbufferavailable(struct eth_device *dev)
{
u32 reg;
u32 txpingbusy;
u32 txpongbusy;
+ struct xemaclite *emaclite = dev->priv;
+
/*
* Read the other buffer register
* and determine if the other buffer is available
*/
- reg = in_be32 (instanceptr->baseaddress +
- instanceptr->nexttxbuffertouse + 0);
+ reg = in_be32 (dev->iobase +
+ emaclite->nexttxbuffertouse + 0);
txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
- reg = in_be32 (instanceptr->baseaddress +
- (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
+ reg = in_be32 (dev->iobase +
+ (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
{
u32 reg;
u32 baseaddress;
+ struct xemaclite *emaclite = dev->priv;
u32 maxtry = 1000;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
- while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
+ while (!xemaclite_txbufferavailable(dev) && maxtry) {
udelay (10);
maxtry--;
}
if (!maxtry) {
printf ("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
+ out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
+ out_be32 (dev->iobase + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET, 0);
#endif
return -1;
}
/* Determine the expected TX buffer address */
- baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
+ baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
+ emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
#endif
debug ("Send packet from 0x%x\n", baseaddress);
/* Write the frame to the buffer */
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
- debug ("Send packet from 0x%x\n", baseaddress);
+ debug("Send packet from 0x%x\n", baseaddress);
/* Write the frame to the buffer */
xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
u32 length;
u32 reg;
u32 baseaddress;
+ struct xemaclite *emaclite = dev->priv;
- baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
+ baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
debug ("Testing data at address 0x%x\n", baseaddress);
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
+ emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
#endif
} else {
#ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG
int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
{
struct eth_device *dev;
+ struct xemaclite *emaclite;
- dev = malloc(sizeof(*dev));
+ dev = calloc(1, sizeof(*dev));
if (dev == NULL)
return -1;
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "Xilinx_Emaclite");
+ emaclite = calloc(1, sizeof(struct xemaclite));
+ if (emaclite == NULL) {
+ free(dev);
+ return -1;
+ }
+
+ dev->priv = emaclite;
+
+ sprintf(dev->name, "Xelite.%x", base_addr);
dev->iobase = base_addr;
- dev->priv = 0;
dev->init = emaclite_init;
dev->halt = emaclite_halt;
dev->send = emaclite_send;
projects / people / ms / u-boot.git / commitdiff
