clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c

Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index baa60a52e6877484ac7cb24ae3b2466fb5f9c10a..f6644ee6d16f881be63a6f9661f15a25152942e0 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -46,6 +46,14 @@ config CLK_BOSTON
        help
          Enable this to support the clocks
 
+config CLK_STM32F
+       bool "Enable clock driver support for STM32F family"
+       depends on CLK && (STM32F7 || STM32F4)
+       default y
+       help
+         This clock driver adds support for RCC clock management
+         for STM32F4 and STM32F7 SoCs.
+
 config CLK_ZYNQ
        bool "Enable clock driver support for Zynq"
        depends on CLK && ARCH_ZYNQ

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 83fe88ce9f516bc88960032889922dffc5584faa..bcc8f82fb65db2c3e12df6331a2810876971b13d 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -21,5 +21,5 @@ obj-$(CONFIG_CLK_AT91) += at91/
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_STM32F7) += clk_stm32f7.o
+obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_STM32H7) += clk_stm32h7.o

diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f.c
similarity index 98%
rename from drivers/clk/clk_stm32f7.c
rename to drivers/clk/clk_stm32f.c
index 4c69740f73e4e80026ad91abd6f069113c3e1174..10f44859cda1ae169d3720b1abd40741b5100a2f 100644 (file)
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f.c
@@ -197,6 +197,7 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
        struct stm32_rcc_regs *regs = priv->base;
        u32 sysclk = 0;
        u32 shift = 0;
+       u16 pllm, plln, pllp;
        /* Prescaler table lookups for clock computation */
        u8 ahb_psc_table[16] = {
                0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
@@ -207,7 +208,6 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
 
        if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
                        RCC_CFGR_SWS_PLL) {
-               u16 pllm, plln, pllp;
                pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
                plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
                        >> RCC_PLLCFGR_PLLN_SHIFT);
@@ -228,25 +228,21 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
                        (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
                        >> RCC_CFGR_HPRE_SHIFT)];
                return sysclk >>= shift;
-               break;
        /* APB1 CLOCK */
        case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
                shift = apb_psc_table[(
                        (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
                        >> RCC_CFGR_PPRE1_SHIFT)];
                return sysclk >>= shift;
-               break;
        /* APB2 CLOCK */
        case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
                shift = apb_psc_table[(
                        (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
                        >> RCC_CFGR_PPRE2_SHIFT)];
                return sysclk >>= shift;
-               break;
        default:
                pr_err("clock index %ld out of range\n", clk->id);
                return -EINVAL;
-               break;
        }
 }
 
@@ -288,7 +284,7 @@ static int stm32_clk_probe(struct udevice *dev)
        struct ofnode_phandle_args args;
        int err;
 
-       debug("%s: stm32_clk_probe\n", __func__);
+       debug("%s\n", __func__);
 
        struct stm32_clk *priv = dev_get_priv(dev);
        fdt_addr_t addr;
@@ -346,8 +342,8 @@ static const struct udevice_id stm32_clk_ids[] = {
        {}
 };
 
-U_BOOT_DRIVER(stm32f7_clk) = {
-       .name                   = "stm32f7_clk",
+U_BOOT_DRIVER(stm32fx_clk) = {
+       .name                   = "stm32fx_clk",
        .id                     = UCLASS_CLK,
        .of_match               = stm32_clk_ids,
        .ops                    = &stm32_clk_ops,