mips: bmips: add bcm63xx-spi driver support for BCM6348

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
index 711b643b5a44817d28214ab2e102f3b185f2febb..540b9fea5ba9901f025ec87be5dbba513d3ec161 100644 (file)
--- a/arch/mips/dts/brcm,bcm6348.dtsi
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -12,6 +12,10 @@
 / {
        compatible = "brcm,bcm6348";
 
+       aliases {
+               spi0 = &spi;
+       };
+
        cpus {
                reg = <0xfffe0000 0x4>;
                #address-cells = <1>;
@@ -118,6 +122,19 @@
                        status = "disabled";
                };
 
+               spi: spi@fffe0c00 {
+                       compatible = "brcm,bcm6348-spi";
+                       reg = <0xfffe0c00 0xc0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&periph_clk BCM6348_CLK_SPI>;
+                       resets = <&periph_rst BCM6348_RST_SPI>;
+                       spi-max-frequency = <20000000>;
+                       num-cs = <4>;
+
+                       status = "disabled";
+               };
+
                memory-controller@fffe2300 {
                        compatible = "brcm,bcm6338-mc";
                        reg = <0xfffe2300 0x38>;