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[thirdparty/gcc.git] / gcc / config / riscv / riscv.h

3 days ago	Kito Cheng	RISC-V: Support -march=unset	blob \| commitdiff \| raw
2025-06-19	Dongyan Chen	RISC-V: Add generic tune as default.	blob \| commitdiff \| raw \| diff to current
2025-04-16	Kito Cheng	RISC-V: Put jump table in text for large code model	blob \| commitdiff \| raw \| diff to current
2025-01-17	Monk Chiang	RISC-V: Add -fcf-protection=[full\|branch\|return] to...	blob \| commitdiff \| raw \| diff to current
2025-01-17	Monk Chiang	RISC-V: Add Zicfilp ISA extension.	blob \| commitdiff \| raw \| diff to current
2025-01-17	Monk Chiang	RISC-V: Add Zicfiss ISA extension.	blob \| commitdiff \| raw \| diff to current
2025-01-02	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2024-12-17	Kito Cheng	RISC-V: Add cr and cf constraint	blob \| commitdiff \| raw \| diff to current
2024-12-06	Hau Hsu	RISC-V: Add --with-cmodel configure option	blob \| commitdiff \| raw \| diff to current
2024-11-13	Yangyu Chen	RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P	blob \| commitdiff \| raw \| diff to current
2024-11-13	Yangyu Chen	Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V	blob \| commitdiff \| raw \| diff to current
2024-10-09	Jovan Vukic	RISC-V: Optimize branches with shifted immediate operands	blob \| commitdiff \| raw \| diff to current
2024-10-08	Palmer Dabbelt	[RISC-V][PR target/116615] RISC-V: Use default LOGICAL_...	blob \| commitdiff \| raw \| diff to current
2024-09-24	Yixuan Chen	[PATCH] RISC-V: Fix FIXED_REGISTERS comment missing...	blob \| commitdiff \| raw \| diff to current
2024-08-09	Raphael Moreira...	RISC-V: Enable stack clash in alloca	blob \| commitdiff \| raw \| diff to current
2024-08-09	Raphael Moreira...	RISC-V: Add support to vector stack-clash protection	blob \| commitdiff \| raw \| diff to current
2024-08-09	Raphael Moreira...	RISC-V: Stack-clash protection implemention	blob \| commitdiff \| raw \| diff to current
2024-08-08	Jin Ma	RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'	blob \| commitdiff \| raw \| diff to current
2024-06-25	Kewen Lin	Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook...	blob \| commitdiff \| raw \| diff to current
2024-06-05	Robin Dapp	RISC-V: Introduce -mvector-strict-align.	blob \| commitdiff \| raw \| diff to current
2024-05-21	Vineet Gupta	RISC-V: avoid LUI based const mat in prologue/epilogue...	blob \| commitdiff \| raw \| diff to current
2024-05-14	Vineet Gupta	RISC-V: avoid LUI based const materialization ... ...	blob \| commitdiff \| raw \| diff to current
2024-05-03	Vineet Gupta	RISC-V: miscll comment fixes [NFC]	blob \| commitdiff \| raw \| diff to current
2024-04-11	Pan Li	RISC-V: Bugfix ICE for the vector return arg in mode...	blob \| commitdiff \| raw \| diff to current
2024-04-08	Tatsuyuki Ishi	RISC-V: Implement TLS Descriptors.	blob \| commitdiff \| raw \| diff to current
2024-03-28	Palmer Dabbelt	RISC-V: Add vxsat as a register	blob \| commitdiff \| raw \| diff to current
2024-02-16	Kito Cheng	RISC-V: Add new option -march=help to print all support...	blob \| commitdiff \| raw \| diff to current
2024-02-05	Monk Chiang	RISC-V: Support scheduling for sifive p400 series	blob \| commitdiff \| raw \| diff to current
2024-02-01	Monk Chiang	RISC-V: Support scheduling for sifive p600 series	blob \| commitdiff \| raw \| diff to current
2024-01-18	Jun Sha (Joshua)	RISC-V: Adds the prefix "th." for the instructions...	blob \| commitdiff \| raw \| diff to current
2024-01-16	Yanzhang Wang	RISC-V: delete all the vector psabi checking.	blob \| commitdiff \| raw \| diff to current
2024-01-10	Jin Ma	RISC-V: T-HEAD: Add support for the XTheadInt ISA extension	blob \| commitdiff \| raw \| diff to current
2024-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2023-11-27	Tsukasa OI	RISC-V: Initial RV64E and LP64E support	blob \| commitdiff \| raw \| diff to current
2023-11-16	Kito Cheng	RISC-V: Implement target attribute	blob \| commitdiff \| raw \| diff to current
2023-10-31	Christoph Müllner	riscv: thead: Add support for the XTheadFMemIdx ISA...	blob \| commitdiff \| raw \| diff to current
2023-10-31	Christoph Müllner	riscv: thead: Add support for the XTheadMemIdx ISA...	blob \| commitdiff \| raw \| diff to current
2023-10-13	Kito Cheng	RISC-V: Fix the riscv_legitimize_poly_move issue on...	blob \| commitdiff \| raw \| diff to current
2023-10-10	Andrew Waterman	RISC-V: far-branch: Handle far jumps and branches for...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Lehua Ding	RISC-V: Part-3: Output .variant_cc directive for vector...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Lehua Ding	RISC-V: Part-2: Save/Restore vector registers which...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Lehua Ding	RISC-V: Part-1: Select suitable vector registers for...	blob \| commitdiff \| raw \| diff to current
2023-08-30	Fei Gao	RISC-V: support cm.push cm.pop cm.popret in zcmp	blob \| commitdiff \| raw \| diff to current
2023-08-29	Edwin Lu	RISC-V: generate builtin macro for compilation with...	blob \| commitdiff \| raw \| diff to current
2023-08-14	Jiawei	RISC-V: Enable compressible features when use ZC* exten...	blob \| commitdiff \| raw \| diff to current
2023-08-10	Pan Li	RISC-V: Refactor RVV frm_mode attr for rounding mode...	blob \| commitdiff \| raw \| diff to current
2023-07-20	Juzhe-Zhong	RISC-V: Refactor RVV machine modes	blob \| commitdiff \| raw \| diff to current
2023-07-12	Christoph Müllner	riscv: Prepare backend for index registers	blob \| commitdiff \| raw \| diff to current
2023-07-12	Christoph Müllner	riscv: Define Xmode macro	blob \| commitdiff \| raw \| diff to current
2023-06-29	Pan Li	RISC-V: Support vfadd static rounding mode by mode...	blob \| commitdiff \| raw \| diff to current
2023-06-13	Yanzhang Wang	RISC-V: Add vector psabi checking.	blob \| commitdiff \| raw \| diff to current
2023-05-29	Pan Li	RISC-V: Using merge approach to optimize repeating...	blob \| commitdiff \| raw \| diff to current
2023-05-17	Jin Ma	RISC-V: Remove trailing spaces on lines.	blob \| commitdiff \| raw \| diff to current
2023-05-17	Juzhe-Zhong	RISC-V: Add mode switching target hook to insert roundi...	blob \| commitdiff \| raw \| diff to current
2023-05-16	Juzhe-Zhong	RISC-V: Add FRM and rounding mode operand into floating...	blob \| commitdiff \| raw \| diff to current
2023-05-15	Juzhe-Zhong	RISC-V: Add rounding mode operand for fixed-point patterns	blob \| commitdiff \| raw \| diff to current
2023-05-05	Pan Li	RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to...	blob \| commitdiff \| raw \| diff to current
2023-04-20	Juzhe-Zhong	RISC-V: Fix RVV register order	blob \| commitdiff \| raw \| diff to current
2023-03-23	Pan Li	RISC-V: Bugfix for rvv bool mode size adjustment	blob \| commitdiff \| raw \| diff to current
2023-03-07	Pan Li	RISC-V: Bugfix for rvv bool mode precision adjustment	blob \| commitdiff \| raw \| diff to current
2023-02-13	Kito Cheng	RISC-V: Handle vlenb correctly in unwinding	blob \| commitdiff \| raw \| diff to current
2023-02-12	Ju-Zhe Zhong	RISC-V: Add integer widening instructions	blob \| commitdiff \| raw \| diff to current
2023-02-10	Ju-Zhe Zhong	RISC-V: Add binary vx C/C++ support	blob \| commitdiff \| raw \| diff to current
2023-02-03	Monk Chiang	RISC-V: Remove unnecessary register class.	blob \| commitdiff \| raw \| diff to current
2023-01-02	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2022-12-01	Ju-Zhe Zhong	RISC-V: Add duplicate vector support.	blob \| commitdiff \| raw \| diff to current
2022-11-18	Philipp Tomsich	RISC-V: Use bseti/bclri/binvi to extend reach of ori...	blob \| commitdiff \| raw \| diff to current
2022-11-11	Ju-Zhe Zhong	RISC-V: Add RVV registers register spilling	blob \| commitdiff \| raw \| diff to current
2022-10-26	Ju-Zhe Zhong	RISC-V: ADJUST_NUNITS according to -march.	blob \| commitdiff \| raw \| diff to current
2022-10-26	Ju-Zhe Zhong	RISC-V: Support load/store in mov<mode> pattern for...	blob \| commitdiff \| raw \| diff to current
2022-10-24	Ju-Zhe Zhong	RISC-V: Fix REG_CLASS_CONTENTS.	blob \| commitdiff \| raw \| diff to current
2022-10-05	Ju-Zhe Zhong	RISC-V: Introduce RVV header to enable builtin types	blob \| commitdiff \| raw \| diff to current
2022-09-23	Vineet Gupta	RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand	blob \| commitdiff \| raw \| diff to current
2022-09-02	Iain Buclaw	d: Fix #error You must define PREFERRED_DEBUGGING_TYPE...	blob \| commitdiff \| raw \| diff to current
2022-09-02	Kito Cheng	RISC-V: Implement TARGET_COMPUTE_MULTILIB	blob \| commitdiff \| raw \| diff to current
2022-09-01	zhongjuzhe	RISC-V: Fix comment in riscv.h	blob \| commitdiff \| raw \| diff to current
2022-09-01	zhongjuzhe	RISC-V: Fix riscv_vector_chunks configuration according...	blob \| commitdiff \| raw \| diff to current
2022-08-29	zhongjuzhe	RISC-V: Add RVV registers	blob \| commitdiff \| raw \| diff to current
2022-08-24	Andrew Pinski	[RISCV] Fix PR 106586: riscv32 vs ZBS	blob \| commitdiff \| raw \| diff to current
2022-08-18	zhongjuzhe	RISC-V: Add runtime invariant support	blob \| commitdiff \| raw \| diff to current
2022-06-02	Philipp Tomsich	RISC-V: bitmanip: improve constant-loading for (1ULL...	blob \| commitdiff \| raw \| diff to current
2022-05-23	Vineet Gupta	RISC-V: Enable TARGET_SUPPORTS_WIDE_INT	blob \| commitdiff \| raw \| diff to current
2022-05-13	Philipp Tomsich	RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO	blob \| commitdiff \| raw \| diff to current
2022-02-05	Kito Cheng	RISC-V: Always pass -misa-spec to assembler [PR104219]	blob \| commitdiff \| raw \| diff to current
2022-01-17	Martin Liska	Change references of .c files to .cc files	blob \| commitdiff \| raw \| diff to current
2022-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2021-10-25	Jim Wilson	RISC-V: Implement instruction patterns for ZBS extension.	blob \| commitdiff \| raw \| diff to current
2021-05-25	Kito Cheng	RISC-V: Pass -mno-relax to assembler	blob \| commitdiff \| raw \| diff to current
2021-04-30	LevyHsu	RISC-V: Add patterns for builtin overflow.	blob \| commitdiff \| raw \| diff to current
2021-04-14	Iain Buclaw	d: Add TARGET_D_REGISTER_CPU_TARGET_INFO	blob \| commitdiff \| raw \| diff to current
2021-03-23	Marcus Comstedt	RISC-V: Add riscv{32,64}be with big endian as default	blob \| commitdiff \| raw \| diff to current
2021-03-23	Marcus Comstedt	RISC-V: Support -mlittle-endian and -mbig-endian	blob \| commitdiff \| raw \| diff to current
2021-01-04	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2020-11-30	Kito Cheng	RISC-V: Always define MULTILIB_DEFAULTS	blob \| commitdiff \| raw \| diff to current
2020-11-18	Kito Cheng	RISC-V: Support version controling for ISA standard...	blob \| commitdiff \| raw \| diff to current
2020-11-14	Monk Chiang	PR target/97682 - Fix to reuse t1 register between...	blob \| commitdiff \| raw \| diff to current
2020-10-15	Kito Cheng	RISC-V: Add support for -mcpu option.	blob \| commitdiff \| raw \| diff to current
2020-09-17	Yeting Kuo	RISC-V: fix a typo in riscv.h	blob \| commitdiff \| raw \| diff to current
2020-06-22	Kito Cheng	RISC-V: Normalize arch string in driver time	blob \| commitdiff \| raw \| diff to current
2020-05-19	Kito Cheng	RISC-V: Handle implied extension for -march parser.	blob \| commitdiff \| raw \| diff to current
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