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3 hours ago	Jennifer Schmitz	aarch64: Force vector in SVE gimple_folder::fold_active...	tree \| commitdiff
8 hours ago	Jiawei	RISC-V: Allow profiles input in '--with-arch' option.	tree \| commitdiff
8 hours ago	Jiawei	RISC-V: Configure Profiles definitions in the definitio...	tree \| commitdiff
8 hours ago	Dongyan Chen	RISC-V: Imply zicsr for sdtrig and ssstrict extensions.	tree \| commitdiff
10 hours ago	liuhongt	Optimize vpermpd to vbroadcastf128 for specific permuta...	tree \| commitdiff
13 hours ago	Alexandre Oliva	[ppc] [vxworks] allow code model selection	tree \| commitdiff
23 hours ago	Georg-Johann Lay	AVR: Support AVR32EB14/20/28/32.	tree \| commitdiff
24 hours ago	H.J. Lu	x86: Don't align destination for a single instruction	tree \| commitdiff
25 hours ago	Xi Ruoyao	LoongArch: Fix wrong code from bstrpick split	tree \| commitdiff
4 days ago	Tamar Christina	Aarch64: Add support for addhn vectorizer optabs for...	tree \| commitdiff
5 days ago	Wilco Dijkstra	AArch64: Add isfinite expander [PR 66462]	tree \| commitdiff
5 days ago	Xi Ruoyao	LoongArch: Fix the semantic of 16B CAS	tree \| commitdiff
5 days ago	Xi Ruoyao	LoongArch: Fix the "%t" modifier handling for (const_int 0)	tree \| commitdiff
5 days ago	Tsukasa OI	RISC-V: Suppress cross CC sibcall optimization from...	tree \| commitdiff
5 days ago	Robin Dapp	RISC-V: Add min/max patterns for ifcvt.	tree \| commitdiff
5 days ago	Kito Cheng	RISC-V: Fix can_find_related_mode_p for VLS types	tree \| commitdiff
5 days ago	Takayuki 'January...	xtensa: Correct a typo	tree \| commitdiff
5 days ago	Peter Bergner	RISC-V: Fix typo in tt-ascalon-d8's pipeline descriptio...	tree \| commitdiff
5 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar single widening...	tree \| commitdiff
6 days ago	Juergen Christ	s390: Implement clz and ctz for SI mode	tree \| commitdiff
6 days ago	Maximilian Immanue...	s390: fix vec_extract_plus define insn	tree \| commitdiff
6 days ago	Andrew Stubbs	amdgcn: fix GFX10/GFX11 VGPR counts	tree \| commitdiff
6 days ago	Andrew Stubbs	amdgcn: fix builtin codegen at -O0	tree \| commitdiff
6 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar dual widening...	tree \| commitdiff
6 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar single widening...	tree \| commitdiff
6 days ago	Kyrylo Tkachov	Revert "aarch64: Handle DImode BCAX operations"	tree \| commitdiff
7 days ago	H.J. Lu	x86: Enable SSE4.1 ceil/floor/trunc for -Os	tree \| commitdiff
7 days ago	liuhongt	Use vpermil{ps,pd} instead of vperm{d,q} when permutati...	tree \| commitdiff
7 days ago	liuhongt	Exclude fake cross-lane permutation from avx256_avoid_v...	tree \| commitdiff
7 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar widening floating...	tree \| commitdiff
7 days ago	Anton Blanchard	RISC-V: Adjust tt-ascalon-d8 branch cost	tree \| commitdiff
8 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar single-width...	tree \| commitdiff
8 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar single-width...	tree \| commitdiff
8 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar single-width...	tree \| commitdiff
8 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar widening floating...	tree \| commitdiff
8 days ago	Paul-Antoine Arras	RISC-V: Add patterns for vector-scalar IEEE floating...	tree \| commitdiff
8 days ago	Kuan-Lin Chen	RISC-V: Add support for the XAndesvdot ISA extension.	tree \| commitdiff
8 days ago	Jeff Law	[RISC-V] Fix ordering of pipeline models	tree \| commitdiff
8 days ago	Kuan-Lin Chen	RISC-V: Add support for the XAndesvpackfph ISA extension.	tree \| commitdiff
9 days ago	Georg-Johann Lay	AVR: ad target/121794 - Invoke zero_reg less.	tree \| commitdiff
9 days ago	Pan Li	RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub...	tree \| commitdiff
9 days ago	Kuan-Lin Chen	RISC-V: Add support for the XAndesvsintload ISA extension.	tree \| commitdiff
9 days ago	Kuan-Lin Chen	RISC-V: Add support for the XAndesvbfhcvt ISA extension.	tree \| commitdiff
9 days ago	Anton Blanchard	RISC-V: Add tt-ascalon-d8 pipeline description	tree \| commitdiff
10 days ago	Robin Dapp	RISC-V: Check if we can vec_extract [PR121510].	tree \| commitdiff
10 days ago	Georg-Johann Lay	AVR: target/121794 - Invoke zero_reg less.	tree \| commitdiff
11 days ago	Kyrylo Tkachov	aarch64: Use SVE for V2DImode integer min/max operations	tree \| commitdiff
11 days ago	Pan Li	RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx...	tree \| commitdiff
11 days ago	Richard Earnshaw	arm: wrong code from vset_lane_* [PR121775]	tree \| commitdiff
12 days ago	Robin Dapp	RISC-V: Use correct target in expand_vec_perm [PR121780].	tree \| commitdiff
12 days ago	Kito Cheng	RISC-V: Always register vector built-in functions durin...	tree \| commitdiff
12 days ago	Kuan-Lin Chen	RISC-V: Add support for the XAndesbfhcvt ISA extension.	tree \| commitdiff
12 days ago	Kuan-Lin Chen	RISC-V: Add support for the XAndesperf ISA extension.	tree \| commitdiff
12 days ago	Kuan-Lin Chen	RISC-V: Add basic XAndes vendor extension support.	tree \| commitdiff
12 days ago	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar floating-point max	tree \| commitdiff
12 days ago	Austin Law	[RISC-V][PR target/121213] Avoid unnecessary sign exten...	tree \| commitdiff
12 days ago	Kyrylo Tkachov	aarch64: PR target/121749: Use correct predicate for...	tree \| commitdiff
13 days ago	Robin Dapp	RISC-V: Fix is_vlmax_len_p and use for strided ops.	tree \| commitdiff
13 days ago	Robin Dapp	RISC-V: Handle overlap in expand_vec_perm PR121742.	tree \| commitdiff
2025-09-02	Kito Cheng	RISC-V: Remove unused print_ext_doc_entry function...	tree \| commitdiff
2025-09-01	Yoshinori Sato	PR target/89828 Inernal compiler error on "-fno-omit...	tree \| commitdiff
2025-09-01	Richard Biener	Introduce abstraction for vect reduction info, tracked...	tree \| commitdiff
2025-09-01	liuhongt	Fix ICE due to wrong operand is passed to ix86_vgf2p8af...	tree \| commitdiff
2025-08-31	Takayuki 'January...	xtensa: Optimize branch whether (reg:SI) is within...	tree \| commitdiff
2025-08-31	Shreya Munnangi	[RISC-V] Improve initial RTL generation for SImode...	tree \| commitdiff
2025-08-30	Jakub Jelinek	phiopt, math-opts: Adjust spaceship_replacement and...	tree \| commitdiff
2025-08-30	H.J. Lu	x86-64: Use UNSPEC_DTPOFF to check source operand in...	tree \| commitdiff
2025-08-29	Takayuki 'January...	xtensa: Rewrite bswapsi2_internal with compact syntax	tree \| commitdiff
2025-08-29	Jeff Law	[RISC-V][PR target/121548] Avoid bogus index into recog...	tree \| commitdiff
2025-08-29	Paul-Antoine Arras	RISC-V: Add patterns for vector-scalar IEEE floating...	tree \| commitdiff
2025-08-29	H.J. Lu	x86: Allow by_pieces op when expanding memcpy/memset...	tree \| commitdiff
2025-08-29	H.J. Lu	x86: Handle constant in any modes in setmem_epilogue_ge...	tree \| commitdiff
2025-08-29	H.J. Lu	x86-64: Improve source operand check for TLS_CALL	tree \| commitdiff
2025-08-29	Pan Li	RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac...	tree \| commitdiff
2025-08-28	Paul-Antoine Arras	RISC-V: Add pattern for vector-scalar floating-point min	tree \| commitdiff
2025-08-28	Wilco Dijkstra	AArch64: Add isinf expander [PR 66462]	tree \| commitdiff
2025-08-27	H.J. Lu	x86-64: Emit the TLS call after debug marker	tree \| commitdiff
2025-08-27	Jeff Law	More RISC-V testsuite hygiene	tree \| commitdiff
2025-08-26	liuhongt	Enable unroll in the vectorizer when there's reduction...	tree \| commitdiff
2025-08-26	Paul-Antoine Arras	[PATCH] RISC-V: Add pattern for reverse floating-point...	tree \| commitdiff
2025-08-26	Tamar Christina	AArch64: extend cost model to cost outer loop vect...	tree \| commitdiff
2025-08-26	Paul-Antoine Arras	[PATCH] RISC-V: Add pattern for vector-scalar single...	tree \| commitdiff
2025-08-26	Jeff Law	Fix RISC-V bootstrap	tree \| commitdiff
2025-08-26	Richard Biener	Compute vect_reduc_type off SLP node instead of stmt...	tree \| commitdiff
2025-08-26	Jakub Jelinek	i386: Fix up recent changes to use GFNI for rotates...	tree \| commitdiff
2025-08-26	Pan Li	RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx...	tree \| commitdiff
2025-08-25	Takayuki 'January...	xtensa: Make use of compact insn definition syntax...	tree \| commitdiff
2025-08-25	Takayuki 'January...	xtensa: Simplify "*masktrue_const_bitcmpl" insn pattern	tree \| commitdiff
2025-08-25	Takayuki 'January...	xtensa: Simplify "zero_extend[hq]isi2" insn patterns	tree \| commitdiff
2025-08-25	Indu Bhagat	targhooks: i386: rename TAG_SIZE to TAG_BITSIZE	tree \| commitdiff
2025-08-25	Kito Cheng	RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE...	tree \| commitdiff
2025-08-25	Andi Kleen	Use x86 GFNI for vectorized constant byte shifts/rotates	tree \| commitdiff
2025-08-25	Xi Ruoyao	LoongArch: Fix ICE in highway-1.3.0 testsuite [PR121634]	tree \| commitdiff
2025-08-23	Sam James	i386: wire up --with-tls to control -mtls-dialect=...	tree \| commitdiff
2025-08-22	Kishan Parmar	rs6000: Add shift count guards to avoid undefined behav...	tree \| commitdiff
2025-08-22	H.J. Lu	Emit the TLS call after NOTE_INSN_FUNCTION_BEG	tree \| commitdiff
2025-08-22	Sebastian Huber	RTEMS: Add riscv multilibs	tree \| commitdiff
2025-08-21	Dimitar Dimitrov	pru: libgcc: Add software implementation for multiplication	tree \| commitdiff
2025-08-21	Dimitar Dimitrov	pru: Define multilib for different core variants	tree \| commitdiff
2025-08-21	Dimitar Dimitrov	pru: Add options to disable MUL/FILL/ZERO instructions	tree \| commitdiff
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