* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/variant_pcs-1.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-2.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-now.d: New test.
* testsuite/ld-aarch64/variant_pcs-r.d: New test.
* testsuite/ld-aarch64/variant_pcs-shared.d: New test.
* testsuite/ld-aarch64/variant_pcs.ld: New linker script for tests.
ld/ChangeLog:
* testsuite/ld-aarch64/variant_pcs-now.d: Use --hash-style=sysv.
* testsuite/ld-aarch64/variant_pcs-shared.d: Likewise.
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias
symbols independently. This is needed for ifunc symbols which are
aliased to the resolver using .set and don't expect resolver attributes
to override the ifunc symbol attributes. This means .variant_pcs must be
added explicitly to aliases.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define.
* config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare.
(OBJ_COPY_SYMBOL_ATTRIBUTES): Define.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS.
gas/ChangeLog:
* config/tc-aarch64.c (s_variant_pcs): New function.
* doc/c-aarch64.texi: Document .variant_pcs.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
The bottom 2 bits of st_other are used for visibility, the top 6 bits are
de facto reserved for processor specific use. This patch defines a
bits to mark function symbols that follow a variant procedure call standard
with different register usage convention.
A dynamic tag is also defined that marks modules with R_<CLS>_JUMP_SLOT
relocations referencing symbols marked with STO_AARCH64_VARIANT_PCS.
This can be used by dynamic linkers that support lazy binding to decide
what registers need to be preserved during symbol resolution.
Ensure that debug information for ARM security functions is not dropped by the linker when performing garbage collection.
onsider a file containing only Armv8-M secure entry functions.
This file is compiled and linked with "-march=armv8-m.main -mfloat-abi=hard
-mfpu=fpv5-sp-d16 -mcmse -static --specs=rdimon.specs
-Wl,--section-start,.gnu.sgstubs=0x190000 -ffunction-sections
-fdata-sections
-Wl,--gc-sections -g" options to generate an executable.
The executable generated does not contain any debug information of these
secure entry
functions even though it contains secure entry functions in the .text
section.
Example:
$ cat main.c
int main (void)
{
return 0;
}
[AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
Andre Vieira [Tue, 21 May 2019 15:27:28 +0000 (16:27 +0100)]
[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M Baseline
gas/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backport from mainline
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW
replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
Tamar Christina [Tue, 21 May 2019 10:03:45 +0000 (11:03 +0100)]
AArch64: Add SVE DWARF registers
The SVE DRAWF register names are missing from binutils, this may cause objdump
and readelf to ignore certain DRAWF output as the registers are unknown (most
notably CIEs).
This patch adds the registers in accordance to the "DWARF for ARM(r) 64-bit
Architecture (AARch64) with SVE support" documentation [1].
* dwarf.c (dwarf_regnames_aarch64): Add SVE registers.
* testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test.
* testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test.
Alan Modra [Fri, 17 May 2019 09:39:42 +0000 (19:09 +0930)]
PR24567, assertion failure in ldlang.c:6868 when compiling with -flto
As the existing comment said: "a common ought to be overridden by a
def in a -flto object". This patch makes the code actually do that,
rather than allowing a normal object file common to override a -flto
defined symbol.
PR 24567
* plugin.c (plugin_notice): Do not let a common symbol override
a non-common definition in IR.
projects / thirdparty / binutils-gdb.git / log
