This series of patches adds support for 2 boards from Netstal Maschinen.
The HCU4 has a PPC405Gpr and
the HCU5 has a PPC440EPX.
The HCU4 has a somehow complicated flash setup, as the booteprom is
only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more
elegant solution.
The HCU5 has only a booteprom as the whole code will be downloaded from a
different board which has HD, CD-ROM, etc and where all code is stored.
This is my third try. I incorporated all suggestions made by Wolfgang and Stefan.
Thanks them a lot.
Kim Phillips [Thu, 26 Jul 2007 00:25:33 +0000 (19:25 -0500)]
mpc83xx: add support for the MPC8323E RDB
MPC8323E based board with 64MB fixed SDRAM, 16MB flash,
five 10/100 ethernet ports connected via an ICPlus IP175C
switch, one PCI slot, and serial. Features not supported
in this patch are SD card interface, 2 USB ports, and the
two phone ports.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Jerry Van Baren [Thu, 5 Jul 2007 01:34:24 +0000 (21:34 -0400)]
mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabled
Several node strings were not correct (trailing slashes and properties
in the strings)
Added setting of the timebase-frequency.
Improved error messages and use debug() instead of printf().
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Jerry Van Baren [Thu, 5 Jul 2007 01:27:30 +0000 (21:27 -0400)]
mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path().
The new name matches more closely the kernel's name, which is also
a much better description.
These are the mpc83xx changes made necessary by the function name change.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Dave Liu [Mon, 25 Jun 2007 02:41:56 +0000 (10:41 +0800)]
mpc83xx: Add support for the display of reset status
83xx processor family has many reset sources, such as
power on reset, software hard reset, software soft reset,
JTAG, bus monitor, software watchdog, check stop reset,
external hard reset, external software reset.
sometimes, to figure out the fault of system, we need to
know the cause of reset early before the prompt of
u-boot present.
Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Dave Liu [Mon, 25 Jun 2007 05:21:12 +0000 (13:21 +0800)]
mpc83xx: Revise the MPC8360EMDS readme doc
When the rev2.x silicon mount on the MPC8360EMDS baord,
and if you are using the u-boot version after the commit 3fc0bd159103b536e1c54c6f4457a09b3aba66ca.
to make the ethernet interface usable, we have to setup
the jumpers correctly.
Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Timur Tabi [Tue, 3 Jul 2007 18:46:32 +0000 (13:46 -0500)]
FSL I2C driver programs the two I2C busses differently
The i2c_init() function in fsl_i2c.c programs the two I2C busses differently.
The second I2C bus has its slave address programmed incorrectly and is
missing a 5-us delay.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Timur Tabi [Tue, 3 Jul 2007 18:04:34 +0000 (13:04 -0500)]
Update SCCR programming in cpu_init_f() to support all 83xx processors
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors. The code to update some bitfields was
compiled only on some processors. Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Jason Jin [Tue, 10 Jul 2007 01:03:22 +0000 (09:03 +0800)]
Remove the bios emulator from MAI board.
The bios emulator in the MAI board can not pass compile
and have a lot of crap in it. remove it and will have a
clean and small bios emulator in the drivers directory
which can be uesed for every board.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Jason Jin [Fri, 6 Jul 2007 00:34:56 +0000 (08:34 +0800)]
This is a BIOS emulator, porting from SciTech for u-boot, mainly for
ATI video card BIOS. and can be used for x86 code emulation by some
modifications.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Ed Swarthout [Thu, 2 Aug 2007 19:09:49 +0000 (14:09 -0500)]
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts.
All of the PCI/PCI-Express driver and initialization code that
was in the MPC8641HPCN port has now been moved into the common
drivers/fsl_pci_init.c. In a subsequent patch, this will be
utilized by the 85xx ports as well.
Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added.
Also enable the second PCI-Express controller on 8641
by getting its BATS and CFG_ setup right.
Fixed a u16 vendor compiler warning in AHCI driver too.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
cm1_qp1 -> cm5200: single U-Boot image for modules from the cm5200 family.
Add the ability for modules from the Schindler cm5200 family to use a
single U-Boot image:
- rename cm1_qp1 to cm5200
- add run-time module detection
- parametrize SDRAM configuration according to the module we are running on
Few minor, board-specific fixes included in this patch:
- better MAC address handling
- updated default environment ('update' command uses +{filesize} now)
- improved error messages in the auto-update code
- allow booting U-Boot from RAM (CFG_RAMBOOT)
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
[ppc440SPe] Graceful recovery from machine check during PCIe configuration
During config transactions on the PCIe bus an attempt to scan for a
non-existent device can lead to a machine check exception with certain
peripheral devices. In order to avoid crashing in such scenarios the
instrumented versions of the config cycle read routines are introduced, so
the exceptions fixups framework can gracefully recover.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Rafal Jaworowski <raj@semihalf.com>
[ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A
This brings back separate settings for PCIe bus numbers depending on chip
revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa
commit. 440SPe rev. A does NOT work properly with the same settings as for
the rev. B (no devices are seen on the bus during enumeration).
Changed storage type of cfg_simulate_spd_eeprom to const
Changed storage type of gpio_tab to stack storage
(Cannot access global data declarations in .bss until afer code relocation)
Improved SDRAM tests to catch problems where data is not uniquely addressable
(e.g. incorrectly programmed SDRAM row or columns)
Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
Fixed AM29LV320DT (OpCode Flash) sector map
Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
Change Lime SDRAM initialization to now support 100MHz and
133MHz (if enabled). Also the framebuffer is initialized to
display a blue rectangle with a white border.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Mon, 16 Jul 2007 06:53:51 +0000 (08:53 +0200)]
ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup
The new function remove_tlb() can be used to remove the TLB's used to
map a specific memory region. This is especially useful for the DDR(2)
setup routines which configure the SDRAM area temporarily as a cached
area (for speedup on auto-calibration and ECC generation) and later
need this area uncached for normal usage.