]> git.ipfire.org Git - people/ms/u-boot.git/log
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9 years agorockchip: Add basic support for jerry
Simon Glass [Sun, 30 Aug 2015 22:55:42 +0000 (16:55 -0600)] 
rockchip: Add basic support for jerry

This builds and displays an SPL message, but does not function beyond that.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add basic support for firefly-rk3288
Simon Glass [Sun, 30 Aug 2015 22:55:41 +0000 (16:55 -0600)] 
rockchip: Add basic support for firefly-rk3288

The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.

This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add SPI driver
Simon Glass [Wed, 2 Sep 2015 01:19:37 +0000 (19:19 -0600)] 
rockchip: Add SPI driver

Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add I2C driver
Simon Glass [Sun, 30 Aug 2015 22:55:39 +0000 (16:55 -0600)] 
rockchip: Add I2C driver

Add an I2C driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add core SoC start-up code
Simon Glass [Sun, 30 Aug 2015 22:55:38 +0000 (16:55 -0600)] 
rockchip: Add core SoC start-up code

Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add an MMC driver
Simon Glass [Sun, 30 Aug 2015 22:55:37 +0000 (16:55 -0600)] 
rockchip: Add an MMC driver

Add an MMC driver which supports RK3288, but may also support other SoCs.
It uses the Designware MMC device.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: rk3288: Add SDRAM init
Simon Glass [Sun, 30 Aug 2015 22:55:36 +0000 (16:55 -0600)] 
rockchip: rk3288: Add SDRAM init

Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: rk3288: Add pinctrl driver
Simon Glass [Sun, 30 Aug 2015 22:55:35 +0000 (16:55 -0600)] 
rockchip: rk3288: Add pinctrl driver

Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: rk3288: Add a simple syscon driver
Simon Glass [Sun, 30 Aug 2015 22:55:34 +0000 (16:55 -0600)] 
rockchip: rk3288: Add a simple syscon driver

Add a driver that provides access to system controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: rk3288: Add SoC reset driver
Simon Glass [Sun, 30 Aug 2015 22:55:33 +0000 (16:55 -0600)] 
rockchip: rk3288: Add SoC reset driver

We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: rk3288: Add header files for PMU and GRF
Simon Glass [Sun, 30 Aug 2015 22:55:32 +0000 (16:55 -0600)] 
rockchip: rk3288: Add header files for PMU and GRF

PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: rk3288: Add clock driver
Simon Glass [Sun, 30 Aug 2015 22:55:31 +0000 (16:55 -0600)] 
rockchip: rk3288: Add clock driver

Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3288.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agopower: regulator: Add a driver for ACT8846 regulators
Simon Glass [Sun, 30 Aug 2015 22:55:30 +0000 (16:55 -0600)] 
power: regulator: Add a driver for ACT8846 regulators

Add a full regulator driver for the ACT8846. This provides easy access to
voltage and current settings for each regulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agopower: Add support for ACT8846 PMIC
Simon Glass [Sun, 30 Aug 2015 22:55:29 +0000 (16:55 -0600)] 
power: Add support for ACT8846 PMIC

Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and
is connected to the I2C bus. This driver supports using a regulator driver
to access the regulators.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add basic peripheral and clock definitions
Simon Glass [Sun, 30 Aug 2015 22:55:28 +0000 (16:55 -0600)] 
rockchip: Add basic peripheral and clock definitions

Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: gpio: Add rockchip GPIO driver
Simon Glass [Sun, 30 Aug 2015 22:55:27 +0000 (16:55 -0600)] 
rockchip: gpio: Add rockchip GPIO driver

This supports RK3288 at present. It does not implement functions or support
for pull up/down.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add support for the SPI image
Simon Glass [Sun, 30 Aug 2015 22:55:26 +0000 (16:55 -0600)] 
rockchip: Add support for the SPI image

The Rockchip boot ROM requires a particular file format for booting from SPI.
It consists of a 512-byte header encoded with RC4, some padding and then up
to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.

Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format. This allows booting from SPI flash on supported
machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add support for the SD image
Simon Glass [Sun, 30 Aug 2015 22:55:25 +0000 (16:55 -0600)] 
rockchip: Add support for the SD image

The Rockchip boot ROM requires a particular file format. It consists of
64KB of zeroes, a 512-byte header encoded with RC4, and then some executable
code.

Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add the rkimage format to mkimage
Simon Glass [Sun, 30 Aug 2015 22:55:24 +0000 (16:55 -0600)] 
rockchip: Add the rkimage format to mkimage

Rockchip SoCs require certain formats for code that they execute, The
simplest format is a 4-byte header at the start of a binary file. Add
support for this so that we can create images that the boot ROM understands.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agomkimage: Allow the original file size to be recorded
Simon Glass [Sun, 30 Aug 2015 22:55:23 +0000 (16:55 -0600)] 
mkimage: Allow the original file size to be recorded

Allow the image handler to store the original input file size so that it
can reference it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agomkimage: Allow padding to any length
Simon Glass [Sun, 30 Aug 2015 22:55:22 +0000 (16:55 -0600)] 
mkimage: Allow padding to any length

At present there is an arbitrary limit of 4KB for padding. Rockchip needs
more than that, so remove this restriction.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agorockchip: rk3288: dts: Make core devices available early
Simon Glass [Sun, 30 Aug 2015 22:55:21 +0000 (16:55 -0600)] 
rockchip: rk3288: dts: Make core devices available early

In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Bring in RK3288 device tree file includes and bindings
Simon Glass [Sun, 30 Aug 2015 22:55:20 +0000 (16:55 -0600)] 
rockchip: Bring in RK3288 device tree file includes and bindings

Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agorockchip: Add serial support
Simon Glass [Sun, 30 Aug 2015 22:55:19 +0000 (16:55 -0600)] 
rockchip: Add serial support

Add support for the Rockchip serial device using the ns16550 driver.
This uses driver model and device tree for both SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoarm: reset: Avoid a build error when the reset uclass is enabled
Simon Glass [Sun, 30 Aug 2015 22:55:18 +0000 (16:55 -0600)] 
arm: reset: Avoid a build error when the reset uclass is enabled

There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodm: Provide better debugging when a device fails to bind
Simon Glass [Sun, 30 Aug 2015 22:55:17 +0000 (16:55 -0600)] 
dm: Provide better debugging when a device fails to bind

All devices should bind without error. But when they don't, they can cause
driver model init to fail. A real situation where this can happen is when
there is a missing uclass.

Add a debug() call to dm_scan_fdt_node to make this easier to track.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodm: Improve handling of a missing uclass
Simon Glass [Sun, 30 Aug 2015 22:55:16 +0000 (16:55 -0600)] 
dm: Improve handling of a missing uclass

When a uclass definition is missing, no drivers in that uclass can operate.
This can happen if a board has a strange collection of options (e.g. the
driver is enabled but the uclass is not).

Unfortunately this is very confusing at present. Starting up driver model
results in a -ENOENT error, which is pretty generic. Quite a big of digging
is needed to get to the root cause.

To help with this, change the error to a very strange one with no other
users in U-Boot. Also add a debug message.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agommc: Support bypass mode with the get_mmc_clk() method
Simon Glass [Sun, 30 Aug 2015 22:55:15 +0000 (16:55 -0600)] 
mmc: Support bypass mode with the get_mmc_clk() method

Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
9 years agodm: led: Tidy up SPL options for the led and led-gpio
Simon Glass [Sun, 30 Aug 2015 22:55:14 +0000 (16:55 -0600)] 
dm: led: Tidy up SPL options for the led and led-gpio

At present SPL does not have its own option. But these features can
increase SPL code size. Adjust the Kconfig and Makefile so that
separate a SPL option can be selected.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agopinctrl: Add the concept of peripheral IDs
Simon Glass [Sun, 30 Aug 2015 22:55:13 +0000 (16:55 -0600)] 
pinctrl: Add the concept of peripheral IDs

My original pinctrl patch operating using a peripheral ID enum. This was
shared between pinmux and clock and provides an easy way to specify a device
that needs to be controlled, even it is does not (yet) have a driver within
driver model.

Masahiro's new simple pinctrl gets around this by providing a
set_state_simple() pinctrl method. By passing a device to that call the
peripheral ID becomes unnecessary. If the driver needs it, it can calculate
it itself and use it internally.

However this does not solve the problem for peripheral clocks. The 'pure'
solution would be to pass a driver to the clock uclass also. But this
requires that all devices should have a driver, and a struct udevide. Also
a key optimisation of the clock uclass is allowing a peripheral clock to
be set even when there is no device for that clock.

There may be a better way to achive the same goal, but for now it seems
expedient to add in peripheral ID to the pinctrl uclass. Two methods are
added - one to get the peripheral ID and one to select it. The existing
set_state_simple() is effectively the union of these.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agopinctrl: Add help text to Kconfig
Simon Glass [Sun, 30 Aug 2015 22:55:12 +0000 (16:55 -0600)] 
pinctrl: Add help text to Kconfig

The pinctrl Kconfig options should have help messages. Add this to a few
options.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini [Mon, 31 Aug 2015 16:12:27 +0000 (12:12 -0400)] 
Merge branch 'master' of http://git.denx.de/u-boot-sunxi

9 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Mon, 31 Aug 2015 15:43:47 +0000 (11:43 -0400)] 
Merge git://git.denx.de/u-boot-dm

9 years agosunxi: increase SYS_MONITOR_LEN
Boris Brezillon [Mon, 27 Jul 2015 14:21:26 +0000 (16:21 +0200)] 
sunxi: increase SYS_MONITOR_LEN

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
9 years agodts: fix dependency of OF_SPL_REMOVE_PROPS
Masahiro Yamada [Fri, 28 Aug 2015 11:28:42 +0000 (20:28 +0900)] 
dts: fix dependency of OF_SPL_REMOVE_PROPS

This should depend on SPL_OF_CONTROL (it is not equivalent to
SPL && OF_CONTROL).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agopinctrl: sandbox: add sandbox pinctrl driver
Masahiro Yamada [Thu, 27 Aug 2015 03:44:30 +0000 (12:44 +0900)] 
pinctrl: sandbox: add sandbox pinctrl driver

This driver actually does nothing but test pinctrl uclass, and
demonstrate how things work.

To try this driver, uncomment /* #define DEBUG */ in the
drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be
displayed.

  DRAM:  128 MiB
  sandbox pinmux: group = 1 (serial_a), function = 1 (serial)
  Using default environment

  In:    cros-ec-keyb
  Out:   lcd
  Err:   lcd
  Net:   Net Initialization Skipped
  eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000
  => i2c dev 0
  Setting bus to 0
  sandbox pinmux: group = 0 (i2c), function = 0 (i2c)
  sandbox pinconf: group = 0 (i2c), param = 3, arg = 1

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agopinctrl: add pin control uclass support
Masahiro Yamada [Thu, 27 Aug 2015 03:44:29 +0000 (12:44 +0900)] 
pinctrl: add pin control uclass support

This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.

This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.

This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print.  Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.

We are often limited on code size for SPL.  Besides, we still have
many boards that do not support device tree configuration.  The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards.  So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface.  With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc.  They must be
done in each low-level driver.  In return, you can save much memory
footprint and it might be useful especially for SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: core: allow device_bind() to not return a device pointer
Masahiro Yamada [Thu, 27 Aug 2015 03:44:28 +0000 (12:44 +0900)] 
dm: core: allow device_bind() to not return a device pointer

This is useful when we want to bind a device, but do not need the
pointer to the device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agotegra: nyan: Enable TPM command and driver
Simon Glass [Sun, 23 Aug 2015 00:31:44 +0000 (18:31 -0600)] 
tegra: nyan: Enable TPM command and driver

The TPM is listed in the device tree. Enable the driver and 'tpm' command
so that it can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Enable 'tpmtest' command for Chrome OS boards with TPMs
Simon Glass [Sun, 23 Aug 2015 00:31:43 +0000 (18:31 -0600)] 
tpm: Enable 'tpmtest' command for Chrome OS boards with TPMs

This command provides a few useful tests so enable it for common boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: tpm: Add a 'tpmtest' command
Simon Glass [Sun, 23 Aug 2015 00:31:42 +0000 (18:31 -0600)] 
dm: tpm: Add a 'tpmtest' command

These tests come from Chrome OS code. They are not particularly tidy but can
be useful for checking that the TPM is behaving correctly. Some knowledge of
TPM operation is required to use these.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Add functions to access flags and permissions
Simon Glass [Sun, 23 Aug 2015 00:31:41 +0000 (18:31 -0600)] 
tpm: Add functions to access flags and permissions

Add a few new functions which will be used by the test command in a future
patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Add a 'tpm info' command
Simon Glass [Sun, 23 Aug 2015 00:31:40 +0000 (18:31 -0600)] 
tpm: Add a 'tpm info' command

Add a command to display basic information about a TPM such as the model and
open/close state. This can be useful for debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: tpm: Convert LPC driver to driver model
Simon Glass [Sun, 23 Aug 2015 00:31:39 +0000 (18:31 -0600)] 
dm: tpm: Convert LPC driver to driver model

Convert the tpm_tis_lpc driver to use driver model and update boards which
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: tpm: Convert I2C driver to driver model
Simon Glass [Sun, 23 Aug 2015 00:31:38 +0000 (18:31 -0600)] 
dm: tpm: Convert I2C driver to driver model

Convert the tpm_tis_i2c driver to use driver model and update boards which
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agoexynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices
Simon Glass [Sun, 23 Aug 2015 00:31:37 +0000 (18:31 -0600)] 
exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices

Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Check that parse_byte_string() has data to parse
Simon Glass [Sun, 23 Aug 2015 00:31:36 +0000 (18:31 -0600)] 
tpm: Check that parse_byte_string() has data to parse

Rather then crashing when there is no data, print an error. The error is
printed by the caller to parse_byte_string().

Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: tpm: sandbox: Convert TPM driver to driver model
Simon Glass [Sun, 23 Aug 2015 00:31:35 +0000 (18:31 -0600)] 
dm: tpm: sandbox: Convert TPM driver to driver model

Convert the sandbox TPM driver to use driver model. Add it to the device
tree so that it can be found on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Report tpm errors on the command line
Simon Glass [Sun, 23 Aug 2015 00:31:34 +0000 (18:31 -0600)] 
tpm: Report tpm errors on the command line

When a 'tpm' command fails, we set the return code but give no indication
of failure. This can be confusing.

Add an error message when any tpm command fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: i2c: Add a command to adjust the offset length
Simon Glass [Sun, 23 Aug 2015 00:31:33 +0000 (18:31 -0600)] 
dm: i2c: Add a command to adjust the offset length

I2C chips can support a register offset, with registers accessible by
sending this offset as the first part of any read or write transaction.
Most I2C chips have a single byte offset, thus the offset length is 1.
This provides access for up 256 registers.

However other offset lengths are supported, including 0.

Add a command to provide access to the offset length from the command
line. This allows the offset length to be read or written.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: tpm: Convert the TPM command and library to driver model
Simon Glass [Sun, 23 Aug 2015 00:31:32 +0000 (18:31 -0600)] 
dm: tpm: Convert the TPM command and library to driver model

Add driver model support to the TPM command and the TPM library. Both
support only a single TPM at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agodm: tpm: Add a uclass for Trusted Platform Modules
Simon Glass [Sun, 23 Aug 2015 00:31:31 +0000 (18:31 -0600)] 
dm: tpm: Add a uclass for Trusted Platform Modules

Add a new uclass for TPMs which uses almost the same TIS (TPM Interface
Specification) as is currently implemented. Since init() is handled by the
normal driver model probe() method, we don't need to implement that. Also
rename the transfer method to xfer() which is a less clumbsy name.

Once all drivers and users are converted to driver model we can remove the
old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Tidy up delays
Simon Glass [Sun, 23 Aug 2015 00:31:30 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Tidy up delays

Use a _US suffix for microseconds and a _MS suffic for milliseconds. Move
all timeouts and delays into one place. Use mdelay() instead of udelay()
where appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Use a consistent tpm_tis_i2c_ prefix
Simon Glass [Sun, 23 Aug 2015 00:31:29 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Use a consistent tpm_tis_i2c_ prefix

Use the same prefix on each function for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Simplify init code
Simon Glass [Sun, 23 Aug 2015 00:31:28 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Simplify init code

Move all the init and uninit code into one place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Move definitions into the header file
Simon Glass [Sun, 23 Aug 2015 00:31:27 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Move definitions into the header file

Some definitions are in the C file and some are in the header file. Move
everything into the header file for consistency and to reduce clutter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Merge struct tpm into tpm_chip
Simon Glass [Sun, 23 Aug 2015 00:31:26 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Merge struct tpm into tpm_chip

There are too many structures storing the same sort of information. Move the
fields from struct tpm into struct tpm_chip and remove the former struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Merge struct tpm_dev into tpm_chip
Simon Glass [Sun, 23 Aug 2015 00:31:25 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Merge struct tpm_dev into tpm_chip

There are too many structures storing the same sort of information. Move the
fields from struct tpm_dev into struct tpm_chip and remove the former
struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Drop struct tpm_vendor_specific
Simon Glass [Sun, 23 Aug 2015 00:31:24 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Drop struct tpm_vendor_specific

This function is misnamed since it only applies to a single driver. Merge
its fields into its parent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: tpm_tis_i2c: Drop unnecessary methods
Simon Glass [Sun, 23 Aug 2015 00:31:23 +0000 (18:31 -0600)] 
tpm: tpm_tis_i2c: Drop unnecessary methods

The function methods in struct tpm_vendor_specific just call local functions.
Change the code to use a direct call.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Move the I2C TPM code into one file
Simon Glass [Sun, 23 Aug 2015 00:31:22 +0000 (18:31 -0600)] 
tpm: Move the I2C TPM code into one file

The current Infineon I2C TPM driver is written in two parts, intended to
support use with other I2C devices. However we don't have any users and the
Atmel I2C TPM device does not use this file.

We should simplify this and remove the unused abstration. As a first step,
move the code into one file.

Also the name tpm_private.h suggests that the header file is generic to all
TPMs but it is not. Rename it indicate that it relates only to this driver

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Convert drivers to use SPDX
Simon Glass [Sun, 23 Aug 2015 00:31:21 +0000 (18:31 -0600)] 
tpm: Convert drivers to use SPDX

Add an SPDX header to two drivers that don't have it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Convert board config TPM options to Kconfig
Simon Glass [Sun, 23 Aug 2015 00:31:20 +0000 (18:31 -0600)] 
tpm: Convert board config TPM options to Kconfig

Convert all TPM options to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Add Kconfig options for TPMs
Simon Glass [Sun, 23 Aug 2015 00:31:19 +0000 (18:31 -0600)] 
tpm: Add Kconfig options for TPMs

Add new Kconfig options for TPMs in preparation for moving boards to use
Kconfig for TPM configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Drop two unused options
Simon Glass [Sun, 23 Aug 2015 00:31:18 +0000 (18:31 -0600)] 
tpm: Drop two unused options

The address of the I2C TPM is now defined in the device tree so there is no
need for the CONFIG options.

Remove them from the README and board config to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agotpm: Remove old pre-driver-model I2C code
Simon Glass [Sun, 23 Aug 2015 00:31:17 +0000 (18:31 -0600)] 
tpm: Remove old pre-driver-model I2C code

This is not used anymore by any board so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
9 years agoexynos: Rise ARM voltage to 1.1V for chained bootloaders
Misha Komarovskiy [Tue, 25 Aug 2015 08:53:26 +0000 (11:53 +0300)] 
exynos: Rise ARM voltage to 1.1V for chained bootloaders

If board uses downstream Chrome OS U-Boot as first stage
bootloader and upstream version is chained second stage,
1.1V is minimum voltage borderline.

Signed-off-by: Misha Komarovskiy <zombah@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agobuildman: Correct 'Series-cover-cc' detection logic
Simon Glass [Sun, 23 Aug 2015 00:28:01 +0000 (18:28 -0600)] 
buildman: Correct 'Series-cover-cc' detection logic

This requires 'Series-cover_cc' at present which is incorrect. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodrivers: kconfig: Sort driver menu in alphabetical order
Bin Meng [Fri, 21 Aug 2015 05:44:16 +0000 (22:44 -0700)] 
drivers: kconfig: Sort driver menu in alphabetical order

Sort different types of drivers in alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodrivers: kconfig: Move PHYS_TO_BUS to "Device Drivers" menu
Bin Meng [Fri, 21 Aug 2015 05:44:15 +0000 (22:44 -0700)] 
drivers: kconfig: Move PHYS_TO_BUS to "Device Drivers" menu

Right now PHYS_TO_BUS shows in the Kconfig main menu, move it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodrivers: kconfig: Move "Generic Driver Options" menu to the top
Bin Meng [Fri, 21 Aug 2015 05:44:14 +0000 (22:44 -0700)] 
drivers: kconfig: Move "Generic Driver Options" menu to the top

Make "Generic Driver Options" menu show on the top in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: core: Add Kconfig for simple bus driver
Marek Vasut [Sun, 2 Aug 2015 23:15:48 +0000 (01:15 +0200)] 
dm: core: Add Kconfig for simple bus driver

Add Kconfig entries for the simple-bus driver, both for U-Boot
and for SPL. The simple-bus is enabled by default in U-Boot and
disabled by default in SPL to preserve the original behavior.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Modified to fit on top of Masahiro's $(SPL) setup:
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodm: Use dev_get_addr() where possible
Simon Glass [Tue, 11 Aug 2015 14:33:29 +0000 (08:33 -0600)] 
dm: Use dev_get_addr() where possible

This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
9 years agodm: simplify uclass_foreach_dev() implementation
Masahiro Yamada [Mon, 10 Aug 2015 16:09:43 +0000 (01:09 +0900)] 
dm: simplify uclass_foreach_dev() implementation

This can be simply written with list_for_each_entry(), maybe
this macro was not necessary in the first place.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agosunxi: mmc: set transfer timeout according to byte_cnt.
Yousong Zhou [Sat, 29 Aug 2015 13:26:11 +0000 (21:26 +0800)] 
sunxi: mmc: set transfer timeout according to byte_cnt.

Originally a timeout value of 2 seconds was used regardless of the size
of data to be transfered.  This prevented slow devices from working
correctly while there was no much gain for faster devices, e.g. it takes
3708ms for a transfer of uImage of size 1899008 bytes.

Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
9 years agosunxi: Enable non-secure access to RTC on sun6i (A31s)
Chen-Yu Tsai [Tue, 25 Aug 2015 02:49:19 +0000 (10:49 +0800)] 
sunxi: Enable non-secure access to RTC on sun6i (A31s)

On the A31s the RTC is by default secured. Thus when u-boot
loads the kernel in non-secure world, the RTC is unavailable. The
SoC has a TrustZone Protection Controller, which can be used to
enable non-secure access to the RTC.

On the A31 the TZPC doesn't seem to do anything, i.e. changes to
its register contents do not affect access to the RTC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
9 years agosunxi: Fix MAINTAINERS board sorting
Hans de Goede [Thu, 27 Aug 2015 18:07:28 +0000 (20:07 +0200)] 
sunxi: Fix MAINTAINERS board sorting

The boards are sorted by SoC, move the Mele_A1000G_quad entry to the list
of sun6i boards where it belongs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: Add support for the Olimex A20 EVB
Marcus Cooper [Wed, 26 Aug 2015 18:38:33 +0000 (20:38 +0200)] 
sunxi: Add support for the Olimex A20 EVB

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
9 years agosunxi: Add inet98v_rev2 defconfig and dts file
Hans de Goede [Tue, 25 Aug 2015 12:20:49 +0000 (14:20 +0200)] 
sunxi: Add inet98v_rev2 defconfig and dts file

The inet98v_rev2 is a pcb used in generic A13 based tablets. It features
volume buttons, a power barrel, micro-usb otg, headphone connector and
a power button.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: Add inet97fv2_defconfig
Hans de Goede [Sat, 22 Aug 2015 18:06:02 +0000 (20:06 +0200)] 
sunxi: Add inet97fv2_defconfig

The inet97fv2 is a board found in the first generation of cheap allwinner
A10 based 7" tablets.

Note that this patch does not add a dts file as we already have one from
our dts syncs with the kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: Ampe_A76_defconfig: Add otg id pin configuration
Hans de Goede [Tue, 25 Aug 2015 12:19:06 +0000 (14:19 +0200)] 
sunxi: Ampe_A76_defconfig: Add otg id pin configuration

Add otg id pin configuration, this speeds up bootup when no host cable
is plugged into the otg port.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agomtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig
Hans de Goede [Fri, 21 Aug 2015 19:49:51 +0000 (21:49 +0200)] 
mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig

Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like
SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends,
to avoid double defining it for SoCs which have not yet moved to Kconfig
for this.

Having this in Kconfig is useful because this is something which may
differ from one board to the other even when using the same SoC.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Scott Wood <scottwood@freescale.com>
9 years agosunxi_nand_spl: clear status flags in SPL implementation
Boris Brezillon [Sat, 29 Aug 2015 10:29:38 +0000 (12:29 +0200)] 
sunxi_nand_spl: clear status flags in SPL implementation

Some status flags remain set until you explicetly clear the bit
in the status register.
Fix the SPL implementation to avoid false positive.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[hdegoede@redhat.com: Port from v2015.07 to v2015.10]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
9 years agosunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END
Hans de Goede [Fri, 21 Aug 2015 13:23:57 +0000 (15:23 +0200)] 
sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END

We only ever use syndrome mode for the partitions which contain the SPL,
as that is required for the BROM to be able to read the SPL.

Instead of using some arbritray limit for deciding whether or not to
use syndrome, be smart and check if u-boot-dtb.bin is directly behind
the SPL, if it is not then it is on its own partition and we should not
use syndrome.

Note the reason why we only use syndrome mode for the SPL is because it
comeswith weaker randomization, introducing a risk for more bit errors,
so we want to avoid it when possible.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXI
Hans de Goede [Sun, 16 Aug 2015 12:48:22 +0000 (14:48 +0200)] 
sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXI

We eventually want to add full nand support, since it makes no sense
to build SPL with nand support and u-boot without, or the other way
around, a single option will suffice.

Renaming the Kconfig option now makes things easier when we add full
nand support in the future.

The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an
"ifdef CONFIG_SPL_BUILD" block in the Makefile.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Add support for backup boot partitions
Hans de Goede [Sat, 15 Aug 2015 19:51:33 +0000 (21:51 +0200)] 
sunxi_nand_spl: Add support for backup boot partitions

The BROM does not care / use bad page markings, instead it deals with
any bad pages in the first erase-block by simply trying to load "boot0"
from the next erase-block.

This commit implements the same strategy for the sunxi spl nand code,
allowing it to boot from the backup boot partition when the main boot
partition is bad (tested by erasing the main boot partition).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Auto detect nand configuration parameters
Hans de Goede [Sat, 15 Aug 2015 19:23:08 +0000 (21:23 +0200)] 
sunxi_nand_spl: Auto detect nand configuration parameters

Auto detect the nand configuration parameters, like the BROM does.

This allows us to get rid of various Kconfig settings, and is
necessary to support generic boards like the mk802 which have seen
many production runs with different nands.

The full blown u-boot/kernel nand driver uses the nand id to determine
this info, for the SPL we do as the BROM does and simply try a few
standard configs.

Note the table only contains configs which are known to actually be used,
rather then all the configs the BROM tries. This means that it may need
to be updated in the future as we add support for nand on more boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Parametrize lowlevel read functions
Hans de Goede [Sat, 15 Aug 2015 18:51:53 +0000 (20:51 +0200)] 
sunxi_nand_spl: Parametrize lowlevel read functions

Parametrize the lowlevel nand_read_page function, instead of directly
using the CONFIG_foo settings for page-size, etc. there and add a few
wrappers / helper functions for calling it.

This is a preparation patch for adding auto-detecting of the nand
parameters like the BROM does.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Properly config page-size in the nand ctl register
Hans de Goede [Sat, 15 Aug 2015 18:05:13 +0000 (20:05 +0200)] 
sunxi_nand_spl: Properly config page-size in the nand ctl register

Properly config page-size in the nand ctl register, it seems that things
work fine without doing this, but still lets play it safe and properly
set the page-size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Add support for sun4i and sun5i SoCs
Hans de Goede [Sat, 15 Aug 2015 11:17:49 +0000 (13:17 +0200)] 
sunxi_nand_spl: Add support for sun4i and sun5i SoCs

Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.

Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _off
Hans de Goede [Sat, 15 Aug 2015 10:41:09 +0000 (12:41 +0200)] 
sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _off

Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a good idea in general, and
it fixes / adds support for ecc strengths of 56, 60 and 64 bits.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Add proper cache flusing
Hans de Goede [Sat, 15 Aug 2015 10:32:24 +0000 (12:32 +0200)] 
sunxi_nand_spl: Add proper cache flusing

We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly luck, but lets not rely on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Turn off clocks when we're done with the nand
Hans de Goede [Sat, 15 Aug 2015 09:59:25 +0000 (11:59 +0200)] 
sunxi_nand_spl: Turn off clocks when we're done with the nand

Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.

Without this the kernel will not boot properly when it is built with
dma-controller support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Make sure the DMA controller is enabled
Hans de Goede [Sat, 15 Aug 2015 09:58:03 +0000 (11:58 +0200)] 
sunxi_nand_spl: Make sure the DMA controller is enabled

We use DMA for nand data transfers in the SPL, so make sure the DMA
controller is enabled.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary
Hans de Goede [Sat, 15 Aug 2015 09:55:26 +0000 (11:55 +0200)] 
sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary

Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Do not bother writing the spare-area reg in syndrome mode
Hans de Goede [Sat, 15 Aug 2015 10:43:26 +0000 (12:43 +0200)] 
sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome mode

In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE.

So the current code only serves to confuse the user -> remove it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: We only need to reset the nand chip once
Hans de Goede [Sat, 15 Aug 2015 09:38:33 +0000 (11:38 +0200)] 
sunxi_nand_spl: We only need to reset the nand chip once

There is no need to reset the nand chip for every ecc-block read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Drop unnecessary temp buf
Hans de Goede [Sat, 15 Aug 2015 07:33:41 +0000 (09:33 +0200)] 
sunxi_nand_spl: Drop unnecessary temp buf

nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for "overshooting" up to
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks.

This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in
SPL size, which is a lot on the total 24k we have.

Note this changes the dma destination from SRAM to DRAM, so this patch
updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi_nand_spl: Fix CONFIG_SPL_NAND_SUNXI handling
Hans de Goede [Sat, 15 Aug 2015 07:38:22 +0000 (09:38 +0200)] 
sunxi_nand_spl: Fix CONFIG_SPL_NAND_SUNXI handling

CONFIG_SPL_NAND_SUPPORT gets used via IS_ENABLED so it must be defined
to 1, rather then just being defined.

While at remove 2 other unused NAND related defines from sunxi-common.h.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: Add CONFIG_MMC0_CD_PIN to various boards
Hans de Goede [Sat, 15 Aug 2015 09:46:01 +0000 (11:46 +0200)] 
sunxi: Add CONFIG_MMC0_CD_PIN to various boards

Add CONFIG_MMC0_CD_PIN to various boards, this stops the SPL from still
trying to access the sdcard when there is none (e.g. when booting from
nand).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>