Jerry DeLisle [Sat, 11 Jul 2026 04:47:59 +0000 (21:47 -0700)]
fortran: [PR78718] ICE in gfc_get_symbol_decl, at fortran/trans-decl.c
PR fortran/78718
gcc/fortran/ChangeLog:
* resolve.cc (was_declared): Recognize the RESULT attribute so a
function's result variable is not mistaken for a host-associated
symbol of the same name.
I noticed that as of commit 7cb252f60c1f600066300ede2781a2c9e3808adb
"libgomp: Add by-device capabilities for OpenMP 'omp requires' handling",
'libgomp.fortran/reverse-offload-5.f90' no longer XFAILs NVIDIA GPU offloading
execution, no matter whether non-USM or USM single-GPU system. That was
suspicious, given that this commit shouldn't cause any such difference in
behavior, per my understanding. Well, turns out, this commit indeed didn't
magically fix the failure, but it's just another case of non-existing static
type checking of flag values...
James K. Lowden [Wed, 22 Jul 2026 17:43:46 +0000 (13:43 -0400)]
cobol: Accept ASSIGN TO DEVICE.
For SELECT fd-name ASSIGN TO dev, "dev" may name either a runtime
environment variable (as previously) or, as now, an
implementation-defined device. New warnings govern dialect
variations. Fixes RT 3617.
gcc/cobol/ChangeLog:
* cbldiag.h (enum cbl_diag_id_t): New warnings.
* cobol1.cc (cobol_langhook_handle_option): Process warnings.
* gcobol.1: Document warnings and devices.
* lang-specs.h: Accept warngings.
* lang.opt: Define warnings.
* messages.cc: Associate warnings with dialects.
* parse.y: Parse new syntax.
Jerry DeLisle [Tue, 21 Jul 2026 16:15:50 +0000 (09:15 -0700)]
fortran: [PR53296] Fix character array-ctor function called twice
Avoid the redundant generated call to the pre chain when
no_function_call is set.
Also fix a related stack-buffer-overflow: gfc_conv_array_parameter
wrote over the array constructor's. The specified length was to short.
Use the explicit character type-spec length instead.
PR fortran/53296
gcc/fortran/ChangeLog:
* trans-expr.cc (gfc_conv_procedure_call): Skip the redundant
function call added to the pre chain when no_function_call is
set and the character result length was already determined
without running the callee.
* trans-array.cc (gfc_conv_array_parameter): Convert an array
constructor's explicit character type-spec length directly
instead of using the first elements length.
Andrea Pinski [Tue, 21 Jul 2026 18:25:34 +0000 (11:25 -0700)]
Fix maintainer_utils.py for older jsonscheme [PR126162]
Some semi-older distros don't have a new enough jsonscheme
installed. So this moves the scheme to the older json scheme
rather than using the 2020 one.
PR testsuite/126162
contrib/ChangeLog:
* maintainer_utils.py: Move to the older scheme which
is valid for MAINTAINERS.yml.
Signed-off-by: Andrea Pinski <andrew.pinski@oss.qualcomm.com> Co-authored-by: Arsen Arsenović <aarsenovic@baylibre.com>
Split the movxo pattern into DMF and non-DMF variants.
Use DMF move instructions (dmxxinstdmr512, dmmr, and dmxxextfdmr512)
for accumulator/DMR moves while retaining the existing split for
non-DMR operands.
2026-07-15 Vijay Shankar <vijay@linux.ibm.com>
gcc/ChangeLog:
* config/rs6000/mma.md (*movxo): renamed to movxo_nodmf
(*movxo_nodmf): updated contraint to use wD and add !TARGET_DMF
(*movxo_dmf): New pattern to handle dmf insert/extract from vsx
rs6000: Add TDOmode reload patterns for DMR registers
Add define_insn_and_split patterns for reloading TDOmode values between
Dense Math Registers (DMRs) and memory when TARGET_DMF is enabled.
2026-07-15 Surya Kumari Jangala <jskumari@linux.ibm.com>
Peter Bergner <bergner@linux.ibm.com>
gcc:
* config/rs6000/mma.md (UNSPEC_DMR_RELOAD_FROM_MEMORY): New unspec.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(reload_tdo_load): New define_insn_and_split.
(reload_tdo_store): Likewise.
* config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Set
reload_load and reload_store for TDOmode when TARGET_DMF.
This patch
- Tweaks the signed overflow handling in __mulQ64_work.
- Rename misnomed fx24-mul.c to fx64-mul-1.c.
- Adds more test cases in fx64-mul-2.c.
libgcc/
* config/avr/lib1funcs-fixed.S (__mulQ64_work): Tweak
overflow handling. Use __negsi2 (non-saturating negation)
to negate.
gcc/testsuite/
* gcc.target/avr/fx24-mul.c: Renamed to...
* gcc.target/avr/fx64-mul-1.c: ...this.
* gcc.target/avr/fx64-mul-2.c: New test.
* gcc.target/avr/fx64-mul.h: New file.
testsuite: require cortex-a53 in reg_equal_test.c test
The original purpose of the test is to verify that, when the backend
emits a mov-pair sequence, the sequence carries a REG_EQUAL note for the
final constant value. Make that precondition explicit instead of
depending on target-specific tuning behavior, by forcing the test to
a CPU with the required properties.
gcc/testsuite/ChangeLog:
* gcc.target/arm/reg_equal_test.c: Add require effective target
cortex-a53 for test.
Jakub Jelinek [Wed, 22 Jul 2026 09:56:48 +0000 (11:56 +0200)]
libstdc++: Update Linux baselines for GCC 17.0
The following patch applies the powerpc64le-linux-gnu/baseline_symbols.txt
and x86_64-linux-gnu/baseline_symbols.txt r17-2579 changes to all
other linux arches which have recently updated baseline_symbols.txt
(i.e. those which have GLIBCXX_3.4.35 symbol version in it).
Those 3 symbols are architecture independent, they don't have any
size_t etc. argument that depends on the architecture, j (unsigned int) for
the last one is unsigned int on all arches.
On most the patch applied cleanly, on some (powerpc*/s390x*) I had to
manually resolve fuzz, as
FUNC:_ZNKSt16bad_array_length4whatEv@@CXXABI_1.3.8
there wasn't followed by
FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18
but some @@GLIBCXX_LDBL_3.4 symbols (which are _ZNKSt17* though, so the
two new comes alphabetically sorted before those).
libgomp: Add by-device capabilities for OpenMP 'omp requires' handling
Before the capabilities of a device were statically set to a generic
by-device-type value. This has been modified to additionally set them
to a value for a specific device.
On the plugin side, this permits to set the unified-shared memory
capability for only a subset of devices and to mark devices that are
integrated GPUs (APU) and support USM, which in turn permitted to move
the handling of OpenMP requirements from the plugin back to target.c
and permits in future to automatically enable unified-shared memory
for integrated GPUs/APUs.
The check for whether host memory can be accessed is for Nvidia GPUs
whether pageableMemoryAccess is supported (unchanged) and for AMD GPUs
whether SVM_ACCESSIBLE_BY_DEFAULT is supported (unchanged, global
property) and, if not, now also whether the device is an APU and
either XNACK is enabled or not supported by the hardware. For systems
with a single GPU, the result should be identical.
Note: The resulting capability is currently only used with
omp requires unified_shared_memory / self_maps
such that this flag is only set if the user code has this requirement
and all devices not supporting the host-memory access are filtered out.
Co-authored-by: Andrew Stubbs <ams@baylibre.com> Co-authored-by: supers1ngular <supers1ngular@baylibre.com>
include/ChangeLog:
Add move support for the new TDOmode opaque type used to represent
1024-bit Dense Math Registers that may be supported by future Power
processors.
Implement the movtdo pattern to support moves between memory, VSX
registers, and Dense Math Registers. Memory moves and VSX
register-to-register moves are handled by the generic multi-register
splitter. Dense Math Register-to-Register moves use dmmr, while moves
between VSX and Dense Math Registers are expanded using dm_insert1024
and dm_extract512.
gcc/
* config/rs6000/mma.md (UNSPEC_DMF_EXTRACT512): New unspec.
(dm_extract512): New insn.
(movtdo): New expander.
(*movtdo): New insn_and_split to support TDOmode moves between
memory, VSX registers, and Dense Math Registers.
* config/rs6000/rs6000.cc (rs6000_emit_move): Diagnose constant
assignments to TDOmode objects.
(rs6000_split_multireg_move): Handle TDOmode when splitting
multi-register moves.
rs6000: Build DMF accumulators using DMR insert operations
A future PowerPC processor may provide the Dense Math Facility (DMF),
where accumulators are backed by dedicated Dense Math Registers (DMRs).
Update accumulator assembly to build accumulators in DMRs using the new
DMR insert operations rather than xxmtacc/xxmfacc.
Add DMR register predicate support, enable the required OOmode VSX pair
patterns under TARGET_DMF, use accumulator operands for MMA accumulator
assembly and disassembly, and avoid emitting xxmtacc/xxmfacc during
internal accumulator moves and GIMPLE folding when DMF is enabled.
Add DMF instruction type and ISA attributes for instruction scheduling
and enablement.
2026-07-22 Kishan Parmar <kishan@linux.ibm.com>
gcc/
* config/rs6000/mma.md (UNSPEC_DMF_INSERT512): New unspec.
(UNSPEC_DMF_INSERT1024): Likewise.
(movoo): Enable for TARGET_DMF.
(*movoo): Likewise.
(vsx_assemble_pair): Likewise.
(*vsx_assemble_pair): Likewise.
(vsx_disassemble_pair): Likewise.
(*vsx_disassemble_pair): Likewise.
(dm_insert512): New insn.
(dm_insert1024): Likewise.
(mma_assemble_acc): Use accumulator_operand.
Build accumulators via DMR insert operations when TARGET_DMF.
(*mma_assemble_acc): Use accumulator_operand.
(mma_<acc>): New define_expand treating xxmtacc/xxmfacc as no-ops
for TARGET_DMF.
(*mma_<acc>): Restrict to !TARGET_DMF and use accumulator_operand.
(mma_disassemble_acc): Use accumulator_operand.
* config/rs6000/predicates.md (dmr_register_operand): New predicate.
(gpc_reg_operand): Accept DMR registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do
not emit xxmfacc for DISASSEMBLE_ACC when TARGET_DMF.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Allow
OOmode in VSX register pairs for TARGET_DMF.
(rs6000_split_multireg_move): Avoid emitting xxmtacc/xxmfacc when
TARGET_DMF.
* config/rs6000/rs6000.md (type): Add dmf type.
(isa): Add mma and dmf ISA attributes.
(enabled): Add mma and dmf enable conditions.
gcc/testsuite/
* gcc.target/powerpc/dmf-xxacc.c: New test.
* gcc.target/powerpc/nodmf-xxacc.c: New test.
Juergen Christ [Tue, 10 Feb 2026 13:13:03 +0000 (14:13 +0100)]
s390x: Implement vec_cbranch_{all,any}
This enables early-exit vectorization on s390x.
Adjust the test suite since s390x does not support variable length
vectors and only supports basic vector load schemes.
gcc/ChangeLog:
* config/s390/s390-protos.h (s390_expand_vec_compare_gen_cc):
New function.
* config/s390/s390.cc (s390_expand_vec_compare_cc): Extract
part of this function into a ...
(s390_expand_vec_compare_gen_cc): ... new function.
* config/s390/vector.md (vec_cbranch_any<mode>): Implement.
(vec_cbranch_all<mode>): Implement.
rs6000: Add %wD constraint and predicate for accumulators
The future processor may introduce new set of registers for
accumulators. This patch adds a constraint and predicate for the
accumulator registers which can be used by the dense math and mma
patterns.
rs6000: Add support for Dense Math Facility (DMF) registers
The Dense Math Facility, which may be present in a future processor,
extends the Power architecture's computational capabilities by providing
eight dedicated registers (dmr0-dmr7) that can efficiently handle large
matrix operations. These registers will also be used in cryptographic
operations.
There are no operations to load/store Dense Math registers from/to
memory. For loading from memory, the 1024 bit value is first loaded into
8 VSX registers which are then copied into a DMR register. Similarly,
to store the contents of a DMR register into memory, the the contents
of the DMR are copied to 8 VSX registers which are then loaded into
memory.
Key Features:
1. Register Infrastructure:
- Adds 8 new DMR registers (dmr0-dmr7), numbered 111-118
- Each register is 1024 bits (128 bytes) in size
- Registers are call-used (caller-saved) following ABI conventions
- Increases total pseudo registers from 111 to 119
2. Data Type Support:
- TDOmode: New 1024-bit mode specifically for DMR operations
- XOmode: Extended to support both MMA accumulators (in FPRs) and
DMR registers, providing flexibility in register allocation
- Both modes support DMR registers when TARGET_DMF is enabled
- TDOmode and XOmode excluded from register tying to prevent
incorrect cross-class allocation
3. Register Allocation:
- Integrated DMR_REGS into the register class hierarchy
- Added to register pressure classes for optimal allocation
- Implements proper register allocation ordering
- DMR registers can be allocated for XOmode and TDOmode values
4. Addressing and Memory Operations:
- Supports offset addressing mode for TDOmode values
- Implements secondary reload mechanisms for DMR ↔ VSX transfers
- New rs6000_dmr_register_move_cost helper computes move costs
between a DMR register and any register class via VSX:
XOmode costs 2, TDOmode costs 4, other modes scale by nregs
- Ensures proper alignment requirements (vector alignment)
- rs6000_register_move_cost and rs6000_memory_move_cost extended
to handle DMR_REGS as source or destination
5. Register Moves and Transfers:
- Enables simple moves between DMR and VSX registers
6. Debugging and Toolchain Support:
- Assigns debugger register numbers 112-119 for DMR registers
Fold `(x == CST) ? x : CST` and `(x != CST) ? CST : x` to `CST` for
integral scalar and vector types. This catches cases where earlier
folding has converted bitwise mask expressions into conditional selects,
including ARM MVE predicate-to-vector mask forms.
James K. Lowden [Tue, 21 Jul 2026 19:41:21 +0000 (15:41 -0400)]
cobol: Enable Bison parser stack growth.
Work around a Bison error when compiling C output with a C++ compiler.
Although the Bison manual states that a user-defined location type
must be trivially copyable, it nevertheless normally does not emit
stack-growth logic if __cplusplus is defined to the preprocessor.
Consequently a large program that drives the stack above 200 elements
aborts with a "memory exhausted" error.
To enable stack growth, define the undocumented YYLTYPE_IS_TRIVIAL
variable. Use a static assert to ensure the type meets the
requirement.
A patch was submitted to the Bison project that hopefully will make
this workaround unnecessary sometime mid-century.
Which is nice, but the whilelo in the pre-header is unneeded. Due to the
architecturally defined minimum and maximum vector lengths[1] we know that at
any vector length the predicate is an all lanes active predicate, i.e. p7 is
always ptrue.
We can use gimple-isel these days while we still have range information on
the operands of .WHILE_ULTs to do this folding.
As such this patch folds whenever possible WHILE_ULTs into ptrue which are
cheaper to execute and so lowers our costs for entering the loops. i.e. the
above generates:
Tamar Christina [Tue, 21 Jul 2026 19:48:39 +0000 (20:48 +0100)]
AArch64: Move SVE ptrue VL folding helpers
The 3rd patch in this series will modify these functions, but I have to re-order
and extract some shared functionality to avoid duplicate and having to forward
declare stuff.
I thus separated out the refactoring bit from the parts that use and change
these functions.
The successive modifications made to 'xtensa_legitimize_address()' have
worsened the readability of the code, and the modifications themselves
are difficult to understand.
Therefore, this patch resolves these issues by completely rewriting the
function to make its intent clear.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_legitimize_address):
Completely rewrite it into an equivalent but more easily under-
standable description.
When the Windowed Register Option (TARGET_WINDOWED_ABI) is enabled, and this
macro is not defined, "phantom" DF livenesses occurs in the function epilogue,
which can hinder certain optimizations. Indeed, in the following example,
the low-overhead loop optimization is rejected because the epilogue BB, which
succeeds the target loop BB, is incorrectly identified as using the loop
iterator.
/* example */
void test(char *q, const char *p, unsigned int n) {
do
*q = *p, ++q, ++p;
while (n-- != 1);
}
Tamar Christina [Tue, 21 Jul 2026 19:46:33 +0000 (20:46 +0100)]
vect: replace usages of SLP_TREE_SCALAR_SMTS where possible
Continuing the work started in GCC 12 with g:a0dae768c6f78eba
this patch replaces uses of SLP_TREE_SCALAR_STMTS with SLP_TREE_LANES when used
to determine the number of lanes in the SLP tree. This de-couples the need to
have the same number of scalar statements as lanes in the SLP tree.
gcc/ChangeLog:
* tree-vect-slp-patterns.cc (compatible_complex_nodes_p): Support
mismatched group sizes and use group size to iterate.
* tree-vect-slp.cc (vect_build_slp_instance,
vect_analyze_slp_reduc_chain, vect_analyze_slp_reduction,
vect_analyze_slp_reduction_group, vect_analyze_slp_instance,
vect_analyze_slp): Compare against lanes instead of .length ().
(vect_optimize_slp_pass::get_result_with_layout): replace .length ()
with .exist ().
(vect_transform_slp_perm_load_1): Use lanes instead of .length ().
(vect_remove_slp_scalar_calls): Replace iterators.
* tree-vect-stmts.cc (vectorizable_shift): Use group size over ops
length.
Thomas Koenig [Tue, 21 Jul 2026 17:04:48 +0000 (19:04 +0200)]
Fix a few false positive warnings with unused/undefined warnings.
Trying out the new warnings on actual code found a new false positives.
The charlen of an ALLOCATE was not marked as used, the expression
in SELECT CASE was not marked as used and host-associated variables
were not exempt from testing.
All fixed with the attached patch.
gcc/fortran/ChangeLog:
PR fortran/126333
* resolve.cc (resolve_allocate_deallocate): Resolve charlen of ts
and set as used if present.
(resolve_select): Mark code->expr1 as used.
(find_unused_vs_set): Do not complain about host-associated
variables which are not marked private.
gcc/testsuite/ChangeLog:
PR fortran/126333
* gfortran.dg/warn_undefined_vars_8.f90: New test.
* gfortran.dg/warn_undefined_vars_9.f90: New test.
* gfortran.dg/warn_unused_but_set_variable_5.f90: New test.
Add a new %W print modifier to print_operand that prints the VSX
register number plus two.
Some future Power instruction patterns require printing two VSX
registers corresponding to a __vector_pair operand. The existing
%x print modifier emits the first VSX register using VSX register
numbering. Add a new %W print modifier to emit the second VSX
register of the pair.
Pan Li [Mon, 20 Jul 2026 05:38:42 +0000 (13:38 +0800)]
RISC-V: Add test cases for vfwcvt.f.xu.v reg overlap overlap
Add test cases for vfwcvt.f.xu.v register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c: New test.
Pan Li [Mon, 20 Jul 2026 05:35:43 +0000 (13:35 +0800)]
RISC-V: Add test cases for vfwcvt.f.x.v reg overlap
Add test cases for vfwcvt.f.x.v register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c: New test.
out-of-SSA: Preserve storage for split partition decls [PR126341]
create_tmp_var_raw marks a replacement declaration as ignored. At -O0,
this can change use_register_for_decl from memory for the original user
declaration to a pseudo for the replacement. A partition can already own
memory from a parameter default definition, which then makes set_rtl reject
that memory for another name in the partition.
If the replacement would use a register, copy DECL_IGNORED_P so it keeps the
storage choice made during coalescing. Keep declarations that already use
memory unchanged. Add a checking assertion for the memory invariant.
Bootstrapped and tested on aarch64-none-linux-gnu and x86_64-linux.
gcc/ChangeLog:
PR middle-end/126341
* tree-outof-ssa.cc (split_overlapping_partition_decls): Preserve
DECL_IGNORED_P. Check that the replacement uses memory.
gcc/testsuite/ChangeLog:
PR middle-end/126341
* gcc.dg/pr126341.c: New test.
AVR: Add 64-bit fixed-point multiplications to libgcc.
This patch adds (un)saturated 64-bit fixed-point multiplications
to libgcc. The saturating functions are just aliases of the
vanilla versions, which are also saturating.
Roger Sayle [Tue, 21 Jul 2026 08:45:15 +0000 (09:45 +0100)]
i386: Split DI<->V2DI patterns before reload with -m32.
While investigating improvements to x86's stv2 pass (to correctly cost
moves between SI<->V4SI and DI<->V2DI), I noticed that we're currently
relatively inefficient for DI mode transfers on 32-bit targets with
SSE2, where reload ultimately decides to perform these moves via the
stack. It's possible to do better by making the highpart and lowpart
registers explicit before reload.
Consider the test case below:
typedef long long v2di __attribute__ ((__vector_size__ (16)));
long long foo(v2di x)
{
return x[0];
}
long long ext();
v2di mem;
void bar()
{
long long x = ext();
mem = (v2di){x,0};
}
where foo tests V2DI->DI mode, and bar tests DI->V2DI mode.
Currently -m32 -O2 -msse2 generates:
bar: subl $12, %esp
call ext
movd %eax, %xmm0
movd %edx, %xmm1
punpckldq %xmm1, %xmm0
movaps %xmm0, mem
addl $12, %esp
ret
2026-07-21 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
gcc/ChangeLog
* config/i386/sse.md (define_split): Split *vec_extractv2di_0_sse
before reload on !TARGET_64BIT with TARGET_SSE2.
(define_split): Likewise split *vec_concatv2di_0 before reload
on !TARGET_64BIT with TARGET_SSE2.
gcc/testsuite/ChangeLog
* gcc.target/i386/sse2-stv-7.c: New test case.
* gcc.target/i386/sse4_1-stv-13.c: Likewise.
Tomasz Kamiński [Mon, 20 Jul 2026 09:53:48 +0000 (11:53 +0200)]
libstdc++: Introduce GLIBCXX_3.4.37 version for symbols not backported to GCC-16.
As part of the backport of r17-471-ge79f0f818c0e42 and r17-2193-g50cbacfaa1e776),
the corresponding exports of chrono::__detail::__recent_leap_second_info and
specializations of basic_format_arg::_M_handle_unrecognized also need to be
introduced. This also require bump of the libtool_VERSION to 3.4.36.
This patch bumps version again to 3.4.37 and moves remaining symbols defined
in GCC 17 (basic_string's _S_allocate_at_least and _M_create_plus) to it.
libstdc++-v3/ChangeLog:
* acinclude.m4 (libtool_VERSION): Bump version.
* config/abi/pre/gnu.ver (GLIBCXX_3.4.37): Add new symbol
version and move basic_string's _S_allocate_at_least and
_M_create_plus symbols to it.
* config/abi/post/x86_64-linux-gnu/baseline_symbols.txt:
Regenerate and include new 3.4.36 symbols.
* config/abi/post/powerpc64le-linux-gnu/baseline_symbols.txt:
Likewise.
* configure: Regenerate.
* testsuite/util/testsuite_abi.cc: Update known_versions
and latestp.
Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Signed-off-by: Tomasz Kamiński <tkaminsk@redhat.com>
H.J. Lu [Wed, 13 May 2026 00:27:50 +0000 (08:27 +0800)]
x86: Don't set cum->preserve_none_abi for x86-64 MS calls
In 64-bit mode, preserve_none attribute uses the same number of integer
parameters passed in registers as SYSV ABI, but with a different set of
6 registers, by setting cum->preserve_none_abi to true. Don't set
cum->preserve_none_abi to true for MS ABI functions with preserve_none
attribute to keep the number of integer parameters passed in registers
unchanged as 4. This treats preserve_none attribute the same way as
no_callee_saved_registers attribute for MS ABI functions.
gcc/
PR target/125297
* config/i386/i386.cc (init_cumulative_args): Don't set
cum->preserve_none_abi to true for MS ABI functions.
* doc/extend.texi: Update x86-64 preserve_none attribute
documentation.
Jakub Jelinek [Mon, 20 Jul 2026 21:32:40 +0000 (23:32 +0200)]
c++: implement CWG3020 - Missing specification for __has_cpp_attribute(indeterminate) [PR126309]
The paper which introduced indeterminate attribute has not added a value
for __has_cpp_attribute, so I've missed it and didn't add it to
c_common_has_attribute. Later CWG issue fixed this up.
chris hermansen [Mon, 20 Jul 2026 16:42:15 +0000 (18:42 +0200)]
a68: new version of proc whole, dependencies and test
A replacement for proc whole provided in the Revised Report on p.159.
Several factors motivated me to propose this replacement for the RR code.
Most importantly, the RR whole fails for an argument value of -max_int - 1, as
well as any short short, short, long or long long equivalents, because the RR
version applies the operator ABS to the argument, and on any hardware using
twos-complement representation, ABS (-max_int - 1) cannot provide a correct
positive value. This replacement code does not apply ABS to the argument and
is therefore immune to this problem.
As well, replacement works on the argument from left to right, rather than
right to left (the approach taken in the RR version). Working from left to
right in this way requires either:
- processing all 10 digits (speaking of 32 bit integers for the time being),
meaning worthless effort for every leading zero digit, or
- determining how many significant digits there are, which means some lookup
code (I believe this is faster but I haven't benchmarked it at this point)
Having determined beforehand how many significant digits there are, we can
allocate a working buffer of exactly the right length, which eliminates:
- the (expensive) digit-by-digit string concatenation approach used in the RR
version
- the need to always ensure a long-enough fixed-length buffer should GNU Algol
68 begin to support longer integers (128, 256, whatever)
- the need to trim a fixed-length buffer to the desired length once the
converted integer is in place
Finally, working left to right
- eliminates the need to apply ABS to the number to be converted, as noted
previously, thereby eliminating the dependency on ABS
- replaces one (expensive) integer division with one (less expensive)
integer multiplication using a looked-up power of 10
van Vliet's proposed whole and subwhole are more efficient than the RR version,
but still depend on ABS delivering a correct value.
Included with this replacement proc whole is a test program to ensure that the
correct results for the extreme values are produced, along with a set of
randomly chosen other values distributed across the range.
Signed-off-by: Chris Hermansen <clhermansen@gmail.com>
libga68/ChangeLog
* standard.a68.in (Integer): New mode.
(whole_max_entry): New variable.
(whole_p10): Likewise.
(whole_stop_after): Likewise.
(whole_powers_of_10): Likewise.
(WHOLEDIGITS): New operator.
(whole): Rewrite.
(subwhole): Likewise.
bpf: TARGET_RTX_COSTS: treat 32-bit CONST_INT as cheap/free
This is to prefer constant return to be setup from imm constant vs.
using a prior reg known to have the same value (by control flow analysis).
While there's nothing wrong with existing approach, it can sometimes leads
to additional sign-extensions and other corner cases which trip up the
bpf kernel verifier bounds checking for return reg.The verifier improvements
are being worked on but lets adjust the cost model anyways so that constants
are favored. There's no additional overhead from new codegen anyways.
* config/bpf/bpf.cc (bpf_rtx_costs): set CONST_INT 0 insns.
* config/bpf/bpf.h (BPF_IMM32_P): New helper macro.
* config/bpf/predicates.md (imm32_operand): Use new macro.
gcc/testsuite/ChangeLog:
* gcc.target/bpf/const-cost-model.c: New test prefers const.
* gcc.target/bpf/const-cost-model-2.c: New test prefers const.
The default cost of MULT/DIV/MOD in rtx_cost () is high: 5,7 insns
respectively. This causes even a trivial mpy by 7 to be synthesized.
Given these have direct equivalents in BPF ISA, fix the cost to generate
native BPF insns.
Note the existing divmod-licall-2.c test was a bit fragile as it forced
cast signed an actual unsigned int which is provably non-negative.
In the new cost model compiler would generate a native unsigned divide
even though it not available for -mcpu=v3, tripping up the test.
Fix by ensuring the arg is actually signed.
Robert Dubner [Mon, 20 Jul 2026 17:17:25 +0000 (13:17 -0400)]
cobol: Insert "Do not edit" text into generated DejaGNU tests.
The tests in gcc/testsuite/cobol.dg/group2 are created by a script from a
larger set of autotest tests. After a brief comedy of procedural errors, we
decided to incorporate "Do not edit" comments into those tests.
Jakub Jelinek [Mon, 20 Jul 2026 17:27:23 +0000 (19:27 +0200)]
passes: Make gcc buildable again with mawk <= 1.3.3
On Wed, Jul 15, 2026 at 12:49:50PM -0400, Nathan Sidwell wrote:
> Fair enough, I committed this
Unfortunately it seems some versions of Debian/Ubuntu use mawk instead
of gawk by default, and mawk pretends to be POSIX compatible, but at least
versions <= 1.3.3 didn't support POSIX character classes.
We don't really need the various UTF-8 fancy blanks, and even this very
own script already uses sub(/^[ \t]*/, "", arg3); elsewhere, so this
patch just replaces [[:blank:]] with [ \t].
2026-07-20 Jakub Jelinek <jakub@redhat.com>
* gen-pass-instances.awk: Use [ \t] instead of [[:blank:]]
for compatibility with mawk <= 1.3.3.
Mikael Morin [Wed, 15 Jul 2026 15:29:38 +0000 (17:29 +0200)]
fortran: Use the setter to update the descriptor data field
A MODIFY_EXPR was generated manually using the data reference returned by
the getter. Just use the setter instead. Fixed in two different places.
gcc/fortran/ChangeLog:
* trans-expr.cc (gfc_conv_class_to_class): Use the data setter
instead of generating a MODIFY_EXPR of the result of the data
getter.
* trans-intrinsic.cc (conv_intrinsic_move_alloc): Likewise.
Fortran, OpenMP: Consolidate iterator group start/finish code
This patch consolidates some repetitive code from gfc_trans_omp_clauses
into new functions, and adds some comments. There are no functional
changes.
gcc/fortran/ChangeLog
* trans-openmp.cc (handle_iterator): Add comments. Rename
iter_block parameter to outer_block, since that's what's actually
being passed; the start/end/step expressions are outside the scope
of the iterator variables.
(start_iterator_group, finish_iterator_group): New functions,
broken out from...
(gfc_trans_omp_clauses): ...here.
Alex Coplan [Fri, 17 Jul 2026 17:40:52 +0000 (18:40 +0100)]
aarch64: Fix up TME deprecation warning
This is a follow-up patch to Richard E's r17-2498-g17f084306c68c4 (#186
on the Forge). As Alice pointed out in her review:
https://gcc.gnu.org/pipermail/gcc-patches/2026-July/724391.html
the original patch missed things like +memtag+tme due to the string
parsing approach. This instead just inspects the parsed feature flags
from aarch64_parse_extension to determine whether to warn in the target
attribute/pragma case.
+tme on the command line is handled as per Richard's original patch (no
change there).
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_handle_attr_isa_flags):
Warn if +tme is enabled by the target attribute/pragma, relying
on the feature flags from aarch64_parse_extension.
(aarch64_process_target_attr): Drop +tme warning based on custom
string parsing.
testsuite: arm: remove xfail for MVE, NEON and thumb1 [PR124364]
On MVE or NEON capable targers and thumb1 targets, I see these:
XPASS: gcc.dg/Wstringop-overflow-47.c pr97027 (test for warnings, line 72)
XPASS: gcc.dg/Wstringop-overflow-47.c pr97027 (test for warnings, line 77)
XPASS: gcc.dg/Wstringop-overflow-47.c pr97027 note (test for warnings, line 68)
Replace the 5-argument OMPT dispatch builtins and libgomp implementations
(niter, start, incr, chunk_size, istart) with a 2-argument form (start,
iterations) describing the chunk actually being dispatched, which is all the
information OMPT needs.
GOMP_scope_start is emitted only for task reductions without -fopenmp-ompt
(unchanged). With -fopenmp-ompt, both GOMP_scope_start_with_end and
GOMP_scope_end are emitted, whether a task reduction is specified or not.
gcc/ChangeLog:
* omp-builtins.def (BUILT_IN_GOMP_SCOPE_START_WITH_END): New
builtin.
(BUILT_IN_GOMP_SCOPE_END): Likewise.
* omp-low.cc (lower_omp_scope): Emit calls to
GOMP_scope_start_with_end and GOMP_scope_end when -fopenmp-ompt.
libgomp/ChangeLog:
* libgomp.map: Add GOMP_scope_start_with_end and GOMP_scope_end.
* libgomp_g.h (GOMP_scope_start_with_end): Declare.
(GOMP_scope_end): Likewise.
* scope.c (GOMP_scope_start_with_end): New function.
(GOMP_scope_end): New stub.
gcc/testsuite/ChangeLog:
* c-c++-common/gomp/scope-7.c: New test.
* c-c++-common/gomp/scope-8.c: New test.
testsuite: skip test for targets that can deref null [PR126261]
As arm-none-eabi targets might have readable memory at address 0,
g++.dg/torture/pr101373.C test will "work" on some targets, while others
might tigger a fault. To avoid the ambiguity, lets skip the test if
target allows null to be dereferenced.
testsuite: arm: xfail crypto tests for -mthumb -mfloat-abi=hard [PR124043]
In r15-1579-g792f97b44ffc5e, a new late-combine pass was introduced that
changes the generated assembler from
ldr r3, [sp]
vdup.32 q8, r3
to
vld1.32 {d16[], d17[]}, [sp]
with -mthumb -mfloat-abi=hard. Due to this changed, the check
Here we have a redundant sign extension and inefficient address arithmetic.
This can be simplified into two instructions, a load and a return.
The lw insn is already doing a sign extension from 32 to 64 bits, making
the separate sext.w unnecessary. Adding a copy of the pattern that
explicitly shows the sign extension in the RTL, with the modes adjusted
accordingly, no longer emits the sext.w insn. I also generalized the pattern to
support both sign and zero extension. These changes have been reflected
on the total store ordering memory consistency model as well. As Zalrsc
doesn't support zero extending load-acquire instructions, I introduced a new
iterator, ensuring zero extend is limited to !TARGET_ZALRSC for load.
The addi and lw are combined into lw a0,4(a5) by adjusting the memory
operand constraint to handle offsets in the load patterns. The validity of
the memory operand constraint depends on the value of operand 2 - the
memory model. I introduced new constraint alternatives, such that the
behavior of the memory operand constraint is triggered on whether the
memory model acquire is being used or not and the Zalrsc or non-Zalrsc
targets accordingly. Similar changes were made for the store patterns
where the inefficient address arithmetic problem was also present.
PR target/124741
gcc/
* config/riscv/constraints.md (B1, B2, B3, B4): New constraints for
atomic loads with and without ZALASR & MEMMODEL_ACQUIRE.
* config/riscv/iterators.md (cond_extend): New iterator to for use
in extending atomic loads.
* config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Adjust
contraints to enable folding small offsets into memory load.
(atomic_store_rvwmo): Likewise.
(extending atomic_load_rvwmo): New pattern.
* config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Adjust
constraints to enable folding small offsets into memory load.
(atomic_store_ztso): Likewise.
(extending atomic_load_ztso): New pattern.
gcc/testsuite/
* gcc.target/riscv/load-zalasr.c: Testcases for atomic load compiled
with rv64 and zalasr ext.
* gcc.target/riscv/load.c: Testcases for atomic load compiled with
rv64.
* gcc.target/riscv/load32-zalasr.c: Testcases for atomic load
compiled with rv32 and zalasr ext.
* gcc.target/riscv/load32.c: Testcases for atomic load compiled with
rv32.
* gcc.target/riscv/store-zalasr.c: Testcases for atomic store
compiled with rv64 and zalasr ext.
* gcc.target/riscv/store.c: Testcases for atomic store compiled
with rv64.
* gcc.target/riscv/store32-zalasr.c: Testcases for atomic store
compiled with rv32 and zalasr ext.
* gcc.target/riscv/store32.c: Testcases for atomic store compiled
with rv32.
Co-authored-by: Jeff Law <jeffrey.law@oss.qualcomm.com>
When two adjacent Zone lines have different total offsets and the
new line's rule set has a rule firing within jump of the boundary
(where jump = old_total - new_total > 0, i.e. local time goes
backward at the boundary), zic folds that rule into the boundary
itself: the single transition emitted has the rule's save value
already applied, so the new line begins with the post-rule save
rather than briefly using the pre-rule save and then transitioning
again moments later.
Canonical examples handled by the new merge block:
* America/Argentina/Buenos_Aires 1999-10-03: lines change
stdoff -3 → -4 with an Argentina DST rule firing on the same
day. Without the merge, chrono emits a 1-hour stretch of
offset=-4 save=0 and then transitions to offset=-3 save=1;
with the merge, the boundary itself is at offset=-3 save=1.
* Europe/Berlin 1945-05-24: lines split a rule set, with the
So 1945-May-24 rule (save=2, "CEMT") firing at 01:00 UTC in
the new frame, inside the 1h backward window.
Similarly, when the zone expansion algorithm is resumed after DST
span (save = 1h), we will revisit the corresponding STD transition,
for example: given offset +2h, the transition happening at 12:00
local time, will be considered twice:
* 09:00 UT (2h + 1h) - proper ending of DST span
* 10:00 UT (2h) - after re-entry.
Previously this transition were rejected using the (now removed)
rule_start - t < days(1) check, preventing us from emitting the one
hour STD time range followed by rest of same range. In this patch,
we reuse same merge logic, as such STD transition happens during
backward jump from boundary introduced by previous expansion.
This patch address both of the above by computing length of the
backward jump (merge_window) at the start of the expansion (regardless
if initial or re-entry), and then considering initial rule transition
happening in [info.begin + merge_window] to apply at info.begin.
libstdc++-v3/ChangeLog:
PR libstdc++/124854
* src/c++20/tzdb.cc (ZoneInfo::save): Define.
(time_zone::_M_get_sys_info): Fold initial transition if they
occurs in duplicated local time window (merge_window) due move
from DST to STD zone.
* testsuite/std/time/time_zone/wall_cascade.cc (test_next_year):
Test that 1945 Pacific/Auckland transition is properly handled.
(test_negative): Adjust test to avoid zone merge.
* testsuite/std/time/time_zone/zone_merge.cc: New test.
Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Co-authored-by: Álvaro Begué <alvaro.begue@gmail.com> Signed-off-by: Álvaro Begué <alvaro.begue@gmail.com> Signed-off-by: Tomasz Kamiński <tkaminsk@redhat.com>
Mikael Morin [Mon, 20 Jul 2026 09:09:33 +0000 (11:09 +0200)]
fortran: array descriptor: Rename dim subfields internal accessors [PR122521]
Drop the gfc prefix from the internal function giving access to the lbound,
ubound, and stride fields. This aligns the function names with the rest of
the compiler dropping the prefix for static functions.
Mikael Morin [Mon, 20 Jul 2026 09:09:22 +0000 (11:09 +0200)]
fortran: array descriptor: Add a setter for the token field [PR122521]
Add a setter function to set the value of the token field of array
descriptors.
Contrary to the preceding patches touching the other fields, this one
doesn't create a getter and retains direct access to the field. Indeed,
token is special because its address is taken and passed to library
functions to implement coarray behaviour.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_token_set): New function.
* trans-descriptor.h (gfc_conv_descriptor_token_set): New
declaration.
* trans-array.cc (gfc_conv_expr_descriptor,
gfc_conv_array_parameter, gfc_trans_deferred_array): Use
gfc_conv_descriptor_token_set to set the value of the token.
* trans-expr.cc (gfc_conv_derived_to_class,
gfc_trans_subcomponent_assign, gfc_trans_scalar_assign): Likewise.
* trans-intrinsic.cc (conv_intrinsic_move_alloc): Likewise.
Mikael Morin [Mon, 20 Jul 2026 09:09:11 +0000 (11:09 +0200)]
fortran: array descriptor: Remove access to dim field elements [PR122521]
Remove from the public API the function giving direct acces to individual
dimension descriptors. Another function remains giving access to the full
array of dimension descriptors.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_dimension): Make static
and rename ...
(conv_descriptor_dimension): ... to this.
(gfc_conv_descriptor_subfield): Update caller.
* trans-descriptor.h (gfc_conv_descriptor_dimension): Remove
declaration.
Mikael Morin [Mon, 20 Jul 2026 09:08:51 +0000 (11:08 +0200)]
fortran: array descriptor: Add accessors for the dtype field [PR122521]
Use accessor functions to get or set the dtype field of array descriptors
and remove from the public API the function giving direct acces to the
field.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_dtype): Make static and
rename ...
(conv_descriptor_dtype): ... to this.
(conv_descriptor_rank conv_descriptor_version,
conv_descriptor_elem_len, gfc_conv_descriptor_attribute,
conv_descriptor_type): Update callers.
(gfc_conv_descriptor_dtype_get, gfc_conv_descriptor_dtype_set):
New functions.
* trans-descriptor.h (gfc_conv_descriptor_dtype): Remove
declaration.
(gfc_conv_descriptor_dtype_get, gfc_conv_descriptor_dtype_set):
New declarations.
* trans-array.cc (gfc_trans_create_temp_array, gfc_array_init_size,
gfc_conv_expr_descriptor, gfc_resize_assumed_rank_dim_field,
gfc_conv_array_parameter, structure_alloc_comps,
gfc_alloc_allocatable_for_assignment, gfc_trans_class_array,
gfc_trans_deferred_array): Use gfc_conv_descriptor_dtype_get to get
the value of the dtype field and gfc_conv_descriptor_dtype_set to
update it.
* trans-decl.cc (gfc_conv_cfi_to_gfc): Likewise.
* trans-expr.cc (gfc_conv_scalar_to_descriptor,
gfc_class_array_data_assign, gfc_conv_derived_to_class,
gfc_conv_class_to_class, set_dtype_for_unallocated,
gfc_trans_pointer_assignment, fcncall_realloc_result): Likewise.
* trans-intrinsic.cc (conv_isocbinding_subroutine): Likewise.
* trans-stmt.cc (trans_associate_var): Likewise.
Mikael Morin [Mon, 20 Jul 2026 09:08:40 +0000 (11:08 +0200)]
fortran: array descriptor: Add accessors for the type field [PR122521]
Add accessor functions to get or set the value of the type field of array
descriptors, and remove from the public API the function giving direct acces
to the field.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (get_type_field): New function.
(gfc_get_descriptor_field): Use it.
(gfc_conv_descriptor_type): Make static and rename ...
(conv_descriptor_type): ... to this.
(gfc_conv_descriptor_type_get, gfc_conv_descriptor_type_set): New
functions.
* trans-descriptor.h (gfc_conv_descriptor_type): Remove declaration.
(gfc_conv_descriptor_type_get, gfc_conv_descriptor_type_set): New
declarations.
* trans-expr.cc (gfc_conv_gfc_desc_to_cfi_desc): Use
gfc_conv_descriptor_type_get to get the value of the type field.
* trans-decl.cc (gfc_conv_cfi_to_gfc): Use
gfc_conv_descriptor_type_set to set the value of the type field.
Mikael Morin [Mon, 20 Jul 2026 09:08:29 +0000 (11:08 +0200)]
fortran: array descriptor: Add accessors for the rank field [PR122521]
Add accessor functions to get or set the value of the rank field of array
descriptors, and remove from the public API the function giving direct acces
to the field.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_rank): Make static and
rename ...
(conv_descriptor_rank): ... to this.
(gfc_conv_descriptor_rank_get, gfc_conv_descriptor_rank_set): New
functions.
* trans-descriptor.h (gfc_conv_descriptor_rank): Remove declaration.
(gfc_conv_descriptor_rank_get, gfc_conv_descriptor_rank_set): New
declarations.
* trans-array.cc (gfc_trans_create_temp_array,
gfc_conv_ss_startstride, gfc_tree_array_size,
gfc_resize_assumed_rank_dim_field, gfc_conv_array_parameter,
gfc_full_array_size, duplicate_allocatable_coarray): Use
gfc_conv_descriptor_rank_get to get the value of the rank field,
and gfc_conv_descriptor_rank_set to set it.
* trans-decl.cc (gfc_conv_cfi_to_gfc): Likewise.
* trans-expr.cc (gfc_conv_derived_to_class, gfc_conv_variable,
gfc_conv_gfc_desc_to_cfi_desc, conv_null_actual,
gfc_trans_structure_assign): Likewise.
* trans-intrinsic.cc (gfc_conv_intrinsic_rank,
gfc_conv_intrinsic_bound, gfc_conv_intrinsic_sizeof,
gfc_conv_associated): Likewise.
* trans-openmp.cc (gfc_omp_get_array_size): Likewise.
* trans-stmt.cc (gfc_trans_select_rank_cases): Likewise.
Mikael Morin [Mon, 20 Jul 2026 09:08:15 +0000 (11:08 +0200)]
fortran: array descriptor: Add accessors for the version field [PR122521]
Add accessor functions to get or set the value of the version field of array
descriptors, and remove from the public API the function giving direct acces
to the field.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_version): Make static and
rename ...
(conv_descriptor_version): ... to this.
(gfc_conv_descriptor_version_get, gfc_conv_descriptor_version_set):
New functions.
* trans-descriptor.h (gfc_conv_descriptor_version): Remove
declaration.
(gfc_conv_descriptor_version_get, gfc_conv_descriptor_version_set):
New declarations.
* trans.cc (gfc_deallocate_with_status): Use
gfc_conv_descriptor_version_get to get the value of the version
field, and gfc_conv_descriptor_version_set to set it.
* trans-array.cc (gfc_array_allocate, structure_alloc_comps,
gfc_alloc_allocatable_for_assignment): Likewise.
Mikael Morin [Mon, 20 Jul 2026 09:07:59 +0000 (11:07 +0200)]
fortran: array descriptor: Add accessors for the elem_len field [PR122521]
Add accessor functions to get or set the value of the elem_len field of
array descriptors, and remove from the public API the function giving direct
acces to the field.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_elem_len): Make static
and rename ...
(conv_descriptor_elem_len): ... to this.
(gfc_conv_descriptor_elem_len_get,
gfc_conv_descriptor_elem_len_set): New functions.
* trans-descriptor.h (gfc_conv_descriptor_elem_len): Remove
declaration.
(gfc_conv_descriptor_elem_len_get,
gfc_conv_descriptor_elem_len_set): New declarations.
* trans-decl.cc (gfc_conv_cfi_to_gfc): Use
gfc_conv_descriptor_elem_len_get to get the value of the elem_len
field and gfc_conv_descriptor_elem_len_set to set it.
* trans-array.cc (gfc_array_init_size,
gfc_alloc_allocatable_for_assignment): Likewise.
* trans-expr.cc (gfc_conv_scalar_to_descriptor,
gfc_conv_gfc_desc_to_cfi_desc, gfc_trans_pointer_assignment):
Likewise.
* trans-intrinsic.cc (gfc_conv_is_contiguous_expr,
gfc_conv_intrinsic_sizeof): Likewise.
* trans-openmp.cc (gfc_omp_array_size, gfc_omp_deep_mapping_item):
Likewise.
Mikael Morin [Mon, 20 Jul 2026 09:07:41 +0000 (11:07 +0200)]
fortran: array descriptor: Use the setter to modify the offset [PR122521]
Use the setter function to generate code modifying the array descriptor
offset and remove from the public API the function giving direct access to
that field.
PR fortran/122521
gcc/fortran/ChangeLog:
* trans-descriptor.cc (gfc_conv_descriptor_offset): Make static and
rename ...
(conv_descriptor_offset): ... to this.
(gfc_conv_descriptor_offset_get,
gfc_conv_descriptor_offset_set): Update callers.
* trans-descriptor.h (gfc_conv_descriptor_offset): Remove
declaration.
* trans-array.cc (gfc_alloc_allocatable_for_assignment): Use the
setter function to generate a modification of the array descriptor
offset.
Tomasz Kamiński [Mon, 20 Jul 2026 07:10:57 +0000 (09:10 +0200)]
libstc++: Use standard FLT_EVAL_METHOD in piecewise distributions tests.
libstdc++-v3/ChangeLog:
* testsuite/26_numerics/random/piecewise_constant_distribution/operators/serialize2.cc:
Include <cfloat> and use FLT_EVAL_METHOD instead of
__FLT_EVAL_METHOD__.
* testsuite/26_numerics/random/piecewise_linear_distribution/operators/serialize2.cc:
Likewise.
Fortran/OpenMP: Add parsing support for spatial dimensions
Adds 'dim(...)' modifier parsing for spatial dimensions to the num_teams,
thread_limit, and num_threads clauses.
Add strict + relaxed modifier support to the thread_limit and num_threads
clauses. [For teams, the effect of strict/relaxed is provided by the
lower_bound feature.]
For num_threads, support specifying multiple values - to be applicable
for nested parallel constructs.
NOTE: All added features (but 'relaxed') will fail after parsing with
a 'sorry, unimplemented' as only the parsing support has been added and
not the actual feature.
gcc/fortran/ChangeLog:
* dump-parse-tree.cc (show_omp_clauses): Handle spatial dimension
in num_teams and it and strict/relaxed in thread_limits and
num_threads.
* trans-openmp.cc (gfc_trans_omp_clauses, gfc_split_omp_clauses,
gfc_trans_omp_target): Likewise.
* openmp.cc (gfc_free_omp_clauses, gfc_match_omp_clauses,
resolve_omp_clauses): Likewise.
(match_omp_oacc_expr_list): Return current locus for a parse
fail instead of resetting the locus.
* gfortran.h (gfc_omp_clauses): Changed gfc_expr num_threads,
num_teams_lower, num_teams_upper, and thread_limit to
gfc_expr_list num_threads_list, num_teams_list, and thread_limit_list.
Add thread_limit_strict, num_threads_strict, num_teams_dims,
thread_limit_dims, and num_threads_dims.
* frontend-passes.cc (gfc_code_walker): Update for this change.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/spatial-dimensions-1.f90: New test.
* gfortran.dg/gomp/spatial-dimensions-2.f90: New test.
* gfortran.dg/gomp/spatial-dimensions-3.f90: New test.
Tomasz Kamiński [Fri, 17 Jul 2026 19:14:42 +0000 (21:14 +0200)]
libstdc++: Fix condition for stopping lazy zone expansion [PR116110]
At indicated by the pre-existing comment, the lazy zone expansion can be
only resumed from STD (save == 0) zone. However, the current condition
for stopping on DST (save != 0) doesn't ensure that, as some rule specify
transitions between DST zones. For example August 1945 of Y rule used by
America/Dawson only change letters:
Y 1942 o - F 9 2 1 W
Y 1945 o - Au 14 23u 1 P
This patch correct the condition, by using next_rule (i.e. one applying
after last expanded zone): either there is no zone (last expanded range)
or it have save zero.
libstdc++-v3/ChangeLog:
PR libstdc++/116110
* src/c++20/tzdb.cc (time_zone::_M_get_sys_info): Correct
condition for stopping zone expansion before STD zone.
* testsuite/std/time/time_zone/116110.cc (test_dawson):
Add test for America/Dawson August 1945 transition.
Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Signed-off-by: Tomasz Kamiński <tkaminsk@redhat.com>
Tomasz Kamiński [Fri, 17 Jul 2026 11:21:39 +0000 (13:21 +0200)]
libstdc++: Prevent overflow in find_active_rule to_local conversion. [PR116110]
As when member of Transitions::Entries that do not correspond
to rule activation (rule is empty) is either minimum or maximum
value of sys_seconds, adjusting it to std_offset lead to overflow
(and UB). In practice this caused next.when to have very low value,
and thus considered to be active rule. The to_local conversion now
return local_seconds constucted directly from time_since_epoch
(i.e. minimum and maximum).
In consequence above, the save was still not applied for zones
that specified UNTIL after firing of last rule, that also have
non zero save (e.g. Asia/Bishkek 2005 transition).
libstdc++-v3/ChangeLog:
PR libstdc++/116110
* src/c++20/tzdb.cc (find_active_rule::to_local): Do not
modify min/max values for rules.
* testsuite/std/time/time_zone/wall_cascade.cc: Add test
for last_transition.
Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Signed-off-by: Tomasz Kamiński <tkaminsk@redhat.com>
Pan Li [Sun, 19 Jul 2026 09:25:21 +0000 (17:25 +0800)]
RISC-V: Add test cases for vfwcvt.f.f.v reg overlap
Add test cases for vfwcvt.f.f.v register group overlap, please
note it is not overlap as much as possible.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f-f32-mf2.c: New test.
Philipp Tomsich [Sun, 19 Jul 2026 16:26:41 +0000 (18:26 +0200)]
match.pd: Make the (trunc)copysign(extend x, extend y) vector-safe [PR126291]
The (convert (copysigns (convert@2 @0) (convert @1))) rules evaluate
TYPE_PRECISION on the outer and inner types after only types_match, so
a vectorized copysign chain like
trips the vector_type tree check while gimple_simplify evaluates the
guard (the ICE does not require the precision test to hold: evaluating
TYPE_PRECISION on a vector type is what triggers it).
Use element_precision, mirroring the abs fix. No equivalent of the
target_supports_op_p check is needed here, since the existing
direct_internal_fn_supported_p guard already handles vector types
correctly.
The REAL_CST variant cannot match vectors (a vector constant is a
VECTOR_CST), but is converted as well for consistency.
Bootstrapped and regtested on x86_64-pc-linux-gnu.
Philipp Tomsich [Thu, 16 Jul 2026 04:45:03 +0000 (06:45 +0200)]
match.pd: Make the (trunc)abs(extend x) guard vector-safe [PR126291]
The (convert (abs (convert@1 @0))) -> (abs @0) rule added by r17-2276-ge2c4fc6b1cff evaluates TYPE_PRECISION on the outer and inner types
after only types_match, so a vectorized abs-of-narrowed chain like
trips the vector_type tree check when gimple_simplify visits the
outer conversion (ICE during fre). Use element_precision
so the guard is evaluable for vectors, and require target support
for ABS on the narrow vector type before enabling the transform
there.
Bootstrapped and regtested on aarch64-unknown-linux-gnu, x86_64-pc-linux-gnu
and riscv64-unknown-linux-gnu.
PR tree-optimization/126291
gcc/ChangeLog:
* match.pd ((trunc)abs (extend x) -> abs (x)): Use
element_precision. Require target ABS support for the
vector case.
projects / thirdparty / gcc.git / log
