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2022-12-19	Ju-Zhe Zhong	RISC-V: Change vlmul printing rule	commit \| commitdiff \| tree
2022-12-19	Kito Cheng	RISC-V: Fix vwrite_csr.c and vread_csr.c	commit \| commitdiff \| tree
2022-12-19	Kito Cheng	RISC-V: Fix RVV related testsuite	commit \| commitdiff \| tree
2022-12-01	Ju-Zhe Zhong	RISC-V: Remove tail && mask policy operand for vmclr...	commit \| commitdiff \| tree
2022-12-01	Ju-Zhe Zhong	RISC-V: Add attributes for VSETVL PASS	commit \| commitdiff \| tree
2022-12-01	Ju-Zhe Zhong	RISC-V: Add duplicate vector support.	commit \| commitdiff \| tree
2022-11-11	Ju-Zhe Zhong	RISC-V: Add RVV registers register spilling	commit \| commitdiff \| tree
2022-10-31	Ju-Zhe Zhong	RISC-V: Change constexpr back to CONSTEXPR	commit \| commitdiff \| tree
2022-10-27	Jiawei	RISC-V: Add zhinx/zhinxmin testcases.	commit \| commitdiff \| tree
2022-10-27	Jiawei	RISC-V: Limit regs use for z*inx extension.	commit \| commitdiff \| tree
2022-10-27	Jiawei	RISC-V: Target support for z*inx extension.	commit \| commitdiff \| tree
2022-10-27	Jiawei	RISC-V: Minimal support of z*inx extension.	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: Fix epilogue generation for barrier.	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: ADJUST_NUNITS according to -march.	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: Support load/store in mov<mode> pattern for...	commit \| commitdiff \| tree
2022-10-26	Monk Chiang	RISC-V: Recognized Svinval and Svnapot extensions	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: Adjust table indentation in commnet for riscv...	commit \| commitdiff \| tree
2022-10-26	Kito Cheng	RISC-V: Add h extension support	commit \| commitdiff \| tree
2022-10-24	Kito Cheng	RISC-V: Support --target-help for -mcpu/-mtune	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Support (set (mem) (const_poly_int))	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Replace CONSTEXPR with constexpr	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Remove unused TI/TF vector modes.	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Fix REG_CLASS_CONTENTS.	commit \| commitdiff \| tree
2022-10-21	Monk Chiang	RISC-V: Add type attribute for atomic instructions.	commit \| commitdiff \| tree
2022-10-21	Ju-Zhe Zhong	RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.	commit \| commitdiff \| tree
2022-10-21	Ju-Zhe Zhong	RISC-V: Add RVV intrinsic basic framework.	commit \| commitdiff \| tree
2022-10-17	Ju-Zhe Zhong	RISC-V: Fix format[NFC]	commit \| commitdiff \| tree
2022-10-17	Ju-Zhe Zhong	RISC-V: Reorganize mangle_builtin_type.[NFC]	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Remove TUPLE size macro define. [NFC]	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Apply clang-format for riscv-vector-builtins...	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Refine register_builtin_types function. [NFC]	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Move function place to make it looks better...	commit \| commitdiff \| tree
2022-10-11	Ju-Zhe Zhong	RISC-V: move struct vector_type_info from .h to ... Reviewed-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2022-10-11	Ju-Zhe Zhong	RISC-V: Add missing vsetvl instruction type. Reviewed-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2022-10-10	Kito Cheng	RISC-V: Add riscv_vector.h wrapper in testsuite to...	commit \| commitdiff \| tree
2022-10-10	Kito Cheng	RISC-V: Adjust testcase for rvv/base/user-1.c	commit \| commitdiff \| tree
2022-10-10	Kito Cheng	RISC-V: Add newline to the end of file [NFC]	commit \| commitdiff \| tree
2022-10-05	Ju-Zhe Zhong	RISC-V: Introduce RVV header to enable builtin types	commit \| commitdiff \| tree
2022-10-05	Vineet Gupta	RISC-V: remove deprecate pic code model macro	commit \| commitdiff \| tree
2022-09-30	Jiawei	RISC-V: Add '-m[no]-csr-check' option in gcc.	commit \| commitdiff \| tree
2022-09-28	Ju-Zhe Zhong	RISC-V: Add ABI-defined RVV types.	commit \| commitdiff \| tree
2022-09-23	Vineet Gupta	RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand	commit \| commitdiff \| tree
2022-09-23	zhongjuzhe	RISC-V: Add RVV machine modes.	commit \| commitdiff \| tree
2022-09-23	zhongjuzhe	RISC-V: Support poly move manipulation and selftests.	commit \| commitdiff \| tree
2022-09-09	Kito Cheng	RISC-V: Suppress build warnings	commit \| commitdiff \| tree
2022-09-05	Kito Cheng	RISC-V: Fix division instructions for `m` with `zmmul...	commit \| commitdiff \| tree
2022-09-05	LiaoShihua	RISC-V: Support Zmmul extension	commit \| commitdiff \| tree
2022-09-02	Kito Cheng	RISC-V: Implement TARGET_COMPUTE_MULTILIB	commit \| commitdiff \| tree
2022-09-02	Kito Cheng	Add TARGET_COMPUTE_MULTILIB hook to override multi...	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_...	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Add csrr vlenb instruction.	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Add RVV constraints.	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Fix comment in riscv.h	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Fix riscv_vector_chunks configuration according...	commit \| commitdiff \| tree
2022-08-29	Kito Cheng	RISC-V: Suppress -Wclass-memaccess warning	commit \| commitdiff \| tree
2022-08-29	zhongjuzhe	RISC-V: Add RVV registers	commit \| commitdiff \| tree
2022-08-29	zhongjuzhe	RISC-V: Add RVV instructions classification	commit \| commitdiff \| tree
2022-08-18	zhongjuzhe	RISC-V: Add runtime invariant support	commit \| commitdiff \| tree
2022-08-16	Kito Cheng	RISC-V: Support zfh and zfhmin extension	commit \| commitdiff \| tree
2022-08-16	Kito Cheng	RISC-V: Support _Float16 type.	commit \| commitdiff \| tree
2022-08-16	Kito Cheng	soft-fp: Update soft-fp from glibc	commit \| commitdiff \| tree
2022-07-01	Kito Cheng	Revert "testsuite/102690: Only check warning for lp64...	commit \| commitdiff \| tree
2022-06-30	Kito Cheng	testsuite/102690: Only check warning for lp64 in Warray...	commit \| commitdiff \| tree
2022-06-20	yulong	RISC-V: Fix a bug that is the CMO builtins are missing...	commit \| commitdiff \| tree
2022-06-17	Kito Cheng	RISC-V: Supress warning for comparison of integer expression...	commit \| commitdiff \| tree
2022-06-16	Jia-wei Chen	RISC-V/testsuite: Fix pr105666.c under rv32	commit \| commitdiff \| tree
2022-05-30	Vineet Gupta	RISC-V/testsuite: constraint some of tests to hard_float	commit \| commitdiff \| tree
2022-05-25	Simon Cook	RISC-V: Don't unconditionally add m,a,f,d in arch-canonicalize	commit \| commitdiff \| tree
2022-05-24	ShiYulong	RISC-V: Cache Management Operation instructions testcases	commit \| commitdiff \| tree
2022-05-24	ShiYulong	RISC-V: Cache Management Operation instructions	commit \| commitdiff \| tree
2022-05-24	ShiYulong	RISC-V: Add mininal support for Zicbo[mzp]	commit \| commitdiff \| tree
2022-05-24	Vineet Gupta	RISC-V: Inhibit FP <--> int register moves via tune...	commit \| commitdiff \| tree
2022-05-23	Tsukasa OI	RISC-V: Fix canonical extension order (K and J)	commit \| commitdiff \| tree
2022-05-09	Kito Cheng	RISC-V: Fix wrong expansion for arch-canonicalize	commit \| commitdiff \| tree
2022-04-28	Jia-Wei Chen	testsuite: Skip target not support -pthread [PR104676].	commit \| commitdiff \| tree
2022-04-11	Kito Cheng	RISC-V: Support -misa-spec for arch-canonicalize and...	commit \| commitdiff \| tree
2022-04-11	Kito Cheng	RISC-V: Sync arch-canonicalize and riscv-common.cc	commit \| commitdiff \| tree
2022-03-21	Kito Cheng	RISC-V: Implement misc macro for vector extensions.	commit \| commitdiff \| tree
2022-03-16	Kito Cheng	RISC-V: Add version info for zk, zkn and zks	commit \| commitdiff \| tree
2022-03-16	LiaoShihua	RISC-V: Handle combine extension in canonical ordering.	commit \| commitdiff \| tree
2022-02-05	Kito Cheng	RISC-V: Fix detection of zifencei support for binutils	commit \| commitdiff \| tree
2022-02-05	Kito Cheng	RISC-V: Always pass -misa-spec to assembler [PR104219]	commit \| commitdiff \| tree
2022-01-24	Kito Cheng	RISC-V: Fix testcase after bump isa spec version	commit \| commitdiff \| tree
2022-01-24	Kito Cheng	RISC-V: Do not emit zcisr and zifencei if i-ext is 2.0	commit \| commitdiff \| tree
2022-01-24	Jia-Wei Chen	RISC-V: Change default ISA version into 20191213	commit \| commitdiff \| tree
2022-01-24	LiaoShihua	RISC-V: Update testcases info with new implement info	commit \| commitdiff \| tree
2022-01-06	Kito Cheng	RISC-V: Minimal support of vector extensions	commit \| commitdiff \| tree
2022-01-06	Kito Cheng	RISC-V: Allow extension name contain digit	commit \| commitdiff \| tree
2021-12-27	LiaoShihua	RISC-V: fixed testcase riscv/pr103302.c	commit \| commitdiff \| tree
2021-12-06	Nelson Chu	RISC-V: jal cannot refer to a default visibility symbol...	commit \| commitdiff \| tree
2021-12-03	SiYu Wu	RISC-V: Add implied defines of Zk, Zkn and Zks	commit \| commitdiff \| tree
2021-12-03	SiYu Wu	RISC-V: Add option defines for Scalar Cryptography	commit \| commitdiff \| tree
2021-11-11	Kito Cheng	RISC-V: Fix wrong zifencei handling in riscv_subset_list...	commit \| commitdiff \| tree
2021-11-09	Kito Cheng	[PR/target 102957] Allow Z*-ext extension with only...	commit \| commitdiff \| tree
2021-10-28	Kito Cheng	RISC-V: Fix wrong predicator for zero_extendsidi2_internal...	commit \| commitdiff \| tree
2021-10-28	Kito Cheng	RISC-V: Handle zi* extension correctly for arch-canonicalize...	commit \| commitdiff \| tree
2021-10-25	Kito Cheng	RISC-V: Cost model for ZBS extension.	commit \| commitdiff \| tree
2021-10-25	Jim Wilson	RISC-V: Implement instruction patterns for ZBS extension. Kito Cheng <kito.cheng@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-10-25	Jim Wilson	RISC-V: Use li and rori to load constants.	commit \| commitdiff \| tree
2021-10-25	Kito Cheng	RISC-V: Cost model for zbb extension. 2021-10-25 Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
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