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2024-01-22	xuli	RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]	commit \| commitdiff \| tree
2023-12-19	xuli	testsuite: Fix dump checks under different riscv-sim...	commit \| commitdiff \| tree
2023-12-19	xuli	testsuite: Fix cpymem-2.c dump checks under different...	commit \| commitdiff \| tree
2023-12-18	xuli	testsuite: Fix cpymem-1.c dump checks under different...	commit \| commitdiff \| tree
2023-12-18	xuli	RISC-V: Add viota missed avl_type attribute	commit \| commitdiff \| tree
2023-12-06	xuli	RISC-V: Remove useless modes	commit \| commitdiff \| tree
2023-12-05	xuli	RISC-V: FAIL:g++.dg/torture/vshuf-v[2\|4]di.C -Os (execution...	commit \| commitdiff \| tree
2023-11-29	xuli	RISC-V: Add explicit braces to eliminate warning.	commit \| commitdiff \| tree
2023-11-20	xuli	RISC-V: Implement -mmemcpy-strategy= options[PR112537]	commit \| commitdiff \| tree
2023-11-08	xuli	RISC-V: Eliminate unused parameter warning.	commit \| commitdiff \| tree
2023-11-06	xuli	RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV... Signed-off-by: Li Xu <xuli1@eswincomputing.com>	commit \| commitdiff \| tree
2023-11-02	xuli	RISC-V: Support vcreate intrinsics for non-tuple types	commit \| commitdiff \| tree
2023-11-01	xuli	RISC-V: Support vundefine intrinsics for tuple types	commit \| commitdiff \| tree
2023-10-24	xuli	RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]	commit \| commitdiff \| tree
2023-10-07	xuli	RISC-V: Fix scan-assembler-times of RVV test case	commit \| commitdiff \| tree
2023-09-28	xuli	RISC-V: Bugfix for RTL check[PR111533]	commit \| commitdiff \| tree
2023-09-22	xuli	RISC-V: Optimization of vrgather.vv into vrgatherei16...	commit \| commitdiff \| tree
2023-09-21	xuli	RISC-V: Optimized for strided load/store with stride...	commit \| commitdiff \| tree
2023-09-12	xuli	RISC-V: Elimilate warning in class vcreate	commit \| commitdiff \| tree
2023-09-12	xuli	RISC-V: Add vcreate intrinsics for RVV tuple types	commit \| commitdiff \| tree
2023-07-31	xuli	MAINTAINERS: Add myself to write after approval Signed-off-by: Li Xu <xuli1@eswincomputing.com>	commit \| commitdiff \| tree
2023-07-28	xuli	RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]	commit \| commitdiff \| tree
2023-07-26	Li Xu	RISC-V: Fix vector tuple intrinsic	commit \| commitdiff \| tree
2023-06-25	Li Xu	RISC-V: fix expand function of vlmul_ext RVV intrinsic	commit \| commitdiff \| tree
2023-06-20	Li Xu	RISC-V: Set the natural size of constant vector mask...	commit \| commitdiff \| tree
2023-06-19	Li Xu	RISC-V: Fix VWEXTF iterator requirement	commit \| commitdiff \| tree
2023-06-06	Li Xu	RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in...	commit \| commitdiff \| tree
2023-05-10	Li Xu	RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f...	commit \| commitdiff \| tree
2023-04-05	Li Xu	RISC-V: Fix typos	commit \| commitdiff \| tree
2023-04-03	Li Xu	RISC-V: Fix typo	commit \| commitdiff \| tree

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