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2024-02-02	Pan Li	RISC-V: Cleanup the comments for the psabi Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2024-02-02	Juzhe-Zhong	RISC-V: Remove vsetvl_pre bogus instructions in VSETVL...	commit \| commitdiff \| tree
2024-01-31	Juzhe-Zhong	RISC-V: Fix VSETLV PASS compile-time issue	commit \| commitdiff \| tree
2024-01-30	Pan Li	RISC-V: Bugfix for vls mode aggregated in GPR calling... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2024-01-30	Juzhe-Zhong	RISC-V: Fix regression	commit \| commitdiff \| tree
2024-01-26	Juzhe-Zhong	RISC-V: Fix incorrect LCM delete bug [VSETVL PASS]	commit \| commitdiff \| tree
2024-01-25	Yanzhang Wang	RISC-V: remove param riscv-vector-abi. [PR113538]	commit \| commitdiff \| tree
2024-01-25	Juzhe-Zhong	RISC-V: Add LCM delete block predecessors dump information	commit \| commitdiff \| tree
2024-01-25	Juzhe-Zhong	RISC-V: Remove redundant full available computation...	commit \| commitdiff \| tree
2024-01-25	Juzhe-Zhong	RISC-V: Add optim-no-fusion compile option [VSETVL...	commit \| commitdiff \| tree
2024-01-24	Juzhe-Zhong	RISC-V: Fix large memory usage of VSETVL PASS [PR113495]	commit \| commitdiff \| tree
2024-01-22	Juzhe-Zhong	RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x	commit \| commitdiff \| tree
2024-01-22	Juzhe-Zhong	RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes	commit \| commitdiff \| tree
2024-01-20	Juzhe-Zhong	RISC-V: Suppress warning	commit \| commitdiff \| tree
2024-01-18	Juzhe-Zhong	RISC-V: Add has compatible check for conflict vsetvl...	commit \| commitdiff \| tree
2024-01-17	Pan Li	RISC-V: Fix asm checks regression due to recent middle... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2024-01-16	Juzhe-Zhong	RISC-V: Report Sorry when users enable RVV in big-endian...	commit \| commitdiff \| tree
2024-01-16	Yanzhang Wang	RISC-V: delete vector abi checking in all relevant...	commit \| commitdiff \| tree
2024-01-16	Yanzhang Wang	RISC-V: delete all the vector psabi checking.	commit \| commitdiff \| tree
2024-01-15	Juzhe-Zhong	RISC-V: Fix regression (GCC-14 compare with GCC-13...	commit \| commitdiff \| tree
2024-01-15	Juzhe-Zhong	RISC-V: Add optimized dump check of VLS reduc tests	commit \| commitdiff \| tree
2024-01-15	Juzhe-Zhong	RISC-V: Fix attributes bug configuration of ternary...	commit \| commitdiff \| tree
2024-01-12	Juzhe-Zhong	RISC-V: Adjust scalar_to_vec cost	commit \| commitdiff \| tree
2024-01-12	Juzhe-Zhong	RISC-V: Enhance a testcase	commit \| commitdiff \| tree
2024-01-12	Pan Li	RISC-V: Update the comments of riscv_v_ext_mode_p ... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2024-01-11	Pan Li	LOOP-UNROLL: Leverage HAS_SIGNED_ZERO for var expansion Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2024-01-11	Juzhe-Zhong	RISC-V: VLA preempts VLS on unknown NITERS loop	commit \| commitdiff \| tree
2024-01-10	Juzhe-Zhong	RISC-V: Switch RVV cost model.	commit \| commitdiff \| tree
2024-01-10	Juzhe-Zhong	RISC-V: Minor tweak dynamic cost model	commit \| commitdiff \| tree
2024-01-10	Juzhe-Zhong	RISC-V: Refine unsigned avg_floor/avg_ceil	commit \| commitdiff \| tree
2024-01-09	Juzhe-Zhong	RISC-V: Fix loop invariant check	commit \| commitdiff \| tree
2024-01-09	Juzhe-Zhong	RISC-V: Fix comments of segment load/store intrinsic...	commit \| commitdiff \| tree
2024-01-07	Juzhe-Zhong	RISC-V: Use MAX instead of std::max [VSETVL PASS]	commit \| commitdiff \| tree
2024-01-06	Juzhe-Zhong	RISC-V: Update MAX_SEW for available vsevl info[VSETVL...	commit \| commitdiff \| tree
2024-01-06	Juzhe-Zhong	RISC-V: Teach liveness computation loop invariant shift...	commit \| commitdiff \| tree
2024-01-06	Juzhe-Zhong	RISC-V: Allow simplification non-vlmax with len = NUNITS...	commit \| commitdiff \| tree
2024-01-05	Pan Li	Revert "RISC-V: Add crypto vector api-testing cases."	commit \| commitdiff \| tree
2024-01-05	Pan Li	Revert "RISC-V: Add crypto vector builtin function."	commit \| commitdiff \| tree
2024-01-04	Juzhe-Zhong	RISC-V: Make liveness estimation be aware of .vi variant	commit \| commitdiff \| tree
2024-01-04	Pan Li	Revert "RISC-V: Make liveness estimation be aware of...	commit \| commitdiff \| tree
2024-01-04	Juzhe-Zhong	RISC-V: Refine LMUL computation for MASK_LEN_LOAD/MASK_LEN_S...	commit \| commitdiff \| tree
2024-01-04	Juzhe-Zhong	RISC-V: Fix bug of earliest fusion for infinite loop...	commit \| commitdiff \| tree
2024-01-04	Juzhe-Zhong	RISC-V: Fix indent	commit \| commitdiff \| tree
2024-01-03	Juzhe-Zhong	RISC-V: Make liveness be aware of rgroup number of...	commit \| commitdiff \| tree
2024-01-02	Juzhe-Zhong	RISC-V: Add simplification of dummy len and dummy mask...	commit \| commitdiff \| tree
2024-01-02	Juzhe-Zhong	RISC-V: Declare STMT_VINFO_TYPE (...) as local variable	commit \| commitdiff \| tree
2024-01-02	Juzhe-Zhong	RISC-V: Count pointer type SSA into RVV regs liveness...	commit \| commitdiff \| tree
2023-12-29	Juzhe-Zhong	RISC-V: Robostify testcase pr113112-1.c	commit \| commitdiff \| tree
2023-12-29	Juzhe-Zhong	RISC-V: Disallow transformation into VLMAX AVL for...	commit \| commitdiff \| tree
2023-12-28	Juzhe-Zhong	RISC-V: Make dynamic LMUL cost model more accurate...	commit \| commitdiff \| tree
2023-12-27	Juzhe-Zhong	RISC-V: Make known NITERS loop be aware of dynamic...	commit \| commitdiff \| tree
2023-12-26	Juzhe-Zhong	RISC-V: Fix typo	commit \| commitdiff \| tree
2023-12-26	Juzhe-Zhong	RISC-V: Some minior tweak on dynamic LMUL cost model	commit \| commitdiff \| tree
2023-12-25	Juzhe-Zhong	RISC-V: Move RVV V_REGS liveness computation into analyze_lo...	commit \| commitdiff \| tree
2023-12-25	Juzhe-Zhong	RISC-V: Add one more ASM check in PR113112-1.c	commit \| commitdiff \| tree
2023-12-24	Pan Li	RISC-V: XFail the signbit-5 run test for RVV Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-23	Juzhe-Zhong	RISC-V: Make PHI initial value occupy live V_REG in...	commit \| commitdiff \| tree
2023-12-21	Juzhe-Zhong	RISC-V: Add dynamic LMUL test for x264	commit \| commitdiff \| tree
2023-12-20	Juzhe-Zhong	RISC-V: Optimize SELECT_VL codegen when length is known...	commit \| commitdiff \| tree
2023-12-20	Juzhe-Zhong	RISC-V: Fix bug of VSETVL fusion	commit \| commitdiff \| tree
2023-12-20	demin.han	RISC-V: Fix calculation of max live vregs	commit \| commitdiff \| tree
2023-12-20	Pan Li	RISC-V: Bugfix for the const vector in single steps Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-20	Juzhe-Zhong	RISC-V: Fix ICE of moving SUBREG of vector mode to...	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Refine some codes of expand_const_vector [NFC]	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Force scalable vector on all vsetvl tests	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Fix FAIL of dynamic-lmul2-7.c	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Remove 256/512/1024 VLS vectors	commit \| commitdiff \| tree
2023-12-18	Pan Li	RISC-V: Rename the rvv test case. Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-18	Juzhe-Zhong	RISC-V: Support one more overlap for wv instructions	commit \| commitdiff \| tree
2023-12-18	Juzhe-Zhong	RISC-V: Enable vect test for RV32	commit \| commitdiff \| tree
2023-12-18	Juzhe-Zhong	RISC-V: Fix natural regsize for fixed-vlmax of -march...	commit \| commitdiff \| tree
2023-12-18	Pan Li	RISC-V: Bugfix for the RVV const vector Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-18	Pan Li	RISC-V: Fix POLY INT handle bug Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Fix vmerge optimization bug in vec_perm vectorization	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Remove xfail for some of the SLP tests	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Adjust test	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Tweak generic vector COST model	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	Middle-end: Do not model address cost for SELECT_VL...	commit \| commitdiff \| tree
2023-12-14	Juzhe-Zhong	RISC-V: Add failed SLP testcase	commit \| commitdiff \| tree
2023-12-14	Juzhe-Zhong	RISC-V: Add RVV builtin vectorization cost model	commit \| commitdiff \| tree
2023-12-13	Pan Li	RISC-V: Refine test cases for both PR112929 and PR112988 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-13	Juzhe-Zhong	RISC-V: Postpone full available optimization [VSETVL...	commit \| commitdiff \| tree
2023-12-13	demin.han	RISC-V: Fix dynamic lmul tests depended on abi	commit \| commitdiff \| tree
2023-12-13	Juzhe-Zhong	Middle-end: Adjust decrement IV style partial vectorization...	commit \| commitdiff \| tree
2023-12-12	Juzhe-Zhong	RISC-V: Apply vla vs. vls mode heuristic vector COST...	commit \| commitdiff \| tree
2023-12-12	Juzhe-Zhong	RISC-V: Refactor Dynamic LMUL codes	commit \| commitdiff \| tree
2023-12-12	Pan Li	RISC-V: Disable RVV VCOMPRESS avl propagation Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-12	Juzhe-Zhong	RISC-V: Move RVV POLY VALUE estimation from riscv.cc...	commit \| commitdiff \| tree
2023-12-11	Juzhe-Zhong	RISC-V: Support highest overlap for wv instructions	commit \| commitdiff \| tree
2023-12-09	Juzhe-Zhong	RISC-V: Fix VLS mode movmiaslign bug	commit \| commitdiff \| tree
2023-12-08	Pan Li	RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-07	Juzhe-Zhong	RISC-V: Support interleave vector with different step...	commit \| commitdiff \| tree
2023-12-06	Juzhe-Zhong	RISC-V: Fix VSETVL PASS bug	commit \| commitdiff \| tree
2023-12-05	Juzhe-Zhong	RISC-V: Block VLSmodes according to TARGET_MAX_LMUL...	commit \| commitdiff \| tree
2023-12-05	Juzhe-Zhong	RISC-V: Add blocker for gather/scatter auto-vectorization	commit \| commitdiff \| tree
2023-12-04	Juzhe-Zhong	RISC-V: Fix overlap group incorrect overlap on v0	commit \| commitdiff \| tree
2023-12-04	Juzhe-Zhong	RISC-V: Support highest-number regno overlap for widen...	commit \| commitdiff \| tree
2023-12-04	Pan Li	RISC-V: Add test case for bug PR112813 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-04	Juzhe-Zhong	RISC-V: Robostify the W43, W86, W87 constraint enabled...	commit \| commitdiff \| tree
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