arch/arm/boot/dts/armada-370.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Contains definitions specific to the Armada 370 SoC that are not
  15  * common to all Armada SoCs.
  16  */
  17
  18 #include "armada-370-xp.dtsi"
  19 /include/ "skeleton.dtsi"
  20
  21 / {
  22         model = "Marvell Armada 370 family SoC";
  23         compatible = "marvell,armada370", "marvell,armada-370-xp";
  24
  25         aliases {
  26                 gpio0 = &gpio0;
  27                 gpio1 = &gpio1;
  28                 gpio2 = &gpio2;
  29         };
  30
  31         soc {
  32                 compatible = "marvell,armada370-mbus", "simple-bus";
  33
  34                 bootrom {
  35                         compatible = "marvell,bootrom";
  36                         reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
  37                 };
  38
  39                 pcie-controller {
  40                         compatible = "marvell,armada-370-pcie";
  41                         status = "disabled";
  42                         device_type = "pci";
  43
  44                         #address-cells = <3>;
  45                         #size-cells = <2>;
  46
  47                         msi-parent = <&mpic>;
  48                         bus-range = <0x00 0xff>;
  49
  50                         ranges =
  51                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  52                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  53                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
  54                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
  55                                 0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
  56                                 0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
  57
  58                         pcie@1,0 {
  59                                 device_type = "pci";
  60                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  61                                 reg = <0x0800 0 0 0 0>;
  62                                 #address-cells = <3>;
  63                                 #size-cells = <2>;
  64                                 #interrupt-cells = <1>;
  65                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  66                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
  67                                 interrupt-map-mask = <0 0 0 0>;
  68                                 interrupt-map = <0 0 0 0 &mpic 58>;
  69                                 marvell,pcie-port = <0>;
  70                                 marvell,pcie-lane = <0>;
  71                                 clocks = <&gateclk 5>;
  72                                 status = "disabled";
  73                         };
  74
  75                         pcie@2,0 {
  76                                 device_type = "pci";
  77                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
  78                                 reg = <0x1000 0 0 0 0>;
  79                                 #address-cells = <3>;
  80                                 #size-cells = <2>;
  81                                 #interrupt-cells = <1>;
  82                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  83                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
  84                                 interrupt-map-mask = <0 0 0 0>;
  85                                 interrupt-map = <0 0 0 0 &mpic 62>;
  86                                 marvell,pcie-port = <1>;
  87                                 marvell,pcie-lane = <0>;
  88                                 clocks = <&gateclk 9>;
  89                                 status = "disabled";
  90                         };
  91                 };
  92
  93                 internal-regs {
  94                         L2: l2-cache {
  95                                 compatible = "marvell,aurora-outer-cache";
  96                                 reg = <0x08000 0x1000>;
  97                                 cache-id-part = <0x100>;
  98                                 wt-override;
  99                         };
 100
 101                         i2c0: i2c@11000 {
 102                                 reg = <0x11000 0x20>;
 103                         };
 104
 105                         i2c1: i2c@11100 {
 106                                 reg = <0x11100 0x20>;
 107                         };
 108
 109                         pinctrl {
 110                                 compatible = "marvell,mv88f6710-pinctrl";
 111                                 reg = <0x18000 0x38>;
 112
 113                                 sdio_pins1: sdio-pins1 {
 114                                         marvell,pins = "mpp9",  "mpp11", "mpp12",
 115                                                         "mpp13", "mpp14", "mpp15";
 116                                         marvell,function = "sd0";
 117                                 };
 118
 119                                 sdio_pins2: sdio-pins2 {
 120                                         marvell,pins = "mpp47", "mpp48", "mpp49",
 121                                                         "mpp50", "mpp51", "mpp52";
 122                                         marvell,function = "sd0";
 123                                 };
 124
 125                                 sdio_pins3: sdio-pins3 {
 126                                         marvell,pins = "mpp48", "mpp49", "mpp50",
 127                                                         "mpp51", "mpp52", "mpp53";
 128                                         marvell,function = "sd0";
 129                                 };
 130                         };
 131
 132                         gpio0: gpio@18100 {
 133                                 compatible = "marvell,orion-gpio";
 134                                 reg = <0x18100 0x40>;
 135                                 ngpios = <32>;
 136                                 gpio-controller;
 137                                 #gpio-cells = <2>;
 138                                 interrupt-controller;
 139                                 #interrupt-cells = <2>;
 140                                 interrupts = <82>, <83>, <84>, <85>;
 141                         };
 142
 143                         gpio1: gpio@18140 {
 144                                 compatible = "marvell,orion-gpio";
 145                                 reg = <0x18140 0x40>;
 146                                 ngpios = <32>;
 147                                 gpio-controller;
 148                                 #gpio-cells = <2>;
 149                                 interrupt-controller;
 150                                 #interrupt-cells = <2>;
 151                                 interrupts = <87>, <88>, <89>, <90>;
 152                         };
 153
 154                         gpio2: gpio@18180 {
 155                                 compatible = "marvell,orion-gpio";
 156                                 reg = <0x18180 0x40>;
 157                                 ngpios = <2>;
 158                                 gpio-controller;
 159                                 #gpio-cells = <2>;
 160                                 interrupt-controller;
 161                                 #interrupt-cells = <2>;
 162                                 interrupts = <91>;
 163                         };
 164
 165                         system-controller@18200 {
 166                                 compatible = "marvell,armada-370-xp-system-controller";
 167                                 reg = <0x18200 0x100>;
 168                         };
 169
 170                         gateclk: clock-gating-control@18220 {
 171                                 compatible = "marvell,armada-370-gating-clock";
 172                                 reg = <0x18220 0x4>;
 173                                 clocks = <&coreclk 0>;
 174                                 #clock-cells = <1>;
 175                         };
 176
 177                         coreclk: mvebu-sar@18230 {
 178                                 compatible = "marvell,armada-370-core-clock";
 179                                 reg = <0x18230 0x08>;
 180                                 #clock-cells = <1>;
 181                         };
 182
 183                         thermal@18300 {
 184                                 compatible = "marvell,armada370-thermal";
 185                                 reg = <0x18300 0x4
 186                                         0x18304 0x4>;
 187                                 status = "okay";
 188                         };
 189
 190                         interrupt-controller@20000 {
 191                                 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
 192                         };
 193
 194                         timer@20300 {
 195                                 compatible = "marvell,armada-370-timer";
 196                                 clocks = <&coreclk 2>;
 197                         };
 198
 199                         usb@50000 {
 200                                 clocks = <&coreclk 0>;
 201                         };
 202
 203                         usb@51000 {
 204                                 clocks = <&coreclk 0>;
 205                         };
 206
 207                         xor@60800 {
 208                                 compatible = "marvell,orion-xor";
 209                                 reg = <0x60800 0x100
 210                                        0x60A00 0x100>;
 211                                 status = "okay";
 212
 213                                 xor00 {
 214                                         interrupts = <51>;
 215                                         dmacap,memcpy;
 216                                         dmacap,xor;
 217                                 };
 218                                 xor01 {
 219                                         interrupts = <52>;
 220                                         dmacap,memcpy;
 221                                         dmacap,xor;
 222                                         dmacap,memset;
 223                                 };
 224                         };
 225
 226                         xor@60900 {
 227                                 compatible = "marvell,orion-xor";
 228                                 reg = <0x60900 0x100
 229                                        0x60b00 0x100>;
 230                                 status = "okay";
 231
 232                                 xor10 {
 233                                         interrupts = <94>;
 234                                         dmacap,memcpy;
 235                                         dmacap,xor;
 236                                 };
 237                                 xor11 {
 238                                         interrupts = <95>;
 239                                         dmacap,memcpy;
 240                                         dmacap,xor;
 241                                         dmacap,memset;
 242                                 };
 243                         };
 244                 };
 245         };
 246 };