arch/arm/boot/dts/armada-xp-axpwifiap.dts

   1 /*
   2  * Device Tree file for Marvell RD-AXPWiFiAP.
   3  *
   4  * Note: this board is shipped with a new generation boot loader that
   5  * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
   6  * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
   7  * used.
   8  *
   9  * Copyright (C) 2013 Marvell
  10  *
  11  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public
  14  * License version 2.  This program is licensed "as is" without any
  15  * warranty of any kind, whether express or implied.
  16  */
  17
  18 /dts-v1/;
  19 #include "armada-xp-mv78230.dtsi"
  20
  21 / {
  22         model = "Marvell RD-AXPWiFiAP";
  23         compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
  24
  25         chosen {
  26                 bootargs = "console=ttyS0,115200 earlyprintk";
  27         };
  28
  29         memory {
  30                 device_type = "memory";
  31                 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
  32         };
  33
  34         soc {
  35                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  36                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
  37
  38                 pcie-controller {
  39                         status = "okay";
  40
  41                         /* First mini-PCIe port */
  42                         pcie@1,0 {
  43                                 /* Port 0, Lane 0 */
  44                                 status = "okay";
  45                         };
  46
  47                         /* Second mini-PCIe port */
  48                         pcie@2,0 {
  49                                 /* Port 0, Lane 1 */
  50                                 status = "okay";
  51                         };
  52
  53                         /* Renesas uPD720202 USB 3.0 controller */
  54                         pcie@3,0 {
  55                                 /* Port 0, Lane 3 */
  56                                 status = "okay";
  57                         };
  58                 };
  59
  60                 internal-regs {
  61                         pinctrl {
  62                                 pinctrl-0 = <&pmx_phy_int>;
  63                                 pinctrl-names = "default";
  64
  65                                 pmx_ge0: pmx-ge0 {
  66                                         marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
  67                                                        "mpp4", "mpp5", "mpp6", "mpp7",
  68                                                        "mpp8", "mpp9", "mpp10", "mpp11";
  69                                         marvell,function = "ge0";
  70                                 };
  71
  72                                 pmx_ge1: pmx-ge1 {
  73                                         marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
  74                                                        "mpp16", "mpp17", "mpp18", "mpp19",
  75                                                        "mpp20", "mpp21", "mpp22", "mpp23";
  76                                         marvell,function = "ge1";
  77                                 };
  78
  79                                 pmx_keys: pmx-keys {
  80                                         marvell,pins = "mpp33";
  81                                         marvell,function = "gpio";
  82                                 };
  83
  84                                 pmx_spi: pmx-spi {
  85                                         marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
  86                                         marvell,function = "spi";
  87                                 };
  88
  89                                 pmx_phy_int: pmx-phy-int {
  90                                         marvell,pins = "mpp32";
  91                                         marvell,function = "gpio";
  92                                 };
  93                         };
  94
  95                         serial@12000 {
  96                                 clock-frequency = <250000000>;
  97                                 status = "okay";
  98                         };
  99
 100                         serial@12100 {
 101                                 clock-frequency = <250000000>;
 102                                 status = "okay";
 103                         };
 104
 105                         sata@a0000 {
 106                                 nr-ports = <1>;
 107                                 status = "okay";
 108                         };
 109
 110                         mdio {
 111                                 phy0: ethernet-phy@0 {
 112                                         reg = <0>;
 113                                 };
 114
 115                                 phy1: ethernet-phy@1 {
 116                                         reg = <1>;
 117                                 };
 118                         };
 119
 120                         ethernet@70000 {
 121                                 pinctrl-0 = <&pmx_ge0>;
 122                                 pinctrl-names = "default";
 123                                 status = "okay";
 124                                 phy = <&phy0>;
 125                                 phy-mode = "rgmii-id";
 126                         };
 127                         ethernet@74000 {
 128                                 pinctrl-0 = <&pmx_ge1>;
 129                                 pinctrl-names = "default";
 130                                 status = "okay";
 131                                 phy = <&phy1>;
 132                                 phy-mode = "rgmii-id";
 133                         };
 134
 135                         spi0: spi@10600 {
 136                                 status = "okay";
 137                                 pinctrl-0 = <&pmx_spi>;
 138                                 pinctrl-names = "default";
 139
 140                                 spi-flash@0 {
 141                                         #address-cells = <1>;
 142                                         #size-cells = <1>;
 143                                         compatible = "n25q128a13";
 144                                         reg = <0>; /* Chip select 0 */
 145                                         spi-max-frequency = <108000000>;
 146                                 };
 147                         };
 148                 };
 149         };
 150
 151         gpio_keys {
 152                 compatible = "gpio-keys";
 153                 #address-cells = <1>;
 154                 #size-cells = <0>;
 155                 pinctrl-0 = <&pmx_keys>;
 156                 pinctrl-names = "default";
 157
 158                 button@1 {
 159                         label = "Factory Reset Button";
 160                         linux,code = <141>; /* KEY_SETUP */
 161                         gpios = <&gpio1 1 1>;
 162                 };
 163         };
 164 };