arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts

   1 /*
   2  * The code contained herein is licensed under the GNU General Public
   3  * License. You may obtain a copy of the GNU General Public License
   4  * Version 2 or later at the following locations:
   5  *
   6  * http://www.opensource.org/licenses/gpl-license.html
   7  * http://www.gnu.org/copyleft/gpl.html
   8  */
   9
  10 #include "imx27-phytec-phycore-som.dts"
  11
  12 / {
  13         model = "Phytec pcm970";
  14         compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
  15 };
  16
  17 &cspi1 {
  18         fsl,spi-num-chipselects = <2>;
  19         cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
  20 };
  21
  22 &sdhci2 {
  23         bus-width = <4>;
  24         cd-gpios = <&gpio3 29 0>;
  25         wp-gpios = <&gpio3 28 0>;
  26         vmmc-supply = <&vmmc1_reg>;
  27         status = "okay";
  28 };
  29
  30 &uart1 {
  31         fsl,uart-has-rtscts;
  32 };
  33
  34 &uart2 {
  35         fsl,uart-has-rtscts;
  36         status = "okay";
  37 };
  38
  39 &weim {
  40         can@d4000000 {
  41                 compatible = "nxp,sja1000";
  42                 reg = <4 0x00000000 0x00000100>;
  43                 interrupt-parent = <&gpio5>;
  44                 interrupts = <19 0x2>;
  45                 nxp,external-clock-frequency = <16000000>;
  46                 nxp,tx-output-config = <0x16>;
  47                 nxp,no-comparator-bypass;
  48                 fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
  49         };
  50 };