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[people/arne_f/kernel.git] / arch / arm / boot / dts / imx51.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15
16 / {
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
30 ethernet0 = &fec;
31 };
32
33 tzic: tz-interrupt-controller@e0000000 {
34 compatible = "fsl,imx51-tzic", "fsl,tzic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0xe0000000 0x4000>;
38 };
39
40 clocks {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 ckil {
45 compatible = "fsl,imx-ckil", "fixed-clock";
46 clock-frequency = <32768>;
47 };
48
49 ckih1 {
50 compatible = "fsl,imx-ckih1", "fixed-clock";
51 clock-frequency = <0>;
52 };
53
54 ckih2 {
55 compatible = "fsl,imx-ckih2", "fixed-clock";
56 clock-frequency = <0>;
57 };
58
59 osc {
60 compatible = "fsl,imx-osc", "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 cpu@0 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a8";
71 reg = <0>;
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks 24>;
74 clock-names = "cpu";
75 operating-points = <
76 /* kHz uV (No regulator support) */
77 160000 0
78 800000 0
79 >;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&tzic>;
88 ranges;
89
90 iram: iram@1ffe0000 {
91 compatible = "mmio-sram";
92 reg = <0x1ffe0000 0x20000>;
93 };
94
95 ipu: ipu@40000000 {
96 #crtc-cells = <1>;
97 compatible = "fsl,imx51-ipu";
98 reg = <0x40000000 0x20000000>;
99 interrupts = <11 10>;
100 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
101 clock-names = "bus", "di0", "di1";
102 resets = <&src 2>;
103 };
104
105 aips@70000000 { /* AIPS1 */
106 compatible = "fsl,aips-bus", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0x70000000 0x10000000>;
110 ranges;
111
112 spba@70000000 {
113 compatible = "fsl,spba-bus", "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0x70000000 0x40000>;
117 ranges;
118
119 esdhc1: esdhc@70004000 {
120 compatible = "fsl,imx51-esdhc";
121 reg = <0x70004000 0x4000>;
122 interrupts = <1>;
123 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
124 clock-names = "ipg", "ahb", "per";
125 status = "disabled";
126 };
127
128 esdhc2: esdhc@70008000 {
129 compatible = "fsl,imx51-esdhc";
130 reg = <0x70008000 0x4000>;
131 interrupts = <2>;
132 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
133 clock-names = "ipg", "ahb", "per";
134 bus-width = <4>;
135 status = "disabled";
136 };
137
138 uart3: serial@7000c000 {
139 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
140 reg = <0x7000c000 0x4000>;
141 interrupts = <33>;
142 clocks = <&clks 32>, <&clks 33>;
143 clock-names = "ipg", "per";
144 status = "disabled";
145 };
146
147 ecspi1: ecspi@70010000 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "fsl,imx51-ecspi";
151 reg = <0x70010000 0x4000>;
152 interrupts = <36>;
153 clocks = <&clks 51>, <&clks 52>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
157
158 ssi2: ssi@70014000 {
159 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
160 reg = <0x70014000 0x4000>;
161 interrupts = <30>;
162 clocks = <&clks 49>;
163 dmas = <&sdma 24 1 0>,
164 <&sdma 25 1 0>;
165 dma-names = "rx", "tx";
166 fsl,fifo-depth = <15>;
167 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
168 status = "disabled";
169 };
170
171 esdhc3: esdhc@70020000 {
172 compatible = "fsl,imx51-esdhc";
173 reg = <0x70020000 0x4000>;
174 interrupts = <3>;
175 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
176 clock-names = "ipg", "ahb", "per";
177 bus-width = <4>;
178 status = "disabled";
179 };
180
181 esdhc4: esdhc@70024000 {
182 compatible = "fsl,imx51-esdhc";
183 reg = <0x70024000 0x4000>;
184 interrupts = <4>;
185 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
186 clock-names = "ipg", "ahb", "per";
187 bus-width = <4>;
188 status = "disabled";
189 };
190 };
191
192 usbphy0: usbphy@0 {
193 compatible = "usb-nop-xceiv";
194 clocks = <&clks 75>;
195 clock-names = "main_clk";
196 status = "okay";
197 };
198
199 usbotg: usb@73f80000 {
200 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
201 reg = <0x73f80000 0x0200>;
202 interrupts = <18>;
203 clocks = <&clks 108>;
204 fsl,usbmisc = <&usbmisc 0>;
205 fsl,usbphy = <&usbphy0>;
206 status = "disabled";
207 };
208
209 usbh1: usb@73f80200 {
210 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
211 reg = <0x73f80200 0x0200>;
212 interrupts = <14>;
213 clocks = <&clks 108>;
214 fsl,usbmisc = <&usbmisc 1>;
215 status = "disabled";
216 };
217
218 usbh2: usb@73f80400 {
219 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
220 reg = <0x73f80400 0x0200>;
221 interrupts = <16>;
222 clocks = <&clks 108>;
223 fsl,usbmisc = <&usbmisc 2>;
224 status = "disabled";
225 };
226
227 usbh3: usb@73f80600 {
228 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
229 reg = <0x73f80600 0x0200>;
230 interrupts = <17>;
231 clocks = <&clks 108>;
232 fsl,usbmisc = <&usbmisc 3>;
233 status = "disabled";
234 };
235
236 usbmisc: usbmisc@73f80800 {
237 #index-cells = <1>;
238 compatible = "fsl,imx51-usbmisc";
239 reg = <0x73f80800 0x200>;
240 clocks = <&clks 108>;
241 };
242
243 gpio1: gpio@73f84000 {
244 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
245 reg = <0x73f84000 0x4000>;
246 interrupts = <50 51>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 gpio2: gpio@73f88000 {
254 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
255 reg = <0x73f88000 0x4000>;
256 interrupts = <52 53>;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 };
262
263 gpio3: gpio@73f8c000 {
264 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
265 reg = <0x73f8c000 0x4000>;
266 interrupts = <54 55>;
267 gpio-controller;
268 #gpio-cells = <2>;
269 interrupt-controller;
270 #interrupt-cells = <2>;
271 };
272
273 gpio4: gpio@73f90000 {
274 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
275 reg = <0x73f90000 0x4000>;
276 interrupts = <56 57>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 };
282
283 kpp: kpp@73f94000 {
284 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
285 reg = <0x73f94000 0x4000>;
286 interrupts = <60>;
287 clocks = <&clks 0>;
288 status = "disabled";
289 };
290
291 wdog1: wdog@73f98000 {
292 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
293 reg = <0x73f98000 0x4000>;
294 interrupts = <58>;
295 clocks = <&clks 0>;
296 };
297
298 wdog2: wdog@73f9c000 {
299 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
300 reg = <0x73f9c000 0x4000>;
301 interrupts = <59>;
302 clocks = <&clks 0>;
303 status = "disabled";
304 };
305
306 gpt: timer@73fa0000 {
307 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
308 reg = <0x73fa0000 0x4000>;
309 interrupts = <39>;
310 clocks = <&clks 36>, <&clks 41>;
311 clock-names = "ipg", "per";
312 };
313
314 iomuxc: iomuxc@73fa8000 {
315 compatible = "fsl,imx51-iomuxc";
316 reg = <0x73fa8000 0x4000>;
317 };
318
319 pwm1: pwm@73fb4000 {
320 #pwm-cells = <2>;
321 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
322 reg = <0x73fb4000 0x4000>;
323 clocks = <&clks 37>, <&clks 38>;
324 clock-names = "ipg", "per";
325 interrupts = <61>;
326 };
327
328 pwm2: pwm@73fb8000 {
329 #pwm-cells = <2>;
330 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
331 reg = <0x73fb8000 0x4000>;
332 clocks = <&clks 39>, <&clks 40>;
333 clock-names = "ipg", "per";
334 interrupts = <94>;
335 };
336
337 uart1: serial@73fbc000 {
338 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
339 reg = <0x73fbc000 0x4000>;
340 interrupts = <31>;
341 clocks = <&clks 28>, <&clks 29>;
342 clock-names = "ipg", "per";
343 status = "disabled";
344 };
345
346 uart2: serial@73fc0000 {
347 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
348 reg = <0x73fc0000 0x4000>;
349 interrupts = <32>;
350 clocks = <&clks 30>, <&clks 31>;
351 clock-names = "ipg", "per";
352 status = "disabled";
353 };
354
355 src: src@73fd0000 {
356 compatible = "fsl,imx51-src";
357 reg = <0x73fd0000 0x4000>;
358 #reset-cells = <1>;
359 };
360
361 clks: ccm@73fd4000{
362 compatible = "fsl,imx51-ccm";
363 reg = <0x73fd4000 0x4000>;
364 interrupts = <0 71 0x04 0 72 0x04>;
365 #clock-cells = <1>;
366 };
367 };
368
369 aips@80000000 { /* AIPS2 */
370 compatible = "fsl,aips-bus", "simple-bus";
371 #address-cells = <1>;
372 #size-cells = <1>;
373 reg = <0x80000000 0x10000000>;
374 ranges;
375
376 iim: iim@83f98000 {
377 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
378 reg = <0x83f98000 0x4000>;
379 interrupts = <69>;
380 clocks = <&clks 107>;
381 };
382
383 owire: owire@83fa4000 {
384 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
385 reg = <0x83fa4000 0x4000>;
386 interrupts = <88>;
387 clocks = <&clks 159>;
388 status = "disabled";
389 };
390
391 ecspi2: ecspi@83fac000 {
392 #address-cells = <1>;
393 #size-cells = <0>;
394 compatible = "fsl,imx51-ecspi";
395 reg = <0x83fac000 0x4000>;
396 interrupts = <37>;
397 clocks = <&clks 53>, <&clks 54>;
398 clock-names = "ipg", "per";
399 status = "disabled";
400 };
401
402 sdma: sdma@83fb0000 {
403 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
404 reg = <0x83fb0000 0x4000>;
405 interrupts = <6>;
406 clocks = <&clks 56>, <&clks 56>;
407 clock-names = "ipg", "ahb";
408 #dma-cells = <3>;
409 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
410 };
411
412 cspi: cspi@83fc0000 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
416 reg = <0x83fc0000 0x4000>;
417 interrupts = <38>;
418 clocks = <&clks 55>, <&clks 55>;
419 clock-names = "ipg", "per";
420 status = "disabled";
421 };
422
423 i2c2: i2c@83fc4000 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
427 reg = <0x83fc4000 0x4000>;
428 interrupts = <63>;
429 clocks = <&clks 35>;
430 status = "disabled";
431 };
432
433 i2c1: i2c@83fc8000 {
434 #address-cells = <1>;
435 #size-cells = <0>;
436 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
437 reg = <0x83fc8000 0x4000>;
438 interrupts = <62>;
439 clocks = <&clks 34>;
440 status = "disabled";
441 };
442
443 ssi1: ssi@83fcc000 {
444 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
445 reg = <0x83fcc000 0x4000>;
446 interrupts = <29>;
447 clocks = <&clks 48>;
448 dmas = <&sdma 28 0 0>,
449 <&sdma 29 0 0>;
450 dma-names = "rx", "tx";
451 fsl,fifo-depth = <15>;
452 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
453 status = "disabled";
454 };
455
456 audmux: audmux@83fd0000 {
457 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
458 reg = <0x83fd0000 0x4000>;
459 status = "disabled";
460 };
461
462 weim: weim@83fda000 {
463 #address-cells = <2>;
464 #size-cells = <1>;
465 compatible = "fsl,imx51-weim";
466 reg = <0x83fda000 0x1000>;
467 clocks = <&clks 57>;
468 ranges = <
469 0 0 0xb0000000 0x08000000
470 1 0 0xb8000000 0x08000000
471 2 0 0xc0000000 0x08000000
472 3 0 0xc8000000 0x04000000
473 4 0 0xcc000000 0x02000000
474 5 0 0xce000000 0x02000000
475 >;
476 status = "disabled";
477 };
478
479 nfc: nand@83fdb000 {
480 compatible = "fsl,imx51-nand";
481 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
482 interrupts = <8>;
483 clocks = <&clks 60>;
484 status = "disabled";
485 };
486
487 pata: pata@83fe0000 {
488 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
489 reg = <0x83fe0000 0x4000>;
490 interrupts = <70>;
491 clocks = <&clks 172>;
492 status = "disabled";
493 };
494
495 ssi3: ssi@83fe8000 {
496 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
497 reg = <0x83fe8000 0x4000>;
498 interrupts = <96>;
499 clocks = <&clks 50>;
500 dmas = <&sdma 46 0 0>,
501 <&sdma 47 0 0>;
502 dma-names = "rx", "tx";
503 fsl,fifo-depth = <15>;
504 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
505 status = "disabled";
506 };
507
508 fec: ethernet@83fec000 {
509 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
510 reg = <0x83fec000 0x4000>;
511 interrupts = <87>;
512 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
513 clock-names = "ipg", "ahb", "ptp";
514 status = "disabled";
515 };
516 };
517 };
518 };
519
520 &iomuxc {
521 audmux {
522 pinctrl_audmux_1: audmuxgrp-1 {
523 fsl,pins = <
524 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
525 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
526 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
527 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
528 >;
529 };
530 };
531
532 fec {
533 pinctrl_fec_1: fecgrp-1 {
534 fsl,pins = <
535 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
536 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
537 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
538 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
539 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
540 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
541 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
542 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
543 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
544 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
545 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
546 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
547 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
548 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
549 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
550 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
551 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
552 >;
553 };
554
555 pinctrl_fec_2: fecgrp-2 {
556 fsl,pins = <
557 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
558 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
559 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
560 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
561 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
562 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
563 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
564 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
565 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
566 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
567 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
568 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
569 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
570 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
571 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
572 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
573 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
574 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
575 >;
576 };
577 };
578
579 ecspi1 {
580 pinctrl_ecspi1_1: ecspi1grp-1 {
581 fsl,pins = <
582 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
583 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
584 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
585 >;
586 };
587 };
588
589 ecspi2 {
590 pinctrl_ecspi2_1: ecspi2grp-1 {
591 fsl,pins = <
592 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
593 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
594 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
595 >;
596 };
597 };
598
599 esdhc1 {
600 pinctrl_esdhc1_1: esdhc1grp-1 {
601 fsl,pins = <
602 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
603 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
604 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
605 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
606 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
607 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
608 >;
609 };
610 };
611
612 esdhc2 {
613 pinctrl_esdhc2_1: esdhc2grp-1 {
614 fsl,pins = <
615 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
616 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
617 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
618 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
619 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
620 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
621 >;
622 };
623 };
624
625 i2c2 {
626 pinctrl_i2c2_1: i2c2grp-1 {
627 fsl,pins = <
628 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
629 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
630 >;
631 };
632
633 pinctrl_i2c2_2: i2c2grp-2 {
634 fsl,pins = <
635 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
636 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
637 >;
638 };
639
640 pinctrl_i2c2_3: i2c2grp-3 {
641 fsl,pins = <
642 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
643 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
644 >;
645 };
646 };
647
648 ipu_disp1 {
649 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
650 fsl,pins = <
651 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
652 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
653 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
654 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
655 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
656 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
657 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
658 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
659 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
660 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
661 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
662 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
663 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
664 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
665 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
666 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
667 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
668 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
669 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
670 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
671 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
672 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
673 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
674 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
675 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
676 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
677 >;
678 };
679 };
680
681 ipu_disp2 {
682 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
683 fsl,pins = <
684 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
685 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
686 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
687 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
688 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
689 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
690 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
691 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
692 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
693 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
694 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
695 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
696 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
697 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
698 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
699 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
700 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
701 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
702 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
703 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
704 >;
705 };
706 };
707
708 kpp {
709 pinctrl_kpp_1: kppgrp-1 {
710 fsl,pins = <
711 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
712 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
713 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
714 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
715 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
716 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
717 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
718 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
719 >;
720 };
721 };
722
723 pata {
724 pinctrl_pata_1: patagrp-1 {
725 fsl,pins = <
726 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
727 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
728 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
729 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
730 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
731 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
732 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
733 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
734 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
735 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
736 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
737 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
738 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
739 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
740 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
741 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
742 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
743 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
744 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
745 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
746 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
747 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
748 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
749 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
750 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
751 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
752 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
753 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
754 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
755 >;
756 };
757 };
758
759 uart1 {
760 pinctrl_uart1_1: uart1grp-1 {
761 fsl,pins = <
762 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
763 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
764 >;
765 };
766
767 pinctrl_uart1_rtscts_1: uart1rtscts-1 {
768 fsl,pins = <
769 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
770 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
771 >;
772 };
773 };
774
775 uart2 {
776 pinctrl_uart2_1: uart2grp-1 {
777 fsl,pins = <
778 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
779 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
780 >;
781 };
782 };
783
784 uart3 {
785 pinctrl_uart3_1: uart3grp-1 {
786 fsl,pins = <
787 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
788 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
789 >;
790 };
791
792 pinctrl_uart3_rtscts_1: uart3rtscts-1 {
793 fsl,pins = <
794 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
795 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
796 >;
797 };
798
799 pinctrl_uart3_2: uart3grp-2 {
800 fsl,pins = <
801 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
802 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
803 >;
804 };
805 };
806
807 usbh1 {
808 pinctrl_usbh1_1: usbh1grp-1 {
809 fsl,pins = <
810 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
811 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
812 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
813 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
814 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
815 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
816 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
817 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
818 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
819 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
820 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
821 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
822 >;
823 };
824 };
825
826 usbh2 {
827 pinctrl_usbh2_1: usbh2grp-1 {
828 fsl,pins = <
829 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
830 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
831 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
832 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
833 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
834 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
835 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
836 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
837 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
838 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
839 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
840 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
841 >;
842 };
843 };
844 };
Arne's tree of linux kernel.