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1 /*
2 * Copyright (C) 2012 STMicroelectronics Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9 #include "stih41x.dtsi"
10 #include "stih416-clock.dtsi"
11 #include "stih416-pinctrl.dtsi"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 / {
14 L2: cache-controller {
15 compatible = "arm,pl310-cache";
16 reg = <0xfffe2000 0x1000>;
17 arm,data-latency = <3 3 3>;
18 arm,tag-latency = <2 2 2>;
19 cache-unified;
20 cache-level = <2>;
21 };
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 interrupt-parent = <&intc>;
27 ranges;
28 compatible = "simple-bus";
29
30 syscfg_sbc:sbc-syscfg@fe600000{
31 compatible = "st,stih416-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0x1000>;
33 };
34
35 syscfg_front:front-syscfg@fee10000{
36 compatible = "st,stih416-front-syscfg", "syscon";
37 reg = <0xfee10000 0x1000>;
38 };
39
40 syscfg_rear:rear-syscfg@fe830000{
41 compatible = "st,stih416-rear-syscfg", "syscon";
42 reg = <0xfe830000 0x1000>;
43 };
44
45 /* MPE */
46 syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
47 compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
48 reg = <0xfddf0000 0x1000>;
49 };
50
51 syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
52 compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
53 reg = <0xfd6a0000 0x1000>;
54 };
55
56 syscfg_cpu:cpu-syscfg@fdde0000{
57 compatible = "st,stih416-cpu-syscfg", "syscon";
58 reg = <0xfdde0000 0x1000>;
59 };
60
61 syscfg_compo:compo-syscfg@fd320000{
62 compatible = "st,stih416-compo-syscfg", "syscon";
63 reg = <0xfd320000 0x1000>;
64 };
65
66 syscfg_transport:transport-syscfg@fd690000{
67 compatible = "st,stih416-transport-syscfg", "syscon";
68 reg = <0xfd690000 0x1000>;
69 };
70
71 syscfg_lpm:lpm-syscfg@fe4b5100{
72 compatible = "st,stih416-lpm-syscfg", "syscon";
73 reg = <0xfe4b5100 0x8>;
74 };
75
76 serial2: serial@fed32000{
77 compatible = "st,asc";
78 status = "disabled";
79 reg = <0xfed32000 0x2c>;
80 interrupts = <0 197 0>;
81 clocks = <&CLK_S_ICN_REG_0>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
84 };
85
86 /* SBC_UART1 */
87 sbc_serial1: serial@fe531000 {
88 compatible = "st,asc";
89 status = "disabled";
90 reg = <0xfe531000 0x2c>;
91 interrupts = <0 210 0>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_sbc_serial1>;
94 clocks = <&CLK_SYSIN>;
95 };
96
97 i2c@fed40000 {
98 compatible = "st,comms-ssc4-i2c";
99 reg = <0xfed40000 0x110>;
100 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&CLK_S_ICN_REG_0>;
102 clock-names = "ssc";
103 clock-frequency = <400000>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_i2c0_default>;
106
107 status = "disabled";
108 };
109
110 i2c@fed41000 {
111 compatible = "st,comms-ssc4-i2c";
112 reg = <0xfed41000 0x110>;
113 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&CLK_S_ICN_REG_0>;
115 clock-names = "ssc";
116 clock-frequency = <400000>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_i2c1_default>;
119
120 status = "disabled";
121 };
122
123 i2c@fe540000 {
124 compatible = "st,comms-ssc4-i2c";
125 reg = <0xfe540000 0x110>;
126 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&CLK_SYSIN>;
128 clock-names = "ssc";
129 clock-frequency = <400000>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
132
133 status = "disabled";
134 };
135
136 i2c@fe541000 {
137 compatible = "st,comms-ssc4-i2c";
138 reg = <0xfe541000 0x110>;
139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&CLK_SYSIN>;
141 clock-names = "ssc";
142 clock-frequency = <400000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
145
146 status = "disabled";
147 };
148 };
149 };