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powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit)
[people/arne_f/kernel.git] / arch / powerpc / kernel / head_booke.h
1 #ifndef __HEAD_BOOKE_H__
2 #define __HEAD_BOOKE_H__
3
4 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
5 #include <asm/kvm_asm.h>
6 #include <asm/kvm_booke_hv_asm.h>
7
8 /*
9 * Macros used for common Book-e exception handling
10 */
11
12 #define SET_IVOR(vector_number, vector_label) \
13 li r26,vector_label@l; \
14 mtspr SPRN_IVOR##vector_number,r26; \
15 sync
16
17 #if (THREAD_SHIFT < 15)
18 #define ALLOC_STACK_FRAME(reg, val) \
19 addi reg,reg,val
20 #else
21 #define ALLOC_STACK_FRAME(reg, val) \
22 addis reg,reg,val@ha; \
23 addi reg,reg,val@l
24 #endif
25
26 /*
27 * Macro used to get to thread save registers.
28 * Note that entries 0-3 are used for the prolog code, and the remaining
29 * entries are available for specific exception use in the event a handler
30 * requires more than 4 scratch registers.
31 */
32 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
33
34 #define NORMAL_EXCEPTION_PROLOG(intno) \
35 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
36 mfspr r10, SPRN_SPRG_THREAD; \
37 stw r11, THREAD_NORMSAVE(0)(r10); \
38 stw r13, THREAD_NORMSAVE(2)(r10); \
39 mfcr r13; /* save CR in r13 for now */\
40 mfspr r11, SPRN_SRR1; \
41 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
42 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
43 mr r11, r1; \
44 beq 1f; \
45 START_BTB_FLUSH_SECTION \
46 BTB_FLUSH(r11) \
47 END_BTB_FLUSH_SECTION \
48 /* if from user, start at top of this thread's kernel stack */ \
49 lwz r11, THREAD_INFO-THREAD(r10); \
50 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
51 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
52 stw r13, _CCR(r11); /* save various registers */ \
53 stw r12,GPR12(r11); \
54 stw r9,GPR9(r11); \
55 mfspr r13, SPRN_SPRG_RSCRATCH0; \
56 stw r13, GPR10(r11); \
57 lwz r12, THREAD_NORMSAVE(0)(r10); \
58 stw r12,GPR11(r11); \
59 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
60 mflr r10; \
61 stw r10,_LINK(r11); \
62 mfspr r12,SPRN_SRR0; \
63 stw r1, GPR1(r11); \
64 mfspr r9,SPRN_SRR1; \
65 stw r1, 0(r11); \
66 mr r1, r11; \
67 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
68 stw r0,GPR0(r11); \
69 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
70 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
71 stw r10, 8(r11); \
72 SAVE_4GPRS(3, r11); \
73 SAVE_2GPRS(7, r11)
74
75 /* To handle the additional exception priority levels on 40x and Book-E
76 * processors we allocate a stack per additional priority level.
77 *
78 * On 40x critical is the only additional level
79 * On 44x/e500 we have critical and machine check
80 * On e200 we have critical and debug (machine check occurs via critical)
81 *
82 * Additionally we reserve a SPRG for each priority level so we can free up a
83 * GPR to use as the base for indirect access to the exception stacks. This
84 * is necessary since the MMU is always on, for Book-E parts, and the stacks
85 * are offset from KERNELBASE.
86 *
87 * There is some space optimization to be had here if desired. However
88 * to allow for a common kernel with support for debug exceptions either
89 * going to critical or their own debug level we aren't currently
90 * providing configurations that micro-optimize space usage.
91 */
92
93 #define MC_STACK_BASE mcheckirq_ctx
94 #define CRIT_STACK_BASE critirq_ctx
95
96 /* only on e500mc/e200 */
97 #define DBG_STACK_BASE dbgirq_ctx
98
99 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
100
101 #ifdef CONFIG_SMP
102 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
103 mfspr r8,SPRN_PIR; \
104 slwi r8,r8,2; \
105 addis r8,r8,level##_STACK_BASE@ha; \
106 lwz r8,level##_STACK_BASE@l(r8); \
107 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
108 #else
109 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
110 lis r8,level##_STACK_BASE@ha; \
111 lwz r8,level##_STACK_BASE@l(r8); \
112 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
113 #endif
114
115 /*
116 * Exception prolog for critical/machine check exceptions. This is a
117 * little different from the normal exception prolog above since a
118 * critical/machine check exception can potentially occur at any point
119 * during normal exception processing. Thus we cannot use the same SPRG
120 * registers as the normal prolog above. Instead we use a portion of the
121 * critical/machine check exception stack at low physical addresses.
122 */
123 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
124 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
125 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
126 stw r9,GPR9(r8); /* save various registers */\
127 mfcr r9; /* save CR in r9 for now */\
128 stw r10,GPR10(r8); \
129 stw r11,GPR11(r8); \
130 stw r9,_CCR(r8); /* save CR on stack */\
131 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
132 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
133 START_BTB_FLUSH_SECTION \
134 BTB_FLUSH(r10) \
135 END_BTB_FLUSH_SECTION \
136 andi. r11,r11,MSR_PR; \
137 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
138 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
139 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
140 beq 1f; \
141 /* COMING FROM USER MODE */ \
142 stw r9,_CCR(r11); /* save CR */\
143 lwz r10,GPR10(r8); /* copy regs from exception stack */\
144 lwz r9,GPR9(r8); \
145 stw r10,GPR10(r11); \
146 lwz r10,GPR11(r8); \
147 stw r9,GPR9(r11); \
148 stw r10,GPR11(r11); \
149 b 2f; \
150 /* COMING FROM PRIV MODE */ \
151 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \
152 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \
153 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \
154 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \
155 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \
156 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \
157 mr r11,r8; \
158 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
159 stw r12,GPR12(r11); /* save various registers */\
160 mflr r10; \
161 stw r10,_LINK(r11); \
162 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
163 stw r12,_DEAR(r11); /* since they may have had stuff */\
164 mfspr r9,SPRN_ESR; /* in them at the point where the */\
165 stw r9,_ESR(r11); /* exception was taken */\
166 mfspr r12,exc_level_srr0; \
167 stw r1,GPR1(r11); \
168 mfspr r9,exc_level_srr1; \
169 stw r1,0(r11); \
170 mr r1,r11; \
171 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
172 stw r0,GPR0(r11); \
173 SAVE_4GPRS(3, r11); \
174 SAVE_2GPRS(7, r11)
175
176 #define CRITICAL_EXCEPTION_PROLOG(intno) \
177 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
178 #define DEBUG_EXCEPTION_PROLOG \
179 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
180 #define MCHECK_EXCEPTION_PROLOG \
181 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
182 SPRN_MCSRR0, SPRN_MCSRR1)
183
184 /*
185 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
186 * being delivered to the host. This exception can only happen
187 * inside a KVM guest -- so we just handle up to the DO_KVM rather
188 * than try to fit this into one of the existing prolog macros.
189 */
190 #define GUEST_DOORBELL_EXCEPTION \
191 START_EXCEPTION(GuestDoorbell); \
192 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
193 mfspr r10, SPRN_SPRG_THREAD; \
194 stw r11, THREAD_NORMSAVE(0)(r10); \
195 mfspr r11, SPRN_SRR1; \
196 stw r13, THREAD_NORMSAVE(2)(r10); \
197 mfcr r13; /* save CR in r13 for now */\
198 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
199 trap
200
201 /*
202 * Exception vectors.
203 */
204 #define START_EXCEPTION(label) \
205 .align 5; \
206 label:
207
208 #define EXCEPTION(n, intno, label, hdlr, xfer) \
209 START_EXCEPTION(label); \
210 NORMAL_EXCEPTION_PROLOG(intno); \
211 addi r3,r1,STACK_FRAME_OVERHEAD; \
212 xfer(n, hdlr)
213
214 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
215 START_EXCEPTION(label); \
216 CRITICAL_EXCEPTION_PROLOG(intno); \
217 addi r3,r1,STACK_FRAME_OVERHEAD; \
218 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
219 NOCOPY, crit_transfer_to_handler, \
220 ret_from_crit_exc)
221
222 #define MCHECK_EXCEPTION(n, label, hdlr) \
223 START_EXCEPTION(label); \
224 MCHECK_EXCEPTION_PROLOG; \
225 mfspr r5,SPRN_ESR; \
226 stw r5,_ESR(r11); \
227 addi r3,r1,STACK_FRAME_OVERHEAD; \
228 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
229 NOCOPY, mcheck_transfer_to_handler, \
230 ret_from_mcheck_exc)
231
232 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
233 li r10,trap; \
234 stw r10,_TRAP(r11); \
235 lis r10,msr@h; \
236 ori r10,r10,msr@l; \
237 copyee(r10, r9); \
238 bl tfer; \
239 .long hdlr; \
240 .long ret
241
242 #define COPY_EE(d, s) rlwimi d,s,0,16,16
243 #define NOCOPY(d, s)
244
245 #define EXC_XFER_STD(n, hdlr) \
246 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
247 ret_from_except_full)
248
249 #define EXC_XFER_LITE(n, hdlr) \
250 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
251 ret_from_except)
252
253 #define EXC_XFER_EE(n, hdlr) \
254 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
255 ret_from_except_full)
256
257 #define EXC_XFER_EE_LITE(n, hdlr) \
258 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
259 ret_from_except)
260
261 /* Check for a single step debug exception while in an exception
262 * handler before state has been saved. This is to catch the case
263 * where an instruction that we are trying to single step causes
264 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
265 * the exception handler generates a single step debug exception.
266 *
267 * If we get a debug trap on the first instruction of an exception handler,
268 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
269 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
270 * The exception handler was handling a non-critical interrupt, so it will
271 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
272 * the MSR_DE bit set.
273 */
274 #define DEBUG_DEBUG_EXCEPTION \
275 START_EXCEPTION(DebugDebug); \
276 DEBUG_EXCEPTION_PROLOG; \
277 \
278 /* \
279 * If there is a single step or branch-taken exception in an \
280 * exception entry sequence, it was probably meant to apply to \
281 * the code where the exception occurred (since exception entry \
282 * doesn't turn off DE automatically). We simulate the effect \
283 * of turning off DE on entry to an exception handler by turning \
284 * off DE in the DSRR1 value and clearing the debug status. \
285 */ \
286 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
287 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
288 beq+ 2f; \
289 \
290 lis r10,interrupt_base@h; /* check if exception in vectors */ \
291 ori r10,r10,interrupt_base@l; \
292 cmplw r12,r10; \
293 blt+ 2f; /* addr below exception vectors */ \
294 \
295 lis r10,interrupt_end@h; \
296 ori r10,r10,interrupt_end@l; \
297 cmplw r12,r10; \
298 bgt+ 2f; /* addr above exception vectors */ \
299 \
300 /* here it looks like we got an inappropriate debug exception. */ \
301 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
302 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
303 mtspr SPRN_DBSR,r10; \
304 /* restore state and get out */ \
305 lwz r10,_CCR(r11); \
306 lwz r0,GPR0(r11); \
307 lwz r1,GPR1(r11); \
308 mtcrf 0x80,r10; \
309 mtspr SPRN_DSRR0,r12; \
310 mtspr SPRN_DSRR1,r9; \
311 lwz r9,GPR9(r11); \
312 lwz r12,GPR12(r11); \
313 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
314 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
315 lwz r10,GPR10(r8); \
316 lwz r11,GPR11(r8); \
317 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
318 \
319 PPC_RFDI; \
320 b .; \
321 \
322 /* continue normal handling for a debug exception... */ \
323 2: mfspr r4,SPRN_DBSR; \
324 addi r3,r1,STACK_FRAME_OVERHEAD; \
325 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
326
327 #define DEBUG_CRIT_EXCEPTION \
328 START_EXCEPTION(DebugCrit); \
329 CRITICAL_EXCEPTION_PROLOG(DEBUG); \
330 \
331 /* \
332 * If there is a single step or branch-taken exception in an \
333 * exception entry sequence, it was probably meant to apply to \
334 * the code where the exception occurred (since exception entry \
335 * doesn't turn off DE automatically). We simulate the effect \
336 * of turning off DE on entry to an exception handler by turning \
337 * off DE in the CSRR1 value and clearing the debug status. \
338 */ \
339 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
340 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
341 beq+ 2f; \
342 \
343 lis r10,interrupt_base@h; /* check if exception in vectors */ \
344 ori r10,r10,interrupt_base@l; \
345 cmplw r12,r10; \
346 blt+ 2f; /* addr below exception vectors */ \
347 \
348 lis r10,interrupt_end@h; \
349 ori r10,r10,interrupt_end@l; \
350 cmplw r12,r10; \
351 bgt+ 2f; /* addr above exception vectors */ \
352 \
353 /* here it looks like we got an inappropriate debug exception. */ \
354 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
355 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
356 mtspr SPRN_DBSR,r10; \
357 /* restore state and get out */ \
358 lwz r10,_CCR(r11); \
359 lwz r0,GPR0(r11); \
360 lwz r1,GPR1(r11); \
361 mtcrf 0x80,r10; \
362 mtspr SPRN_CSRR0,r12; \
363 mtspr SPRN_CSRR1,r9; \
364 lwz r9,GPR9(r11); \
365 lwz r12,GPR12(r11); \
366 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
367 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
368 lwz r10,GPR10(r8); \
369 lwz r11,GPR11(r8); \
370 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
371 \
372 rfci; \
373 b .; \
374 \
375 /* continue normal handling for a critical exception... */ \
376 2: mfspr r4,SPRN_DBSR; \
377 addi r3,r1,STACK_FRAME_OVERHEAD; \
378 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
379
380 #define DATA_STORAGE_EXCEPTION \
381 START_EXCEPTION(DataStorage) \
382 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
383 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
384 stw r5,_ESR(r11); \
385 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
386 EXC_XFER_LITE(0x0300, handle_page_fault)
387
388 #define INSTRUCTION_STORAGE_EXCEPTION \
389 START_EXCEPTION(InstructionStorage) \
390 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
391 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
392 stw r5,_ESR(r11); \
393 mr r4,r12; /* Pass SRR0 as arg2 */ \
394 li r5,0; /* Pass zero as arg3 */ \
395 EXC_XFER_LITE(0x0400, handle_page_fault)
396
397 #define ALIGNMENT_EXCEPTION \
398 START_EXCEPTION(Alignment) \
399 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
400 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
401 stw r4,_DEAR(r11); \
402 addi r3,r1,STACK_FRAME_OVERHEAD; \
403 EXC_XFER_EE(0x0600, alignment_exception)
404
405 #define PROGRAM_EXCEPTION \
406 START_EXCEPTION(Program) \
407 NORMAL_EXCEPTION_PROLOG(PROGRAM); \
408 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
409 stw r4,_ESR(r11); \
410 addi r3,r1,STACK_FRAME_OVERHEAD; \
411 EXC_XFER_STD(0x0700, program_check_exception)
412
413 #define DECREMENTER_EXCEPTION \
414 START_EXCEPTION(Decrementer) \
415 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
416 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
417 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
418 addi r3,r1,STACK_FRAME_OVERHEAD; \
419 EXC_XFER_LITE(0x0900, timer_interrupt)
420
421 #define FP_UNAVAILABLE_EXCEPTION \
422 START_EXCEPTION(FloatingPointUnavailable) \
423 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
424 beq 1f; \
425 bl load_up_fpu; /* if from user, just load it up */ \
426 b fast_exception_return; \
427 1: addi r3,r1,STACK_FRAME_OVERHEAD; \
428 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
429
430 #ifndef __ASSEMBLY__
431 struct exception_regs {
432 unsigned long mas0;
433 unsigned long mas1;
434 unsigned long mas2;
435 unsigned long mas3;
436 unsigned long mas6;
437 unsigned long mas7;
438 unsigned long srr0;
439 unsigned long srr1;
440 unsigned long csrr0;
441 unsigned long csrr1;
442 unsigned long dsrr0;
443 unsigned long dsrr1;
444 unsigned long saved_ksp_limit;
445 };
446
447 /* ensure this structure is always sized to a multiple of the stack alignment */
448 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
449
450 #endif /* __ASSEMBLY__ */
451 #endif /* __HEAD_BOOKE_H__ */
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