arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/init.h>
  34 #include <linux/threads.h>
  35 #include <asm/processor.h>
  36 #include <asm/page.h>
  37 #include <asm/mmu.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/cputable.h>
  40 #include <asm/thread_info.h>
  41 #include <asm/ppc_asm.h>
  42 #include <asm/asm-offsets.h>
  43 #include <asm/cache.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/export.h>
  46 #include "head_booke.h"
  47
  48 /* As with the other PowerPC ports, it is expected that when code
  49  * execution begins here, the following registers contain valid, yet
  50  * optional, information:
  51  *
  52  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  53  *   r4 - Starting address of the init RAM disk
  54  *   r5 - Ending address of the init RAM disk
  55  *   r6 - Start of kernel command line string (e.g. "mem=128")
  56  *   r7 - End of kernel command line string
  57  *
  58  */
  59         __HEAD
  60 _ENTRY(_stext);
  61 _ENTRY(_start);
  62         /*
  63          * Reserve a word at a fixed location to store the address
  64          * of abatron_pteptrs
  65          */
  66         nop
  67
  68         /* Translate device tree address to physical, save in r30/r31 */
  69         bl      get_phys_addr
  70         mr      r30,r3
  71         mr      r31,r4
  72
  73         li      r25,0                   /* phys kernel start (low) */
  74         li      r24,0                   /* CPU number */
  75         li      r23,0                   /* phys kernel start (high) */
  76
  77 #ifdef CONFIG_RELOCATABLE
  78         LOAD_REG_ADDR_PIC(r3, _stext)   /* Get our current runtime base */
  79
  80         /* Translate _stext address to physical, save in r23/r25 */
  81         bl      get_phys_addr
  82         mr      r23,r3
  83         mr      r25,r4
  84
  85         bl      0f
  86 0:      mflr    r8
  87         addis   r3,r8,(is_second_reloc - 0b)@ha
  88         lwz     r19,(is_second_reloc - 0b)@l(r3)
  89
  90         /* Check if this is the second relocation. */
  91         cmpwi   r19,1
  92         bne     1f
  93
  94         /*
  95          * For the second relocation, we already get the real memstart_addr
  96          * from device tree. So we will map PAGE_OFFSET to memstart_addr,
  97          * then the virtual address of start kernel should be:
  98          *          PAGE_OFFSET + (kernstart_addr - memstart_addr)
  99          * Since the offset between kernstart_addr and memstart_addr should
 100          * never be beyond 1G, so we can just use the lower 32bit of them
 101          * for the calculation.
 102          */
 103         lis     r3,PAGE_OFFSET@h
 104
 105         addis   r4,r8,(kernstart_addr - 0b)@ha
 106         addi    r4,r4,(kernstart_addr - 0b)@l
 107         lwz     r5,4(r4)
 108
 109         addis   r6,r8,(memstart_addr - 0b)@ha
 110         addi    r6,r6,(memstart_addr - 0b)@l
 111         lwz     r7,4(r6)
 112
 113         subf    r5,r7,r5
 114         add     r3,r3,r5
 115         b       2f
 116
 117 1:
 118         /*
 119          * We have the runtime (virutal) address of our base.
 120          * We calculate our shift of offset from a 64M page.
 121          * We could map the 64M page we belong to at PAGE_OFFSET and
 122          * get going from there.
 123          */
 124         lis     r4,KERNELBASE@h
 125         ori     r4,r4,KERNELBASE@l
 126         rlwinm  r6,r25,0,0x3ffffff              /* r6 = PHYS_START % 64M */
 127         rlwinm  r5,r4,0,0x3ffffff               /* r5 = KERNELBASE % 64M */
 128         subf    r3,r5,r6                        /* r3 = r6 - r5 */
 129         add     r3,r4,r3                        /* Required Virtual Address */
 130
 131 2:      bl      relocate
 132
 133         /*
 134          * For the second relocation, we already set the right tlb entries
 135          * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
 136         */
 137         cmpwi   r19,1
 138         beq     set_ivor
 139 #endif
 140
 141 /* We try to not make any assumptions about how the boot loader
 142  * setup or used the TLBs.  We invalidate all mappings from the
 143  * boot loader and load a single entry in TLB1[0] to map the
 144  * first 64M of kernel memory.  Any boot info passed from the
 145  * bootloader needs to live in this first 64M.
 146  *
 147  * Requirement on bootloader:
 148  *  - The page we're executing in needs to reside in TLB1 and
 149  *    have IPROT=1.  If not an invalidate broadcast could
 150  *    evict the entry we're currently executing in.
 151  *
 152  *  r3 = Index of TLB1 were executing in
 153  *  r4 = Current MSR[IS]
 154  *  r5 = Index of TLB1 temp mapping
 155  *
 156  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
 157  * if needed
 158  */
 159
 160 _ENTRY(__early_start)
 161
 162 #define ENTRY_MAPPING_BOOT_SETUP
 163 #include "fsl_booke_entry_mapping.S"
 164 #undef ENTRY_MAPPING_BOOT_SETUP
 165
 166 set_ivor:
 167         /* Establish the interrupt vector offsets */
 168         SET_IVOR(0,  CriticalInput);
 169         SET_IVOR(1,  MachineCheck);
 170         SET_IVOR(2,  DataStorage);
 171         SET_IVOR(3,  InstructionStorage);
 172         SET_IVOR(4,  ExternalInput);
 173         SET_IVOR(5,  Alignment);
 174         SET_IVOR(6,  Program);
 175         SET_IVOR(7,  FloatingPointUnavailable);
 176         SET_IVOR(8,  SystemCall);
 177         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 178         SET_IVOR(10, Decrementer);
 179         SET_IVOR(11, FixedIntervalTimer);
 180         SET_IVOR(12, WatchdogTimer);
 181         SET_IVOR(13, DataTLBError);
 182         SET_IVOR(14, InstructionTLBError);
 183         SET_IVOR(15, DebugCrit);
 184
 185         /* Establish the interrupt vector base */
 186         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 187         mtspr   SPRN_IVPR,r4
 188
 189         /* Setup the defaults for TLB entries */
 190         li      r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
 191 #ifdef CONFIG_E200
 192         oris    r2,r2,MAS4_TLBSELD(1)@h
 193 #endif
 194         mtspr   SPRN_MAS4, r2
 195
 196 #if 0
 197         /* Enable DOZE */
 198         mfspr   r2,SPRN_HID0
 199         oris    r2,r2,HID0_DOZE@h
 200         mtspr   SPRN_HID0, r2
 201 #endif
 202
 203 #if !defined(CONFIG_BDI_SWITCH)
 204         /*
 205          * The Abatron BDI JTAG debugger does not tolerate others
 206          * mucking with the debug registers.
 207          */
 208         lis     r2,DBCR0_IDM@h
 209         mtspr   SPRN_DBCR0,r2
 210         isync
 211         /* clear any residual debug events */
 212         li      r2,-1
 213         mtspr   SPRN_DBSR,r2
 214 #endif
 215
 216 #ifdef CONFIG_SMP
 217         /* Check to see if we're the second processor, and jump
 218          * to the secondary_start code if so
 219          */
 220         LOAD_REG_ADDR_PIC(r24, boot_cpuid)
 221         lwz     r24, 0(r24)
 222         cmpwi   r24, -1
 223         mfspr   r24,SPRN_PIR
 224         bne     __secondary_start
 225 #endif
 226
 227         /*
 228          * This is where the main kernel code starts.
 229          */
 230
 231         /* ptr to current */
 232         lis     r2,init_task@h
 233         ori     r2,r2,init_task@l
 234
 235         /* ptr to current thread */
 236         addi    r4,r2,THREAD    /* init task's THREAD */
 237         mtspr   SPRN_SPRG_THREAD,r4
 238
 239         /* stack */
 240         lis     r1,init_thread_union@h
 241         ori     r1,r1,init_thread_union@l
 242         li      r0,0
 243         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 244
 245         CURRENT_THREAD_INFO(r22, r1)
 246         stw     r24, TI_CPU(r22)
 247
 248         bl      early_init
 249
 250 #ifdef CONFIG_RELOCATABLE
 251         mr      r3,r30
 252         mr      r4,r31
 253 #ifdef CONFIG_PHYS_64BIT
 254         mr      r5,r23
 255         mr      r6,r25
 256 #else
 257         mr      r5,r25
 258 #endif
 259         bl      relocate_init
 260 #endif
 261
 262 #ifdef CONFIG_DYNAMIC_MEMSTART
 263         lis     r3,kernstart_addr@ha
 264         la      r3,kernstart_addr@l(r3)
 265 #ifdef CONFIG_PHYS_64BIT
 266         stw     r23,0(r3)
 267         stw     r25,4(r3)
 268 #else
 269         stw     r25,0(r3)
 270 #endif
 271 #endif
 272
 273 /*
 274  * Decide what sort of machine this is and initialize the MMU.
 275  */
 276         mr      r3,r30
 277         mr      r4,r31
 278         bl      machine_init
 279         bl      MMU_init
 280
 281         /* Setup PTE pointers for the Abatron bdiGDB */
 282         lis     r6, swapper_pg_dir@h
 283         ori     r6, r6, swapper_pg_dir@l
 284         lis     r5, abatron_pteptrs@h
 285         ori     r5, r5, abatron_pteptrs@l
 286         lis     r4, KERNELBASE@h
 287         ori     r4, r4, KERNELBASE@l
 288         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 289         stw     r6, 0(r5)
 290
 291         /* Let's move on */
 292         lis     r4,start_kernel@h
 293         ori     r4,r4,start_kernel@l
 294         lis     r3,MSR_KERNEL@h
 295         ori     r3,r3,MSR_KERNEL@l
 296         mtspr   SPRN_SRR0,r4
 297         mtspr   SPRN_SRR1,r3
 298         rfi                     /* change context and jump to start_kernel */
 299
 300 /* Macros to hide the PTE size differences
 301  *
 302  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 303  *   r10 -- EA of fault
 304  *   r11 -- PGDIR pointer
 305  *   r12 -- free
 306  *   label 2: is the bailout case
 307  *
 308  * if we find the pte (fall through):
 309  *   r11 is low pte word
 310  *   r12 is pointer to the pte
 311  *   r10 is the pshift from the PGD, if we're a hugepage
 312  */
 313 #ifdef CONFIG_PTE_64BIT
 314 #ifdef CONFIG_HUGETLB_PAGE
 315 #define FIND_PTE        \
 316         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 317         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 318         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 319         blt     1000f;                  /* Normal non-huge page */      \
 320         beq     2f;                     /* Bail if no table */          \
 321         oris    r11, r11, PD_HUGE@h;    /* Put back address bit */      \
 322         andi.   r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
 323         xor     r12, r10, r11;          /* drop size bits from pointer */ \
 324         b       1001f;                                                  \
 325 1000:   rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 326         li      r10, 0;                 /* clear r10 */                 \
 327 1001:   lwz     r11, 4(r12);            /* Get pte entry */
 328 #else
 329 #define FIND_PTE        \
 330         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 331         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 332         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 333         beq     2f;                     /* Bail if no table */          \
 334         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 335         lwz     r11, 4(r12);            /* Get pte entry */
 336 #endif /* HUGEPAGE */
 337 #else /* !PTE_64BIT */
 338 #define FIND_PTE        \
 339         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 340         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 341         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 342         beq     2f;                     /* Bail if no table */                  \
 343         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 344         lwz     r11, 0(r12);            /* Get Linux PTE */
 345 #endif
 346
 347 /*
 348  * Interrupt vector entry code
 349  *
 350  * The Book E MMUs are always on so we don't need to handle
 351  * interrupts in real mode as with previous PPC processors. In
 352  * this case we handle interrupts in the kernel virtual address
 353  * space.
 354  *
 355  * Interrupt vectors are dynamically placed relative to the
 356  * interrupt prefix as determined by the address of interrupt_base.
 357  * The interrupt vectors offsets are programmed using the labels
 358  * for each interrupt vector entry.
 359  *
 360  * Interrupt vectors must be aligned on a 16 byte boundary.
 361  * We align on a 32 byte cache line boundary for good measure.
 362  */
 363
 364 interrupt_base:
 365         /* Critical Input Interrupt */
 366         CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
 367
 368         /* Machine Check Interrupt */
 369 #ifdef CONFIG_E200
 370         /* no RFMCI, MCSRRs on E200 */
 371         CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
 372                            machine_check_exception)
 373 #else
 374         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 375 #endif
 376
 377         /* Data Storage Interrupt */
 378         START_EXCEPTION(DataStorage)
 379         NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
 380         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 381         stw     r5,_ESR(r11)
 382         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 383         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 384         bne     1f
 385         EXC_XFER_LITE(0x0300, handle_page_fault)
 386 1:
 387         addi    r3,r1,STACK_FRAME_OVERHEAD
 388         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 389
 390         /* Instruction Storage Interrupt */
 391         INSTRUCTION_STORAGE_EXCEPTION
 392
 393         /* External Input Interrupt */
 394         EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
 395
 396         /* Alignment Interrupt */
 397         ALIGNMENT_EXCEPTION
 398
 399         /* Program Interrupt */
 400         PROGRAM_EXCEPTION
 401
 402         /* Floating Point Unavailable Interrupt */
 403 #ifdef CONFIG_PPC_FPU
 404         FP_UNAVAILABLE_EXCEPTION
 405 #else
 406 #ifdef CONFIG_E200
 407         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 408         EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
 409                   program_check_exception, EXC_XFER_EE)
 410 #else
 411         EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
 412                   unknown_exception, EXC_XFER_EE)
 413 #endif
 414 #endif
 415
 416         /* System Call Interrupt */
 417         START_EXCEPTION(SystemCall)
 418         NORMAL_EXCEPTION_PROLOG(SYSCALL)
 419         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 420
 421         /* Auxiliary Processor Unavailable Interrupt */
 422         EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
 423                   unknown_exception, EXC_XFER_EE)
 424
 425         /* Decrementer Interrupt */
 426         DECREMENTER_EXCEPTION
 427
 428         /* Fixed Internal Timer Interrupt */
 429         /* TODO: Add FIT support */
 430         EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
 431                   unknown_exception, EXC_XFER_EE)
 432
 433         /* Watchdog Timer Interrupt */
 434 #ifdef CONFIG_BOOKE_WDT
 435         CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
 436 #else
 437         CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
 438 #endif
 439
 440         /* Data TLB Error Interrupt */
 441         START_EXCEPTION(DataTLBError)
 442         mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
 443         mfspr   r10, SPRN_SPRG_THREAD
 444         stw     r11, THREAD_NORMSAVE(0)(r10)
 445 #ifdef CONFIG_KVM_BOOKE_HV
 446 BEGIN_FTR_SECTION
 447         mfspr   r11, SPRN_SRR1
 448 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 449 #endif
 450         stw     r12, THREAD_NORMSAVE(1)(r10)
 451         stw     r13, THREAD_NORMSAVE(2)(r10)
 452         mfcr    r13
 453         stw     r13, THREAD_NORMSAVE(3)(r10)
 454         DO_KVM  BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
 455 START_BTB_FLUSH_SECTION
 456         mfspr r11, SPRN_SRR1
 457         andi. r10,r11,MSR_PR
 458         beq 1f
 459         BTB_FLUSH(r10)
 460 1:
 461 END_BTB_FLUSH_SECTION
 462         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 463
 464         /* If we are faulting a kernel address, we have to use the
 465          * kernel page tables.
 466          */
 467         lis     r11, PAGE_OFFSET@h
 468         cmplw   5, r10, r11
 469         blt     5, 3f
 470         lis     r11, swapper_pg_dir@h
 471         ori     r11, r11, swapper_pg_dir@l
 472
 473         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 474         rlwinm  r12,r12,0,16,1
 475         mtspr   SPRN_MAS1,r12
 476
 477         b       4f
 478
 479         /* Get the PGD for the current thread */
 480 3:
 481         mfspr   r11,SPRN_SPRG_THREAD
 482         lwz     r11,PGDIR(r11)
 483
 484 4:
 485         /* Mask of required permission bits. Note that while we
 486          * do copy ESR:ST to _PAGE_RW position as trying to write
 487          * to an RO page is pretty common, we don't do it with
 488          * _PAGE_DIRTY. We could do it, but it's a fairly rare
 489          * event so I'd rather take the overhead when it happens
 490          * rather than adding an instruction here. We should measure
 491          * whether the whole thing is worth it in the first place
 492          * as we could avoid loading SPRN_ESR completely in the first
 493          * place...
 494          *
 495          * TODO: Is it worth doing that mfspr & rlwimi in the first
 496          *       place or can we save a couple of instructions here ?
 497          */
 498         mfspr   r12,SPRN_ESR
 499 #ifdef CONFIG_PTE_64BIT
 500         li      r13,_PAGE_PRESENT
 501         oris    r13,r13,_PAGE_ACCESSED@h
 502 #else
 503         li      r13,_PAGE_PRESENT|_PAGE_ACCESSED
 504 #endif
 505         rlwimi  r13,r12,11,29,29
 506
 507         FIND_PTE
 508         andc.   r13,r13,r11             /* Check permission */
 509
 510 #ifdef CONFIG_PTE_64BIT
 511 #ifdef CONFIG_SMP
 512         subf    r13,r11,r12             /* create false data dep */
 513         lwzx    r13,r11,r13             /* Get upper pte bits */
 514 #else
 515         lwz     r13,0(r12)              /* Get upper pte bits */
 516 #endif
 517 #endif
 518
 519         bne     2f                      /* Bail if permission/valid mismach */
 520
 521         /* Jump to common tlb load */
 522         b       finish_tlb_load
 523 2:
 524         /* The bailout.  Restore registers to pre-exception conditions
 525          * and call the heavyweights to help us out.
 526          */
 527         mfspr   r10, SPRN_SPRG_THREAD
 528         lwz     r11, THREAD_NORMSAVE(3)(r10)
 529         mtcr    r11
 530         lwz     r13, THREAD_NORMSAVE(2)(r10)
 531         lwz     r12, THREAD_NORMSAVE(1)(r10)
 532         lwz     r11, THREAD_NORMSAVE(0)(r10)
 533         mfspr   r10, SPRN_SPRG_RSCRATCH0
 534         b       DataStorage
 535
 536         /* Instruction TLB Error Interrupt */
 537         /*
 538          * Nearly the same as above, except we get our
 539          * information from different registers and bailout
 540          * to a different point.
 541          */
 542         START_EXCEPTION(InstructionTLBError)
 543         mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
 544         mfspr   r10, SPRN_SPRG_THREAD
 545         stw     r11, THREAD_NORMSAVE(0)(r10)
 546 #ifdef CONFIG_KVM_BOOKE_HV
 547 BEGIN_FTR_SECTION
 548         mfspr   r11, SPRN_SRR1
 549 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 550 #endif
 551         stw     r12, THREAD_NORMSAVE(1)(r10)
 552         stw     r13, THREAD_NORMSAVE(2)(r10)
 553         mfcr    r13
 554         stw     r13, THREAD_NORMSAVE(3)(r10)
 555         DO_KVM  BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
 556 START_BTB_FLUSH_SECTION
 557         mfspr r11, SPRN_SRR1
 558         andi. r10,r11,MSR_PR
 559         beq 1f
 560         BTB_FLUSH(r10)
 561 1:
 562 END_BTB_FLUSH_SECTION
 563
 564         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 565
 566         /* If we are faulting a kernel address, we have to use the
 567          * kernel page tables.
 568          */
 569         lis     r11, PAGE_OFFSET@h
 570         cmplw   5, r10, r11
 571         blt     5, 3f
 572         lis     r11, swapper_pg_dir@h
 573         ori     r11, r11, swapper_pg_dir@l
 574
 575         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 576         rlwinm  r12,r12,0,16,1
 577         mtspr   SPRN_MAS1,r12
 578
 579         /* Make up the required permissions for kernel code */
 580 #ifdef CONFIG_PTE_64BIT
 581         li      r13,_PAGE_PRESENT | _PAGE_BAP_SX
 582         oris    r13,r13,_PAGE_ACCESSED@h
 583 #else
 584         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
 585 #endif
 586         b       4f
 587
 588         /* Get the PGD for the current thread */
 589 3:
 590         mfspr   r11,SPRN_SPRG_THREAD
 591         lwz     r11,PGDIR(r11)
 592
 593         /* Make up the required permissions for user code */
 594 #ifdef CONFIG_PTE_64BIT
 595         li      r13,_PAGE_PRESENT | _PAGE_BAP_UX
 596         oris    r13,r13,_PAGE_ACCESSED@h
 597 #else
 598         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
 599 #endif
 600
 601 4:
 602         FIND_PTE
 603         andc.   r13,r13,r11             /* Check permission */
 604
 605 #ifdef CONFIG_PTE_64BIT
 606 #ifdef CONFIG_SMP
 607         subf    r13,r11,r12             /* create false data dep */
 608         lwzx    r13,r11,r13             /* Get upper pte bits */
 609 #else
 610         lwz     r13,0(r12)              /* Get upper pte bits */
 611 #endif
 612 #endif
 613
 614         bne     2f                      /* Bail if permission mismach */
 615
 616         /* Jump to common TLB load point */
 617         b       finish_tlb_load
 618
 619 2:
 620         /* The bailout.  Restore registers to pre-exception conditions
 621          * and call the heavyweights to help us out.
 622          */
 623         mfspr   r10, SPRN_SPRG_THREAD
 624         lwz     r11, THREAD_NORMSAVE(3)(r10)
 625         mtcr    r11
 626         lwz     r13, THREAD_NORMSAVE(2)(r10)
 627         lwz     r12, THREAD_NORMSAVE(1)(r10)
 628         lwz     r11, THREAD_NORMSAVE(0)(r10)
 629         mfspr   r10, SPRN_SPRG_RSCRATCH0
 630         b       InstructionStorage
 631
 632 /* Define SPE handlers for e200 and e500v2 */
 633 #ifdef CONFIG_SPE
 634         /* SPE Unavailable */
 635         START_EXCEPTION(SPEUnavailable)
 636         NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
 637         beq     1f
 638         bl      load_up_spe
 639         b       fast_exception_return
 640 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 641         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 642 #elif defined(CONFIG_SPE_POSSIBLE)
 643         EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
 644                   unknown_exception, EXC_XFER_EE)
 645 #endif /* CONFIG_SPE_POSSIBLE */
 646
 647         /* SPE Floating Point Data */
 648 #ifdef CONFIG_SPE
 649         EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
 650                   SPEFloatingPointException, EXC_XFER_EE)
 651
 652         /* SPE Floating Point Round */
 653         EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
 654                   SPEFloatingPointRoundException, EXC_XFER_EE)
 655 #elif defined(CONFIG_SPE_POSSIBLE)
 656         EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
 657                   unknown_exception, EXC_XFER_EE)
 658         EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
 659                   unknown_exception, EXC_XFER_EE)
 660 #endif /* CONFIG_SPE_POSSIBLE */
 661
 662
 663         /* Performance Monitor */
 664         EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
 665                   performance_monitor_exception, EXC_XFER_STD)
 666
 667         EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
 668
 669         CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
 670                            CriticalDoorbell, unknown_exception)
 671
 672         /* Debug Interrupt */
 673         DEBUG_DEBUG_EXCEPTION
 674         DEBUG_CRIT_EXCEPTION
 675
 676         GUEST_DOORBELL_EXCEPTION
 677
 678         CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
 679                            unknown_exception)
 680
 681         /* Hypercall */
 682         EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
 683
 684         /* Embedded Hypervisor Privilege */
 685         EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
 686
 687 interrupt_end:
 688
 689 /*
 690  * Local functions
 691  */
 692
 693 /*
 694  * Both the instruction and data TLB miss get to this
 695  * point to load the TLB.
 696  *      r10 - tsize encoding (if HUGETLB_PAGE) or available to use
 697  *      r11 - TLB (info from Linux PTE)
 698  *      r12 - available to use
 699  *      r13 - upper bits of PTE (if PTE_64BIT) or available to use
 700  *      CR5 - results of addr >= PAGE_OFFSET
 701  *      MAS0, MAS1 - loaded with proper value when we get here
 702  *      MAS2, MAS3 - will need additional info from Linux PTE
 703  *      Upon exit, we reload everything and RFI.
 704  */
 705 finish_tlb_load:
 706 #ifdef CONFIG_HUGETLB_PAGE
 707         cmpwi   6, r10, 0                       /* check for huge page */
 708         beq     6, finish_tlb_load_cont         /* !huge */
 709
 710         /* Alas, we need more scratch registers for hugepages */
 711         mfspr   r12, SPRN_SPRG_THREAD
 712         stw     r14, THREAD_NORMSAVE(4)(r12)
 713         stw     r15, THREAD_NORMSAVE(5)(r12)
 714         stw     r16, THREAD_NORMSAVE(6)(r12)
 715         stw     r17, THREAD_NORMSAVE(7)(r12)
 716
 717         /* Get the next_tlbcam_idx percpu var */
 718 #ifdef CONFIG_SMP
 719         lwz     r12, THREAD_INFO-THREAD(r12)
 720         lwz     r15, TI_CPU(r12)
 721         lis     r14, __per_cpu_offset@h
 722         ori     r14, r14, __per_cpu_offset@l
 723         rlwinm  r15, r15, 2, 0, 29
 724         lwzx    r16, r14, r15
 725 #else
 726         li      r16, 0
 727 #endif
 728         lis     r17, next_tlbcam_idx@h
 729         ori     r17, r17, next_tlbcam_idx@l
 730         add     r17, r17, r16                   /* r17 = *next_tlbcam_idx */
 731         lwz     r15, 0(r17)                     /* r15 = next_tlbcam_idx */
 732
 733         lis     r14, MAS0_TLBSEL(1)@h           /* select TLB1 (TLBCAM) */
 734         rlwimi  r14, r15, 16, 4, 15             /* next_tlbcam_idx entry */
 735         mtspr   SPRN_MAS0, r14
 736
 737         /* Extract TLB1CFG(NENTRY) */
 738         mfspr   r16, SPRN_TLB1CFG
 739         andi.   r16, r16, 0xfff
 740
 741         /* Update next_tlbcam_idx, wrapping when necessary */
 742         addi    r15, r15, 1
 743         cmpw    r15, r16
 744         blt     100f
 745         lis     r14, tlbcam_index@h
 746         ori     r14, r14, tlbcam_index@l
 747         lwz     r15, 0(r14)
 748 100:    stw     r15, 0(r17)
 749
 750         /*
 751          * Calc MAS1_TSIZE from r10 (which has pshift encoded)
 752          * tlb_enc = (pshift - 10).
 753          */
 754         subi    r15, r10, 10
 755         mfspr   r16, SPRN_MAS1
 756         rlwimi  r16, r15, 7, 20, 24
 757         mtspr   SPRN_MAS1, r16
 758
 759         /* copy the pshift for use later */
 760         mr      r14, r10
 761
 762         /* fall through */
 763
 764 #endif /* CONFIG_HUGETLB_PAGE */
 765
 766         /*
 767          * We set execute, because we don't have the granularity to
 768          * properly set this at the page level (Linux problem).
 769          * Many of these bits are software only.  Bits we don't set
 770          * here we (properly should) assume have the appropriate value.
 771          */
 772 finish_tlb_load_cont:
 773 #ifdef CONFIG_PTE_64BIT
 774         rlwinm  r12, r11, 32-2, 26, 31  /* Move in perm bits */
 775         andi.   r10, r11, _PAGE_DIRTY
 776         bne     1f
 777         li      r10, MAS3_SW | MAS3_UW
 778         andc    r12, r12, r10
 779 1:      rlwimi  r12, r13, 20, 0, 11     /* grab RPN[32:43] */
 780         rlwimi  r12, r11, 20, 12, 19    /* grab RPN[44:51] */
 781 2:      mtspr   SPRN_MAS3, r12
 782 BEGIN_MMU_FTR_SECTION
 783         srwi    r10, r13, 12            /* grab RPN[12:31] */
 784         mtspr   SPRN_MAS7, r10
 785 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
 786 #else
 787         li      r10, (_PAGE_EXEC | _PAGE_PRESENT)
 788         mr      r13, r11
 789         rlwimi  r10, r11, 31, 29, 29    /* extract _PAGE_DIRTY into SW */
 790         and     r12, r11, r10
 791         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 792         slwi    r10, r12, 1
 793         or      r10, r10, r12
 794         iseleq  r12, r12, r10
 795         rlwimi  r13, r12, 0, 20, 31     /* Get RPN from PTE, merge w/ perms */
 796         mtspr   SPRN_MAS3, r13
 797 #endif
 798
 799         mfspr   r12, SPRN_MAS2
 800 #ifdef CONFIG_PTE_64BIT
 801         rlwimi  r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
 802 #else
 803         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 804 #endif
 805 #ifdef CONFIG_HUGETLB_PAGE
 806         beq     6, 3f                   /* don't mask if page isn't huge */
 807         li      r13, 1
 808         slw     r13, r13, r14
 809         subi    r13, r13, 1
 810         rlwinm  r13, r13, 0, 0, 19      /* bottom bits used for WIMGE/etc */
 811         andc    r12, r12, r13           /* mask off ea bits within the page */
 812 #endif
 813 3:      mtspr   SPRN_MAS2, r12
 814
 815 #ifdef CONFIG_E200
 816         /* Round robin TLB1 entries assignment */
 817         mfspr   r12, SPRN_MAS0
 818
 819         /* Extract TLB1CFG(NENTRY) */
 820         mfspr   r11, SPRN_TLB1CFG
 821         andi.   r11, r11, 0xfff
 822
 823         /* Extract MAS0(NV) */
 824         andi.   r13, r12, 0xfff
 825         addi    r13, r13, 1
 826         cmpw    0, r13, r11
 827         addi    r12, r12, 1
 828
 829         /* check if we need to wrap */
 830         blt     7f
 831
 832         /* wrap back to first free tlbcam entry */
 833         lis     r13, tlbcam_index@ha
 834         lwz     r13, tlbcam_index@l(r13)
 835         rlwimi  r12, r13, 0, 20, 31
 836 7:
 837         mtspr   SPRN_MAS0,r12
 838 #endif /* CONFIG_E200 */
 839
 840 tlb_write_entry:
 841         tlbwe
 842
 843         /* Done...restore registers and get out of here.  */
 844         mfspr   r10, SPRN_SPRG_THREAD
 845 #ifdef CONFIG_HUGETLB_PAGE
 846         beq     6, 8f /* skip restore for 4k page faults */
 847         lwz     r14, THREAD_NORMSAVE(4)(r10)
 848         lwz     r15, THREAD_NORMSAVE(5)(r10)
 849         lwz     r16, THREAD_NORMSAVE(6)(r10)
 850         lwz     r17, THREAD_NORMSAVE(7)(r10)
 851 #endif
 852 8:      lwz     r11, THREAD_NORMSAVE(3)(r10)
 853         mtcr    r11
 854         lwz     r13, THREAD_NORMSAVE(2)(r10)
 855         lwz     r12, THREAD_NORMSAVE(1)(r10)
 856         lwz     r11, THREAD_NORMSAVE(0)(r10)
 857         mfspr   r10, SPRN_SPRG_RSCRATCH0
 858         rfi                                     /* Force context change */
 859
 860 #ifdef CONFIG_SPE
 861 /* Note that the SPE support is closely modeled after the AltiVec
 862  * support.  Changes to one are likely to be applicable to the
 863  * other!  */
 864 _GLOBAL(load_up_spe)
 865 /*
 866  * Disable SPE for the task which had SPE previously,
 867  * and save its SPE registers in its thread_struct.
 868  * Enables SPE for use in the kernel on return.
 869  * On SMP we know the SPE units are free, since we give it up every
 870  * switch.  -- Kumar
 871  */
 872         mfmsr   r5
 873         oris    r5,r5,MSR_SPE@h
 874         mtmsr   r5                      /* enable use of SPE now */
 875         isync
 876         /* enable use of SPE after return */
 877         oris    r9,r9,MSR_SPE@h
 878         mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
 879         li      r4,1
 880         li      r10,THREAD_ACC
 881         stw     r4,THREAD_USED_SPE(r5)
 882         evlddx  evr4,r10,r5
 883         evmra   evr4,evr4
 884         REST_32EVRS(0,r10,r5,THREAD_EVR0)
 885         blr
 886
 887 /*
 888  * SPE unavailable trap from kernel - print a message, but let
 889  * the task use SPE in the kernel until it returns to user mode.
 890  */
 891 KernelSPE:
 892         lwz     r3,_MSR(r1)
 893         oris    r3,r3,MSR_SPE@h
 894         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 895 #ifdef CONFIG_PRINTK
 896         lis     r3,87f@h
 897         ori     r3,r3,87f@l
 898         mr      r4,r2           /* current */
 899         lwz     r5,_NIP(r1)
 900         bl      printk
 901 #endif
 902         b       ret_from_except
 903 #ifdef CONFIG_PRINTK
 904 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 905 #endif
 906         .align  4,0
 907
 908 #endif /* CONFIG_SPE */
 909
 910 /*
 911  * Translate the effec addr in r3 to phys addr. The phys addr will be put
 912  * into r3(higher 32bit) and r4(lower 32bit)
 913  */
 914 get_phys_addr:
 915         mfmsr   r8
 916         mfspr   r9,SPRN_PID
 917         rlwinm  r9,r9,16,0x3fff0000     /* turn PID into MAS6[SPID] */
 918         rlwimi  r9,r8,28,0x00000001     /* turn MSR[DS] into MAS6[SAS] */
 919         mtspr   SPRN_MAS6,r9
 920
 921         tlbsx   0,r3                    /* must succeed */
 922
 923         mfspr   r8,SPRN_MAS1
 924         mfspr   r12,SPRN_MAS3
 925         rlwinm  r9,r8,25,0x1f           /* r9 = log2(page size) */
 926         li      r10,1024
 927         slw     r10,r10,r9              /* r10 = page size */
 928         addi    r10,r10,-1
 929         and     r11,r3,r10              /* r11 = page offset */
 930         andc    r4,r12,r10              /* r4 = page base */
 931         or      r4,r4,r11               /* r4 = devtree phys addr */
 932 #ifdef CONFIG_PHYS_64BIT
 933         mfspr   r3,SPRN_MAS7
 934 #endif
 935         blr
 936
 937 /*
 938  * Global functions
 939  */
 940
 941 #ifdef CONFIG_E200
 942 /* Adjust or setup IVORs for e200 */
 943 _GLOBAL(__setup_e200_ivors)
 944         li      r3,DebugDebug@l
 945         mtspr   SPRN_IVOR15,r3
 946         li      r3,SPEUnavailable@l
 947         mtspr   SPRN_IVOR32,r3
 948         li      r3,SPEFloatingPointData@l
 949         mtspr   SPRN_IVOR33,r3
 950         li      r3,SPEFloatingPointRound@l
 951         mtspr   SPRN_IVOR34,r3
 952         sync
 953         blr
 954 #endif
 955
 956 #ifdef CONFIG_E500
 957 #ifndef CONFIG_PPC_E500MC
 958 /* Adjust or setup IVORs for e500v1/v2 */
 959 _GLOBAL(__setup_e500_ivors)
 960         li      r3,DebugCrit@l
 961         mtspr   SPRN_IVOR15,r3
 962         li      r3,SPEUnavailable@l
 963         mtspr   SPRN_IVOR32,r3
 964         li      r3,SPEFloatingPointData@l
 965         mtspr   SPRN_IVOR33,r3
 966         li      r3,SPEFloatingPointRound@l
 967         mtspr   SPRN_IVOR34,r3
 968         li      r3,PerformanceMonitor@l
 969         mtspr   SPRN_IVOR35,r3
 970         sync
 971         blr
 972 #else
 973 /* Adjust or setup IVORs for e500mc */
 974 _GLOBAL(__setup_e500mc_ivors)
 975         li      r3,DebugDebug@l
 976         mtspr   SPRN_IVOR15,r3
 977         li      r3,PerformanceMonitor@l
 978         mtspr   SPRN_IVOR35,r3
 979         li      r3,Doorbell@l
 980         mtspr   SPRN_IVOR36,r3
 981         li      r3,CriticalDoorbell@l
 982         mtspr   SPRN_IVOR37,r3
 983         sync
 984         blr
 985
 986 /* setup ehv ivors for */
 987 _GLOBAL(__setup_ehv_ivors)
 988         li      r3,GuestDoorbell@l
 989         mtspr   SPRN_IVOR38,r3
 990         li      r3,CriticalGuestDoorbell@l
 991         mtspr   SPRN_IVOR39,r3
 992         li      r3,Hypercall@l
 993         mtspr   SPRN_IVOR40,r3
 994         li      r3,Ehvpriv@l
 995         mtspr   SPRN_IVOR41,r3
 996         sync
 997         blr
 998 #endif /* CONFIG_PPC_E500MC */
 999 #endif /* CONFIG_E500 */
1000
1001 #ifdef CONFIG_SPE
1002 /*
1003  * extern void __giveup_spe(struct task_struct *prev)
1004  *
1005  */
1006 _GLOBAL(__giveup_spe)
1007         addi    r3,r3,THREAD            /* want THREAD of task */
1008         lwz     r5,PT_REGS(r3)
1009         cmpi    0,r5,0
1010         SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1011         evxor   evr6, evr6, evr6        /* clear out evr6 */
1012         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
1013         li      r4,THREAD_ACC
1014         evstddx evr6, r4, r3            /* save off accumulator */
1015         beq     1f
1016         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1017         lis     r3,MSR_SPE@h
1018         andc    r4,r4,r3                /* disable SPE for previous task */
1019         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1020 1:
1021         blr
1022 #endif /* CONFIG_SPE */
1023
1024 /*
1025  * extern void abort(void)
1026  *
1027  * At present, this routine just applies a system reset.
1028  */
1029 _GLOBAL(abort)
1030         li      r13,0
1031         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1032         isync
1033         mfmsr   r13
1034         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1035         mtmsr   r13
1036         isync
1037         mfspr   r13,SPRN_DBCR0
1038         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1039         mtspr   SPRN_DBCR0,r13
1040         isync
1041
1042 _GLOBAL(set_context)
1043
1044 #ifdef CONFIG_BDI_SWITCH
1045         /* Context switch the PTE pointer for the Abatron BDI2000.
1046          * The PGDIR is the second parameter.
1047          */
1048         lis     r5, abatron_pteptrs@h
1049         ori     r5, r5, abatron_pteptrs@l
1050         stw     r4, 0x4(r5)
1051 #endif
1052         mtspr   SPRN_PID,r3
1053         isync                   /* Force context change */
1054         blr
1055
1056 #ifdef CONFIG_SMP
1057 /* When we get here, r24 needs to hold the CPU # */
1058         .globl __secondary_start
1059 __secondary_start:
1060         LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1061         lwz     r3,0(r3)
1062         mtctr   r3
1063         li      r26,0           /* r26 safe? */
1064
1065         bl      switch_to_as1
1066         mr      r27,r3          /* tlb entry */
1067         /* Load each CAM entry */
1068 1:      mr      r3,r26
1069         bl      loadcam_entry
1070         addi    r26,r26,1
1071         bdnz    1b
1072         mr      r3,r27          /* tlb entry */
1073         LOAD_REG_ADDR_PIC(r4, memstart_addr)
1074         lwz     r4,0(r4)
1075         mr      r5,r25          /* phys kernel start */
1076         rlwinm  r5,r5,0,~0x3ffffff      /* aligned 64M */
1077         subf    r4,r5,r4        /* memstart_addr - phys kernel start */
1078         li      r5,0            /* no device tree */
1079         li      r6,0            /* not boot cpu */
1080         bl      restore_to_as0
1081
1082
1083         lis     r3,__secondary_hold_acknowledge@h
1084         ori     r3,r3,__secondary_hold_acknowledge@l
1085         stw     r24,0(r3)
1086
1087         li      r3,0
1088         mr      r4,r24          /* Why? */
1089         bl      call_setup_cpu
1090
1091         /* get current_thread_info and current */
1092         lis     r1,secondary_ti@ha
1093         lwz     r1,secondary_ti@l(r1)
1094         lwz     r2,TI_TASK(r1)
1095
1096         /* stack */
1097         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1098         li      r0,0
1099         stw     r0,0(r1)
1100
1101         /* ptr to current thread */
1102         addi    r4,r2,THREAD    /* address of our thread_struct */
1103         mtspr   SPRN_SPRG_THREAD,r4
1104
1105         /* Setup the defaults for TLB entries */
1106         li      r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1107         mtspr   SPRN_MAS4,r4
1108
1109         /* Jump to start_secondary */
1110         lis     r4,MSR_KERNEL@h
1111         ori     r4,r4,MSR_KERNEL@l
1112         lis     r3,start_secondary@h
1113         ori     r3,r3,start_secondary@l
1114         mtspr   SPRN_SRR0,r3
1115         mtspr   SPRN_SRR1,r4
1116         sync
1117         rfi
1118         sync
1119
1120         .globl __secondary_hold_acknowledge
1121 __secondary_hold_acknowledge:
1122         .long   -1
1123 #endif
1124
1125 /*
1126  * Create a tlb entry with the same effective and physical address as
1127  * the tlb entry used by the current running code. But set the TS to 1.
1128  * Then switch to the address space 1. It will return with the r3 set to
1129  * the ESEL of the new created tlb.
1130  */
1131 _GLOBAL(switch_to_as1)
1132         mflr    r5
1133
1134         /* Find a entry not used */
1135         mfspr   r3,SPRN_TLB1CFG
1136         andi.   r3,r3,0xfff
1137         mfspr   r4,SPRN_PID
1138         rlwinm  r4,r4,16,0x3fff0000     /* turn PID into MAS6[SPID] */
1139         mtspr   SPRN_MAS6,r4
1140 1:      lis     r4,0x1000               /* Set MAS0(TLBSEL) = 1 */
1141         addi    r3,r3,-1
1142         rlwimi  r4,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
1143         mtspr   SPRN_MAS0,r4
1144         tlbre
1145         mfspr   r4,SPRN_MAS1
1146         andis.  r4,r4,MAS1_VALID@h
1147         bne     1b
1148
1149         /* Get the tlb entry used by the current running code */
1150         bl      0f
1151 0:      mflr    r4
1152         tlbsx   0,r4
1153
1154         mfspr   r4,SPRN_MAS1
1155         ori     r4,r4,MAS1_TS           /* Set the TS = 1 */
1156         mtspr   SPRN_MAS1,r4
1157
1158         mfspr   r4,SPRN_MAS0
1159         rlwinm  r4,r4,0,~MAS0_ESEL_MASK
1160         rlwimi  r4,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
1161         mtspr   SPRN_MAS0,r4
1162         tlbwe
1163         isync
1164         sync
1165
1166         mfmsr   r4
1167         ori     r4,r4,MSR_IS | MSR_DS
1168         mtspr   SPRN_SRR0,r5
1169         mtspr   SPRN_SRR1,r4
1170         sync
1171         rfi
1172
1173 /*
1174  * Restore to the address space 0 and also invalidate the tlb entry created
1175  * by switch_to_as1.
1176  * r3 - the tlb entry which should be invalidated
1177  * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1178  * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1179  * r6 - boot cpu
1180 */
1181 _GLOBAL(restore_to_as0)
1182         mflr    r0
1183
1184         bl      0f
1185 0:      mflr    r9
1186         addi    r9,r9,1f - 0b
1187
1188         /*
1189          * We may map the PAGE_OFFSET in AS0 to a different physical address,
1190          * so we need calculate the right jump and device tree address based
1191          * on the offset passed by r4.
1192          */
1193         add     r9,r9,r4
1194         add     r5,r5,r4
1195         add     r0,r0,r4
1196
1197 2:      mfmsr   r7
1198         li      r8,(MSR_IS | MSR_DS)
1199         andc    r7,r7,r8
1200
1201         mtspr   SPRN_SRR0,r9
1202         mtspr   SPRN_SRR1,r7
1203         sync
1204         rfi
1205
1206         /* Invalidate the temporary tlb entry for AS1 */
1207 1:      lis     r9,0x1000               /* Set MAS0(TLBSEL) = 1 */
1208         rlwimi  r9,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
1209         mtspr   SPRN_MAS0,r9
1210         tlbre
1211         mfspr   r9,SPRN_MAS1
1212         rlwinm  r9,r9,0,2,31            /* Clear MAS1 Valid and IPPROT */
1213         mtspr   SPRN_MAS1,r9
1214         tlbwe
1215         isync
1216
1217         cmpwi   r4,0
1218         cmpwi   cr1,r6,0
1219         cror    eq,4*cr1+eq,eq
1220         bne     3f                      /* offset != 0 && is_boot_cpu */
1221         mtlr    r0
1222         blr
1223
1224         /*
1225          * The PAGE_OFFSET will map to a different physical address,
1226          * jump to _start to do another relocation again.
1227         */
1228 3:      mr      r3,r5
1229         bl      _start
1230
1231 /*
1232  * We put a few things here that have to be page-aligned. This stuff
1233  * goes at the beginning of the data segment, which is page-aligned.
1234  */
1235         .data
1236         .align  12
1237         .globl  sdata
1238 sdata:
1239         .globl  empty_zero_page
1240 empty_zero_page:
1241         .space  4096
1242 EXPORT_SYMBOL(empty_zero_page)
1243         .globl  swapper_pg_dir
1244 swapper_pg_dir:
1245         .space  PGD_TABLE_SIZE
1246
1247 /*
1248  * Room for two PTE pointers, usually the kernel and current user pointers
1249  * to their respective root page table.
1250  */
1251 abatron_pteptrs:
1252         .space  8