2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
28 #include <linux/fault-inject.h>
29 #include <linux/log2.h>
30 #include <linux/random.h>
31 #include <linux/seq_file.h>
32 #include <linux/stop_machine.h>
34 #include <asm/set_memory.h>
37 #include <drm/i915_drm.h>
40 #include "i915_vgpu.h"
41 #include "i915_trace.h"
42 #include "intel_drv.h"
43 #include "intel_frontbuffer.h"
45 #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM)
48 * DOC: Global GTT views
50 * Background and previous state
52 * Historically objects could exists (be bound) in global GTT space only as
53 * singular instances with a view representing all of the object's backing pages
54 * in a linear fashion. This view will be called a normal view.
56 * To support multiple views of the same object, where the number of mapped
57 * pages is not equal to the backing store, or where the layout of the pages
58 * is not linear, concept of a GGTT view was added.
60 * One example of an alternative view is a stereo display driven by a single
61 * image. In this case we would have a framebuffer looking like this
67 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
68 * rendering. In contrast, fed to the display engine would be an alternative
69 * view which could look something like this:
74 * In this example both the size and layout of pages in the alternative view is
75 * different from the normal view.
77 * Implementation and usage
79 * GGTT views are implemented using VMAs and are distinguished via enum
80 * i915_ggtt_view_type and struct i915_ggtt_view.
82 * A new flavour of core GEM functions which work with GGTT bound objects were
83 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
84 * renaming in large amounts of code. They take the struct i915_ggtt_view
85 * parameter encapsulating all metadata required to implement a view.
87 * As a helper for callers which are only interested in the normal view,
88 * globally const i915_ggtt_view_normal singleton instance exists. All old core
89 * GEM API functions, the ones not taking the view parameter, are operating on,
90 * or with the normal GGTT view.
92 * Code wanting to add or use a new GGTT view needs to:
94 * 1. Add a new enum with a suitable name.
95 * 2. Extend the metadata in the i915_ggtt_view structure if required.
96 * 3. Add support to i915_get_vma_pages().
98 * New views are required to build a scatter-gather table from within the
99 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
100 * exists for the lifetime of an VMA.
102 * Core API is designed to have copy semantics which means that passed in
103 * struct i915_ggtt_view does not need to be persistent (left around after
104 * calling the core API functions).
109 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
111 static void gen6_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
113 /* Note that as an uncached mmio write, this should flush the
114 * WCB of the writes into the GGTT before it triggers the invalidate.
116 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
119 static void guc_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
121 gen6_ggtt_invalidate(dev_priv
);
122 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
125 static void gmch_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
127 intel_gtt_chipset_flush();
130 static inline void i915_ggtt_invalidate(struct drm_i915_private
*i915
)
132 i915
->ggtt
.invalidate(i915
);
135 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
138 bool has_aliasing_ppgtt
;
140 bool has_full_48bit_ppgtt
;
142 has_aliasing_ppgtt
= dev_priv
->info
.has_aliasing_ppgtt
;
143 has_full_ppgtt
= dev_priv
->info
.has_full_ppgtt
;
144 has_full_48bit_ppgtt
= dev_priv
->info
.has_full_48bit_ppgtt
;
146 if (intel_vgpu_active(dev_priv
)) {
147 /* GVT-g has no support for 32bit ppgtt */
148 has_full_ppgtt
= false;
149 has_full_48bit_ppgtt
= intel_vgpu_has_full_48bit_ppgtt(dev_priv
);
152 if (!has_aliasing_ppgtt
)
156 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
157 * execlists, the sole mechanism available to submit work.
159 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
162 if (enable_ppgtt
== 1)
165 if (enable_ppgtt
== 2 && has_full_ppgtt
)
168 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
171 /* Disable ppgtt on SNB if VT-d is on. */
172 if (IS_GEN6(dev_priv
) && intel_vtd_active()) {
173 DRM_INFO("Disabling PPGTT because VT-d is on\n");
177 /* Early VLV doesn't have this */
178 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
179 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
183 if (INTEL_GEN(dev_priv
) >= 8 && i915
.enable_execlists
) {
184 if (has_full_48bit_ppgtt
)
191 return has_aliasing_ppgtt
? 1 : 0;
194 static int ppgtt_bind_vma(struct i915_vma
*vma
,
195 enum i915_cache_level cache_level
,
201 if (!(vma
->flags
& I915_VMA_LOCAL_BIND
)) {
202 ret
= vma
->vm
->allocate_va_range(vma
->vm
, vma
->node
.start
,
208 vma
->pages
= vma
->obj
->mm
.pages
;
210 /* Currently applicable only to VLV */
213 pte_flags
|= PTE_READ_ONLY
;
215 vma
->vm
->insert_entries(vma
->vm
, vma
, cache_level
, pte_flags
);
220 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
222 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
225 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
226 enum i915_cache_level level
)
228 gen8_pte_t pte
= _PAGE_PRESENT
| _PAGE_RW
;
232 case I915_CACHE_NONE
:
233 pte
|= PPAT_UNCACHED_INDEX
;
236 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
239 pte
|= PPAT_CACHED_INDEX
;
246 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
247 const enum i915_cache_level level
)
249 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
251 if (level
!= I915_CACHE_NONE
)
252 pde
|= PPAT_CACHED_PDE_INDEX
;
254 pde
|= PPAT_UNCACHED_INDEX
;
258 #define gen8_pdpe_encode gen8_pde_encode
259 #define gen8_pml4e_encode gen8_pde_encode
261 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
262 enum i915_cache_level level
,
265 gen6_pte_t pte
= GEN6_PTE_VALID
;
266 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
269 case I915_CACHE_L3_LLC
:
271 pte
|= GEN6_PTE_CACHE_LLC
;
273 case I915_CACHE_NONE
:
274 pte
|= GEN6_PTE_UNCACHED
;
283 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
284 enum i915_cache_level level
,
287 gen6_pte_t pte
= GEN6_PTE_VALID
;
288 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
291 case I915_CACHE_L3_LLC
:
292 pte
|= GEN7_PTE_CACHE_L3_LLC
;
295 pte
|= GEN6_PTE_CACHE_LLC
;
297 case I915_CACHE_NONE
:
298 pte
|= GEN6_PTE_UNCACHED
;
307 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
308 enum i915_cache_level level
,
311 gen6_pte_t pte
= GEN6_PTE_VALID
;
312 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
314 if (!(flags
& PTE_READ_ONLY
))
315 pte
|= BYT_PTE_WRITEABLE
;
317 if (level
!= I915_CACHE_NONE
)
318 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
323 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
324 enum i915_cache_level level
,
327 gen6_pte_t pte
= GEN6_PTE_VALID
;
328 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
330 if (level
!= I915_CACHE_NONE
)
331 pte
|= HSW_WB_LLC_AGE3
;
336 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
337 enum i915_cache_level level
,
340 gen6_pte_t pte
= GEN6_PTE_VALID
;
341 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
344 case I915_CACHE_NONE
:
347 pte
|= HSW_WT_ELLC_LLC_AGE3
;
350 pte
|= HSW_WB_ELLC_LLC_AGE3
;
357 static struct page
*vm_alloc_page(struct i915_address_space
*vm
, gfp_t gfp
)
361 if (I915_SELFTEST_ONLY(should_fail(&vm
->fault_attr
, 1)))
362 i915_gem_shrink_all(vm
->i915
);
364 if (vm
->free_pages
.nr
)
365 return vm
->free_pages
.pages
[--vm
->free_pages
.nr
];
367 page
= alloc_page(gfp
);
372 set_pages_array_wc(&page
, 1);
377 static void vm_free_pages_release(struct i915_address_space
*vm
)
379 GEM_BUG_ON(!pagevec_count(&vm
->free_pages
));
382 set_pages_array_wb(vm
->free_pages
.pages
,
383 pagevec_count(&vm
->free_pages
));
385 __pagevec_release(&vm
->free_pages
);
388 static void vm_free_page(struct i915_address_space
*vm
, struct page
*page
)
390 if (!pagevec_add(&vm
->free_pages
, page
))
391 vm_free_pages_release(vm
);
394 static int __setup_page_dma(struct i915_address_space
*vm
,
395 struct i915_page_dma
*p
,
398 p
->page
= vm_alloc_page(vm
, gfp
| __GFP_NOWARN
| __GFP_NORETRY
);
399 if (unlikely(!p
->page
))
402 p
->daddr
= dma_map_page(vm
->dma
, p
->page
, 0, PAGE_SIZE
,
403 PCI_DMA_BIDIRECTIONAL
);
404 if (unlikely(dma_mapping_error(vm
->dma
, p
->daddr
))) {
405 vm_free_page(vm
, p
->page
);
412 static int setup_page_dma(struct i915_address_space
*vm
,
413 struct i915_page_dma
*p
)
415 return __setup_page_dma(vm
, p
, I915_GFP_DMA
);
418 static void cleanup_page_dma(struct i915_address_space
*vm
,
419 struct i915_page_dma
*p
)
421 dma_unmap_page(vm
->dma
, p
->daddr
, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
422 vm_free_page(vm
, p
->page
);
425 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
427 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
428 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
429 #define fill_px(ppgtt, px, v) fill_page_dma((vm), px_base(px), (v))
430 #define fill32_px(ppgtt, px, v) fill_page_dma_32((vm), px_base(px), (v))
432 static void fill_page_dma(struct i915_address_space
*vm
,
433 struct i915_page_dma
*p
,
436 u64
* const vaddr
= kmap_atomic(p
->page
);
439 for (i
= 0; i
< 512; i
++)
442 kunmap_atomic(vaddr
);
445 static void fill_page_dma_32(struct i915_address_space
*vm
,
446 struct i915_page_dma
*p
,
449 fill_page_dma(vm
, p
, (u64
)v
<< 32 | v
);
453 setup_scratch_page(struct i915_address_space
*vm
, gfp_t gfp
)
455 return __setup_page_dma(vm
, &vm
->scratch_page
, gfp
| __GFP_ZERO
);
458 static void cleanup_scratch_page(struct i915_address_space
*vm
)
460 cleanup_page_dma(vm
, &vm
->scratch_page
);
463 static struct i915_page_table
*alloc_pt(struct i915_address_space
*vm
)
465 struct i915_page_table
*pt
;
467 pt
= kmalloc(sizeof(*pt
), GFP_KERNEL
| __GFP_NOWARN
);
469 return ERR_PTR(-ENOMEM
);
471 if (unlikely(setup_px(vm
, pt
))) {
473 return ERR_PTR(-ENOMEM
);
480 static void free_pt(struct i915_address_space
*vm
, struct i915_page_table
*pt
)
486 static void gen8_initialize_pt(struct i915_address_space
*vm
,
487 struct i915_page_table
*pt
)
490 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
));
493 static void gen6_initialize_pt(struct i915_address_space
*vm
,
494 struct i915_page_table
*pt
)
497 vm
->pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
, 0));
500 static struct i915_page_directory
*alloc_pd(struct i915_address_space
*vm
)
502 struct i915_page_directory
*pd
;
504 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
| __GFP_NOWARN
);
506 return ERR_PTR(-ENOMEM
);
508 if (unlikely(setup_px(vm
, pd
))) {
510 return ERR_PTR(-ENOMEM
);
517 static void free_pd(struct i915_address_space
*vm
,
518 struct i915_page_directory
*pd
)
524 static void gen8_initialize_pd(struct i915_address_space
*vm
,
525 struct i915_page_directory
*pd
)
530 gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
));
531 for (i
= 0; i
< I915_PDES
; i
++)
532 pd
->page_table
[i
] = vm
->scratch_pt
;
535 static int __pdp_init(struct i915_address_space
*vm
,
536 struct i915_page_directory_pointer
*pdp
)
538 const unsigned int pdpes
= i915_pdpes_per_pdp(vm
);
541 pdp
->page_directory
= kmalloc_array(pdpes
, sizeof(*pdp
->page_directory
),
542 GFP_KERNEL
| __GFP_NOWARN
);
543 if (unlikely(!pdp
->page_directory
))
546 for (i
= 0; i
< pdpes
; i
++)
547 pdp
->page_directory
[i
] = vm
->scratch_pd
;
552 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
554 kfree(pdp
->page_directory
);
555 pdp
->page_directory
= NULL
;
558 static inline bool use_4lvl(const struct i915_address_space
*vm
)
560 return i915_vm_is_48bit(vm
);
563 static struct i915_page_directory_pointer
*
564 alloc_pdp(struct i915_address_space
*vm
)
566 struct i915_page_directory_pointer
*pdp
;
569 WARN_ON(!use_4lvl(vm
));
571 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
573 return ERR_PTR(-ENOMEM
);
575 ret
= __pdp_init(vm
, pdp
);
579 ret
= setup_px(vm
, pdp
);
593 static void free_pdp(struct i915_address_space
*vm
,
594 struct i915_page_directory_pointer
*pdp
)
605 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
606 struct i915_page_directory_pointer
*pdp
)
608 gen8_ppgtt_pdpe_t scratch_pdpe
;
610 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
612 fill_px(vm
, pdp
, scratch_pdpe
);
615 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
616 struct i915_pml4
*pml4
)
621 gen8_pml4e_encode(px_dma(vm
->scratch_pdp
), I915_CACHE_LLC
));
622 for (i
= 0; i
< GEN8_PML4ES_PER_PML4
; i
++)
623 pml4
->pdps
[i
] = vm
->scratch_pdp
;
626 /* Broadwell Page Directory Pointer Descriptors */
627 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
631 struct intel_engine_cs
*engine
= req
->engine
;
636 cs
= intel_ring_begin(req
, 6);
640 *cs
++ = MI_LOAD_REGISTER_IMM(1);
641 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine
, entry
));
642 *cs
++ = upper_32_bits(addr
);
643 *cs
++ = MI_LOAD_REGISTER_IMM(1);
644 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine
, entry
));
645 *cs
++ = lower_32_bits(addr
);
646 intel_ring_advance(req
, cs
);
651 static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt
*ppgtt
,
652 struct drm_i915_gem_request
*req
)
656 for (i
= GEN8_3LVL_PDPES
- 1; i
>= 0; i
--) {
657 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
659 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
667 static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt
*ppgtt
,
668 struct drm_i915_gem_request
*req
)
670 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
673 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
674 * the page table structures, we mark them dirty so that
675 * context switching/execlist queuing code takes extra steps
676 * to ensure that tlbs are flushed.
678 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
680 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.i915
)->ring_mask
;
683 /* Removes entries from a single page table, releasing it if it's empty.
684 * Caller can use the return value to update higher-level entries.
686 static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm
,
687 struct i915_page_table
*pt
,
688 u64 start
, u64 length
)
690 unsigned int num_entries
= gen8_pte_count(start
, length
);
691 unsigned int pte
= gen8_pte_index(start
);
692 unsigned int pte_end
= pte
+ num_entries
;
693 const gen8_pte_t scratch_pte
=
694 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
697 GEM_BUG_ON(num_entries
> pt
->used_ptes
);
699 pt
->used_ptes
-= num_entries
;
703 vaddr
= kmap_atomic_px(pt
);
704 while (pte
< pte_end
)
705 vaddr
[pte
++] = scratch_pte
;
706 kunmap_atomic(vaddr
);
711 static void gen8_ppgtt_set_pde(struct i915_address_space
*vm
,
712 struct i915_page_directory
*pd
,
713 struct i915_page_table
*pt
,
718 pd
->page_table
[pde
] = pt
;
720 vaddr
= kmap_atomic_px(pd
);
721 vaddr
[pde
] = gen8_pde_encode(px_dma(pt
), I915_CACHE_LLC
);
722 kunmap_atomic(vaddr
);
725 static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm
,
726 struct i915_page_directory
*pd
,
727 u64 start
, u64 length
)
729 struct i915_page_table
*pt
;
732 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
733 GEM_BUG_ON(pt
== vm
->scratch_pt
);
735 if (!gen8_ppgtt_clear_pt(vm
, pt
, start
, length
))
738 gen8_ppgtt_set_pde(vm
, pd
, vm
->scratch_pt
, pde
);
739 GEM_BUG_ON(!pd
->used_pdes
);
745 return !pd
->used_pdes
;
748 static void gen8_ppgtt_set_pdpe(struct i915_address_space
*vm
,
749 struct i915_page_directory_pointer
*pdp
,
750 struct i915_page_directory
*pd
,
753 gen8_ppgtt_pdpe_t
*vaddr
;
755 pdp
->page_directory
[pdpe
] = pd
;
759 vaddr
= kmap_atomic_px(pdp
);
760 vaddr
[pdpe
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
761 kunmap_atomic(vaddr
);
764 /* Removes entries from a single page dir pointer, releasing it if it's empty.
765 * Caller can use the return value to update higher-level entries
767 static bool gen8_ppgtt_clear_pdp(struct i915_address_space
*vm
,
768 struct i915_page_directory_pointer
*pdp
,
769 u64 start
, u64 length
)
771 struct i915_page_directory
*pd
;
774 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
775 GEM_BUG_ON(pd
== vm
->scratch_pd
);
777 if (!gen8_ppgtt_clear_pd(vm
, pd
, start
, length
))
780 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
781 GEM_BUG_ON(!pdp
->used_pdpes
);
787 return !pdp
->used_pdpes
;
790 static void gen8_ppgtt_clear_3lvl(struct i915_address_space
*vm
,
791 u64 start
, u64 length
)
793 gen8_ppgtt_clear_pdp(vm
, &i915_vm_to_ppgtt(vm
)->pdp
, start
, length
);
796 static void gen8_ppgtt_set_pml4e(struct i915_pml4
*pml4
,
797 struct i915_page_directory_pointer
*pdp
,
800 gen8_ppgtt_pml4e_t
*vaddr
;
802 pml4
->pdps
[pml4e
] = pdp
;
804 vaddr
= kmap_atomic_px(pml4
);
805 vaddr
[pml4e
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
806 kunmap_atomic(vaddr
);
809 /* Removes entries from a single pml4.
810 * This is the top-level structure in 4-level page tables used on gen8+.
811 * Empty entries are always scratch pml4e.
813 static void gen8_ppgtt_clear_4lvl(struct i915_address_space
*vm
,
814 u64 start
, u64 length
)
816 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
817 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
818 struct i915_page_directory_pointer
*pdp
;
821 GEM_BUG_ON(!use_4lvl(vm
));
823 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
824 GEM_BUG_ON(pdp
== vm
->scratch_pdp
);
826 if (!gen8_ppgtt_clear_pdp(vm
, pdp
, start
, length
))
829 gen8_ppgtt_set_pml4e(pml4
, vm
->scratch_pdp
, pml4e
);
836 struct scatterlist
*sg
;
840 struct gen8_insert_pte
{
847 static __always_inline
struct gen8_insert_pte
gen8_insert_pte(u64 start
)
849 return (struct gen8_insert_pte
) {
850 gen8_pml4e_index(start
),
851 gen8_pdpe_index(start
),
852 gen8_pde_index(start
),
853 gen8_pte_index(start
),
857 static __always_inline
bool
858 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt
*ppgtt
,
859 struct i915_page_directory_pointer
*pdp
,
860 struct sgt_dma
*iter
,
861 struct gen8_insert_pte
*idx
,
862 enum i915_cache_level cache_level
)
864 struct i915_page_directory
*pd
;
865 const gen8_pte_t pte_encode
= gen8_pte_encode(0, cache_level
);
869 GEM_BUG_ON(idx
->pdpe
>= i915_pdpes_per_pdp(&ppgtt
->base
));
870 pd
= pdp
->page_directory
[idx
->pdpe
];
871 vaddr
= kmap_atomic_px(pd
->page_table
[idx
->pde
]);
873 vaddr
[idx
->pte
] = pte_encode
| iter
->dma
;
875 iter
->dma
+= PAGE_SIZE
;
876 if (iter
->dma
>= iter
->max
) {
877 iter
->sg
= __sg_next(iter
->sg
);
883 iter
->dma
= sg_dma_address(iter
->sg
);
884 iter
->max
= iter
->dma
+ iter
->sg
->length
;
887 if (++idx
->pte
== GEN8_PTES
) {
890 if (++idx
->pde
== I915_PDES
) {
893 /* Limited by sg length for 3lvl */
894 if (++idx
->pdpe
== GEN8_PML4ES_PER_PML4
) {
900 GEM_BUG_ON(idx
->pdpe
>= i915_pdpes_per_pdp(&ppgtt
->base
));
901 pd
= pdp
->page_directory
[idx
->pdpe
];
904 kunmap_atomic(vaddr
);
905 vaddr
= kmap_atomic_px(pd
->page_table
[idx
->pde
]);
908 kunmap_atomic(vaddr
);
913 static void gen8_ppgtt_insert_3lvl(struct i915_address_space
*vm
,
914 struct i915_vma
*vma
,
915 enum i915_cache_level cache_level
,
918 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
919 struct sgt_dma iter
= {
920 .sg
= vma
->pages
->sgl
,
921 .dma
= sg_dma_address(iter
.sg
),
922 .max
= iter
.dma
+ iter
.sg
->length
,
924 struct gen8_insert_pte idx
= gen8_insert_pte(vma
->node
.start
);
926 gen8_ppgtt_insert_pte_entries(ppgtt
, &ppgtt
->pdp
, &iter
, &idx
,
930 static void gen8_ppgtt_insert_4lvl(struct i915_address_space
*vm
,
931 struct i915_vma
*vma
,
932 enum i915_cache_level cache_level
,
935 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
936 struct sgt_dma iter
= {
937 .sg
= vma
->pages
->sgl
,
938 .dma
= sg_dma_address(iter
.sg
),
939 .max
= iter
.dma
+ iter
.sg
->length
,
941 struct i915_page_directory_pointer
**pdps
= ppgtt
->pml4
.pdps
;
942 struct gen8_insert_pte idx
= gen8_insert_pte(vma
->node
.start
);
944 while (gen8_ppgtt_insert_pte_entries(ppgtt
, pdps
[idx
.pml4e
++], &iter
,
946 GEM_BUG_ON(idx
.pml4e
>= GEN8_PML4ES_PER_PML4
);
949 static void gen8_free_page_tables(struct i915_address_space
*vm
,
950 struct i915_page_directory
*pd
)
957 for (i
= 0; i
< I915_PDES
; i
++) {
958 if (pd
->page_table
[i
] != vm
->scratch_pt
)
959 free_pt(vm
, pd
->page_table
[i
]);
963 static int gen8_init_scratch(struct i915_address_space
*vm
)
967 ret
= setup_scratch_page(vm
, I915_GFP_DMA
);
971 vm
->scratch_pt
= alloc_pt(vm
);
972 if (IS_ERR(vm
->scratch_pt
)) {
973 ret
= PTR_ERR(vm
->scratch_pt
);
974 goto free_scratch_page
;
977 vm
->scratch_pd
= alloc_pd(vm
);
978 if (IS_ERR(vm
->scratch_pd
)) {
979 ret
= PTR_ERR(vm
->scratch_pd
);
984 vm
->scratch_pdp
= alloc_pdp(vm
);
985 if (IS_ERR(vm
->scratch_pdp
)) {
986 ret
= PTR_ERR(vm
->scratch_pdp
);
991 gen8_initialize_pt(vm
, vm
->scratch_pt
);
992 gen8_initialize_pd(vm
, vm
->scratch_pd
);
994 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
999 free_pd(vm
, vm
->scratch_pd
);
1001 free_pt(vm
, vm
->scratch_pt
);
1003 cleanup_scratch_page(vm
);
1008 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
1010 struct i915_address_space
*vm
= &ppgtt
->base
;
1011 struct drm_i915_private
*dev_priv
= vm
->i915
;
1012 enum vgt_g2v_type msg
;
1016 const u64 daddr
= px_dma(&ppgtt
->pml4
);
1018 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
1019 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
1021 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
1022 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
1024 for (i
= 0; i
< GEN8_3LVL_PDPES
; i
++) {
1025 const u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1027 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
1028 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
1031 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
1032 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
1035 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
1040 static void gen8_free_scratch(struct i915_address_space
*vm
)
1043 free_pdp(vm
, vm
->scratch_pdp
);
1044 free_pd(vm
, vm
->scratch_pd
);
1045 free_pt(vm
, vm
->scratch_pt
);
1046 cleanup_scratch_page(vm
);
1049 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space
*vm
,
1050 struct i915_page_directory_pointer
*pdp
)
1052 const unsigned int pdpes
= i915_pdpes_per_pdp(vm
);
1055 for (i
= 0; i
< pdpes
; i
++) {
1056 if (pdp
->page_directory
[i
] == vm
->scratch_pd
)
1059 gen8_free_page_tables(vm
, pdp
->page_directory
[i
]);
1060 free_pd(vm
, pdp
->page_directory
[i
]);
1066 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
1070 for (i
= 0; i
< GEN8_PML4ES_PER_PML4
; i
++) {
1071 if (ppgtt
->pml4
.pdps
[i
] == ppgtt
->base
.scratch_pdp
)
1074 gen8_ppgtt_cleanup_3lvl(&ppgtt
->base
, ppgtt
->pml4
.pdps
[i
]);
1077 cleanup_px(&ppgtt
->base
, &ppgtt
->pml4
);
1080 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
1082 struct drm_i915_private
*dev_priv
= vm
->i915
;
1083 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1085 if (intel_vgpu_active(dev_priv
))
1086 gen8_ppgtt_notify_vgt(ppgtt
, false);
1089 gen8_ppgtt_cleanup_4lvl(ppgtt
);
1091 gen8_ppgtt_cleanup_3lvl(&ppgtt
->base
, &ppgtt
->pdp
);
1093 gen8_free_scratch(vm
);
1096 static int gen8_ppgtt_alloc_pd(struct i915_address_space
*vm
,
1097 struct i915_page_directory
*pd
,
1098 u64 start
, u64 length
)
1100 struct i915_page_table
*pt
;
1104 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1105 if (pt
== vm
->scratch_pt
) {
1110 gen8_initialize_pt(vm
, pt
);
1112 gen8_ppgtt_set_pde(vm
, pd
, pt
, pde
);
1114 GEM_BUG_ON(pd
->used_pdes
> I915_PDES
);
1117 pt
->used_ptes
+= gen8_pte_count(start
, length
);
1122 gen8_ppgtt_clear_pd(vm
, pd
, from
, start
- from
);
1126 static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm
,
1127 struct i915_page_directory_pointer
*pdp
,
1128 u64 start
, u64 length
)
1130 struct i915_page_directory
*pd
;
1135 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1136 if (pd
== vm
->scratch_pd
) {
1141 gen8_initialize_pd(vm
, pd
);
1142 gen8_ppgtt_set_pdpe(vm
, pdp
, pd
, pdpe
);
1144 GEM_BUG_ON(pdp
->used_pdpes
> i915_pdpes_per_pdp(vm
));
1146 mark_tlbs_dirty(i915_vm_to_ppgtt(vm
));
1149 ret
= gen8_ppgtt_alloc_pd(vm
, pd
, start
, length
);
1157 if (!pd
->used_pdes
) {
1158 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
1159 GEM_BUG_ON(!pdp
->used_pdpes
);
1164 gen8_ppgtt_clear_pdp(vm
, pdp
, from
, start
- from
);
1168 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space
*vm
,
1169 u64 start
, u64 length
)
1171 return gen8_ppgtt_alloc_pdp(vm
,
1172 &i915_vm_to_ppgtt(vm
)->pdp
, start
, length
);
1175 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space
*vm
,
1176 u64 start
, u64 length
)
1178 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1179 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1180 struct i915_page_directory_pointer
*pdp
;
1185 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1186 if (pml4
->pdps
[pml4e
] == vm
->scratch_pdp
) {
1187 pdp
= alloc_pdp(vm
);
1191 gen8_initialize_pdp(vm
, pdp
);
1192 gen8_ppgtt_set_pml4e(pml4
, pdp
, pml4e
);
1195 ret
= gen8_ppgtt_alloc_pdp(vm
, pdp
, start
, length
);
1203 if (!pdp
->used_pdpes
) {
1204 gen8_ppgtt_set_pml4e(pml4
, vm
->scratch_pdp
, pml4e
);
1208 gen8_ppgtt_clear_4lvl(vm
, from
, start
- from
);
1212 static void gen8_dump_pdp(struct i915_hw_ppgtt
*ppgtt
,
1213 struct i915_page_directory_pointer
*pdp
,
1214 u64 start
, u64 length
,
1215 gen8_pte_t scratch_pte
,
1218 struct i915_address_space
*vm
= &ppgtt
->base
;
1219 struct i915_page_directory
*pd
;
1222 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1223 struct i915_page_table
*pt
;
1224 u64 pd_len
= length
;
1225 u64 pd_start
= start
;
1228 if (pdp
->page_directory
[pdpe
] == ppgtt
->base
.scratch_pd
)
1231 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1232 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1234 gen8_pte_t
*pt_vaddr
;
1236 if (pd
->page_table
[pde
] == ppgtt
->base
.scratch_pt
)
1239 pt_vaddr
= kmap_atomic_px(pt
);
1240 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1241 u64 va
= (pdpe
<< GEN8_PDPE_SHIFT
|
1242 pde
<< GEN8_PDE_SHIFT
|
1243 pte
<< GEN8_PTE_SHIFT
);
1247 for (i
= 0; i
< 4; i
++)
1248 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1253 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1254 for (i
= 0; i
< 4; i
++) {
1255 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1256 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1258 seq_puts(m
, " SCRATCH ");
1262 kunmap_atomic(pt_vaddr
);
1267 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1269 struct i915_address_space
*vm
= &ppgtt
->base
;
1270 const gen8_pte_t scratch_pte
=
1271 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
1272 u64 start
= 0, length
= ppgtt
->base
.total
;
1276 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1277 struct i915_page_directory_pointer
*pdp
;
1279 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1280 if (pml4
->pdps
[pml4e
] == ppgtt
->base
.scratch_pdp
)
1283 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1284 gen8_dump_pdp(ppgtt
, pdp
, start
, length
, scratch_pte
, m
);
1287 gen8_dump_pdp(ppgtt
, &ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1291 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt
*ppgtt
)
1293 struct i915_address_space
*vm
= &ppgtt
->base
;
1294 struct i915_page_directory_pointer
*pdp
= &ppgtt
->pdp
;
1295 struct i915_page_directory
*pd
;
1296 u64 start
= 0, length
= ppgtt
->base
.total
;
1300 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1305 gen8_initialize_pd(vm
, pd
);
1306 gen8_ppgtt_set_pdpe(vm
, pdp
, pd
, pdpe
);
1310 pdp
->used_pdpes
++; /* never remove */
1315 gen8_for_each_pdpe(pd
, pdp
, from
, start
, pdpe
) {
1316 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
1319 pdp
->used_pdpes
= 0;
1324 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1325 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1326 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1330 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1332 struct i915_address_space
*vm
= &ppgtt
->base
;
1333 struct drm_i915_private
*dev_priv
= vm
->i915
;
1336 ppgtt
->base
.total
= USES_FULL_48BIT_PPGTT(dev_priv
) ?
1340 ret
= gen8_init_scratch(&ppgtt
->base
);
1342 ppgtt
->base
.total
= 0;
1346 /* There are only few exceptions for gen >=6. chv and bxt.
1347 * And we are not sure about the latter so play safe for now.
1349 if (IS_CHERRYVIEW(dev_priv
) || IS_BROXTON(dev_priv
))
1350 ppgtt
->base
.pt_kmap_wc
= true;
1353 ret
= setup_px(&ppgtt
->base
, &ppgtt
->pml4
);
1357 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1359 ppgtt
->switch_mm
= gen8_mm_switch_4lvl
;
1360 ppgtt
->base
.allocate_va_range
= gen8_ppgtt_alloc_4lvl
;
1361 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_4lvl
;
1362 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_4lvl
;
1364 ret
= __pdp_init(&ppgtt
->base
, &ppgtt
->pdp
);
1368 if (intel_vgpu_active(dev_priv
)) {
1369 ret
= gen8_preallocate_top_level_pdp(ppgtt
);
1371 __pdp_fini(&ppgtt
->pdp
);
1376 ppgtt
->switch_mm
= gen8_mm_switch_3lvl
;
1377 ppgtt
->base
.allocate_va_range
= gen8_ppgtt_alloc_3lvl
;
1378 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_3lvl
;
1379 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_3lvl
;
1382 if (intel_vgpu_active(dev_priv
))
1383 gen8_ppgtt_notify_vgt(ppgtt
, true);
1385 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1386 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1387 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1388 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1393 gen8_free_scratch(&ppgtt
->base
);
1397 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1399 struct i915_address_space
*vm
= &ppgtt
->base
;
1400 struct i915_page_table
*unused
;
1401 gen6_pte_t scratch_pte
;
1402 u32 pd_entry
, pte
, pde
;
1403 u32 start
= 0, length
= ppgtt
->base
.total
;
1405 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
1408 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1410 gen6_pte_t
*pt_vaddr
;
1411 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1412 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1413 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1415 if (pd_entry
!= expected
)
1416 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1420 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1422 pt_vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[pde
]);
1424 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1426 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1430 for (i
= 0; i
< 4; i
++)
1431 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1436 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1437 for (i
= 0; i
< 4; i
++) {
1438 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1439 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1441 seq_puts(m
, " SCRATCH ");
1445 kunmap_atomic(pt_vaddr
);
1449 /* Write pde (index) from the page directory @pd to the page table @pt */
1450 static inline void gen6_write_pde(const struct i915_hw_ppgtt
*ppgtt
,
1451 const unsigned int pde
,
1452 const struct i915_page_table
*pt
)
1454 /* Caller needs to make sure the write completes if necessary */
1455 writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt
)) | GEN6_PDE_VALID
,
1456 ppgtt
->pd_addr
+ pde
);
1459 /* Write all the page tables found in the ppgtt structure to incrementing page
1461 static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt
,
1462 u32 start
, u32 length
)
1464 struct i915_page_table
*pt
;
1467 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
)
1468 gen6_write_pde(ppgtt
, pde
, pt
);
1470 mark_tlbs_dirty(ppgtt
);
1474 static inline u32
get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1476 GEM_BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1477 return ppgtt
->pd
.base
.ggtt_offset
<< 10;
1480 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1481 struct drm_i915_gem_request
*req
)
1483 struct intel_engine_cs
*engine
= req
->engine
;
1486 /* NB: TLBs must be flushed and invalidated before a switch */
1487 cs
= intel_ring_begin(req
, 6);
1491 *cs
++ = MI_LOAD_REGISTER_IMM(2);
1492 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine
));
1493 *cs
++ = PP_DIR_DCLV_2G
;
1494 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine
));
1495 *cs
++ = get_pd_offset(ppgtt
);
1497 intel_ring_advance(req
, cs
);
1502 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1503 struct drm_i915_gem_request
*req
)
1505 struct intel_engine_cs
*engine
= req
->engine
;
1508 /* NB: TLBs must be flushed and invalidated before a switch */
1509 cs
= intel_ring_begin(req
, 6);
1513 *cs
++ = MI_LOAD_REGISTER_IMM(2);
1514 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine
));
1515 *cs
++ = PP_DIR_DCLV_2G
;
1516 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine
));
1517 *cs
++ = get_pd_offset(ppgtt
);
1519 intel_ring_advance(req
, cs
);
1524 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1525 struct drm_i915_gem_request
*req
)
1527 struct intel_engine_cs
*engine
= req
->engine
;
1528 struct drm_i915_private
*dev_priv
= req
->i915
;
1530 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1531 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1535 static void gen8_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1537 struct intel_engine_cs
*engine
;
1538 enum intel_engine_id id
;
1540 for_each_engine(engine
, dev_priv
, id
) {
1541 u32 four_level
= USES_FULL_48BIT_PPGTT(dev_priv
) ?
1542 GEN8_GFX_PPGTT_48B
: 0;
1543 I915_WRITE(RING_MODE_GEN7(engine
),
1544 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1548 static void gen7_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1550 struct intel_engine_cs
*engine
;
1551 u32 ecochk
, ecobits
;
1552 enum intel_engine_id id
;
1554 ecobits
= I915_READ(GAC_ECO_BITS
);
1555 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1557 ecochk
= I915_READ(GAM_ECOCHK
);
1558 if (IS_HASWELL(dev_priv
)) {
1559 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1561 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1562 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1564 I915_WRITE(GAM_ECOCHK
, ecochk
);
1566 for_each_engine(engine
, dev_priv
, id
) {
1567 /* GFX_MODE is per-ring on gen7+ */
1568 I915_WRITE(RING_MODE_GEN7(engine
),
1569 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1573 static void gen6_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1575 u32 ecochk
, gab_ctl
, ecobits
;
1577 ecobits
= I915_READ(GAC_ECO_BITS
);
1578 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1579 ECOBITS_PPGTT_CACHE64B
);
1581 gab_ctl
= I915_READ(GAB_CTL
);
1582 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1584 ecochk
= I915_READ(GAM_ECOCHK
);
1585 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1587 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1590 /* PPGTT support for Sandybdrige/Gen6 and later */
1591 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1592 u64 start
, u64 length
)
1594 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1595 unsigned int first_entry
= start
>> PAGE_SHIFT
;
1596 unsigned int pde
= first_entry
/ GEN6_PTES
;
1597 unsigned int pte
= first_entry
% GEN6_PTES
;
1598 unsigned int num_entries
= length
>> PAGE_SHIFT
;
1599 gen6_pte_t scratch_pte
=
1600 vm
->pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
, 0);
1602 while (num_entries
) {
1603 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
++];
1604 unsigned int end
= min(pte
+ num_entries
, GEN6_PTES
);
1607 num_entries
-= end
- pte
;
1609 /* Note that the hw doesn't support removing PDE on the fly
1610 * (they are cached inside the context with no means to
1611 * invalidate the cache), so we can only reset the PTE
1612 * entries back to scratch.
1615 vaddr
= kmap_atomic_px(pt
);
1617 vaddr
[pte
++] = scratch_pte
;
1618 } while (pte
< end
);
1619 kunmap_atomic(vaddr
);
1625 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1626 struct i915_vma
*vma
,
1627 enum i915_cache_level cache_level
,
1630 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1631 unsigned first_entry
= vma
->node
.start
>> PAGE_SHIFT
;
1632 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1633 unsigned act_pte
= first_entry
% GEN6_PTES
;
1634 const u32 pte_encode
= vm
->pte_encode(0, cache_level
, flags
);
1635 struct sgt_dma iter
;
1638 vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[act_pt
]);
1639 iter
.sg
= vma
->pages
->sgl
;
1640 iter
.dma
= sg_dma_address(iter
.sg
);
1641 iter
.max
= iter
.dma
+ iter
.sg
->length
;
1643 vaddr
[act_pte
] = pte_encode
| GEN6_PTE_ADDR_ENCODE(iter
.dma
);
1645 iter
.dma
+= PAGE_SIZE
;
1646 if (iter
.dma
== iter
.max
) {
1647 iter
.sg
= __sg_next(iter
.sg
);
1651 iter
.dma
= sg_dma_address(iter
.sg
);
1652 iter
.max
= iter
.dma
+ iter
.sg
->length
;
1655 if (++act_pte
== GEN6_PTES
) {
1656 kunmap_atomic(vaddr
);
1657 vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[++act_pt
]);
1661 kunmap_atomic(vaddr
);
1664 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1665 u64 start
, u64 length
)
1667 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1668 struct i915_page_table
*pt
;
1673 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1674 if (pt
== vm
->scratch_pt
) {
1679 gen6_initialize_pt(vm
, pt
);
1680 ppgtt
->pd
.page_table
[pde
] = pt
;
1681 gen6_write_pde(ppgtt
, pde
, pt
);
1687 mark_tlbs_dirty(ppgtt
);
1694 gen6_ppgtt_clear_range(vm
, from
, start
);
1698 static int gen6_init_scratch(struct i915_address_space
*vm
)
1702 ret
= setup_scratch_page(vm
, I915_GFP_DMA
);
1706 vm
->scratch_pt
= alloc_pt(vm
);
1707 if (IS_ERR(vm
->scratch_pt
)) {
1708 cleanup_scratch_page(vm
);
1709 return PTR_ERR(vm
->scratch_pt
);
1712 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1717 static void gen6_free_scratch(struct i915_address_space
*vm
)
1719 free_pt(vm
, vm
->scratch_pt
);
1720 cleanup_scratch_page(vm
);
1723 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1725 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1726 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1727 struct i915_page_table
*pt
;
1730 drm_mm_remove_node(&ppgtt
->node
);
1732 gen6_for_all_pdes(pt
, pd
, pde
)
1733 if (pt
!= vm
->scratch_pt
)
1736 gen6_free_scratch(vm
);
1739 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1741 struct i915_address_space
*vm
= &ppgtt
->base
;
1742 struct drm_i915_private
*dev_priv
= ppgtt
->base
.i915
;
1743 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1746 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1747 * allocator works in address space sizes, so it's multiplied by page
1748 * size. We allocate at the top of the GTT to avoid fragmentation.
1750 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
1752 ret
= gen6_init_scratch(vm
);
1756 ret
= i915_gem_gtt_insert(&ggtt
->base
, &ppgtt
->node
,
1757 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1758 I915_COLOR_UNEVICTABLE
,
1759 0, ggtt
->base
.total
,
1764 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
1765 DRM_DEBUG("Forced to use aperture for PDEs\n");
1767 ppgtt
->pd
.base
.ggtt_offset
=
1768 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1770 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
1771 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1776 gen6_free_scratch(vm
);
1780 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1782 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1785 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1786 u64 start
, u64 length
)
1788 struct i915_page_table
*unused
;
1791 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
1792 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
1795 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1797 struct drm_i915_private
*dev_priv
= ppgtt
->base
.i915
;
1798 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1801 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
1802 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev_priv
))
1803 ppgtt
->switch_mm
= gen6_mm_switch
;
1804 else if (IS_HASWELL(dev_priv
))
1805 ppgtt
->switch_mm
= hsw_mm_switch
;
1806 else if (IS_GEN7(dev_priv
))
1807 ppgtt
->switch_mm
= gen7_mm_switch
;
1811 ret
= gen6_ppgtt_alloc(ppgtt
);
1815 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1817 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1818 gen6_write_page_range(ppgtt
, 0, ppgtt
->base
.total
);
1820 ret
= gen6_alloc_va_range(&ppgtt
->base
, 0, ppgtt
->base
.total
);
1822 gen6_ppgtt_cleanup(&ppgtt
->base
);
1826 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1827 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1828 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1829 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1830 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1831 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1833 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1834 ppgtt
->node
.size
>> 20,
1835 ppgtt
->node
.start
/ PAGE_SIZE
);
1837 DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
1838 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1843 static int __hw_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
1844 struct drm_i915_private
*dev_priv
)
1846 ppgtt
->base
.i915
= dev_priv
;
1847 ppgtt
->base
.dma
= &dev_priv
->drm
.pdev
->dev
;
1849 if (INTEL_INFO(dev_priv
)->gen
< 8)
1850 return gen6_ppgtt_init(ppgtt
);
1852 return gen8_ppgtt_init(ppgtt
);
1855 static void i915_address_space_init(struct i915_address_space
*vm
,
1856 struct drm_i915_private
*dev_priv
,
1859 i915_gem_timeline_init(dev_priv
, &vm
->timeline
, name
);
1861 drm_mm_init(&vm
->mm
, 0, vm
->total
);
1862 vm
->mm
.head_node
.color
= I915_COLOR_UNEVICTABLE
;
1864 INIT_LIST_HEAD(&vm
->active_list
);
1865 INIT_LIST_HEAD(&vm
->inactive_list
);
1866 INIT_LIST_HEAD(&vm
->unbound_list
);
1868 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
1869 pagevec_init(&vm
->free_pages
, false);
1872 static void i915_address_space_fini(struct i915_address_space
*vm
)
1874 if (pagevec_count(&vm
->free_pages
))
1875 vm_free_pages_release(vm
);
1877 i915_gem_timeline_fini(&vm
->timeline
);
1878 drm_mm_takedown(&vm
->mm
);
1879 list_del(&vm
->global_link
);
1882 static void gtt_write_workarounds(struct drm_i915_private
*dev_priv
)
1884 /* This function is for gtt related workarounds. This function is
1885 * called on driver load and after a GPU reset, so you can place
1886 * workarounds here even if they get overwritten by GPU reset.
1888 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
1889 if (IS_BROADWELL(dev_priv
))
1890 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
1891 else if (IS_CHERRYVIEW(dev_priv
))
1892 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
1893 else if (IS_GEN9_BC(dev_priv
))
1894 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
1895 else if (IS_GEN9_LP(dev_priv
))
1896 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
1899 int i915_ppgtt_init_hw(struct drm_i915_private
*dev_priv
)
1901 gtt_write_workarounds(dev_priv
);
1903 /* In the case of execlists, PPGTT is enabled by the context descriptor
1904 * and the PDPs are contained within the context itself. We don't
1905 * need to do anything here. */
1906 if (i915
.enable_execlists
)
1909 if (!USES_PPGTT(dev_priv
))
1912 if (IS_GEN6(dev_priv
))
1913 gen6_ppgtt_enable(dev_priv
);
1914 else if (IS_GEN7(dev_priv
))
1915 gen7_ppgtt_enable(dev_priv
);
1916 else if (INTEL_GEN(dev_priv
) >= 8)
1917 gen8_ppgtt_enable(dev_priv
);
1919 MISSING_CASE(INTEL_GEN(dev_priv
));
1924 struct i915_hw_ppgtt
*
1925 i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
1926 struct drm_i915_file_private
*fpriv
,
1929 struct i915_hw_ppgtt
*ppgtt
;
1932 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1934 return ERR_PTR(-ENOMEM
);
1936 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
1939 return ERR_PTR(ret
);
1942 kref_init(&ppgtt
->ref
);
1943 i915_address_space_init(&ppgtt
->base
, dev_priv
, name
);
1944 ppgtt
->base
.file
= fpriv
;
1946 trace_i915_ppgtt_create(&ppgtt
->base
);
1951 void i915_ppgtt_close(struct i915_address_space
*vm
)
1953 struct list_head
*phases
[] = {
1960 GEM_BUG_ON(vm
->closed
);
1963 for (phase
= phases
; *phase
; phase
++) {
1964 struct i915_vma
*vma
, *vn
;
1966 list_for_each_entry_safe(vma
, vn
, *phase
, vm_link
)
1967 if (!i915_vma_is_closed(vma
))
1968 i915_vma_close(vma
);
1972 void i915_ppgtt_release(struct kref
*kref
)
1974 struct i915_hw_ppgtt
*ppgtt
=
1975 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1977 trace_i915_ppgtt_release(&ppgtt
->base
);
1979 /* vmas should already be unbound and destroyed */
1980 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1981 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1982 WARN_ON(!list_empty(&ppgtt
->base
.unbound_list
));
1984 ppgtt
->base
.cleanup(&ppgtt
->base
);
1985 i915_address_space_fini(&ppgtt
->base
);
1989 /* Certain Gen5 chipsets require require idling the GPU before
1990 * unmapping anything from the GTT when VT-d is enabled.
1992 static bool needs_idle_maps(struct drm_i915_private
*dev_priv
)
1994 /* Query intel_iommu to see if we need the workaround. Presumably that
1997 return IS_GEN5(dev_priv
) && IS_MOBILE(dev_priv
) && intel_vtd_active();
2000 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2002 struct intel_engine_cs
*engine
;
2003 enum intel_engine_id id
;
2005 if (INTEL_INFO(dev_priv
)->gen
< 6)
2008 for_each_engine(engine
, dev_priv
, id
) {
2010 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2011 if (fault_reg
& RING_FAULT_VALID
) {
2012 DRM_DEBUG_DRIVER("Unexpected fault\n"
2014 "\tAddress space: %s\n"
2017 fault_reg
& PAGE_MASK
,
2018 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2019 RING_FAULT_SRCID(fault_reg
),
2020 RING_FAULT_FAULT_TYPE(fault_reg
));
2021 I915_WRITE(RING_FAULT_REG(engine
),
2022 fault_reg
& ~RING_FAULT_VALID
);
2026 /* Engine specific init may not have been done till this point. */
2027 if (dev_priv
->engine
[RCS
])
2028 POSTING_READ(RING_FAULT_REG(dev_priv
->engine
[RCS
]));
2031 void i915_gem_suspend_gtt_mappings(struct drm_i915_private
*dev_priv
)
2033 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2035 /* Don't bother messing with faults pre GEN6 as we have little
2036 * documentation supporting that it's a good idea.
2038 if (INTEL_GEN(dev_priv
) < 6)
2041 i915_check_and_clear_faults(dev_priv
);
2043 ggtt
->base
.clear_range(&ggtt
->base
, 0, ggtt
->base
.total
);
2045 i915_ggtt_invalidate(dev_priv
);
2048 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object
*obj
,
2049 struct sg_table
*pages
)
2052 if (dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2053 pages
->sgl
, pages
->nents
,
2054 PCI_DMA_BIDIRECTIONAL
))
2057 /* If the DMA remap fails, one cause can be that we have
2058 * too many objects pinned in a small remapping table,
2059 * such as swiotlb. Incrementally purge all other objects and
2060 * try again - if there are no more pages to remove from
2061 * the DMA remapper, i915_gem_shrink will return 0.
2063 GEM_BUG_ON(obj
->mm
.pages
== pages
);
2064 } while (i915_gem_shrink(to_i915(obj
->base
.dev
),
2065 obj
->base
.size
>> PAGE_SHIFT
, NULL
,
2067 I915_SHRINK_UNBOUND
|
2068 I915_SHRINK_ACTIVE
));
2073 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2078 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2081 enum i915_cache_level level
,
2084 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2085 gen8_pte_t __iomem
*pte
=
2086 (gen8_pte_t __iomem
*)ggtt
->gsm
+ (offset
>> PAGE_SHIFT
);
2088 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
));
2090 ggtt
->invalidate(vm
->i915
);
2093 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2094 struct i915_vma
*vma
,
2095 enum i915_cache_level level
,
2098 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2099 struct sgt_iter sgt_iter
;
2100 gen8_pte_t __iomem
*gtt_entries
;
2101 const gen8_pte_t pte_encode
= gen8_pte_encode(0, level
);
2104 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
;
2105 gtt_entries
+= vma
->node
.start
>> PAGE_SHIFT
;
2106 for_each_sgt_dma(addr
, sgt_iter
, vma
->pages
)
2107 gen8_set_pte(gtt_entries
++, pte_encode
| addr
);
2111 /* This next bit makes the above posting read even more important. We
2112 * want to flush the TLBs only after we're certain all the PTE updates
2115 ggtt
->invalidate(vm
->i915
);
2118 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2121 enum i915_cache_level level
,
2124 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2125 gen6_pte_t __iomem
*pte
=
2126 (gen6_pte_t __iomem
*)ggtt
->gsm
+ (offset
>> PAGE_SHIFT
);
2128 iowrite32(vm
->pte_encode(addr
, level
, flags
), pte
);
2130 ggtt
->invalidate(vm
->i915
);
2134 * Binds an object into the global gtt with the specified cache level. The object
2135 * will be accessible to the GPU via commands whose operands reference offsets
2136 * within the global GTT as well as accessible by the GPU through the GMADR
2137 * mapped BAR (dev_priv->mm.gtt->gtt).
2139 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2140 struct i915_vma
*vma
,
2141 enum i915_cache_level level
,
2144 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2145 gen6_pte_t __iomem
*entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
;
2146 unsigned int i
= vma
->node
.start
>> PAGE_SHIFT
;
2147 struct sgt_iter iter
;
2149 for_each_sgt_dma(addr
, iter
, vma
->pages
)
2150 iowrite32(vm
->pte_encode(addr
, level
, flags
), &entries
[i
++]);
2153 /* This next bit makes the above posting read even more important. We
2154 * want to flush the TLBs only after we're certain all the PTE updates
2157 ggtt
->invalidate(vm
->i915
);
2160 static void nop_clear_range(struct i915_address_space
*vm
,
2161 u64 start
, u64 length
)
2165 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2166 u64 start
, u64 length
)
2168 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2169 unsigned first_entry
= start
>> PAGE_SHIFT
;
2170 unsigned num_entries
= length
>> PAGE_SHIFT
;
2171 const gen8_pte_t scratch_pte
=
2172 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
2173 gen8_pte_t __iomem
*gtt_base
=
2174 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2175 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2178 if (WARN(num_entries
> max_entries
,
2179 "First entry = %d; Num entries = %d (max=%d)\n",
2180 first_entry
, num_entries
, max_entries
))
2181 num_entries
= max_entries
;
2183 for (i
= 0; i
< num_entries
; i
++)
2184 gen8_set_pte(>t_base
[i
], scratch_pte
);
2187 static void bxt_vtd_ggtt_wa(struct i915_address_space
*vm
)
2189 struct drm_i915_private
*dev_priv
= vm
->i915
;
2192 * Make sure the internal GAM fifo has been cleared of all GTT
2193 * writes before exiting stop_machine(). This guarantees that
2194 * any aperture accesses waiting to start in another process
2195 * cannot back up behind the GTT writes causing a hang.
2196 * The register can be any arbitrary GAM register.
2198 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2201 struct insert_page
{
2202 struct i915_address_space
*vm
;
2205 enum i915_cache_level level
;
2208 static int bxt_vtd_ggtt_insert_page__cb(void *_arg
)
2210 struct insert_page
*arg
= _arg
;
2212 gen8_ggtt_insert_page(arg
->vm
, arg
->addr
, arg
->offset
, arg
->level
, 0);
2213 bxt_vtd_ggtt_wa(arg
->vm
);
2218 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space
*vm
,
2221 enum i915_cache_level level
,
2224 struct insert_page arg
= { vm
, addr
, offset
, level
};
2226 stop_machine(bxt_vtd_ggtt_insert_page__cb
, &arg
, NULL
);
2229 struct insert_entries
{
2230 struct i915_address_space
*vm
;
2231 struct i915_vma
*vma
;
2232 enum i915_cache_level level
;
2235 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg
)
2237 struct insert_entries
*arg
= _arg
;
2239 gen8_ggtt_insert_entries(arg
->vm
, arg
->vma
, arg
->level
, 0);
2240 bxt_vtd_ggtt_wa(arg
->vm
);
2245 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2246 struct i915_vma
*vma
,
2247 enum i915_cache_level level
,
2250 struct insert_entries arg
= { vm
, vma
, level
};
2252 stop_machine(bxt_vtd_ggtt_insert_entries__cb
, &arg
, NULL
);
2255 struct clear_range
{
2256 struct i915_address_space
*vm
;
2261 static int bxt_vtd_ggtt_clear_range__cb(void *_arg
)
2263 struct clear_range
*arg
= _arg
;
2265 gen8_ggtt_clear_range(arg
->vm
, arg
->start
, arg
->length
);
2266 bxt_vtd_ggtt_wa(arg
->vm
);
2271 static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space
*vm
,
2275 struct clear_range arg
= { vm
, start
, length
};
2277 stop_machine(bxt_vtd_ggtt_clear_range__cb
, &arg
, NULL
);
2280 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2281 u64 start
, u64 length
)
2283 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2284 unsigned first_entry
= start
>> PAGE_SHIFT
;
2285 unsigned num_entries
= length
>> PAGE_SHIFT
;
2286 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2287 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2288 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2291 if (WARN(num_entries
> max_entries
,
2292 "First entry = %d; Num entries = %d (max=%d)\n",
2293 first_entry
, num_entries
, max_entries
))
2294 num_entries
= max_entries
;
2296 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
2299 for (i
= 0; i
< num_entries
; i
++)
2300 iowrite32(scratch_pte
, >t_base
[i
]);
2303 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2306 enum i915_cache_level cache_level
,
2309 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2310 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2312 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2315 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2316 struct i915_vma
*vma
,
2317 enum i915_cache_level cache_level
,
2320 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2321 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2323 intel_gtt_insert_sg_entries(vma
->pages
, vma
->node
.start
>> PAGE_SHIFT
,
2327 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2328 u64 start
, u64 length
)
2330 intel_gtt_clear_range(start
>> PAGE_SHIFT
, length
>> PAGE_SHIFT
);
2333 static int ggtt_bind_vma(struct i915_vma
*vma
,
2334 enum i915_cache_level cache_level
,
2337 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2338 struct drm_i915_gem_object
*obj
= vma
->obj
;
2341 if (unlikely(!vma
->pages
)) {
2342 int ret
= i915_get_ggtt_vma_pages(vma
);
2347 /* Currently applicable only to VLV */
2350 pte_flags
|= PTE_READ_ONLY
;
2352 intel_runtime_pm_get(i915
);
2353 vma
->vm
->insert_entries(vma
->vm
, vma
, cache_level
, pte_flags
);
2354 intel_runtime_pm_put(i915
);
2357 * Without aliasing PPGTT there's no difference between
2358 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2359 * upgrade to both bound if we bind either to avoid double-binding.
2361 vma
->flags
|= I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
;
2366 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2368 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2370 intel_runtime_pm_get(i915
);
2371 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
2372 intel_runtime_pm_put(i915
);
2375 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2376 enum i915_cache_level cache_level
,
2379 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2383 if (unlikely(!vma
->pages
)) {
2384 ret
= i915_get_ggtt_vma_pages(vma
);
2389 /* Currently applicable only to VLV */
2391 if (vma
->obj
->gt_ro
)
2392 pte_flags
|= PTE_READ_ONLY
;
2394 if (flags
& I915_VMA_LOCAL_BIND
) {
2395 struct i915_hw_ppgtt
*appgtt
= i915
->mm
.aliasing_ppgtt
;
2397 if (!(vma
->flags
& I915_VMA_LOCAL_BIND
) &&
2398 appgtt
->base
.allocate_va_range
) {
2399 ret
= appgtt
->base
.allocate_va_range(&appgtt
->base
,
2406 appgtt
->base
.insert_entries(&appgtt
->base
, vma
, cache_level
,
2410 if (flags
& I915_VMA_GLOBAL_BIND
) {
2411 intel_runtime_pm_get(i915
);
2412 vma
->vm
->insert_entries(vma
->vm
, vma
, cache_level
, pte_flags
);
2413 intel_runtime_pm_put(i915
);
2419 if (!(vma
->flags
& (I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
))) {
2420 if (vma
->pages
!= vma
->obj
->mm
.pages
) {
2421 GEM_BUG_ON(!vma
->pages
);
2422 sg_free_table(vma
->pages
);
2430 static void aliasing_gtt_unbind_vma(struct i915_vma
*vma
)
2432 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2434 if (vma
->flags
& I915_VMA_GLOBAL_BIND
) {
2435 intel_runtime_pm_get(i915
);
2436 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
2437 intel_runtime_pm_put(i915
);
2440 if (vma
->flags
& I915_VMA_LOCAL_BIND
) {
2441 struct i915_address_space
*vm
= &i915
->mm
.aliasing_ppgtt
->base
;
2443 vm
->clear_range(vm
, vma
->node
.start
, vma
->size
);
2447 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object
*obj
,
2448 struct sg_table
*pages
)
2450 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2451 struct device
*kdev
= &dev_priv
->drm
.pdev
->dev
;
2452 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2454 if (unlikely(ggtt
->do_idle_maps
)) {
2455 if (i915_gem_wait_for_idle(dev_priv
, 0)) {
2456 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2457 /* Wait a bit, in hopes it avoids the hang */
2462 dma_unmap_sg(kdev
, pages
->sgl
, pages
->nents
, PCI_DMA_BIDIRECTIONAL
);
2465 static void i915_gtt_color_adjust(const struct drm_mm_node
*node
,
2466 unsigned long color
,
2470 if (node
->allocated
&& node
->color
!= color
)
2471 *start
+= I915_GTT_PAGE_SIZE
;
2473 /* Also leave a space between the unallocated reserved node after the
2474 * GTT and any objects within the GTT, i.e. we use the color adjustment
2475 * to insert a guard page to prevent prefetches crossing over the
2478 node
= list_next_entry(node
, node_list
);
2479 if (node
->color
!= color
)
2480 *end
-= I915_GTT_PAGE_SIZE
;
2483 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private
*i915
)
2485 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
2486 struct i915_hw_ppgtt
*ppgtt
;
2489 ppgtt
= i915_ppgtt_create(i915
, ERR_PTR(-EPERM
), "[alias]");
2491 return PTR_ERR(ppgtt
);
2493 if (WARN_ON(ppgtt
->base
.total
< ggtt
->base
.total
)) {
2498 if (ppgtt
->base
.allocate_va_range
) {
2499 /* Note we only pre-allocate as far as the end of the global
2500 * GTT. On 48b / 4-level page-tables, the difference is very,
2501 * very significant! We have to preallocate as GVT/vgpu does
2502 * not like the page directory disappearing.
2504 err
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
,
2505 0, ggtt
->base
.total
);
2510 i915
->mm
.aliasing_ppgtt
= ppgtt
;
2512 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2513 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2515 WARN_ON(ggtt
->base
.unbind_vma
!= ggtt_unbind_vma
);
2516 ggtt
->base
.unbind_vma
= aliasing_gtt_unbind_vma
;
2521 i915_ppgtt_put(ppgtt
);
2525 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private
*i915
)
2527 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
2528 struct i915_hw_ppgtt
*ppgtt
;
2530 ppgtt
= fetch_and_zero(&i915
->mm
.aliasing_ppgtt
);
2534 i915_ppgtt_put(ppgtt
);
2536 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2537 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2540 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
)
2542 /* Let GEM Manage all of the aperture.
2544 * However, leave one page at the end still bound to the scratch page.
2545 * There are a number of places where the hardware apparently prefetches
2546 * past the end of the object, and we've seen multiple hangs with the
2547 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2548 * aperture. One page should be enough to keep any prefetching inside
2551 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2552 unsigned long hole_start
, hole_end
;
2553 struct drm_mm_node
*entry
;
2556 ret
= intel_vgt_balloon(dev_priv
);
2560 /* Reserve a mappable slot for our lockless error capture */
2561 ret
= drm_mm_insert_node_in_range(&ggtt
->base
.mm
, &ggtt
->error_capture
,
2562 PAGE_SIZE
, 0, I915_COLOR_UNEVICTABLE
,
2563 0, ggtt
->mappable_end
,
2568 /* Clear any non-preallocated blocks */
2569 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2570 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2571 hole_start
, hole_end
);
2572 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2573 hole_end
- hole_start
);
2576 /* And finally clear the reserved guard page */
2577 ggtt
->base
.clear_range(&ggtt
->base
,
2578 ggtt
->base
.total
- PAGE_SIZE
, PAGE_SIZE
);
2580 if (USES_PPGTT(dev_priv
) && !USES_FULL_PPGTT(dev_priv
)) {
2581 ret
= i915_gem_init_aliasing_ppgtt(dev_priv
);
2589 drm_mm_remove_node(&ggtt
->error_capture
);
2594 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2595 * @dev_priv: i915 device
2597 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
)
2599 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2600 struct i915_vma
*vma
, *vn
;
2602 ggtt
->base
.closed
= true;
2604 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2605 WARN_ON(!list_empty(&ggtt
->base
.active_list
));
2606 list_for_each_entry_safe(vma
, vn
, &ggtt
->base
.inactive_list
, vm_link
)
2607 WARN_ON(i915_vma_unbind(vma
));
2608 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2610 i915_gem_cleanup_stolen(&dev_priv
->drm
);
2612 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2613 i915_gem_fini_aliasing_ppgtt(dev_priv
);
2615 if (drm_mm_node_allocated(&ggtt
->error_capture
))
2616 drm_mm_remove_node(&ggtt
->error_capture
);
2618 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2619 intel_vgt_deballoon(dev_priv
);
2620 i915_address_space_fini(&ggtt
->base
);
2623 ggtt
->base
.cleanup(&ggtt
->base
);
2624 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2626 arch_phys_wc_del(ggtt
->mtrr
);
2627 io_mapping_fini(&ggtt
->mappable
);
2630 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2632 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2633 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2634 return snb_gmch_ctl
<< 20;
2637 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2639 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2640 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2642 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2644 #ifdef CONFIG_X86_32
2645 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2646 if (bdw_gmch_ctl
> 4)
2650 return bdw_gmch_ctl
<< 20;
2653 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2655 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2656 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2659 return 1 << (20 + gmch_ctrl
);
2664 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2666 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2667 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2668 return (size_t)snb_gmch_ctl
<< 25; /* 32 MB units */
2671 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2673 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2674 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2675 return (size_t)bdw_gmch_ctl
<< 25; /* 32 MB units */
2678 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2680 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2681 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2684 * 0x0 to 0x10: 32MB increments starting at 0MB
2685 * 0x11 to 0x16: 4MB increments starting at 8MB
2686 * 0x17 to 0x1d: 4MB increments start at 36MB
2688 if (gmch_ctrl
< 0x11)
2689 return (size_t)gmch_ctrl
<< 25;
2690 else if (gmch_ctrl
< 0x17)
2691 return (size_t)(gmch_ctrl
- 0x11 + 2) << 22;
2693 return (size_t)(gmch_ctrl
- 0x17 + 9) << 22;
2696 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2698 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2699 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2701 if (gen9_gmch_ctl
< 0xf0)
2702 return (size_t)gen9_gmch_ctl
<< 25; /* 32 MB units */
2704 /* 4MB increments starting at 0xf0 for 4MB */
2705 return (size_t)(gen9_gmch_ctl
- 0xf0 + 1) << 22;
2708 static int ggtt_probe_common(struct i915_ggtt
*ggtt
, u64 size
)
2710 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2711 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2712 phys_addr_t phys_addr
;
2715 /* For Modern GENs the PTEs and register space are split in the BAR */
2716 phys_addr
= pci_resource_start(pdev
, 0) + pci_resource_len(pdev
, 0) / 2;
2719 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2720 * dropped. For WC mappings in general we have 64 byte burst writes
2721 * when the WC buffer is flushed, so we can't use it, but have to
2722 * resort to an uncached mapping. The WC issue is easily caught by the
2723 * readback check when writing GTT PTE entries.
2725 if (IS_GEN9_LP(dev_priv
))
2726 ggtt
->gsm
= ioremap_nocache(phys_addr
, size
);
2728 ggtt
->gsm
= ioremap_wc(phys_addr
, size
);
2730 DRM_ERROR("Failed to map the ggtt page table\n");
2734 ret
= setup_scratch_page(&ggtt
->base
, GFP_DMA32
);
2736 DRM_ERROR("Scratch setup failed\n");
2737 /* iounmap will also get called at remove, but meh */
2745 static void cnl_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2747 /* XXX: spec is unclear if this is still needed for CNL+ */
2748 if (!USES_PPGTT(dev_priv
)) {
2749 I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC
);
2753 I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB
| GEN8_PPAT_LLC
);
2754 I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
);
2755 I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
);
2756 I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC
);
2757 I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0));
2758 I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1));
2759 I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2));
2760 I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2763 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2764 * bits. When using advanced contexts each context stores its own PAT, but
2765 * writing this data shouldn't be harmful even in those cases. */
2766 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2770 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2771 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2772 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2773 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2774 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2775 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2776 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2777 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2779 if (!USES_PPGTT(dev_priv
))
2780 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2781 * so RTL will always use the value corresponding to
2783 * So let's disable cache for GGTT to avoid screen corruptions.
2784 * MOCS still can be used though.
2785 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2786 * before this patch, i.e. the same uncached + snooping access
2787 * like on gen6/7 seems to be in effect.
2788 * - So this just fixes blitter/render access. Again it looks
2789 * like it's not just uncached access, but uncached + snooping.
2790 * So we can still hold onto all our assumptions wrt cpu
2791 * clflushing on LLC machines.
2793 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2795 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2796 * write would work. */
2797 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2798 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2801 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2806 * Map WB on BDW to snooped on CHV.
2808 * Only the snoop bit has meaning for CHV, the rest is
2811 * The hardware will never snoop for certain types of accesses:
2812 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2813 * - PPGTT page tables
2814 * - some other special cycles
2816 * As with BDW, we also need to consider the following for GT accesses:
2817 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2818 * so RTL will always use the value corresponding to
2820 * Which means we must set the snoop bit in PAT entry 0
2821 * in order to keep the global status page working.
2823 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2827 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2828 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2829 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2830 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2832 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2833 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2836 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2838 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2841 cleanup_scratch_page(vm
);
2844 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
2846 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2847 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2852 /* TODO: We're not aware of mappable constraints on gen8 yet */
2853 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
2854 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
2856 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(39));
2858 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(39));
2860 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err
);
2862 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2864 if (INTEL_GEN(dev_priv
) >= 9) {
2865 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
2866 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2867 } else if (IS_CHERRYVIEW(dev_priv
)) {
2868 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
2869 size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2871 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
2872 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2875 ggtt
->base
.total
= (size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2877 if (INTEL_GEN(dev_priv
) >= 10)
2878 cnl_setup_private_ppat(dev_priv
);
2879 else if (IS_CHERRYVIEW(dev_priv
) || IS_GEN9_LP(dev_priv
))
2880 chv_setup_private_ppat(dev_priv
);
2882 bdw_setup_private_ppat(dev_priv
);
2884 ggtt
->base
.cleanup
= gen6_gmch_remove
;
2885 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2886 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2887 ggtt
->base
.insert_page
= gen8_ggtt_insert_page
;
2888 ggtt
->base
.clear_range
= nop_clear_range
;
2889 if (!USES_FULL_PPGTT(dev_priv
) || intel_scanout_needs_vtd_wa(dev_priv
))
2890 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
2892 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
2894 /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
2895 if (intel_ggtt_update_needs_vtd_wa(dev_priv
)) {
2896 ggtt
->base
.insert_entries
= bxt_vtd_ggtt_insert_entries__BKL
;
2897 ggtt
->base
.insert_page
= bxt_vtd_ggtt_insert_page__BKL
;
2898 if (ggtt
->base
.clear_range
!= nop_clear_range
)
2899 ggtt
->base
.clear_range
= bxt_vtd_ggtt_clear_range__BKL
;
2902 ggtt
->invalidate
= gen6_ggtt_invalidate
;
2904 return ggtt_probe_common(ggtt
, size
);
2907 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
2909 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2910 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2915 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
2916 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
2918 /* 64/512MB is the current min/max we actually know of, but this is just
2919 * a coarse sanity check.
2921 if (ggtt
->mappable_end
< (64<<20) || ggtt
->mappable_end
> (512<<20)) {
2922 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
2926 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(40));
2928 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40));
2930 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err
);
2931 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2933 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
2935 size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2936 ggtt
->base
.total
= (size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2938 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
2939 ggtt
->base
.insert_page
= gen6_ggtt_insert_page
;
2940 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
2941 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2942 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2943 ggtt
->base
.cleanup
= gen6_gmch_remove
;
2945 ggtt
->invalidate
= gen6_ggtt_invalidate
;
2947 if (HAS_EDRAM(dev_priv
))
2948 ggtt
->base
.pte_encode
= iris_pte_encode
;
2949 else if (IS_HASWELL(dev_priv
))
2950 ggtt
->base
.pte_encode
= hsw_pte_encode
;
2951 else if (IS_VALLEYVIEW(dev_priv
))
2952 ggtt
->base
.pte_encode
= byt_pte_encode
;
2953 else if (INTEL_GEN(dev_priv
) >= 7)
2954 ggtt
->base
.pte_encode
= ivb_pte_encode
;
2956 ggtt
->base
.pte_encode
= snb_pte_encode
;
2958 return ggtt_probe_common(ggtt
, size
);
2961 static void i915_gmch_remove(struct i915_address_space
*vm
)
2963 intel_gmch_remove();
2966 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
2968 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2971 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
2973 DRM_ERROR("failed to set up gmch\n");
2977 intel_gtt_get(&ggtt
->base
.total
,
2979 &ggtt
->mappable_base
,
2980 &ggtt
->mappable_end
);
2982 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
);
2983 ggtt
->base
.insert_page
= i915_ggtt_insert_page
;
2984 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
2985 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
2986 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2987 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2988 ggtt
->base
.cleanup
= i915_gmch_remove
;
2990 ggtt
->invalidate
= gmch_ggtt_invalidate
;
2992 if (unlikely(ggtt
->do_idle_maps
))
2993 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2999 * i915_ggtt_probe_hw - Probe GGTT hardware location
3000 * @dev_priv: i915 device
3002 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
)
3004 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3007 ggtt
->base
.i915
= dev_priv
;
3008 ggtt
->base
.dma
= &dev_priv
->drm
.pdev
->dev
;
3010 if (INTEL_GEN(dev_priv
) <= 5)
3011 ret
= i915_gmch_probe(ggtt
);
3012 else if (INTEL_GEN(dev_priv
) < 8)
3013 ret
= gen6_gmch_probe(ggtt
);
3015 ret
= gen8_gmch_probe(ggtt
);
3019 /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
3020 * This is easier than doing range restriction on the fly, as we
3021 * currently don't have any bits spare to pass in this upper
3024 if (HAS_GUC(dev_priv
) && i915
.enable_guc_loading
) {
3025 ggtt
->base
.total
= min_t(u64
, ggtt
->base
.total
, GUC_GGTT_TOP
);
3026 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3029 if ((ggtt
->base
.total
- 1) >> 32) {
3030 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3031 " of address space! Found %lldM!\n",
3032 ggtt
->base
.total
>> 20);
3033 ggtt
->base
.total
= 1ULL << 32;
3034 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3037 if (ggtt
->mappable_end
> ggtt
->base
.total
) {
3038 DRM_ERROR("mappable aperture extends past end of GGTT,"
3039 " aperture=%llx, total=%llx\n",
3040 ggtt
->mappable_end
, ggtt
->base
.total
);
3041 ggtt
->mappable_end
= ggtt
->base
.total
;
3044 /* GMADR is the PCI mmio aperture into the global GTT. */
3045 DRM_INFO("Memory usable by graphics device = %lluM\n",
3046 ggtt
->base
.total
>> 20);
3047 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
3048 DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt
->stolen_size
>> 20);
3049 if (intel_vtd_active())
3050 DRM_INFO("VT-d active for gfx access\n");
3056 * i915_ggtt_init_hw - Initialize GGTT hardware
3057 * @dev_priv: i915 device
3059 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
)
3061 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3064 INIT_LIST_HEAD(&dev_priv
->vm_list
);
3066 /* Note that we use page colouring to enforce a guard page at the
3067 * end of the address space. This is required as the CS may prefetch
3068 * beyond the end of the batch buffer, across the page boundary,
3069 * and beyond the end of the GTT if we do not provide a guard.
3071 mutex_lock(&dev_priv
->drm
.struct_mutex
);
3072 i915_address_space_init(&ggtt
->base
, dev_priv
, "[global]");
3073 if (!HAS_LLC(dev_priv
) && !USES_PPGTT(dev_priv
))
3074 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
3075 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
3077 if (!io_mapping_init_wc(&dev_priv
->ggtt
.mappable
,
3078 dev_priv
->ggtt
.mappable_base
,
3079 dev_priv
->ggtt
.mappable_end
)) {
3081 goto out_gtt_cleanup
;
3084 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->mappable_base
, ggtt
->mappable_end
);
3087 * Initialise stolen early so that we may reserve preallocated
3088 * objects for the BIOS to KMS transition.
3090 ret
= i915_gem_init_stolen(dev_priv
);
3092 goto out_gtt_cleanup
;
3097 ggtt
->base
.cleanup(&ggtt
->base
);
3101 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
)
3103 if (INTEL_GEN(dev_priv
) < 6 && !intel_enable_gtt())
3109 void i915_ggtt_enable_guc(struct drm_i915_private
*i915
)
3111 GEM_BUG_ON(i915
->ggtt
.invalidate
!= gen6_ggtt_invalidate
);
3113 i915
->ggtt
.invalidate
= guc_ggtt_invalidate
;
3116 void i915_ggtt_disable_guc(struct drm_i915_private
*i915
)
3118 /* We should only be called after i915_ggtt_enable_guc() */
3119 GEM_BUG_ON(i915
->ggtt
.invalidate
!= guc_ggtt_invalidate
);
3121 i915
->ggtt
.invalidate
= gen6_ggtt_invalidate
;
3124 void i915_gem_restore_gtt_mappings(struct drm_i915_private
*dev_priv
)
3126 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3127 struct drm_i915_gem_object
*obj
, *on
;
3129 i915_check_and_clear_faults(dev_priv
);
3131 /* First fill our portion of the GTT with scratch pages */
3132 ggtt
->base
.clear_range(&ggtt
->base
, 0, ggtt
->base
.total
);
3134 ggtt
->base
.closed
= true; /* skip rewriting PTE on VMA unbind */
3136 /* clflush objects bound into the GGTT and rebind them. */
3137 list_for_each_entry_safe(obj
, on
,
3138 &dev_priv
->mm
.bound_list
, global_link
) {
3139 bool ggtt_bound
= false;
3140 struct i915_vma
*vma
;
3142 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3143 if (vma
->vm
!= &ggtt
->base
)
3146 if (!i915_vma_unbind(vma
))
3149 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3155 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3158 ggtt
->base
.closed
= false;
3160 if (INTEL_GEN(dev_priv
) >= 8) {
3161 if (INTEL_GEN(dev_priv
) >= 10)
3162 cnl_setup_private_ppat(dev_priv
);
3163 else if (IS_CHERRYVIEW(dev_priv
) || IS_GEN9_LP(dev_priv
))
3164 chv_setup_private_ppat(dev_priv
);
3166 bdw_setup_private_ppat(dev_priv
);
3171 if (USES_PPGTT(dev_priv
)) {
3172 struct i915_address_space
*vm
;
3174 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3175 struct i915_hw_ppgtt
*ppgtt
;
3177 if (i915_is_ggtt(vm
))
3178 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3180 ppgtt
= i915_vm_to_ppgtt(vm
);
3182 gen6_write_page_range(ppgtt
, 0, ppgtt
->base
.total
);
3186 i915_ggtt_invalidate(dev_priv
);
3189 static struct scatterlist
*
3190 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3191 unsigned int width
, unsigned int height
,
3192 unsigned int stride
,
3193 struct sg_table
*st
, struct scatterlist
*sg
)
3195 unsigned int column
, row
;
3196 unsigned int src_idx
;
3198 for (column
= 0; column
< width
; column
++) {
3199 src_idx
= stride
* (height
- 1) + column
;
3200 for (row
= 0; row
< height
; row
++) {
3202 /* We don't need the pages, but need to initialize
3203 * the entries so the sg list can be happily traversed.
3204 * The only thing we need are DMA addresses.
3206 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3207 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3208 sg_dma_len(sg
) = PAGE_SIZE
;
3217 static noinline
struct sg_table
*
3218 intel_rotate_pages(struct intel_rotation_info
*rot_info
,
3219 struct drm_i915_gem_object
*obj
)
3221 const unsigned long n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3222 unsigned int size
= intel_rotation_info_size(rot_info
);
3223 struct sgt_iter sgt_iter
;
3224 dma_addr_t dma_addr
;
3226 dma_addr_t
*page_addr_list
;
3227 struct sg_table
*st
;
3228 struct scatterlist
*sg
;
3231 /* Allocate a temporary list of source pages for random access. */
3232 page_addr_list
= kvmalloc_array(n_pages
,
3235 if (!page_addr_list
)
3236 return ERR_PTR(ret
);
3238 /* Allocate target SG list. */
3239 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3243 ret
= sg_alloc_table(st
, size
, GFP_KERNEL
);
3247 /* Populate source page list from the object. */
3249 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->mm
.pages
)
3250 page_addr_list
[i
++] = dma_addr
;
3252 GEM_BUG_ON(i
!= n_pages
);
3256 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++) {
3257 sg
= rotate_pages(page_addr_list
, rot_info
->plane
[i
].offset
,
3258 rot_info
->plane
[i
].width
, rot_info
->plane
[i
].height
,
3259 rot_info
->plane
[i
].stride
, st
, sg
);
3262 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3263 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3265 kvfree(page_addr_list
);
3272 kvfree(page_addr_list
);
3274 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3275 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3277 return ERR_PTR(ret
);
3280 static noinline
struct sg_table
*
3281 intel_partial_pages(const struct i915_ggtt_view
*view
,
3282 struct drm_i915_gem_object
*obj
)
3284 struct sg_table
*st
;
3285 struct scatterlist
*sg
, *iter
;
3286 unsigned int count
= view
->partial
.size
;
3287 unsigned int offset
;
3290 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3294 ret
= sg_alloc_table(st
, count
, GFP_KERNEL
);
3298 iter
= i915_gem_object_get_sg(obj
, view
->partial
.offset
, &offset
);
3306 len
= min(iter
->length
- (offset
<< PAGE_SHIFT
),
3307 count
<< PAGE_SHIFT
);
3308 sg_set_page(sg
, NULL
, len
, 0);
3309 sg_dma_address(sg
) =
3310 sg_dma_address(iter
) + (offset
<< PAGE_SHIFT
);
3311 sg_dma_len(sg
) = len
;
3314 count
-= len
>> PAGE_SHIFT
;
3321 iter
= __sg_next(iter
);
3328 return ERR_PTR(ret
);
3332 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3336 /* The vma->pages are only valid within the lifespan of the borrowed
3337 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
3338 * must be the vma->pages. A simple rule is that vma->pages must only
3339 * be accessed when the obj->mm.pages are pinned.
3341 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma
->obj
));
3343 switch (vma
->ggtt_view
.type
) {
3344 case I915_GGTT_VIEW_NORMAL
:
3345 vma
->pages
= vma
->obj
->mm
.pages
;
3348 case I915_GGTT_VIEW_ROTATED
:
3350 intel_rotate_pages(&vma
->ggtt_view
.rotated
, vma
->obj
);
3353 case I915_GGTT_VIEW_PARTIAL
:
3354 vma
->pages
= intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3358 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3359 vma
->ggtt_view
.type
);
3364 if (unlikely(IS_ERR(vma
->pages
))) {
3365 ret
= PTR_ERR(vma
->pages
);
3367 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3368 vma
->ggtt_view
.type
, ret
);
3374 * i915_gem_gtt_reserve - reserve a node in an address_space (GTT)
3375 * @vm: the &struct i915_address_space
3376 * @node: the &struct drm_mm_node (typically i915_vma.mode)
3377 * @size: how much space to allocate inside the GTT,
3378 * must be #I915_GTT_PAGE_SIZE aligned
3379 * @offset: where to insert inside the GTT,
3380 * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node
3381 * (@offset + @size) must fit within the address space
3382 * @color: color to apply to node, if this node is not from a VMA,
3383 * color must be #I915_COLOR_UNEVICTABLE
3384 * @flags: control search and eviction behaviour
3386 * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside
3387 * the address space (using @size and @color). If the @node does not fit, it
3388 * tries to evict any overlapping nodes from the GTT, including any
3389 * neighbouring nodes if the colors do not match (to ensure guard pages between
3390 * differing domains). See i915_gem_evict_for_node() for the gory details
3391 * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on
3392 * evicting active overlapping objects, and any overlapping node that is pinned
3393 * or marked as unevictable will also result in failure.
3395 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3396 * asked to wait for eviction and interrupted.
3398 int i915_gem_gtt_reserve(struct i915_address_space
*vm
,
3399 struct drm_mm_node
*node
,
3400 u64 size
, u64 offset
, unsigned long color
,
3406 GEM_BUG_ON(!IS_ALIGNED(size
, I915_GTT_PAGE_SIZE
));
3407 GEM_BUG_ON(!IS_ALIGNED(offset
, I915_GTT_MIN_ALIGNMENT
));
3408 GEM_BUG_ON(range_overflows(offset
, size
, vm
->total
));
3409 GEM_BUG_ON(vm
== &vm
->i915
->mm
.aliasing_ppgtt
->base
);
3410 GEM_BUG_ON(drm_mm_node_allocated(node
));
3413 node
->start
= offset
;
3414 node
->color
= color
;
3416 err
= drm_mm_reserve_node(&vm
->mm
, node
);
3420 if (flags
& PIN_NOEVICT
)
3423 err
= i915_gem_evict_for_node(vm
, node
, flags
);
3425 err
= drm_mm_reserve_node(&vm
->mm
, node
);
3430 static u64
random_offset(u64 start
, u64 end
, u64 len
, u64 align
)
3434 GEM_BUG_ON(range_overflows(start
, len
, end
));
3435 GEM_BUG_ON(round_up(start
, align
) > round_down(end
- len
, align
));
3437 range
= round_down(end
- len
, align
) - round_up(start
, align
);
3439 if (sizeof(unsigned long) == sizeof(u64
)) {
3440 addr
= get_random_long();
3442 addr
= get_random_int();
3443 if (range
> U32_MAX
) {
3445 addr
|= get_random_int();
3448 div64_u64_rem(addr
, range
, &addr
);
3452 return round_up(start
, align
);
3456 * i915_gem_gtt_insert - insert a node into an address_space (GTT)
3457 * @vm: the &struct i915_address_space
3458 * @node: the &struct drm_mm_node (typically i915_vma.node)
3459 * @size: how much space to allocate inside the GTT,
3460 * must be #I915_GTT_PAGE_SIZE aligned
3461 * @alignment: required alignment of starting offset, may be 0 but
3462 * if specified, this must be a power-of-two and at least
3463 * #I915_GTT_MIN_ALIGNMENT
3464 * @color: color to apply to node
3465 * @start: start of any range restriction inside GTT (0 for all),
3466 * must be #I915_GTT_PAGE_SIZE aligned
3467 * @end: end of any range restriction inside GTT (U64_MAX for all),
3468 * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX
3469 * @flags: control search and eviction behaviour
3471 * i915_gem_gtt_insert() first searches for an available hole into which
3472 * is can insert the node. The hole address is aligned to @alignment and
3473 * its @size must then fit entirely within the [@start, @end] bounds. The
3474 * nodes on either side of the hole must match @color, or else a guard page
3475 * will be inserted between the two nodes (or the node evicted). If no
3476 * suitable hole is found, first a victim is randomly selected and tested
3477 * for eviction, otherwise then the LRU list of objects within the GTT
3478 * is scanned to find the first set of replacement nodes to create the hole.
3479 * Those old overlapping nodes are evicted from the GTT (and so must be
3480 * rebound before any future use). Any node that is currently pinned cannot
3481 * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently
3482 * active and #PIN_NONBLOCK is specified, that node is also skipped when
3483 * searching for an eviction candidate. See i915_gem_evict_something() for
3484 * the gory details on the eviction algorithm.
3486 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3487 * asked to wait for eviction and interrupted.
3489 int i915_gem_gtt_insert(struct i915_address_space
*vm
,
3490 struct drm_mm_node
*node
,
3491 u64 size
, u64 alignment
, unsigned long color
,
3492 u64 start
, u64 end
, unsigned int flags
)
3494 enum drm_mm_insert_mode mode
;
3498 lockdep_assert_held(&vm
->i915
->drm
.struct_mutex
);
3500 GEM_BUG_ON(!IS_ALIGNED(size
, I915_GTT_PAGE_SIZE
));
3501 GEM_BUG_ON(alignment
&& !is_power_of_2(alignment
));
3502 GEM_BUG_ON(alignment
&& !IS_ALIGNED(alignment
, I915_GTT_MIN_ALIGNMENT
));
3503 GEM_BUG_ON(start
>= end
);
3504 GEM_BUG_ON(start
> 0 && !IS_ALIGNED(start
, I915_GTT_PAGE_SIZE
));
3505 GEM_BUG_ON(end
< U64_MAX
&& !IS_ALIGNED(end
, I915_GTT_PAGE_SIZE
));
3506 GEM_BUG_ON(vm
== &vm
->i915
->mm
.aliasing_ppgtt
->base
);
3507 GEM_BUG_ON(drm_mm_node_allocated(node
));
3509 if (unlikely(range_overflows(start
, size
, end
)))
3512 if (unlikely(round_up(start
, alignment
) > round_down(end
- size
, alignment
)))
3515 mode
= DRM_MM_INSERT_BEST
;
3516 if (flags
& PIN_HIGH
)
3517 mode
= DRM_MM_INSERT_HIGH
;
3518 if (flags
& PIN_MAPPABLE
)
3519 mode
= DRM_MM_INSERT_LOW
;
3521 /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3522 * so we know that we always have a minimum alignment of 4096.
3523 * The drm_mm range manager is optimised to return results
3524 * with zero alignment, so where possible use the optimal
3527 BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT
> I915_GTT_PAGE_SIZE
);
3528 if (alignment
<= I915_GTT_MIN_ALIGNMENT
)
3531 err
= drm_mm_insert_node_in_range(&vm
->mm
, node
,
3532 size
, alignment
, color
,
3537 if (flags
& PIN_NOEVICT
)
3540 /* No free space, pick a slot at random.
3542 * There is a pathological case here using a GTT shared between
3543 * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt):
3545 * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->|
3546 * (64k objects) (448k objects)
3548 * Now imagine that the eviction LRU is ordered top-down (just because
3549 * pathology meets real life), and that we need to evict an object to
3550 * make room inside the aperture. The eviction scan then has to walk
3551 * the 448k list before it finds one within range. And now imagine that
3552 * it has to search for a new hole between every byte inside the memcpy,
3553 * for several simultaneous clients.
3555 * On a full-ppgtt system, if we have run out of available space, there
3556 * will be lots and lots of objects in the eviction list! Again,
3557 * searching that LRU list may be slow if we are also applying any
3558 * range restrictions (e.g. restriction to low 4GiB) and so, for
3559 * simplicity and similarilty between different GTT, try the single
3560 * random replacement first.
3562 offset
= random_offset(start
, end
,
3563 size
, alignment
?: I915_GTT_MIN_ALIGNMENT
);
3564 err
= i915_gem_gtt_reserve(vm
, node
, size
, offset
, color
, flags
);
3568 /* Randomly selected placement is pinned, do a search */
3569 err
= i915_gem_evict_something(vm
, size
, alignment
, color
,
3574 return drm_mm_insert_node_in_range(&vm
->mm
, node
,
3575 size
, alignment
, color
,
3576 start
, end
, DRM_MM_INSERT_EVICT
);
3579 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3580 #include "selftests/mock_gtt.c"
3581 #include "selftests/i915_gem_gtt.c"