drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Jie Qiu <jie.qiu@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include "mtk_hdmi_phy.h"
  16
  17 #define HDMI_CON0               0x00
  18 #define RG_HDMITX_PLL_EN                BIT(31)
  19 #define RG_HDMITX_PLL_FBKDIV            (0x7f << 24)
  20 #define PLL_FBKDIV_SHIFT                24
  21 #define RG_HDMITX_PLL_FBKSEL            (0x3 << 22)
  22 #define PLL_FBKSEL_SHIFT                22
  23 #define RG_HDMITX_PLL_PREDIV            (0x3 << 20)
  24 #define PREDIV_SHIFT                    20
  25 #define RG_HDMITX_PLL_POSDIV            (0x3 << 18)
  26 #define POSDIV_SHIFT                    18
  27 #define RG_HDMITX_PLL_RST_DLY           (0x3 << 16)
  28 #define RG_HDMITX_PLL_IR                (0xf << 12)
  29 #define PLL_IR_SHIFT                    12
  30 #define RG_HDMITX_PLL_IC                (0xf << 8)
  31 #define PLL_IC_SHIFT                    8
  32 #define RG_HDMITX_PLL_BP                (0xf << 4)
  33 #define PLL_BP_SHIFT                    4
  34 #define RG_HDMITX_PLL_BR                (0x3 << 2)
  35 #define PLL_BR_SHIFT                    2
  36 #define RG_HDMITX_PLL_BC                (0x3 << 0)
  37 #define PLL_BC_SHIFT                    0
  38 #define HDMI_CON1               0x04
  39 #define RG_HDMITX_PLL_DIVEN             (0x7 << 29)
  40 #define PLL_DIVEN_SHIFT                 29
  41 #define RG_HDMITX_PLL_AUTOK_EN          BIT(28)
  42 #define RG_HDMITX_PLL_AUTOK_KF          (0x3 << 26)
  43 #define RG_HDMITX_PLL_AUTOK_KS          (0x3 << 24)
  44 #define RG_HDMITX_PLL_AUTOK_LOAD        BIT(23)
  45 #define RG_HDMITX_PLL_BAND              (0x3f << 16)
  46 #define RG_HDMITX_PLL_REF_SEL           BIT(15)
  47 #define RG_HDMITX_PLL_BIAS_EN           BIT(14)
  48 #define RG_HDMITX_PLL_BIAS_LPF_EN       BIT(13)
  49 #define RG_HDMITX_PLL_TXDIV_EN          BIT(12)
  50 #define RG_HDMITX_PLL_TXDIV             (0x3 << 10)
  51 #define PLL_TXDIV_SHIFT                 10
  52 #define RG_HDMITX_PLL_LVROD_EN          BIT(9)
  53 #define RG_HDMITX_PLL_MONVC_EN          BIT(8)
  54 #define RG_HDMITX_PLL_MONCK_EN          BIT(7)
  55 #define RG_HDMITX_PLL_MONREF_EN         BIT(6)
  56 #define RG_HDMITX_PLL_TST_EN            BIT(5)
  57 #define RG_HDMITX_PLL_TST_CK_EN         BIT(4)
  58 #define RG_HDMITX_PLL_TST_SEL           (0xf << 0)
  59 #define HDMI_CON2               0x08
  60 #define RGS_HDMITX_PLL_AUTOK_BAND       (0x7f << 8)
  61 #define RGS_HDMITX_PLL_AUTOK_FAIL       BIT(1)
  62 #define RG_HDMITX_EN_TX_CKLDO           BIT(0)
  63 #define HDMI_CON3               0x0c
  64 #define RG_HDMITX_SER_EN                (0xf << 28)
  65 #define RG_HDMITX_PRD_EN                (0xf << 24)
  66 #define RG_HDMITX_PRD_IMP_EN            (0xf << 20)
  67 #define RG_HDMITX_DRV_EN                (0xf << 16)
  68 #define RG_HDMITX_DRV_IMP_EN            (0xf << 12)
  69 #define DRV_IMP_EN_SHIFT                12
  70 #define RG_HDMITX_MHLCK_FORCE           BIT(10)
  71 #define RG_HDMITX_MHLCK_PPIX_EN         BIT(9)
  72 #define RG_HDMITX_MHLCK_EN              BIT(8)
  73 #define RG_HDMITX_SER_DIN_SEL           (0xf << 4)
  74 #define RG_HDMITX_SER_5T1_BIST_EN       BIT(3)
  75 #define RG_HDMITX_SER_BIST_TOG          BIT(2)
  76 #define RG_HDMITX_SER_DIN_TOG           BIT(1)
  77 #define RG_HDMITX_SER_CLKDIG_INV        BIT(0)
  78 #define HDMI_CON4               0x10
  79 #define RG_HDMITX_PRD_IBIAS_CLK         (0xf << 24)
  80 #define RG_HDMITX_PRD_IBIAS_D2          (0xf << 16)
  81 #define RG_HDMITX_PRD_IBIAS_D1          (0xf << 8)
  82 #define RG_HDMITX_PRD_IBIAS_D0          (0xf << 0)
  83 #define PRD_IBIAS_CLK_SHIFT             24
  84 #define PRD_IBIAS_D2_SHIFT              16
  85 #define PRD_IBIAS_D1_SHIFT              8
  86 #define PRD_IBIAS_D0_SHIFT              0
  87 #define HDMI_CON5               0x14
  88 #define RG_HDMITX_DRV_IBIAS_CLK         (0x3f << 24)
  89 #define RG_HDMITX_DRV_IBIAS_D2          (0x3f << 16)
  90 #define RG_HDMITX_DRV_IBIAS_D1          (0x3f << 8)
  91 #define RG_HDMITX_DRV_IBIAS_D0          (0x3f << 0)
  92 #define DRV_IBIAS_CLK_SHIFT             24
  93 #define DRV_IBIAS_D2_SHIFT              16
  94 #define DRV_IBIAS_D1_SHIFT              8
  95 #define DRV_IBIAS_D0_SHIFT              0
  96 #define HDMI_CON6               0x18
  97 #define RG_HDMITX_DRV_IMP_CLK           (0x3f << 24)
  98 #define RG_HDMITX_DRV_IMP_D2            (0x3f << 16)
  99 #define RG_HDMITX_DRV_IMP_D1            (0x3f << 8)
 100 #define RG_HDMITX_DRV_IMP_D0            (0x3f << 0)
 101 #define DRV_IMP_CLK_SHIFT               24
 102 #define DRV_IMP_D2_SHIFT                16
 103 #define DRV_IMP_D1_SHIFT                8
 104 #define DRV_IMP_D0_SHIFT                0
 105 #define HDMI_CON7               0x1c
 106 #define RG_HDMITX_MHLCK_DRV_IBIAS       (0x1f << 27)
 107 #define RG_HDMITX_SER_DIN               (0x3ff << 16)
 108 #define RG_HDMITX_CHLDC_TST             (0xf << 12)
 109 #define RG_HDMITX_CHLCK_TST             (0xf << 8)
 110 #define RG_HDMITX_RESERVE               (0xff << 0)
 111 #define HDMI_CON8               0x20
 112 #define RGS_HDMITX_2T1_LEV              (0xf << 16)
 113 #define RGS_HDMITX_2T1_EDG              (0xf << 12)
 114 #define RGS_HDMITX_5T1_LEV              (0xf << 8)
 115 #define RGS_HDMITX_5T1_EDG              (0xf << 4)
 116 #define RGS_HDMITX_PLUG_TST             BIT(0)
 117
 118 static const u8 PREDIV[3][4] = {
 119         {0x0, 0x0, 0x0, 0x0},   /* 27Mhz */
 120         {0x1, 0x1, 0x1, 0x1},   /* 74Mhz */
 121         {0x1, 0x1, 0x1, 0x1}    /* 148Mhz */
 122 };
 123
 124 static const u8 TXDIV[3][4] = {
 125         {0x3, 0x3, 0x3, 0x2},   /* 27Mhz */
 126         {0x2, 0x1, 0x1, 0x1},   /* 74Mhz */
 127         {0x1, 0x0, 0x0, 0x0}    /* 148Mhz */
 128 };
 129
 130 static const u8 FBKSEL[3][4] = {
 131         {0x1, 0x1, 0x1, 0x1},   /* 27Mhz */
 132         {0x1, 0x0, 0x1, 0x1},   /* 74Mhz */
 133         {0x1, 0x0, 0x1, 0x1}    /* 148Mhz */
 134 };
 135
 136 static const u8 FBKDIV[3][4] = {
 137         {19, 24, 29, 19},       /* 27Mhz */
 138         {19, 24, 14, 19},       /* 74Mhz */
 139         {19, 24, 14, 19}        /* 148Mhz */
 140 };
 141
 142 static const u8 DIVEN[3][4] = {
 143         {0x2, 0x1, 0x1, 0x2},   /* 27Mhz */
 144         {0x2, 0x2, 0x2, 0x2},   /* 74Mhz */
 145         {0x2, 0x2, 0x2, 0x2}    /* 148Mhz */
 146 };
 147
 148 static const u8 HTPLLBP[3][4] = {
 149         {0xc, 0xc, 0x8, 0xc},   /* 27Mhz */
 150         {0xc, 0xf, 0xf, 0xc},   /* 74Mhz */
 151         {0xc, 0xf, 0xf, 0xc}    /* 148Mhz */
 152 };
 153
 154 static const u8 HTPLLBC[3][4] = {
 155         {0x2, 0x3, 0x3, 0x2},   /* 27Mhz */
 156         {0x2, 0x3, 0x3, 0x2},   /* 74Mhz */
 157         {0x2, 0x3, 0x3, 0x2}    /* 148Mhz */
 158 };
 159
 160 static const u8 HTPLLBR[3][4] = {
 161         {0x1, 0x1, 0x0, 0x1},   /* 27Mhz */
 162         {0x1, 0x2, 0x2, 0x1},   /* 74Mhz */
 163         {0x1, 0x2, 0x2, 0x1}    /* 148Mhz */
 164 };
 165
 166 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
 167 {
 168         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 169
 170         dev_dbg(hdmi_phy->dev, "%s\n", __func__);
 171
 172         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
 173         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
 174         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
 175         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
 176         usleep_range(100, 150);
 177         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
 178         usleep_range(100, 150);
 179         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
 180         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
 181
 182         return 0;
 183 }
 184
 185 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
 186 {
 187         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 188
 189         dev_dbg(hdmi_phy->dev, "%s\n", __func__);
 190
 191         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
 192         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
 193         usleep_range(100, 150);
 194         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
 195         usleep_range(100, 150);
 196         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
 197         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
 198         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
 199         usleep_range(100, 150);
 200 }
 201
 202 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 203                                  unsigned long parent_rate)
 204 {
 205         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 206         unsigned int pre_div;
 207         unsigned int div;
 208         unsigned int pre_ibias;
 209         unsigned int hdmi_ibias;
 210         unsigned int imp_en;
 211
 212         dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
 213                 rate, parent_rate);
 214
 215         if (rate <= 27000000) {
 216                 pre_div = 0;
 217                 div = 3;
 218         } else if (rate <= 74250000) {
 219                 pre_div = 1;
 220                 div = 2;
 221         } else {
 222                 pre_div = 1;
 223                 div = 1;
 224         }
 225
 226         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
 227                           (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
 228         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
 229         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
 230                           (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
 231                           RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
 232         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
 233                           (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
 234         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
 235                           (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
 236                           RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
 237         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
 238                           (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
 239         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
 240                           (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
 241                           (0x1 << PLL_BR_SHIFT),
 242                           RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
 243                           RG_HDMITX_PLL_BR);
 244         if (rate < 165000000) {
 245                 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
 246                                         RG_HDMITX_PRD_IMP_EN);
 247                 pre_ibias = 0x3;
 248                 imp_en = 0x0;
 249                 hdmi_ibias = hdmi_phy->ibias;
 250         } else {
 251                 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
 252                                       RG_HDMITX_PRD_IMP_EN);
 253                 pre_ibias = 0x6;
 254                 imp_en = 0xf;
 255                 hdmi_ibias = hdmi_phy->ibias_up;
 256         }
 257         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
 258                           (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
 259                           (pre_ibias << PRD_IBIAS_D2_SHIFT) |
 260                           (pre_ibias << PRD_IBIAS_D1_SHIFT) |
 261                           (pre_ibias << PRD_IBIAS_D0_SHIFT),
 262                           RG_HDMITX_PRD_IBIAS_CLK |
 263                           RG_HDMITX_PRD_IBIAS_D2 |
 264                           RG_HDMITX_PRD_IBIAS_D1 |
 265                           RG_HDMITX_PRD_IBIAS_D0);
 266         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
 267                           (imp_en << DRV_IMP_EN_SHIFT),
 268                           RG_HDMITX_DRV_IMP_EN);
 269         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
 270                           (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
 271                           (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
 272                           (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
 273                           (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
 274                           RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
 275                           RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
 276         mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
 277                           (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
 278                           (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
 279                           (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
 280                           (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
 281                           RG_HDMITX_DRV_IBIAS_CLK |
 282                           RG_HDMITX_DRV_IBIAS_D2 |
 283                           RG_HDMITX_DRV_IBIAS_D1 |
 284                           RG_HDMITX_DRV_IBIAS_D0);
 285         return 0;
 286 }
 287
 288 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 289                                               unsigned long parent_rate)
 290 {
 291         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 292
 293         return hdmi_phy->pll_rate;
 294 }
 295
 296 static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 297         .prepare = mtk_hdmi_pll_prepare,
 298         .unprepare = mtk_hdmi_pll_unprepare,
 299         .set_rate = mtk_hdmi_pll_set_rate,
 300         .round_rate = mtk_hdmi_pll_round_rate,
 301         .recalc_rate = mtk_hdmi_pll_recalc_rate,
 302 };
 303
 304 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 305 {
 306         mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
 307                               RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
 308                               RG_HDMITX_DRV_EN);
 309         usleep_range(100, 150);
 310 }
 311
 312 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 313 {
 314         mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
 315                                 RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
 316                                 RG_HDMITX_SER_EN);
 317 }
 318
 319 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
 320         .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 321         .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
 322         .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
 323         .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
 324 };
 325
 326 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
 327 MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
 328 MODULE_LICENSE("GPL v2");