binutils/patches/binutils-2.23.52.0.1-as-doc-texinfo-fixes.patch0

   1 diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-arc.texi gas/doc/c-arc.texi
   2 *** ../binutils-2.23.52.0.1.orig/gas/doc/c-arc.texi     2013-03-04 08:25:32.051931944 +0000
   3 --- gas/doc/c-arc.texi  2013-03-04 08:26:19.234930452 +0000
   4 *************** The extension instructions are not macro
   5 *** 220,226 ****
   6   encodings for use of these instructions according to the specification
   7   by the user.  The parameters are:
   8
   9 ! @table @bullet
  10   @item @var{name}
  11   Name of the extension instruction
  12
  13 --- 220,226 ----
  14   encodings for use of these instructions according to the specification
  15   by the user.  The parameters are:
  16
  17 ! @table @code
  18   @item @var{name}
  19   Name of the extension instruction
  20
  21 diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-arm.texi gas/doc/c-arm.texi
  22 *** ../binutils-2.23.52.0.1.orig/gas/doc/c-arm.texi     2013-03-04 08:25:32.039931945 +0000
  23 --- gas/doc/c-arm.texi  2013-03-04 08:27:37.462927978 +0000
  24 *************** ARM and THUMB instructions had their own
  25 *** 390,418 ****
  26   @code{unified} syntax, which can be selected via the @code{.syntax}
  27   directive, and has the following main features:
  28
  29 ! @table @bullet
  30 ! @item
  31   Immediate operands do not require a @code{#} prefix.
  32
  33 ! @item
  34   The @code{IT} instruction may appear, and if it does it is validated
  35   against subsequent conditional affixes.  In ARM mode it does not
  36   generate machine code, in THUMB mode it does.
  37
  38 ! @item
  39   For ARM instructions the conditional affixes always appear at the end
  40   of the instruction.  For THUMB instructions conditional affixes can be
  41   used, but only inside the scope of an @code{IT} instruction.
  42
  43 ! @item
  44   All of the instructions new to the V6T2 architecture (and later) are
  45   available.  (Only a few such instructions can be written in the
  46   @code{divided} syntax).
  47
  48 ! @item
  49   The @code{.N} and @code{.W} suffixes are recognized and honored.
  50
  51 ! @item
  52   All instructions set the flags if and only if they have an @code{s}
  53   affix.
  54   @end table
  55 --- 390,418 ----
  56   @code{unified} syntax, which can be selected via the @code{.syntax}
  57   directive, and has the following main features:
  58
  59 ! @table @code
  60 ! @item 1
  61   Immediate operands do not require a @code{#} prefix.
  62
  63 ! @item 2
  64   The @code{IT} instruction may appear, and if it does it is validated
  65   against subsequent conditional affixes.  In ARM mode it does not
  66   generate machine code, in THUMB mode it does.
  67
  68 ! @item 3
  69   For ARM instructions the conditional affixes always appear at the end
  70   of the instruction.  For THUMB instructions conditional affixes can be
  71   used, but only inside the scope of an @code{IT} instruction.
  72
  73 ! @item 4
  74   All of the instructions new to the V6T2 architecture (and later) are
  75   available.  (Only a few such instructions can be written in the
  76   @code{divided} syntax).
  77
  78 ! @item 5
  79   The @code{.N} and @code{.W} suffixes are recognized and honored.
  80
  81 ! @item 6
  82   All instructions set the flags if and only if they have an @code{s}
  83   affix.
  84   @end table
  85 *************** Either @samp{#} or @samp{$} can be used
  86 *** 451,478 ****
  87   @cindex register names, ARM
  88   *TODO* Explain about ARM register naming, and the predefined names.
  89
  90 - @node ARM-Neon-Alignment
  91 - @subsection NEON Alignment Specifiers
  92 -
  93 - @cindex alignment for NEON instructions
  94 - Some NEON load/store instructions allow an optional address
  95 - alignment qualifier.
  96 - The ARM documentation specifies that this is indicated by
  97 - @samp{@@ @var{align}}. However GAS already interprets
  98 - the @samp{@@} character as a "line comment" start,
  99 - so @samp{: @var{align}} is used instead.  For example:
 100 -
 101 - @smallexample
 102 -         vld1.8 @{q0@}, [r0, :128]
 103 - @end smallexample
 104 -
 105 - @node ARM Floating Point
 106 - @section Floating Point
 107 -
 108 - @cindex floating point, ARM (@sc{ieee})
 109 - @cindex ARM floating point (@sc{ieee})
 110 - The ARM family uses @sc{ieee} floating-point numbers.
 111 -
 112   @node ARM-Relocations
 113   @subsection ARM relocation generation
 114
 115 --- 451,456 ----
 116 *************** respectively.  For example to load the 3
 117 *** 519,524 ****
 118 --- 497,524 ----
 119           MOVT r0, #:upper16:foo
 120   @end smallexample
 121
 122 + @node ARM-Neon-Alignment
 123 + @subsection NEON Alignment Specifiers
 124 +
 125 + @cindex alignment for NEON instructions
 126 + Some NEON load/store instructions allow an optional address
 127 + alignment qualifier.
 128 + The ARM documentation specifies that this is indicated by
 129 + @samp{@@ @var{align}}. However GAS already interprets
 130 + the @samp{@@} character as a "line comment" start,
 131 + so @samp{: @var{align}} is used instead.  For example:
 132 +
 133 + @smallexample
 134 +         vld1.8 @{q0@}, [r0, :128]
 135 + @end smallexample
 136 +
 137 + @node ARM Floating Point
 138 + @section Floating Point
 139 +
 140 + @cindex floating point, ARM (@sc{ieee})
 141 + @cindex ARM floating point (@sc{ieee})
 142 + The ARM family uses @sc{ieee} floating-point numbers.
 143 +
 144   @node ARM Directives
 145   @section ARM Machine Directives
 146
 147 diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-cr16.texi gas/doc/c-cr16.texi
 148 *** ../binutils-2.23.52.0.1.orig/gas/doc/c-cr16.texi    2013-03-04 08:25:32.086931943 +0000
 149 --- gas/doc/c-cr16.texi 2013-03-04 08:28:09.304926971 +0000
 150 *************** Operand expression type qualifier is an
 151 *** 44,69 ****
 152   CR16 target operand qualifiers and its size (in bits):
 153
 154   @table @samp
 155 ! @item Immediate Operand
 156 ! - s ---- 4 bits
 157 ! @item
 158 ! - m ---- 16 bits, for movb and movw instructions.
 159 ! @item
 160 ! - m ---- 20 bits, movd instructions.
 161 ! @item
 162 ! - l ---- 32 bits
 163 !
 164 ! @item Absolute Operand
 165 ! - s ---- Illegal specifier for this operand.
 166 ! @item
 167 ! - m ---- 20 bits, movd instructions.
 168 !
 169 ! @item Displacement Operand
 170 ! - s ---- 8 bits
 171 ! @item
 172 ! - m ---- 16 bits
 173 ! @item
 174 ! - l ---- 24 bits
 175   @end table
 176
 177   For example:
 178 --- 44,76 ----
 179   CR16 target operand qualifiers and its size (in bits):
 180
 181   @table @samp
 182 ! @item Immediate Operand: s
 183 ! 4 bits.
 184 !
 185 ! @item Immediate Operand: m
 186 ! 16 bits, for movb and movw instructions.
 187 !
 188 ! @item Immediate Operand: m
 189 ! 20 bits, movd instructions.
 190 !
 191 ! @item Immediate Operand: l
 192 ! 32 bits.
 193 !
 194 ! @item Absolute Operand: s
 195 ! Illegal specifier for this operand.
 196 !
 197 ! @item Absolute Operand: m
 198 ! 20 bits, movd instructions.
 199 !
 200 ! @item Displacement Operand: s
 201 ! 8 bits.
 202 !
 203 ! @item Displacement Operand: m
 204 ! 16 bits.
 205 !
 206 ! @item Displacement Operand: l
 207 ! 24 bits.
 208 !
 209   @end table
 210
 211   For example:
 212 diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-tic54x.texi gas/doc/c-tic54x.texi
 213 *** ../binutils-2.23.52.0.1.orig/gas/doc/c-tic54x.texi  2013-03-04 08:25:32.035931945 +0000
 214 --- gas/doc/c-tic54x.texi       2013-03-04 08:28:38.186926057 +0000
 215 *************** In this example, x is replaced with SYM2
 216 *** 109,115 ****
 217   is replaced with x.  At this point, x has already been encountered
 218   and the substitution stops.
 219
 220 ! @smallexample @code
 221    .asg   "x",SYM1
 222    .asg   "SYM1",SYM2
 223    .asg   "SYM2",x
 224 --- 109,115 ----
 225   is replaced with x.  At this point, x has already been encountered
 226   and the substitution stops.
 227
 228 ! @smallexample
 229    .asg   "x",SYM1
 230    .asg   "SYM1",SYM2
 231    .asg   "SYM2",x
 232 *************** Substitution may be forced in situations
 233 *** 126,139 ****
 234   ambiguous by placing colons on either side of the subsym.  The following
 235   code:
 236
 237 ! @smallexample @code
 238    .eval  "10",x
 239   LAB:X:  add     #x, a
 240   @end smallexample
 241
 242   When assembled becomes:
 243
 244 ! @smallexample @code
 245   LAB10  add     #10, a
 246   @end smallexample
 247
 248 --- 126,139 ----
 249   ambiguous by placing colons on either side of the subsym.  The following
 250   code:
 251
 252 ! @smallexample
 253    .eval  "10",x
 254   LAB:X:  add     #x, a
 255   @end smallexample
 256
 257   When assembled becomes:
 258
 259 ! @smallexample
 260   LAB10  add     #10, a
 261   @end smallexample
 262
 263 *************** The @code{LDX} pseudo-op is provided for
 264 *** 309,315 ****
 265   of a label or address.  For example, if an address @code{_label} resides
 266   in extended program memory, the value of @code{_label} may be loaded as
 267   follows:
 268 ! @smallexample @code
 269    ldx     #_label,16,a    ; loads extended bits of _label
 270    or      #_label,a       ; loads lower 16 bits of _label
 271    bacc    a               ; full address is in accumulator A
 272 --- 309,315 ----
 273   of a label or address.  For example, if an address @code{_label} resides
 274   in extended program memory, the value of @code{_label} may be loaded as
 275   follows:
 276 ! @smallexample
 277    ldx     #_label,16,a    ; loads extended bits of _label
 278    or      #_label,a       ; loads lower 16 bits of _label
 279    bacc    a               ; full address is in accumulator A