binutils: Update to 2.23.51.0.5.

diff --git a/binutils/binutils.nm b/binutils/binutils.nm
index 3bc9dc02faf2c2ef8b613e958388b38617e027b8..00da9a464c5ec50aa8d76be5b276b2ad401f3c9b 100644 (file)
--- a/binutils/binutils.nm
+++ b/binutils/binutils.nm
@@ -4,8 +4,8 @@
 ###############################################################################
 
 name       = binutils
-version    = 2.23.51.0.3
-release    = 3
+version    = 2.23.51.0.5
+release    = 1
 
 maintainer = Michael Tremer <michael.tremer@ipfire.org>
 groups     = Development/Tools

diff --git a/binutils/patches/binutils-2.22-hardened-crtbegin.patch b/binutils/patches/binutils-2.22-hardened-crtbegin.patch
new file mode 100644 (file)
index 0000000..bc26187
--- /dev/null
+++ b/binutils/patches/binutils-2.22-hardened-crtbegin.patch
@@ -0,0 +1,39 @@
+https://bugs.gentoo.org/391899
+https://bugs.gentoo.org/393321
+
+Make sure the default ELF linker script does the right thing with our customer
+PIE+PIC gcc objects (until we get a chance to rename them).
+
+2011-12-05     Magnus Granberg <zorry@gentoo.org>, Alphat-PC <AlphatPC@gmail.com>
+
+       * scripttempl/elf.sc: Add support for crtbeginTS.o
+
+--- a/ld/scripttempl/elf.sc
++++ b/ld/scripttempl/elf.sc
+@@ -225,8 +225,8 @@
+ if test "${ENABLE_INITFINI_ARRAY}" = "yes"; then
+   SORT_INIT_ARRAY="KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))"
+   SORT_FINI_ARRAY="KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))"
+-  CTORS_IN_INIT_ARRAY="KEEP (*(EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .ctors))"
+-  DTORS_IN_FINI_ARRAY="KEEP (*(EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .dtors))"
++  CTORS_IN_INIT_ARRAY="KEEP (*(EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtbeginTS.o *crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .ctors))"
++  DTORS_IN_FINI_ARRAY="KEEP (*(EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtbeginTS.o *crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .dtors))"
+ else
+   SORT_INIT_ARRAY="KEEP (*(SORT(.init_array.*)))"
+   SORT_FINI_ARRAY="KEEP (*(SORT(.fini_array.*)))"
+@@ -264,6 +264,7 @@
+ 
+     KEEP (*crtbegin.o(.ctors))
+     KEEP (*crtbegin?.o(.ctors))
++    KEEP (*crtbeginTS.o(.ctors))
+ 
+     /* We don't want to include the .ctor section from
+        the crtend.o file until after the sorted ctors.
+@@ -280,6 +281,7 @@
+     ${CONSTRUCTING+${DTOR_START}}
+     KEEP (*crtbegin.o(.dtors))
+     KEEP (*crtbegin?.o(.dtors))
++    KEEP (*crtbeginTS.o(.dtors))
+     KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .dtors))
+     KEEP (*(SORT(.dtors.*)))
+     KEEP (*(.dtors))

diff --git a/binutils/patches/binutils-2.22.52.0.2-flexible-tests.patch b/binutils/patches/binutils-2.22.52.0.2-flexible-tests.patch
new file mode 100644 (file)
index 0000000..af6c927
--- /dev/null
+++ b/binutils/patches/binutils-2.22.52.0.2-flexible-tests.patch
@@ -0,0 +1,25 @@
+making some of the address matches more flexible fixes tests when using
+pax/relro/hash patches
+
+--- binutils/ld/testsuite/ld-ifunc/ifunc-2-local-x86-64.d
++++ binutils/ld/testsuite/ld-ifunc/ifunc-2-local-x86-64.d
+@@ -4,6 +4,6 @@
+ #target: x86_64-*-*
+ 
+ #...
+-[ \t0-9a-f]+:[ \t0-9a-f]+call[ \t0-9a-fq]+<\*ABS\*\+0x220@plt>
+-[ \t0-9a-f]+:[ \t0-9a-f]+lea[ \t]+.*\(%rip\),%rax.*[ \t0-9a-fq]+<\*ABS\*\+0x220@plt>
++[ \t0-9a-f]+:[ \t0-9a-f]+call[ \t0-9a-fq]+<\*ABS\*\+0x[a-f0-9]+@plt>
++[ \t0-9a-f]+:[ \t0-9a-f]+lea[ \t]+.*\(%rip\),%rax.*[ \t0-9a-fq]+<\*ABS\*\+0x[a-f0-9]+@plt>
+ #pass
+--- binutils/ld/testsuite/ld-ifunc/ifunc-2-x86-64.d
++++ binutils/ld/testsuite/ld-ifunc/ifunc-2-x86-64.d
+@@ -4,6 +4,6 @@
+ #target: x86_64-*-*
+ 
+ #...
+-[ \t0-9a-f]+:[ \t0-9a-f]+call[ \t0-9a-fq]+<\*ABS\*\+0x220@plt>
+-[ \t0-9a-f]+:[ \t0-9a-f]+lea[ \t]+.*\(%rip\),%rax.*[ \t0-9a-fq]+<\*ABS\*\+0x220@plt>
++[ \t0-9a-f]+:[ \t0-9a-f]+call[ \t0-9a-fq]+<\*ABS\*\+0x[a-f0-9]+@plt>
++[ \t0-9a-f]+:[ \t0-9a-f]+lea[ \t]+.*\(%rip\),%rax.*[ \t0-9a-fq]+<\*ABS\*\+0x[a-f0-9]+@plt>
+ #pass

diff --git a/binutils/patches/binutils-2.23.51.0.3-arm-ldralt.patch b/binutils/patches/binutils-2.23.51.0.3-arm-ldralt.patch
deleted file mode 100644 (file)
index 4a0f9ca..0000000
--- a/binutils/patches/binutils-2.23.51.0.3-arm-ldralt.patch
+++ /dev/null
@@ -1,208 +0,0 @@
-diff -rcp ../binutils-2.23.51.0.3.orig/gas/ChangeLog ./gas/ChangeLog
-*** ../binutils-2.23.51.0.3.orig/gas/ChangeLog 2012-10-23 10:15:13.038870720 +0100
---- ./gas/ChangeLog    2012-10-23 10:17:56.688907041 +0100
-***************
-*** 1,3 ****
---- 1,8 ----
-+ 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+ 
-+      * config/tc-arm.c: Changed ldra and strl-form mnemonics
-+      to lda and stl-form for armv8.
-+ 
-  2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
-  
-       * config/tc-aarch64.c (aarch64_archs): Rename 'armv8' to 'armv8-a'.
-diff -rcp ../binutils-2.23.51.0.3.orig/gas/config/tc-arm.c ./gas/config/tc-arm.c
-*** ../binutils-2.23.51.0.3.orig/gas/config/tc-arm.c   2012-10-23 10:15:13.379871049 +0100
---- ./gas/config/tc-arm.c      2012-10-23 10:16:50.892897421 +0100
-*************** do_strexd (void)
-*** 8738,8744 ****
-  
-  /* ARM V8 STRL.  */
-  static void
-! do_strlex (void)
-  {
-    constraint (inst.operands[0].reg == inst.operands[1].reg
-             || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
---- 8738,8744 ----
-  
-  /* ARM V8 STRL.  */
-  static void
-! do_stlex (void)
-  {
-    constraint (inst.operands[0].reg == inst.operands[1].reg
-             || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
-*************** do_strlex (void)
-*** 8747,8753 ****
-  }
-  
-  static void
-! do_t_strlex (void)
-  {
-    constraint (inst.operands[0].reg == inst.operands[1].reg
-             || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
---- 8747,8753 ----
-  }
-  
-  static void
-! do_t_stlex (void)
-  {
-    constraint (inst.operands[0].reg == inst.operands[1].reg
-             || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
-*************** static const struct asm_opcode insns[] =
-*** 18476,18500 ****
-  
-   tCE("sevl", 320f005, _sevl,    0, (),               noargs, t_hint),
-   TUE("hlt",  1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
-!  TCE("ldraex",       1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("ldraexd",      1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
-                                                       ldrexd, t_ldrexd),
-!  TCE("ldraexb",      1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),   rd_rn,  rd_rn),
-!  TCE("ldraexh",      1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("strlex",       1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
-!                                                      strlex,  t_strlex),
-!  TCE("strlexd",      1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
-                                                       strexd, t_strexd),
-!  TCE("strlexb",      1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
-!                                                      strlex, t_strlex),
-!  TCE("strlexh",      1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
-!                                                      strlex, t_strlex),
-!  TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("ldrab",        1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("ldrah",        1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-!  TCE("strlb",        1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-!  TCE("strlh",        1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-  
-   /* ARMv8 T32 only.  */
-  #undef ARM_VARIANT
---- 18476,18500 ----
-  
-   tCE("sevl", 320f005, _sevl,    0, (),               noargs, t_hint),
-   TUE("hlt",  1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
-!  TCE("ldaex",        1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("ldaexd",       1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
-                                                       ldrexd, t_ldrexd),
-!  TCE("ldaexb",       1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),   rd_rn,  rd_rn),
-!  TCE("ldaexh",       1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("stlex",        1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
-!                                                      stlex,  t_stlex),
-!  TCE("stlexd",       1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
-                                                       strexd, t_strexd),
-!  TCE("stlexb",       1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
-!                                                      stlex, t_stlex),
-!  TCE("stlexh",       1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
-!                                                      stlex, t_stlex),
-!  TCE("lda",  1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
-!  TCE("stl",  180fc90, e8c00faf, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-!  TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-!  TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-  
-   /* ARMv8 T32 only.  */
-  #undef ARM_VARIANT
-diff -rcp ../binutils-2.23.51.0.3.orig/opcodes/arm-dis.c ./opcodes/arm-dis.c
-*** ../binutils-2.23.51.0.3.orig/opcodes/arm-dis.c     2012-10-23 10:15:16.976873621 +0100
---- ./opcodes/arm-dis.c        2012-10-23 10:16:34.204894516 +0100
-*************** static const struct opcode32 arm_opcodes
-*** 889,908 ****
-    /* V8 instructions.  */
-    {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
-    {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
-!   {ARM_EXT_V8,        0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
-  
-    /* Virtualization Extension instructions.  */
-    {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
---- 889,908 ----
-    /* V8 instructions.  */
-    {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
-    {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
-!   {ARM_EXT_V8,        0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
-!   {ARM_EXT_V8,        0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
-  
-    /* Virtualization Extension instructions.  */
-    {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
-*************** static const struct opcode32 thumb32_opc
-*** 1475,1494 ****
-    /* V8 instructions.  */
-    {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
-    {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
-!   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
-  
-    /* V7 instructions.  */
-    {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
---- 1475,1494 ----
-    /* V8 instructions.  */
-    {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
-    {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
-!   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
-!   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
-  
-    /* V7 instructions.  */
-    {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
-diff -rcp ../binutils-2.23.51.0.3.orig/opcodes/ChangeLog ./opcodes/ChangeLog
-*** ../binutils-2.23.51.0.3.orig/opcodes/ChangeLog     2012-10-23 10:15:17.783874153 +0100
---- ./opcodes/ChangeLog        2012-10-23 10:18:43.593915807 +0100
-***************
-*** 1,3 ****
---- 1,8 ----
-+ 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+ 
-+      * arm-dis.c: Changed ldra and strl-form mnemonics
-+      to lda and stl-form.
-+ 
-  2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
-  
-       * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
-

diff --git a/binutils/patches/binutils-2.23.51.0.2-pt-pax-flags-20120807.patch b/binutils/patches/binutils-2.23.51.0.5-pt-pax-flags-20121112.patch
similarity index 50%
rename from binutils/patches/binutils-2.23.51.0.2-pt-pax-flags-20120807.patch
rename to binutils/patches/binutils-2.23.51.0.5-pt-pax-flags-20121112.patch
index 15530168437e85d232dbdae3640179f05442deb2..9b476c3c21092d598e6bcf8c7fd2abed1e6ce783 100644 (file)
--- a/binutils/patches/binutils-2.23.51.0.2-pt-pax-flags-20120807.patch
+++ b/binutils/patches/binutils-2.23.51.0.5-pt-pax-flags-20121112.patch
@@ -1,5 +1,5 @@
---- binutils-2.23.51.0.2/bfd/elf-bfd.h
-+++ binutils-2.23.51.0.2/bfd/elf-bfd.h
+--- binutils-2.23.51.0.5/bfd/elf-bfd.h
++++ binutils-2.23.51.0.5/bfd/elf-bfd.h
 @@ -1577,6 +1577,9 @@ struct elf_obj_tdata
    /* Segment flags for the PT_GNU_STACK segment.  */
    unsigned int stack_flags;
@@ -10,8 +10,8 @@
    /* Symbol version definitions in external objects.  */
    Elf_Internal_Verdef *verdef;
  
---- binutils-2.23.51.0.2/bfd/elf.c
-+++ binutils-2.23.51.0.2/bfd/elf.c
+--- binutils-2.23.51.0.5/bfd/elf.c
++++ binutils-2.23.51.0.5/bfd/elf.c
 @@ -1158,6 +1158,7 @@ get_segment_type (unsigned int p_type)
      case PT_GNU_EH_FRAME: pt = "EH_FRAME"; break;
      case PT_GNU_STACK: pt = "STACK"; break;
@@ -81,19 +81,20 @@
     && (segment->p_type != PT_TLS                                      \
         || (section->flags & SEC_THREAD_LOCAL))                                \
     && (segment->p_type == PT_LOAD                                     \
---- binutils-2.23.51.0.2/bfd/elflink.c
-+++ binutils-2.23.51.0.2/bfd/elflink.c
-@@ -5545,16 +5545,30 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
-     return TRUE;
+--- binutils-2.23.51.0.5/bfd/elflink.c
++++ binutils-2.23.51.0.5/bfd/elflink.c
+@@ -5545,17 +5545,30 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
+       && ! (*bed->elf_backend_always_size_sections) (output_bfd, info))
+     return FALSE;
  
-   bed = get_elf_backend_data (output_bfd);
-+
 +  elf_tdata (output_bfd)->pax_flags = PF_NORANDEXEC;
 +  if (info->execheap)
 +    elf_tdata (output_bfd)->pax_flags |= PF_NOMPROTECT;
 +  else if (info->noexecheap)
 +    elf_tdata (output_bfd)->pax_flags |= PF_MPROTECT;
 +
+   /* Determine any GNU_STACK segment requirements, after the backend
+      has had a chance to set a default segment size.  */
    if (info->execstack)
 -    elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X;
 +    {
@@ -129,8 +130,8 @@
              notesec = s;
            }
          else if (bed->default_execstack)
---- binutils-2.23.51.0.2/binutils/readelf.c
-+++ binutils-2.23.51.0.2/binutils/readelf.c
+--- binutils-2.23.51.0.5/binutils/readelf.c
++++ binutils-2.23.51.0.5/binutils/readelf.c
 @@ -2740,6 +2740,7 @@ get_segment_type (unsigned long p_type)
                        return "GNU_EH_FRAME";
      case PT_GNU_STACK:        return "GNU_STACK";
@@ -139,8 +140,8 @@
  
      default:
        if ((p_type >= PT_LOPROC) && (p_type <= PT_HIPROC))
---- binutils-2.23.51.0.2/include/bfdlink.h
-+++ binutils-2.23.51.0.2/include/bfdlink.h
+--- binutils-2.23.51.0.5/include/bfdlink.h
++++ binutils-2.23.51.0.5/include/bfdlink.h
 @@ -322,6 +322,14 @@ struct bfd_link_info
    /* TRUE if PT_GNU_RELRO segment should be created.  */
    unsigned int relro: 1;
@@ -156,8 +157,8 @@
    /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment
       should be created.  */
    unsigned int eh_frame_hdr: 1;
---- binutils-2.23.51.0.2/include/elf/common.h
-+++ binutils-2.23.51.0.2/include/elf/common.h
+--- binutils-2.23.51.0.5/include/elf/common.h
++++ binutils-2.23.51.0.5/include/elf/common.h
 @@ -429,6 +429,7 @@
  #define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME      /* Solaris uses the same value */
  #define PT_GNU_STACK  (PT_LOOS + 0x474e551) /* Stack flags */
@@ -188,8 +189,8 @@
  /* Values for section header, sh_type field.  */
  
  #define SHT_NULL      0               /* Section header table entry unused */
---- binutils-2.23.51.0.2/ld/emultempl/elf32.em
-+++ binutils-2.23.51.0.2/ld/emultempl/elf32.em
+--- binutils-2.23.51.0.5/ld/emultempl/elf32.em
++++ binutils-2.23.51.0.5/ld/emultempl/elf32.em
 @@ -2285,6 +2285,16 @@ fragment <<EOF
          link_info.noexecstack = TRUE;
          link_info.execstack = FALSE;
@@ -225,8 +226,8 @@
  EOF
  if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then
  fragment <<EOF
---- binutils-2.23.51.0.2/ld/ldgram.y
-+++ binutils-2.23.51.0.2/ld/ldgram.y
+--- binutils-2.23.51.0.5/ld/ldgram.y
++++ binutils-2.23.51.0.5/ld/ldgram.y
 @@ -1119,6 +1119,8 @@ phdr_type:
                            $$ = exp_intop (0x6474e550);
                          else if (strcmp (s, "PT_GNU_STACK") == 0)
@@ -236,8 +237,8 @@
                          else
                            {
                              einfo (_("\
---- binutils-2.23.51.0.2/ld/testsuite/ld-alpha/tlsbin.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-alpha/tlsbin.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-alpha/tlsbin.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-alpha/tlsbin.rd
 @@ -35,13 +35,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
  
  Program Headers:
@@ -254,8 +255,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-alpha/tlsbinr.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-alpha/tlsbinr.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-alpha/tlsbinr.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-alpha/tlsbinr.rd
 @@ -42,6 +42,7 @@ Program Headers:
   +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
   +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
@@ -264,8 +265,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-alpha/tlspic.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-alpha/tlspic.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-alpha/tlspic.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-alpha/tlspic.rd
 @@ -38,6 +38,7 @@ Program Headers:
   +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
   +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
@@ -274,8 +275,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 7 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-elf/eh1.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-elf/eh1.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-elf/eh1.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-elf/eh1.d
 @@ -22,11 +22,11 @@ Contents of the .eh_frame section:
    DW_CFA_nop
    DW_CFA_nop
@@ -291,8 +292,8 @@
    DW_CFA_def_cfa_register: r6 \(rbp\)
  
  00000038 ZERO terminator
---- binutils-2.23.51.0.2/ld/testsuite/ld-elf/eh2.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-elf/eh2.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-elf/eh2.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-elf/eh2.d
 @@ -22,11 +22,11 @@ Contents of the .eh_frame section:
    DW_CFA_nop
    DW_CFA_nop
@@ -308,8 +309,8 @@
    DW_CFA_def_cfa_register: r6 \(rbp\)
  
  00000038 ZERO terminator
---- binutils-2.23.51.0.2/ld/testsuite/ld-elf/eh3.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-elf/eh3.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-elf/eh3.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-elf/eh3.d
 @@ -22,11 +22,11 @@ Contents of the .eh_frame section:
    DW_CFA_nop
    DW_CFA_nop
@@ -325,8 +326,8 @@
    DW_CFA_def_cfa_register: r6 \(rbp\)
  
  00000038 ZERO terminator
---- binutils-2.23.51.0.2/ld/testsuite/ld-elf/orphan-region.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-elf/orphan-region.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-elf/orphan-region.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-elf/orphan-region.d
 @@ -15,7 +15,9 @@
  Program Headers:
    Type.*
@@ -337,8 +338,8 @@
    Segment Sections...
     00     .text .rodata .moredata *
 +   01 +
---- binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsbin.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsbin.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsbin.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsbin.rd
 @@ -44,6 +44,7 @@ Program Headers:
   +LOAD.*
   +DYNAMIC.*
@@ -355,8 +356,8 @@
  
  Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries:
   Offset +Info +Type +Sym.Value +Sym. Name
---- binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsbindesc.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsbindesc.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsbindesc.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsbindesc.rd
 @@ -42,6 +42,7 @@ Program Headers:
   +LOAD.*
   +DYNAMIC.*
@@ -373,8 +374,8 @@
  
  Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries:
   Offset +Info +Type +Sym.Value +Sym. Name
---- binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsdesc.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsdesc.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsdesc.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsdesc.rd
 @@ -39,6 +39,7 @@ Program Headers:
   +LOAD.*
   +DYNAMIC.*
@@ -391,8 +392,8 @@
  
  Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries:
   Offset +Info +Type +Sym.Value +Sym. Name
---- binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsgdesc.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsgdesc.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsgdesc.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsgdesc.rd
 @@ -36,12 +36,14 @@ Program Headers:
   +LOAD.*
   +LOAD.*
@@ -408,8 +409,8 @@
  
  Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
   Offset +Info +Type +Sym.Value +Sym. Name
---- binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsnopic.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlsnopic.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsnopic.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlsnopic.rd
 @@ -37,6 +37,7 @@ Program Headers:
   +LOAD.*
   +DYNAMIC.*
@@ -426,8 +427,8 @@
  
  Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries:
   Offset +Info +Type +Sym.Value +Sym. Name
---- binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlspic.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-i386/tlspic.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlspic.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-i386/tlspic.rd
 @@ -40,6 +40,7 @@ Program Headers:
   +LOAD.*
   +DYNAMIC.*
@@ -444,8 +445,8 @@
  
  Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 26 entries:
   Offset +Info +Type +Sym.Value +Sym. Name
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge1.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge1.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge1.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge1.d
 @@ -4,7 +4,7 @@
  #objdump: -d
  
@@ -455,8 +456,8 @@
  [     ]*[a-f0-9]+:    0b 60 80 02 00 24       \[MMI\]       addl r12=32,r1;;
  [     ]*[a-f0-9]+:    c0 c0 04 00 48 00                   addl r12=24,r1
  [     ]*[a-f0-9]+:    00 00 04 00                         nop.i 0x0;;
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge2.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge2.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge2.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge2.d
 @@ -4,7 +4,7 @@
  #objdump: -d
  
@@ -466,8 +467,8 @@
  [     ]*[a-f0-9]+:    0b 60 80 02 00 24       \[MMI\]       addl r12=32,r1;;
  [     ]*[a-f0-9]+:    c0 c0 04 00 48 00                   addl r12=24,r1
  [     ]*[a-f0-9]+:    00 00 04 00                         nop.i 0x0;;
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge3.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge3.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge3.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge3.d
 @@ -4,7 +4,7 @@
  #objdump: -d
  
@@ -477,8 +478,8 @@
  [     ]*[a-f0-9]+:    0b 60 80 02 00 24       \[MMI\]       addl r12=32,r1;;
  [     ]*[a-f0-9]+:    c0 40 05 00 48 00                   addl r12=40,r1
  [     ]*[a-f0-9]+:    00 00 04 00                         nop.i 0x0;;
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge4.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge4.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge4.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge4.d
 @@ -4,7 +4,7 @@
  #objdump: -d
  
@@ -488,8 +489,8 @@
  [     ]*[a-f0-9]+:    0b 60 80 02 00 24       \[MMI\]       addl r12=32,r1;;
  [     ]*[a-f0-9]+:    c0 40 05 00 48 00                   addl r12=40,r1
  [     ]*[a-f0-9]+:    00 00 04 00                         nop.i 0x0;;
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge5.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/merge5.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge5.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/merge5.d
 @@ -4,7 +4,7 @@
  #objdump: -d
  
@@ -499,8 +500,8 @@
  [     ]*[a-f0-9]+:    0b 60 80 02 00 24       \[MMI\]       addl r12=32,r1;;
  [     ]*[a-f0-9]+:    c0 40 05 00 48 00                   addl r12=40,r1
  [     ]*[a-f0-9]+:    00 00 04 00                         nop.i 0x0;;
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/tlsbin.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/tlsbin.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/tlsbin.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/tlsbin.rd
 @@ -36,13 +36,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
  
  Program Headers:
@@ -518,8 +519,8 @@
   +IA_64_UNWIND .* R +0x8
  #...
  
---- binutils-2.23.51.0.2/ld/testsuite/ld-ia64/tlspic.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-ia64/tlspic.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-ia64/tlspic.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-ia64/tlspic.rd
 @@ -40,6 +40,7 @@ Program Headers:
   +LOAD +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000
   +DYNAMIC +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+140 0x0+140 RW +0x8
@@ -528,8 +529,8 @@
   +IA_64_UNWIND +0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+18 0x0+18 R +0x8
  #...
  
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
 @@ -8,9 +8,9 @@
  .*: +file format.*
  
@@ -543,8 +544,8 @@
  #...
  00408d60 <[^>]*> 3c1c0043     lui     gp,0x43
  00408d64 <[^>]*> 279c2c98     addiu   gp,gp,11416
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is DYN \(Shared object file\)
@@ -567,8 +568,8 @@
   *0*3 * \.dynamic *
   *0*4 *
 + *0*5 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is EXEC \(Executable file\)
@@ -591,8 +592,8 @@
   *0*6 *\.dynamic *
   *0*7 *
 + *0*8 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is EXEC \(Executable file\)
@@ -615,8 +616,8 @@
   *0*6 * \.dynamic *
   *0*7 *
 + *0*8 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is EXEC \(Executable file\)
@@ -639,8 +640,8 @@
   *0*6 * \.dynamic *
   *0*7 *
 + *0*8 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is EXEC \(Executable file\)
@@ -663,8 +664,8 @@
   *0*6 * \.dynamic *
   *0*7 *
 + *0*8 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is EXEC \(Executable file\)
@@ -687,8 +688,8 @@
   *0*5 * \.dynamic *
   *0*6 *
 + *0*7 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
 @@ -1,7 +1,7 @@
  
  Elf file type is EXEC \(Executable file\)
@@ -711,8 +712,8 @@
   *0*6 * \.dynamic *
   *0*7 *
 + *0*8 *
---- binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/tlsbin-o32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-mips-elf/tlsbin-o32.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/tlsbin-o32.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-mips-elf/tlsbin-o32.d
 @@ -2,42 +2,42 @@
  
  Disassembly of section .text:
@@ -794,220 +795,8 @@
 +00400[0-9a-f]{3} <__tls_get_addr>:
 +  400[0-9a-f]{3}:     03e00008        jr      ra
 +  400[0-9a-f]{3}:     00000000        nop
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls.d
-@@ -9,45 +9,45 @@
- 
- Disassembly of section \.text:
- 
--0+100000e8 <_start>:
--    100000e8: 3c 6d 00 00     addis   r3,r13,0
--    100000ec: 60 00 00 00     nop
--    100000f0: 38 63 90 78     addi    r3,r3,-28552
--    100000f4: 3c 6d 00 00     addis   r3,r13,0
--    100000f8: 60 00 00 00     nop
--    100000fc: 38 63 10 00     addi    r3,r3,4096
--    10000100: 3c 6d 00 00     addis   r3,r13,0
--    10000104: 60 00 00 00     nop
--    10000108: 38 63 90 40     addi    r3,r3,-28608
--    1000010c: 3c 6d 00 00     addis   r3,r13,0
--    10000110: 60 00 00 00     nop
--    10000114: 38 63 10 00     addi    r3,r3,4096
--    10000118: 39 23 80 48     addi    r9,r3,-32696
--    1000011c: 3d 23 00 00     addis   r9,r3,0
--    10000120: 81 49 80 50     lwz     r10,-32688\(r9\)
--    10000124: e9 22 80 10     ld      r9,-32752\(r2\)
--    10000128: 7d 49 18 2a     ldx     r10,r9,r3
--    1000012c: 3d 2d 00 00     addis   r9,r13,0
--    10000130: a1 49 90 60     lhz     r10,-28576\(r9\)
--    10000134: 89 4d 90 68     lbz     r10,-28568\(r13\)
--    10000138: 3d 2d 00 00     addis   r9,r13,0
--    1000013c: 99 49 90 70     stb     r10,-28560\(r9\)
--    10000140: 3c 6d 00 00     addis   r3,r13,0
--    10000144: 60 00 00 00     nop
--    10000148: 38 63 90 00     addi    r3,r3,-28672
--    1000014c: 3c 6d 00 00     addis   r3,r13,0
--    10000150: 60 00 00 00     nop
--    10000154: 38 63 10 00     addi    r3,r3,4096
--    10000158: f9 43 80 08     std     r10,-32760\(r3\)
--    1000015c: 3d 23 00 00     addis   r9,r3,0
--    10000160: 91 49 80 10     stw     r10,-32752\(r9\)
--    10000164: e9 22 80 08     ld      r9,-32760\(r2\)
--    10000168: 7d 49 19 2a     stdx    r10,r9,r3
--    1000016c: 3d 2d 00 00     addis   r9,r13,0
--    10000170: b1 49 90 60     sth     r10,-28576\(r9\)
--    10000174: e9 4d 90 2a     lwa     r10,-28632\(r13\)
--    10000178: 3d 2d 00 00     addis   r9,r13,0
--    1000017c: a9 49 90 30     lha     r10,-28624\(r9\)
-+0+10000[0-9a-f]{3} <_start>:
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 78     addi    r3,r3,-28552
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 10 00     addi    r3,r3,4096
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 40     addi    r3,r3,-28608
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 10 00     addi    r3,r3,4096
-+    10000[0-9a-f]{3}: 39 23 80 48     addi    r9,r3,-32696
-+    10000[0-9a-f]{3}: 3d 23 00 00     addis   r9,r3,0
-+    10000[0-9a-f]{3}: 81 49 80 50     lwz     r10,-32688\(r9\)
-+    10000[0-9a-f]{3}: e9 22 80 10     ld      r9,-32752\(r2\)
-+    10000[0-9a-f]{3}: 7d 49 18 2a     ldx     r10,r9,r3
-+    10000[0-9a-f]{3}: 3d 2d 00 00     addis   r9,r13,0
-+    10000[0-9a-f]{3}: a1 49 90 60     lhz     r10,-28576\(r9\)
-+    10000[0-9a-f]{3}: 89 4d 90 68     lbz     r10,-28568\(r13\)
-+    10000[0-9a-f]{3}: 3d 2d 00 00     addis   r9,r13,0
-+    10000[0-9a-f]{3}: 99 49 90 70     stb     r10,-28560\(r9\)
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 00     addi    r3,r3,-28672
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 10 00     addi    r3,r3,4096
-+    10000[0-9a-f]{3}: f9 43 80 08     std     r10,-32760\(r3\)
-+    10000[0-9a-f]{3}: 3d 23 00 00     addis   r9,r3,0
-+    10000[0-9a-f]{3}: 91 49 80 10     stw     r10,-32752\(r9\)
-+    10000[0-9a-f]{3}: e9 22 80 08     ld      r9,-32760\(r2\)
-+    10000[0-9a-f]{3}: 7d 49 19 2a     stdx    r10,r9,r3
-+    10000[0-9a-f]{3}: 3d 2d 00 00     addis   r9,r13,0
-+    10000[0-9a-f]{3}: b1 49 90 60     sth     r10,-28576\(r9\)
-+    10000[0-9a-f]{3}: e9 4d 90 2a     lwa     r10,-28632\(r13\)
-+    10000[0-9a-f]{3}: 3d 2d 00 00     addis   r9,r13,0
-+    10000[0-9a-f]{3}: a9 49 90 30     lha     r10,-28624\(r9\)
- 
--0+10000180 <\.__tls_get_addr>:
--    10000180: 4e 80 00 20     blr
-+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
-+    10000[0-9a-f]{3}: 4e 80 00 20     blr
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls.g
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls.g
-@@ -8,5 +8,5 @@
- .*: +file format elf64-powerpc
- 
- Contents of section \.got:
-- 100101e0 00000000 100181e0 ffffffff ffff8018  .*
-- 100101f0 ffffffff ffff8058                    .*
-+ 10010([0-9a-f]{3}) 00000000 10018\1 ffffffff ffff8018  .*
-+ 10010[0-9a-f]{3} ffffffff ffff8058                    .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls32.d
-@@ -9,42 +9,42 @@
- 
- Disassembly of section \.text:
- 
--0+1800094 <_start>:
-- 1800094:     3c 62 00 00     addis   r3,r2,0
-- 1800098:     38 63 90 3c     addi    r3,r3,-28612
-- 180009c:     3c 62 00 00     addis   r3,r2,0
-- 18000a0:     38 63 10 00     addi    r3,r3,4096
-- 18000a4:     3c 62 00 00     addis   r3,r2,0
-- 18000a8:     38 63 90 20     addi    r3,r3,-28640
-- 18000ac:     3c 62 00 00     addis   r3,r2,0
-- 18000b0:     38 63 10 00     addi    r3,r3,4096
-- 18000b4:     39 23 80 24     addi    r9,r3,-32732
-- 18000b8:     3d 23 00 00     addis   r9,r3,0
-- 18000bc:     81 49 80 28     lwz     r10,-32728\(r9\)
-- 18000c0:     3d 22 00 00     addis   r9,r2,0
-- 18000c4:     a1 49 90 30     lhz     r10,-28624\(r9\)
-- 18000c8:     89 42 90 34     lbz     r10,-28620\(r2\)
-- 18000cc:     3d 22 00 00     addis   r9,r2,0
-- 18000d0:     99 49 90 38     stb     r10,-28616\(r9\)
-- 18000d4:     3c 62 00 00     addis   r3,r2,0
-- 18000d8:     38 63 90 00     addi    r3,r3,-28672
-- 18000dc:     3c 62 00 00     addis   r3,r2,0
-- 18000e0:     38 63 10 00     addi    r3,r3,4096
-- 18000e4:     91 43 80 04     stw     r10,-32764\(r3\)
-- 18000e8:     3d 23 00 00     addis   r9,r3,0
-- 18000ec:     91 49 80 08     stw     r10,-32760\(r9\)
-- 18000f0:     3d 22 00 00     addis   r9,r2,0
-- 18000f4:     b1 49 90 30     sth     r10,-28624\(r9\)
-- 18000f8:     a1 42 90 14     lhz     r10,-28652\(r2\)
-- 18000fc:     3d 22 00 00     addis   r9,r2,0
-- 1800100:     a9 49 90 18     lha     r10,-28648\(r9\)
-+0+1800[0-9a-f]{3} <_start>:
-+ 1800[0-9a-f]{3}:     3c 62 00 00     addis   r3,r2,0
-+ 1800[0-9a-f]{3}:     38 63 90 3c     addi    r3,r3,-28612
-+ 1800[0-9a-f]{3}:     3c 62 00 00     addis   r3,r2,0
-+ 1800[0-9a-f]{3}:     38 63 10 00     addi    r3,r3,4096
-+ 1800[0-9a-f]{3}:     3c 62 00 00     addis   r3,r2,0
-+ 1800[0-9a-f]{3}:     38 63 90 20     addi    r3,r3,-28640
-+ 1800[0-9a-f]{3}:     3c 62 00 00     addis   r3,r2,0
-+ 1800[0-9a-f]{3}:     38 63 10 00     addi    r3,r3,4096
-+ 1800[0-9a-f]{3}:     39 23 80 24     addi    r9,r3,-32732
-+ 1800[0-9a-f]{3}:     3d 23 00 00     addis   r9,r3,0
-+ 1800[0-9a-f]{3}:     81 49 80 28     lwz     r10,-32728\(r9\)
-+ 1800[0-9a-f]{3}:     3d 22 00 00     addis   r9,r2,0
-+ 1800[0-9a-f]{3}:     a1 49 90 30     lhz     r10,-28624\(r9\)
-+ 1800[0-9a-f]{3}:     89 42 90 34     lbz     r10,-28620\(r2\)
-+ 1800[0-9a-f]{3}:     3d 22 00 00     addis   r9,r2,0
-+ 1800[0-9a-f]{3}:     99 49 90 38     stb     r10,-28616\(r9\)
-+ 1800[0-9a-f]{3}:     3c 62 00 00     addis   r3,r2,0
-+ 1800[0-9a-f]{3}:     38 63 90 00     addi    r3,r3,-28672
-+ 1800[0-9a-f]{3}:     3c 62 00 00     addis   r3,r2,0
-+ 1800[0-9a-f]{3}:     38 63 10 00     addi    r3,r3,4096
-+ 1800[0-9a-f]{3}:     91 43 80 04     stw     r10,-32764\(r3\)
-+ 1800[0-9a-f]{3}:     3d 23 00 00     addis   r9,r3,0
-+ 1800[0-9a-f]{3}:     91 49 80 08     stw     r10,-32760\(r9\)
-+ 1800[0-9a-f]{3}:     3d 22 00 00     addis   r9,r2,0
-+ 1800[0-9a-f]{3}:     b1 49 90 30     sth     r10,-28624\(r9\)
-+ 1800[0-9a-f]{3}:     a1 42 90 14     lhz     r10,-28652\(r2\)
-+ 1800[0-9a-f]{3}:     3d 22 00 00     addis   r9,r2,0
-+ 1800[0-9a-f]{3}:     a9 49 90 18     lha     r10,-28648\(r9\)
- 
--0+1800104 <__tls_get_addr>:
-- 1800104:     4e 80 00 20     blr
-+0+1800[0-9a-f]{3} <__tls_get_addr>:
-+ 1800[0-9a-f]{3}:     4e 80 00 20     blr
- Disassembly of section \.got:
- 
--0+1810128 <_GLOBAL_OFFSET_TABLE_-0x4>:
-- 1810128:     4e 80 00 21     blrl
-+0+1810[0-9a-f]{3} <_GLOBAL_OFFSET_TABLE_-0x4>:
-+ 1810[0-9a-f]{3}:     4e 80 00 21     blrl
- 
--0+181012c <_GLOBAL_OFFSET_TABLE_>:
-+0+1810[0-9a-f]{3} <_GLOBAL_OFFSET_TABLE_>:
-       \.\.\.
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls32.g
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls32.g
-@@ -8,4 +8,4 @@
- .*: +file format elf32-powerpc
- 
- Contents of section \.got:
-- 1810128 4e800021 00000000 00000000 00000000  .*
-+ 18101[0-9a-f]{2} 4e800021 00000000 00000000 00000000  .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls32.t
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tls32.t
-@@ -8,5 +8,5 @@
- .*: +file format elf32-powerpc
- 
- Contents of section \.tdata:
-- 1810108 12345678 23456789 3456789a 456789ab  .*
-- 1810118 56789abc 6789abcd 789abcde 00c0ffee  .*
-+ 18101[0-9a-f]{2} 12345678 23456789 3456789a 456789ab  .*
-+ 18101[0-9a-f]{2} 56789abc 6789abcd 789abcde 00c0ffee  .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsexe32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsexe32.d
-@@ -44,4 +44,4 @@ Disassembly of section \.got:
- .*:   4e 80 00 21     blrl
- 
- .* <_GLOBAL_OFFSET_TABLE_>:
--.*:   01 81 02 b8 00 00 00 00 00 00 00 00  .*
-+.*:   01 81 02 [bd]8 00 00 00 00 00 00 00 00  .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsexe32.g
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsexe32.g
-@@ -8,4 +8,4 @@
- 
- Contents of section \.got:
- .* 00000000 00000000 00000000 4e800021  .*
--.* 018102b8 00000000 00000000           .*
-+.* 018102[bd]8 00000000 00000000           .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsexe32.r
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsexe32.r
+--- binutils-2.23.51.0.5/ld/testsuite/ld-powerpc/tlsexe32.r
++++ binutils-2.23.51.0.5/ld/testsuite/ld-powerpc/tlsexe32.r
 @@ -33,13 +33,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
  
  Program Headers:
@@ -1033,425 +822,8 @@
  
  Relocation section '\.rela\.dyn' at offset .* contains 2 entries:
   Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsmark.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsmark.d
-@@ -9,29 +9,29 @@
- 
- Disassembly of section \.text:
- 
--0+100000e8 <_start>:
--    100000e8: 48 00 00 18     b       10000100 <_start\+0x18>
--    100000ec: 60 00 00 00     nop
--    100000f0: 38 63 90 00     addi    r3,r3,-28672
--    100000f4: e8 83 00 00     ld      r4,0\(r3\)
--    100000f8: 3c 6d 00 00     addis   r3,r13,0
--    100000fc: 48 00 00 0c     b       10000108 <_start\+0x20>
--    10000100: 3c 6d 00 00     addis   r3,r13,0
--    10000104: 4b ff ff e8     b       100000ec <_start\+0x4>
--    10000108: 60 00 00 00     nop
--    1000010c: 38 63 10 00     addi    r3,r3,4096
--    10000110: e8 83 80 00     ld      r4,-32768\(r3\)
--    10000114: 3c 6d 00 00     addis   r3,r13,0
--    10000118: 48 00 00 0c     b       10000124 <_start\+0x3c>
--    1000011c: 3c 6d 00 00     addis   r3,r13,0
--    10000120: 48 00 00 14     b       10000134 <_start\+0x4c>
--    10000124: 60 00 00 00     nop
--    10000128: 38 63 90 04     addi    r3,r3,-28668
--    1000012c: e8 a3 00 00     ld      r5,0\(r3\)
--    10000130: 4b ff ff ec     b       1000011c <_start\+0x34>
--    10000134: 60 00 00 00     nop
--    10000138: 38 63 10 00     addi    r3,r3,4096
--    1000013c: e8 a3 80 04     ld      r5,-32764\(r3\)
-+0+10000[0-9a-f]{3} <_start>:
-+    10000[0-9a-f]{3}: 48 00 00 18     b       10000[0-9a-f]{3} <_start\+0x18>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 00     addi    r3,r3,-28672
-+    10000[0-9a-f]{3}: e8 83 00 00     ld      r4,0\(r3\)
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       10000[0-9a-f]{3} <_start\+0x20>
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 4b ff ff e8     b       10000[0-9a-f]{3} <_start\+0x4>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 10 00     addi    r3,r3,4096
-+    10000[0-9a-f]{3}: e8 83 80 00     ld      r4,-32768\(r3\)
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       10000[0-9a-f]{3} <_start\+0x3c>
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 48 00 00 14     b       10000[0-9a-f]{3} <_start\+0x4c>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 04     addi    r3,r3,-28668
-+    10000[0-9a-f]{3}: e8 a3 00 00     ld      r5,0\(r3\)
-+    10000[0-9a-f]{3}: 4b ff ff ec     b       10000[0-9a-f]{3} <_start\+0x34>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 10 00     addi    r3,r3,4096
-+    10000[0-9a-f]{3}: e8 a3 80 04     ld      r5,-32764\(r3\)
- 
--0+10000140 <\.__tls_get_addr>:
--    10000140: 4e 80 00 20     blr
-+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
-+    10000[0-9a-f]{3}: 4e 80 00 20     blr
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsmark32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsmark32.d
-@@ -9,17 +9,17 @@
- 
- Disassembly of section \.text:
- 
--0+1800094 <_start>:
-- 1800094:     48 00 00 14     b       18000a8 <_start\+0x14>
-- 1800098:     38 63 90 00     addi    r3,r3,-28672
-- 180009c:     80 83 00 00     lwz     r4,0\(r3\)
-- 18000a0:     3c 62 00 00     addis   r3,r2,0
-- 18000a4:     48 00 00 0c     b       18000b0 <_start\+0x1c>
-- 18000a8:     3c 62 00 00     addis   r3,r2,0
-- 18000ac:     4b ff ff ec     b       1800098 <_start\+0x4>
-- 18000b0:     38 63 10 00     addi    r3,r3,4096
-- 18000b4:     80 83 80 00     lwz     r4,-32768\(r3\)
-+0+18000[0-9a-f]{2} <_start>:
-+ 18000[0-9a-f]{2}:    48 00 00 14     b       18000[0-9a-f]{2} <_start\+0x14>
-+ 18000[0-9a-f]{2}:    38 63 90 00     addi    r3,r3,-28672
-+ 18000[0-9a-f]{2}:    80 83 00 00     lwz     r4,0\(r3\)
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    48 00 00 0c     b       18000[0-9a-f]{2} <_start\+0x1c>
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    4b ff ff ec     b       18000[0-9a-f]{2} <_start\+0x4>
-+ 18000[0-9a-f]{2}:    38 63 10 00     addi    r3,r3,4096
-+ 18000[0-9a-f]{2}:    80 83 80 00     lwz     r4,-32768\(r3\)
- 
--0+18000b8 <__tls_get_addr>:
-- 18000b8:     4e 80 00 20     blr
--#pass
-\ No newline at end of file
-+0+18000[0-9a-f]{2} <__tls_get_addr>:
-+ 18000[0-9a-f]{2}:    4e 80 00 20     blr
-+#pass
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt1.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt1.d
-@@ -9,17 +9,17 @@
- 
- Disassembly of section \.text:
- 
--0+100000e8 <\.__tls_get_addr>:
--    100000e8: 4e 80 00 20     blr
-+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
-+    10000[0-9a-f]{3}: 4e 80 00 20     blr
- 
- Disassembly of section \.no_opt1:
- 
--0+100000ec <\.no_opt1>:
--    100000ec: 38 62 80 08     addi    r3,r2,-32760
--    100000f0: 2c 24 00 00     cmpdi   r4,0
--    100000f4: 41 82 00 10     beq-    .*
--    100000f8: 4b ff ff f1     bl      100000e8 <\.__tls_get_addr>
--    100000fc: 60 00 00 00     nop
--    10000100: 48 00 00 0c     b       .*
--    10000104: 4b ff ff e5     bl      100000e8 <\.__tls_get_addr>
--    10000108: 60 00 00 00     nop
-+0+10000[0-9a-f]{3} <\.no_opt1>:
-+    10000[0-9a-f]{3}: 38 62 80 08     addi    r3,r2,-32760
-+    10000[0-9a-f]{3}: 2c 24 00 00     cmpdi   r4,0
-+    10000[0-9a-f]{3}: 41 82 00 10     beq-    .*
-+    10000[0-9a-f]{3}: 4b ff ff f1     bl      10000[0-9a-f]{3} <\.__tls_get_addr>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       .*
-+    10000[0-9a-f]{3}: 4b ff ff e5     bl      10000[0-9a-f]{3} <\.__tls_get_addr>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt1_32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt1_32.d
-@@ -9,16 +9,16 @@
- 
- Disassembly of section \.text:
- 
--0+1800094 <__tls_get_addr>:
-- 1800094:     4e 80 00 20     blr
-+0+18000[0-9a-f]{2} <__tls_get_addr>:
-+ 18000[0-9a-f]{2}:    4e 80 00 20     blr
- 
- Disassembly of section \.no_opt1:
- 
--0+1800098 <\.no_opt1>:
-- 1800098:     38 6d ff f4     addi    r3,r13,-12
-- 180009c:     2c 04 00 00     cmpwi   r4,0
-- 18000a0:     41 82 00 0c     beq-    .*
-- 18000a4:     4b ff ff f1     bl      1800094 <__tls_get_addr>
-- 18000a8:     48 00 00 08     b       .*
-- 18000ac:     4b ff ff e9     bl      1800094 <__tls_get_addr>
-+0+18000[0-9a-f]{2} <\.no_opt1>:
-+ 18000[0-9a-f]{2}:    38 6d ff f4     addi    r3,r13,-12
-+ 18000[0-9a-f]{2}:    2c 04 00 00     cmpwi   r4,0
-+ 18000[0-9a-f]{2}:    41 82 00 0c     beq-    .*
-+ 18000[0-9a-f]{2}:    4b ff ff f1     bl      18000[0-9a-f]{2} <__tls_get_addr>
-+ 18000[0-9a-f]{2}:    48 00 00 08     b       .*
-+ 18000[0-9a-f]{2}:    4b ff ff e9     bl      18000[0-9a-f]{2} <__tls_get_addr>
- #pass
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt2.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt2.d
-@@ -9,15 +9,15 @@
- 
- Disassembly of section \.text:
- 
--0+100000e8 <\.__tls_get_addr>:
--    100000e8: 4e 80 00 20     blr
-+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
-+    10000[0-9a-f]{3}: 4e 80 00 20     blr
- 
- Disassembly of section \.no_opt2:
- 
--0+100000ec <\.no_opt2>:
--    100000ec: 38 62 80 08     addi    r3,r2,-32760
--    100000f0: 2c 24 00 00     cmpdi   r4,0
--    100000f4: 41 82 00 08     beq-    .*
--    100000f8: 38 62 80 08     addi    r3,r2,-32760
--    100000fc: 4b ff ff ed     bl      100000e8 <\.__tls_get_addr>
--    10000100: 60 00 00 00     nop
-+0+10000[0-9a-f]{3} <\.no_opt2>:
-+    10000[0-9a-f]{3}: 38 62 80 08     addi    r3,r2,-32760
-+    10000[0-9a-f]{3}: 2c 24 00 00     cmpdi   r4,0
-+    10000[0-9a-f]{3}: 41 82 00 08     beq-    .*
-+    10000[0-9a-f]{3}: 38 62 80 08     addi    r3,r2,-32760
-+    10000[0-9a-f]{3}: 4b ff ff ed     bl      10000[0-9a-f]{3} <\.__tls_get_addr>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt2_32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt2_32.d
-@@ -9,15 +9,15 @@
- 
- Disassembly of section \.text:
- 
--0+1800094 <__tls_get_addr>:
-- 1800094:     4e 80 00 20     blr
-+0+18000[0-9a-f]{2} <__tls_get_addr>:
-+ 18000[0-9a-f]{2}:    4e 80 00 20     blr
- 
- Disassembly of section \.no_opt2:
- 
--0+1800098 <\.no_opt2>:
-- 1800098:     38 6d ff f4     addi    r3,r13,-12
-- 180009c:     2c 04 00 00     cmpwi   r4,0
-- 18000a0:     41 82 00 08     beq-    .*
-- 18000a4:     38 6d ff f4     addi    r3,r13,-12
-- 18000a8:     4b ff ff ed     bl      1800094 <__tls_get_addr>
-+0+18000[0-9a-f]{2} <\.no_opt2>:
-+ 18000[0-9a-f]{2}:    38 6d ff f4     addi    r3,r13,-12
-+ 18000[0-9a-f]{2}:    2c 04 00 00     cmpwi   r4,0
-+ 18000[0-9a-f]{2}:    41 82 00 08     beq-    .*
-+ 18000[0-9a-f]{2}:    38 6d ff f4     addi    r3,r13,-12
-+ 18000[0-9a-f]{2}:    4b ff ff ed     bl      18000[0-9a-f]{2} <__tls_get_addr>
- #pass
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt3.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt3.d
-@@ -9,18 +9,18 @@
- 
- Disassembly of section \.text:
- 
--00000000100000e8 <\.__tls_get_addr>:
--    100000e8: 4e 80 00 20     blr
-+0000000010000[0-9a-f]{3} <\.__tls_get_addr>:
-+    10000[0-9a-f]{3}: 4e 80 00 20     blr
- 
- Disassembly of section \.no_opt3:
- 
--00000000100000ec <\.no_opt3>:
--    100000ec: 38 62 80 08     addi    r3,r2,-32760
--    100000f0: 48 00 00 0c     b       .*
--    100000f4: 38 62 80 18     addi    r3,r2,-32744
--    100000f8: 48 00 00 10     b       .*
--    100000fc: 4b ff ff ed     bl      100000e8 <\.__tls_get_addr>
--    10000100: 60 00 00 00     nop
--    10000104: 48 00 00 0c     b       .*
--    10000108: 4b ff ff e1     bl      100000e8 <\.__tls_get_addr>
--    1000010c: 60 00 00 00     nop
-+0000000010000[0-9a-f]{3} <\.no_opt3>:
-+    10000[0-9a-f]{3}: 38 62 80 08     addi    r3,r2,-32760
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       .*
-+    10000[0-9a-f]{3}: 38 62 80 18     addi    r3,r2,-32744
-+    10000[0-9a-f]{3}: 48 00 00 10     b       .*
-+    10000[0-9a-f]{3}: 4b ff ff ed     bl      10000[0-9a-f]{3} <\.__tls_get_addr>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       .*
-+    10000[0-9a-f]{3}: 4b ff ff e1     bl      10000[0-9a-f]{3} <\.__tls_get_addr>
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt3_32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt3_32.d
-@@ -9,17 +9,17 @@
- 
- Disassembly of section \.text:
- 
--0+1800094 <__tls_get_addr>:
-- 1800094:     4e 80 00 20     blr
-+0+18000[0-9a-f]{2} <__tls_get_addr>:
-+ 18000[0-9a-f]{2}:    4e 80 00 20     blr
- 
- Disassembly of section \.no_opt3:
- 
--0+1800098 <\.no_opt3>:
-- 1800098:     38 6d ff ec     addi    r3,r13,-20
-- 180009c:     48 00 00 0c     b       .*
-- 18000a0:     38 6d ff f4     addi    r3,r13,-12
-- 18000a4:     48 00 00 0c     b       .*
-- 18000a8:     4b ff ff ed     bl      1800094 <__tls_get_addr>
-- 18000ac:     48 00 00 08     b       .*
-- 18000b0:     4b ff ff e5     bl      1800094 <__tls_get_addr>
-+0+18000[0-9a-f]{2} <\.no_opt3>:
-+ 18000[0-9a-f]{2}:    38 6d ff ec     addi    r3,r13,-20
-+ 18000[0-9a-f]{2}:    48 00 00 0c     b       .*
-+ 18000[0-9a-f]{2}:    38 6d ff f4     addi    r3,r13,-12
-+ 18000[0-9a-f]{2}:    48 00 00 0c     b       .*
-+ 18000[0-9a-f]{2}:    4b ff ff ed     bl      18000[0-9a-f]{2} <__tls_get_addr>
-+ 18000[0-9a-f]{2}:    48 00 00 08     b       .*
-+ 18000[0-9a-f]{2}:    4b ff ff e5     bl      18000[0-9a-f]{2} <__tls_get_addr>
- #pass
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt4.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt4.d
-@@ -9,40 +9,40 @@
- 
- Disassembly of section \.text:
- 
--0+100000e8 <\.__tls_get_addr>:
--    100000e8: 4e 80 00 20     blr
-+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
-+    10000[0-9a-f]{3}: 4e 80 00 20     blr
- 
- Disassembly of section \.opt1:
- 
--0+100000ec <\.opt1>:
--    100000ec: 3c 6d 00 00     addis   r3,r13,0
--    100000f0: 2c 24 00 00     cmpdi   r4,0
--    100000f4: 41 82 00 10     beq-    .*
--    100000f8: 60 00 00 00     nop
--    100000fc: 38 63 90 10     addi    r3,r3,-28656
--    10000100: 48 00 00 0c     b       .*
--    10000104: 60 00 00 00     nop
--    10000108: 38 63 90 10     addi    r3,r3,-28656
-+0+10000[0-9a-f]{3} <\.opt1>:
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 2c 24 00 00     cmpdi   r4,0
-+    10000[0-9a-f]{3}: 41 82 00 10     beq-    .*
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 10     addi    r3,r3,-28656
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       .*
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 10     addi    r3,r3,-28656
- 
- Disassembly of section \.opt2:
- 
--0+1000010c <\.opt2>:
--    1000010c: 3c 6d 00 00     addis   r3,r13,0
--    10000110: 2c 24 00 00     cmpdi   r4,0
--    10000114: 41 82 00 08     beq-    .*
--    10000118: 3c 6d 00 00     addis   r3,r13,0
--    1000011c: 60 00 00 00     nop
--    10000120: 38 63 90 10     addi    r3,r3,-28656
-+0+10000[0-9a-f]{3} <\.opt2>:
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 2c 24 00 00     cmpdi   r4,0
-+    10000[0-9a-f]{3}: 41 82 00 08     beq-    .*
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 10     addi    r3,r3,-28656
- 
- Disassembly of section \.opt3:
- 
--0+10000124 <\.opt3>:
--    10000124: 3c 6d 00 00     addis   r3,r13,0
--    10000128: 48 00 00 0c     b       .*
--    1000012c: 3c 6d 00 00     addis   r3,r13,0
--    10000130: 48 00 00 10     b       .*
--    10000134: 60 00 00 00     nop
--    10000138: 38 63 90 10     addi    r3,r3,-28656
--    1000013c: 48 00 00 0c     b       .*
--    10000140: 60 00 00 00     nop
--    10000144: 38 63 90 08     addi    r3,r3,-28664
-+0+10000[0-9a-f]{3} <\.opt3>:
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       .*
-+    10000[0-9a-f]{3}: 3c 6d 00 00     addis   r3,r13,0
-+    10000[0-9a-f]{3}: 48 00 00 10     b       .*
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 10     addi    r3,r3,-28656
-+    10000[0-9a-f]{3}: 48 00 00 0c     b       .*
-+    10000[0-9a-f]{3}: 60 00 00 00     nop
-+    10000[0-9a-f]{3}: 38 63 90 08     addi    r3,r3,-28664
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt4_32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsopt4_32.d
-@@ -9,36 +9,36 @@
- 
- Disassembly of section \.text:
- 
--0+1800094 <__tls_get_addr>:
-- 1800094:     4e 80 00 20     blr
-+0+18000[0-9a-f]{2} <__tls_get_addr>:
-+ 18000[0-9a-f]{2}:    4e 80 00 20     blr
- 
- Disassembly of section \.opt1:
- 
--0+1800098 <\.opt1>:
-- 1800098:     3c 62 00 00     addis   r3,r2,0
-- 180009c:     2c 04 00 00     cmpwi   r4,0
-- 18000a0:     41 82 00 0c     beq-    .*
-- 18000a4:     38 63 90 10     addi    r3,r3,-28656
-- 18000a8:     48 00 00 08     b       .*
-- 18000ac:     38 63 90 10     addi    r3,r3,-28656
-+0+18000[0-9a-f]{2} <\.opt1>:
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    2c 04 00 00     cmpwi   r4,0
-+ 18000[0-9a-f]{2}:    41 82 00 0c     beq-    .*
-+ 18000[0-9a-f]{2}:    38 63 90 10     addi    r3,r3,-28656
-+ 18000[0-9a-f]{2}:    48 00 00 08     b       .*
-+ 18000[0-9a-f]{2}:    38 63 90 10     addi    r3,r3,-28656
- 
- Disassembly of section \.opt2:
- 
--0+18000b0 <\.opt2>:
-- 18000b0:     3c 62 00 00     addis   r3,r2,0
-- 18000b4:     2c 04 00 00     cmpwi   r4,0
-- 18000b8:     41 82 00 08     beq-    .*
-- 18000bc:     3c 62 00 00     addis   r3,r2,0
-- 18000c0:     38 63 90 10     addi    r3,r3,-28656
-+0+18000[0-9a-f]{2} <\.opt2>:
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    2c 04 00 00     cmpwi   r4,0
-+ 18000[0-9a-f]{2}:    41 82 00 08     beq-    .*
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    38 63 90 10     addi    r3,r3,-28656
- 
- Disassembly of section \.opt3:
- 
--0+18000c4 <\.opt3>:
-- 18000c4:     3c 62 00 00     addis   r3,r2,0
-- 18000c8:     48 00 00 0c     b       .*
-- 18000cc:     3c 62 00 00     addis   r3,r2,0
-- 18000d0:     48 00 00 0c     b       .*
-- 18000d4:     38 63 90 10     addi    r3,r3,-28656
-- 18000d8:     48 00 00 08     b       .*
-- 18000dc:     38 63 90 08     addi    r3,r3,-28664
-+0+18000[0-9a-f]{2} <\.opt3>:
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    48 00 00 0c     b       .*
-+ 18000[0-9a-f]{2}:    3c 62 00 00     addis   r3,r2,0
-+ 18000[0-9a-f]{2}:    48 00 00 0c     b       .*
-+ 18000[0-9a-f]{2}:    38 63 90 10     addi    r3,r3,-28656
-+ 18000[0-9a-f]{2}:    48 00 00 08     b       .*
-+ 18000[0-9a-f]{2}:    38 63 90 08     addi    r3,r3,-28664
- #pass
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsso32.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsso32.d
-@@ -42,5 +42,5 @@ Disassembly of section \.got:
- #...
- .*:   4e 80 00 21     blrl
- .* <_GLOBAL_OFFSET_TABLE_>:
--.*:   00 01 03 ec .*
-+.*:   00 01 [0-9a-f]{2} [0-9a-f]{2} .*
- #pass
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsso32.g
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsso32.g
-@@ -9,5 +9,5 @@
- Contents of section \.got:
- .* 00000000 00000000 00000000 00000000  .*
- .* 00000000 00000000 00000000 00000000  .*
--.* 00000000 4e800021 000103ec 00000000  .*
-+.* 00000000 4e800021 00010[0-9a-f]{3} 00000000  .*
- .* 00000000                             .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsso32.r
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlsso32.r
+--- binutils-2.23.51.0.5/ld/testsuite/ld-powerpc/tlsso32.r
++++ binutils-2.23.51.0.5/ld/testsuite/ld-powerpc/tlsso32.r
 @@ -35,6 +35,7 @@ Program Headers:
   +LOAD .* RWE 0x10000
   +DYNAMIC .* RW +0x4
@@ -1481,49 +853,8 @@
  [0-9a-f ]+R_PPC_DTPMOD32 +0
  [0-9a-f ]+R_PPC_DTPREL32 +0
  [0-9a-f ]+R_PPC_DTPMOD32 +0
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlstoc.g
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlstoc.g
-@@ -8,8 +8,8 @@
- .*: +file format elf64-powerpc
- 
- Contents of section \.got:
-- 100101a0 00000000 00000001 00000000 00000000  .*
-- 100101b0 00000000 00000001 00000000 00000000  .*
-- 100101c0 00000000 00000001 00000000 00000000  .*
-- 100101d0 00000000 00000001 00000000 00000000  .*
-- 100101e0 ffffffff ffff8060 00000000 00000000  .*
-+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000  .*
-+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000  .*
-+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000  .*
-+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000  .*
-+ 10010[0-9a-f]{3} ffffffff ffff8060 00000000 00000000  .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlstoc.t
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlstoc.t
-@@ -8,7 +8,7 @@
- .*: +file format elf64-powerpc
- 
- Contents of section \.tdata:
-- 10010148 00c0ffee 00000000 12345678 9abcdef0  .*
-- 10010158 23456789 abcdef01 3456789a bcdef012  .*
-- 10010168 456789ab cdef0123 56789abc def01234  .*
-- 10010178 6789abcd ef012345 789abcde f0123456  .*
-+ 10010180 00c0ffee 00000000 12345678 9abcdef0  .*
-+ 10010190 23456789 abcdef01 3456789a bcdef012  .*
-+ 100101a0 456789ab cdef0123 56789abc def01234  .*
-+ 100101b0 6789abcd ef012345 789abcde f0123456  .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlstocso.g
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-powerpc/tlstocso.g
-@@ -7,7 +7,7 @@
- .*: +file format elf64-powerpc
- 
- Contents of section \.got:
--.* 00000000 000186c0 00000000 00000000  .*
-+.* 00000000 000186f8 00000000 00000000  .*
- .* 00000000 00000000 00000000 00000000  .*
- .* 00000000 00000000 00000000 00000000  .*
- .* 00000000 00000000 00000000 00000000  .*
---- binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlsbin.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlsbin.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlsbin.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlsbin.rd
 @@ -36,6 +36,7 @@ There are [0-9]+ program headers, starting at offset [0-9]+
   +LOAD .* RW +0x1000
   +DYNAMIC .* RW +0x4
@@ -1540,8 +871,8 @@
  
  Relocation section '.rela.dyn' at offset .* contains 4 entries:
   Offset +Info +Type +Sym.Value +Sym. Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlsbin_64.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlsbin_64.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlsbin_64.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlsbin_64.rd
 @@ -36,6 +36,7 @@ There are [0-9]+ program headers, starting at offset [0-9]+
   +LOAD .* RW +0x1000
   +DYNAMIC .* RW +0x8
@@ -1558,8 +889,8 @@
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
   +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlspic.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlspic.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlspic.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlspic.rd
 @@ -39,6 +39,7 @@ Program Headers:
   +LOAD .* RW +0x1000
   +DYNAMIC .* RW +0x4
@@ -1576,8 +907,8 @@
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
   Offset +Info +Type +Sym.Value +Sym. Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlspic_64.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-s390/tlspic_64.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlspic_64.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-s390/tlspic_64.rd
 @@ -39,6 +39,7 @@ Program Headers:
   +LOAD .* RW +0x1000
   +DYNAMIC .* RW +0x8
@@ -1594,20 +925,8 @@
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
   +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-scripts/empty-aligned.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-scripts/empty-aligned.d
-@@ -8,7 +8,9 @@
- Program Headers:
-  +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg +Align
-  +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ [RWE ]+ +0x[0-9a-f]+
-+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
- 
-  Section to Segment mapping:
-  +Segment Sections\.\.\.
-  +00 +.text 
-+ +01 +
---- binutils-2.23.51.0.2/ld/testsuite/ld-sh/tlsbin-2.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sh/tlsbin-2.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sh/tlsbin-2.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sh/tlsbin-2.d
 @@ -44,6 +44,7 @@ Program Headers:
   +LOAD.*
   +DYNAMIC.*
@@ -1624,8 +943,8 @@
  
  Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
   Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-sh/tlspic-2.d
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sh/tlspic-2.d
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sh/tlspic-2.d
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sh/tlspic-2.d
 @@ -32,7 +32,7 @@ Key to Flags:
  
  Elf file type is DYN \(Shared object file\)
@@ -1651,8 +970,8 @@
  
  Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 10 entries:
   Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/gotop32.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/gotop32.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/gotop32.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/gotop32.rd
 @@ -31,6 +31,7 @@ Program Headers:
   +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x10000
   +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+2000 0x0+2000 RW +0x10000
@@ -1661,8 +980,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/gotop64.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/gotop64.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/gotop64.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/gotop64.rd
 @@ -31,6 +31,7 @@ Program Headers:
   +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x100000
   +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+2000 0x0+2000 RW +0x100000
@@ -1671,8 +990,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunbin32.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunbin32.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunbin32.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunbin32.rd
 @@ -30,13 +30,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
  
  Program Headers:
@@ -1690,8 +1009,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunbin64.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunbin64.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunbin64.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunbin64.rd
 @@ -30,13 +30,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
  
  Program Headers:
@@ -1709,8 +1028,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunnopic32.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunnopic32.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunnopic32.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunnopic32.rd
 @@ -32,6 +32,7 @@ Program Headers:
   +LOAD .* RW +0x10000
   +DYNAMIC .* RW +0x4
@@ -1719,8 +1038,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 12 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunnopic64.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunnopic64.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunnopic64.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunnopic64.rd
 @@ -32,6 +32,7 @@ Program Headers:
   +LOAD .* RW +0x100000
   +DYNAMIC .* RW +0x8
@@ -1729,8 +1048,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunpic32.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunpic32.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunpic32.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunpic32.rd
 @@ -36,6 +36,7 @@ Program Headers:
   +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+184 0x0+184 RWE 0x10000
   +DYNAMIC +0x0+2060 0x0+12060 0x0+12060 0x0+98 0x0+98 RW +0x4
@@ -1739,8 +1058,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunpic64.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-sparc/tlssunpic64.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunpic64.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-sparc/tlssunpic64.rd
 @@ -36,6 +36,7 @@ Program Headers:
   +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+3a0 0x0+3a0 RWE 0x100000
   +DYNAMIC +0x0+2060 0x0+102060 0x0+102060 0x0+130 0x0+130 RW +0x8
@@ -1749,8 +1068,8 @@
  #...
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
---- binutils-2.23.51.0.2/ld/testsuite/ld-x86-64/tlsgdesc.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-x86-64/tlsgdesc.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-x86-64/tlsgdesc.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-x86-64/tlsgdesc.rd
 @@ -36,12 +36,14 @@ Program Headers:
   +LOAD.*
   +LOAD.*
@@ -1766,8 +1085,8 @@
  
  Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
   +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
---- binutils-2.23.51.0.2/ld/testsuite/ld-x86-64/tlspic.rd
-+++ binutils-2.23.51.0.2/ld/testsuite/ld-x86-64/tlspic.rd
+--- binutils-2.23.51.0.5/ld/testsuite/ld-x86-64/tlspic.rd
++++ binutils-2.23.51.0.5/ld/testsuite/ld-x86-64/tlspic.rd
 @@ -40,6 +40,7 @@ Program Headers:
   +LOAD +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+244 0x0+244 RW +0x200000
   +DYNAMIC +0x0+1210 0x0+201210 0x0+201210 0x0+130 0x0+130 RW +0x8

diff --git a/binutils/patches/binutils-default-test-flags.patch b/binutils/patches/binutils-default-test-flags.patch
new file mode 100644 (file)
index 0000000..8870fab
--- /dev/null
+++ b/binutils/patches/binutils-default-test-flags.patch
@@ -0,0 +1,35 @@
+many tests rely on order of symbols and the gnu hash style/relro options
+change that.  so to avoid having to constantly thrash in the test files,
+use the normal options that everyone tests against.
+
+--- binutils/ld/testsuite/lib/ld-lib.exp
++++ binutils/ld/testsuite/lib/ld-lib.exp
+@@ -84,7 +84,7 @@
+     global HOSTING_EMU
+ 
+     remote_file host delete $target
+-    return [run_host_cmd_yesno "$ld" "$HOSTING_EMU -o $target -r $objects"]
++    return [run_host_cmd_yesno "$ld" "$HOSTING_EMU --hash-style=sysv -z norelro -o $target -r $objects"]
+ }
+ 
+ # Check to see if ld is being invoked with a non-endian output format
+@@ -158,7 +158,7 @@
+ 
+     remote_file host delete $target
+ 
+-    return [run_host_cmd_yesno "$ld" "$HOSTING_EMU $flags -o $target $objs $libs"]
++    return [run_host_cmd_yesno "$ld" "$HOSTING_EMU --hash-style=sysv -z norelro $flags -o $target $objs $libs"]
+ }
+ 
+ # Link a program using ld, without including any libraries.
+@@ -189,7 +189,9 @@
+     }
+     set ldexe [string replace $ldexe 0 [string last "/" $ldexe] ""]
+     if {[string match "*gcc*" $ldexe] || [string match "*++*" $ldexe]} then {
+-      set ldflags "$gcc_ld_flag $ldflags"
++      set ldflags "$gcc_ld_flag -Wl,--hash-style=sysv -Wl,-z,norelro $ldflags"
++    } else {
++      set ldflags "--hash-style=sysv -z norelro $ldflags"
+     }
+ 
+     remote_file host delete $target

diff --git a/binutils/patches/binutils-use-new-ld-dtags.patch b/binutils/patches/binutils-use-new-ld-dtags.patch
new file mode 100644 (file)
index 0000000..e738897
--- /dev/null
+++ b/binutils/patches/binutils-use-new-ld-dtags.patch
@@ -0,0 +1,24 @@
+--- binutils/ld/ldmain.c
++++ binutils/ld/ldmain.c
+@@ -296,6 +296,7 @@ main (int argc, char **argv)
+ 
+   link_info.allow_undefined_version = TRUE;
+   link_info.keep_memory = TRUE;
++  link_info.new_dtags = TRUE;
+   link_info.combreloc = TRUE;
+   link_info.strip_discarded = TRUE;
+   link_info.callbacks = &link_callbacks;
+--- binutils/ld/ld.texinfo
++++ binutils/ld/ld.texinfo
+@@ -2036,8 +2036,9 @@
+ systems may not understand them. If you specify
+ @option{--enable-new-dtags}, the dynamic tags will be created as needed.
+ If you specify @option{--disable-new-dtags}, no new dynamic tags will be
+-created. By default, the new dynamic tags are not created. Note that
+-those options are only available for ELF systems.
++created. On Gentoo, by default, the new dynamic tags are created (this
++differs from upstream behaviour). Note that those options are only
++available for ELF systems.
+ 
+ @kindex --hash-size=@var{number}
+ @item --hash-size=@var{number}