arch/ppc/kernel/cpu_setup_power4.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <linux/config.h>
  13 #include <asm/processor.h>
  14 #include <asm/page.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/cputable.h>
  17 #include <asm/ppc_asm.h>
  18 #include <asm/offsets.h>
  19 #include <asm/cache.h>
  20
  21 _GLOBAL(__970_cpu_preinit)
  22         /*
  23          * Deal only with PPC970 and PPC970FX.
  24          */
  25         mfspr   r0,SPRN_PVR
  26         srwi    r0,r0,16
  27         cmpwi   cr0,r0,0x39
  28         cmpwi   cr1,r0,0x3c
  29         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
  30         bnelr
  31
  32         /* Make sure HID4:rm_ci is off before MMU is turned off, that large
  33          * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
  34          * HID5:DCBZ32_ill
  35          */
  36         li      r0,0
  37         mfspr   r11,SPRN_HID4
  38         rldimi  r11,r0,40,23    /* clear bit 23 (rm_ci) */
  39         rldimi  r11,r0,2,61     /* clear bit 61 (lg_pg_en) */
  40         sync
  41         mtspr   SPRN_HID4,r11
  42         isync
  43         sync
  44         mfspr   r11,SPRN_HID5
  45         rldimi  r11,r0,6,56     /* clear bits 56 & 57 (DCBZ*) */
  46         sync
  47         mtspr   SPRN_HID5,r11
  48         isync
  49         sync
  50
  51         /* Setup some basic HID1 features */
  52         mfspr   r0,SPRN_HID1
  53         li      r11,0x1200              /* enable i-fetch cacheability */
  54         sldi    r11,r11,44              /* and prefetch */
  55         or      r0,r0,r11
  56         mtspr   SPRN_HID1,r0
  57         mtspr   SPRN_HID1,r0
  58         isync
  59
  60         /* Clear HIOR */
  61         li      r0,0
  62         sync
  63         mtspr   SPRN_HIOR,0             /* Clear interrupt prefix */
  64         isync
  65         blr
  66
  67 _GLOBAL(__setup_cpu_power4)
  68         blr
  69 _GLOBAL(__setup_cpu_ppc970)
  70         mfspr   r0,SPRN_HID0
  71         li      r11,5                   /* clear DOZE and SLEEP */
  72         rldimi  r0,r11,52,8             /* set NAP and DPM */
  73         mtspr   SPRN_HID0,r0
  74         mfspr   r0,SPRN_HID0
  75         mfspr   r0,SPRN_HID0
  76         mfspr   r0,SPRN_HID0
  77         mfspr   r0,SPRN_HID0
  78         mfspr   r0,SPRN_HID0
  79         mfspr   r0,SPRN_HID0
  80         sync
  81         isync
  82         blr
  83
  84 /* Definitions for the table use to save CPU states */
  85 #define CS_HID0         0
  86 #define CS_HID1         8
  87 #define CS_HID4         16
  88 #define CS_HID5         24
  89 #define CS_SIZE         32
  90
  91         .data
  92         .balign L1_CACHE_LINE_SIZE
  93 cpu_state_storage:
  94         .space  CS_SIZE
  95         .balign L1_CACHE_LINE_SIZE,0
  96         .text
  97
  98 /* Called in normal context to backup CPU 0 state. This
  99  * does not include cache settings. This function is also
 100  * called for machine sleep. This does not include the MMU
 101  * setup, BATs, etc... but rather the "special" registers
 102  * like HID0, HID1, HID4, etc...
 103  */
 104 _GLOBAL(__save_cpu_setup)
 105         /* Some CR fields are volatile, we back it up all */
 106         mfcr    r7
 107
 108         /* Get storage ptr */
 109         lis     r5,cpu_state_storage@h
 110         ori     r5,r5,cpu_state_storage@l
 111
 112         /* We only deal with 970 for now */
 113         mfspr   r0,SPRN_PVR
 114         srwi    r0,r0,16
 115         cmpwi   cr0,r0,0x39
 116         cmpwi   cr1,r0,0x3c
 117         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 118         bne     1f
 119
 120         /* Save HID0,1,4 and 5 */
 121         mfspr   r3,SPRN_HID0
 122         std     r3,CS_HID0(r5)
 123         mfspr   r3,SPRN_HID1
 124         std     r3,CS_HID1(r5)
 125         mfspr   r3,SPRN_HID4
 126         std     r3,CS_HID4(r5)
 127         mfspr   r3,SPRN_HID5
 128         std     r3,CS_HID5(r5)
 129
 130 1:
 131         mtcr    r7
 132         blr
 133
 134 /* Called with no MMU context (typically MSR:IR/DR off) to
 135  * restore CPU state as backed up by the previous
 136  * function. This does not include cache setting
 137  */
 138 _GLOBAL(__restore_cpu_setup)
 139         /* Some CR fields are volatile, we back it up all */
 140         mfcr    r7
 141
 142         /* Get storage ptr */
 143         lis     r5,(cpu_state_storage-KERNELBASE)@h
 144         ori     r5,r5,cpu_state_storage@l
 145
 146         /* We only deal with 970 for now */
 147         mfspr   r0,SPRN_PVR
 148         srwi    r0,r0,16
 149         cmpwi   cr0,r0,0x39
 150         cmpwi   cr1,r0,0x3c
 151         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 152         bne     1f
 153
 154         /* Clear interrupt prefix */
 155         li      r0,0
 156         sync
 157         mtspr   SPRN_HIOR,0
 158         isync
 159
 160         /* Restore HID0 */
 161         ld      r3,CS_HID0(r5)
 162         sync
 163         isync
 164         mtspr   SPRN_HID0,r3
 165         mfspr   r3,SPRN_HID0
 166         mfspr   r3,SPRN_HID0
 167         mfspr   r3,SPRN_HID0
 168         mfspr   r3,SPRN_HID0
 169         mfspr   r3,SPRN_HID0
 170         mfspr   r3,SPRN_HID0
 171         sync
 172         isync
 173
 174         /* Restore HID1 */
 175         ld      r3,CS_HID1(r5)
 176         sync
 177         isync
 178         mtspr   SPRN_HID1,r3
 179         mtspr   SPRN_HID1,r3
 180         sync
 181         isync
 182
 183         /* Restore HID4 */
 184         ld      r3,CS_HID4(r5)
 185         sync
 186         isync
 187         mtspr   SPRN_HID4,r3
 188         sync
 189         isync
 190
 191         /* Restore HID5 */
 192         ld      r3,CS_HID5(r5)
 193         sync
 194         isync
 195         mtspr   SPRN_HID5,r3
 196         sync
 197         isync
 198 1:
 199         mtcr    r7
 200         blr
 201