1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
10 #include <linux/refcount.h>
11 #include <linux/uaccess.h>
13 #include <drm/drm_atomic.h>
14 #include <drm/drm_debugfs.h>
15 #include <drm/drm_device.h>
16 #include <drm/drm_encoder.h>
17 #include <drm/drm_gem_cma_helper.h>
18 #include <drm/drm_managed.h>
19 #include <drm/drm_mm.h>
20 #include <drm/drm_modeset_lock.h>
22 #include "uapi/drm/vc4_drm.h"
25 struct drm_gem_object
;
27 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
30 enum vc4_kernel_bo_type
{
31 /* Any kernel allocation (gem_create_object hook) before it
32 * gets another type set.
36 VC4_BO_TYPE_V3D_SHADER
,
41 VC4_BO_TYPE_KERNEL_CACHE
,
45 /* Performance monitor object. The perform lifetime is controlled by userspace
46 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
47 * request, and when this is the case, HW perf counters will be activated just
48 * before the submit_cl is submitted to the GPU and disabled when the job is
49 * done. This way, only events related to a specific job will be counted.
54 /* Tracks the number of users of the perfmon, when this counter reaches
55 * zero the perfmon is destroyed.
59 /* Number of counters activated in this perfmon instance
60 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
64 /* Events counted by the HW perf counters. */
65 u8 events
[DRM_VC4_MAX_PERF_COUNTERS
];
67 /* Storage for counter values. Counters are incremented by the HW
68 * perf counter values every time the perfmon is attached to a GPU job.
69 * This way, perfmon users don't have to retrieve the results after
70 * each job if they want to track events covering several submissions.
71 * Note that counter values can't be reset, but you can fake a reset by
72 * destroying the perfmon and creating a new one.
78 struct drm_device base
;
90 struct vc4_hang_state
*hang_state
;
92 /* The kernel-space BO cache. Tracks buffers that have been
93 * unreferenced by all other users (refcounts of 0!) but not
94 * yet freed, so we can do cheap allocations.
97 /* Array of list heads for entries in the BO cache,
98 * based on number of pages, so we can do O(1) lookups
99 * in the cache when allocating.
101 struct list_head
*size_list
;
102 uint32_t size_list_size
;
104 /* List of all BOs in the cache, ordered by age, so we
105 * can do O(1) lookups when trying to free old
108 struct list_head time_list
;
109 struct work_struct time_work
;
110 struct timer_list time_timer
;
120 /* Protects bo_cache and bo_labels. */
121 struct mutex bo_lock
;
123 /* Purgeable BO pool. All BOs in this pool can have their memory
124 * reclaimed if the driver is unable to allocate new BOs. We also
125 * keep stats related to the purge mechanism here.
128 struct list_head list
;
131 unsigned int purged_num
;
136 uint64_t dma_fence_context
;
138 /* Sequence number for the last job queued in bin_job_list.
139 * Starts at 0 (no jobs emitted).
143 /* Sequence number for the last completed job on the GPU.
144 * Starts at 0 (no jobs completed).
146 uint64_t finished_seqno
;
148 /* List of all struct vc4_exec_info for jobs to be executed in
149 * the binner. The first job in the list is the one currently
150 * programmed into ct0ca for execution.
152 struct list_head bin_job_list
;
154 /* List of all struct vc4_exec_info for jobs that have
155 * completed binning and are ready for rendering. The first
156 * job in the list is the one currently programmed into ct1ca
159 struct list_head render_job_list
;
161 /* List of the finished vc4_exec_infos waiting to be freed by
164 struct list_head job_done_list
;
165 /* Spinlock used to synchronize the job_list and seqno
166 * accesses between the IRQ handler and GEM ioctls.
169 wait_queue_head_t job_wait_queue
;
170 struct work_struct job_done_work
;
172 /* Used to track the active perfmon if any. Access to this field is
173 * protected by job_lock.
175 struct vc4_perfmon
*active_perfmon
;
177 /* List of struct vc4_seqno_cb for callbacks to be made from a
178 * workqueue when the given seqno is passed.
180 struct list_head seqno_cb_list
;
182 /* The memory used for storing binner tile alloc, tile state,
183 * and overflow memory allocations. This is freed when V3D
186 struct vc4_bo
*bin_bo
;
188 /* Size of blocks allocated within bin_bo. */
189 uint32_t bin_alloc_size
;
191 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
194 uint32_t bin_alloc_used
;
196 /* Bitmask of the current bin_alloc used for overflow memory. */
197 uint32_t bin_alloc_overflow
;
199 /* Incremented when an underrun error happened after an atomic commit.
200 * This is particularly useful to detect when a specific modeset is too
201 * demanding in term of memory or HVS bandwidth which is hard to guess
202 * at atomic check time.
206 struct work_struct overflow_mem_work
;
210 /* Set to true when the load tracker is active. */
211 bool load_tracker_enabled
;
213 /* Mutex controlling the power refcount. */
214 struct mutex power_lock
;
217 struct timer_list timer
;
218 struct work_struct reset_work
;
221 struct drm_modeset_lock ctm_state_lock
;
222 struct drm_private_obj ctm_manager
;
223 struct drm_private_obj hvs_channels
;
224 struct drm_private_obj load_tracker
;
226 /* List of vc4_debugfs_info_entry for adding to debugfs once
227 * the minor is available (after drm_dev_register()).
229 struct list_head debugfs_list
;
231 /* Mutex for binner bo allocation. */
232 struct mutex bin_bo_lock
;
233 /* Reference count for our binner bo. */
234 struct kref bin_bo_kref
;
237 static inline struct vc4_dev
*
238 to_vc4_dev(struct drm_device
*dev
)
240 return container_of(dev
, struct vc4_dev
, base
);
244 struct drm_gem_cma_object base
;
246 /* seqno of the last job to render using this BO. */
249 /* seqno of the last job to use the RCL to write to this BO.
251 * Note that this doesn't include binner overflow memory
254 uint64_t write_seqno
;
258 /* List entry for the BO's position in either
259 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
261 struct list_head unref_head
;
263 /* Time in jiffies when the BO was put in vc4->bo_cache. */
264 unsigned long free_time
;
266 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
267 struct list_head size_head
;
269 /* Struct for shader validation state, if created by
270 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
272 struct vc4_validated_shader_info
*validated_shader
;
274 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
275 * for user-allocated labels.
279 /* Count the number of active users. This is needed to determine
280 * whether we can move the BO to the purgeable list or not (when the BO
281 * is used by the GPU or the display engine we can't purge it).
285 /* Store purgeable/purged state here */
287 struct mutex madv_lock
;
290 static inline struct vc4_bo
*
291 to_vc4_bo(struct drm_gem_object
*bo
)
293 return container_of(to_drm_gem_cma_obj(bo
), struct vc4_bo
, base
);
297 struct dma_fence base
;
298 struct drm_device
*dev
;
299 /* vc4 seqno for signaled() test */
303 static inline struct vc4_fence
*
304 to_vc4_fence(struct dma_fence
*fence
)
306 return container_of(fence
, struct vc4_fence
, base
);
309 struct vc4_seqno_cb
{
310 struct work_struct work
;
312 void (*func
)(struct vc4_seqno_cb
*cb
);
317 struct platform_device
*pdev
;
320 struct debugfs_regset32 regset
;
325 struct platform_device
*pdev
;
329 struct clk
*core_clk
;
331 /* Memory manager for CRTCs to allocate space in the display
332 * list. Units are dwords.
334 struct drm_mm dlist_mm
;
335 /* Memory manager for the LBM memory used by HVS scaling. */
336 struct drm_mm lbm_mm
;
339 struct drm_mm_node mitchell_netravali_filter
;
341 struct debugfs_regset32 regset
;
345 struct drm_plane base
;
348 static inline struct vc4_plane
*
349 to_vc4_plane(struct drm_plane
*plane
)
351 return container_of(plane
, struct vc4_plane
, base
);
354 enum vc4_scaling_mode
{
360 struct vc4_plane_state
{
361 struct drm_plane_state base
;
362 /* System memory copy of the display list for this element, computed
363 * at atomic_check time.
366 u32 dlist_size
; /* Number of dwords allocated for the display list */
367 u32 dlist_count
; /* Number of used dwords in the display list. */
369 /* Offset in the dlist to various words, for pageflip or
377 /* Offset where the plane's dlist was last stored in the
378 * hardware at vc4_crtc_atomic_flush() time.
380 u32 __iomem
*hw_dlist
;
382 /* Clipped coordinates of the plane on the display. */
383 int crtc_x
, crtc_y
, crtc_w
, crtc_h
;
384 /* Clipped area being scanned from in the FB. */
387 u32 src_w
[2], src_h
[2];
389 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
390 enum vc4_scaling_mode x_scaling
[2], y_scaling
[2];
394 /* Offset to start scanning out from the start of the plane's
399 /* Our allocation in LBM for temporary storage during scaling. */
400 struct drm_mm_node lbm
;
402 /* Set when the plane has per-pixel alpha content or does not cover
403 * the entire screen. This is a hint to the CRTC that it might need
404 * to enable background color fill.
408 /* Mark the dlist as initialized. Useful to avoid initializing it twice
409 * when async update is not possible.
411 bool dlist_initialized
;
413 /* Load of this plane on the HVS block. The load is expressed in HVS
418 /* Memory bandwidth needed for this plane. This is expressed in
424 static inline struct vc4_plane_state
*
425 to_vc4_plane_state(struct drm_plane_state
*state
)
427 return container_of(state
, struct vc4_plane_state
, base
);
430 enum vc4_encoder_type
{
431 VC4_ENCODER_TYPE_NONE
,
432 VC4_ENCODER_TYPE_HDMI0
,
433 VC4_ENCODER_TYPE_HDMI1
,
434 VC4_ENCODER_TYPE_VEC
,
435 VC4_ENCODER_TYPE_DSI0
,
436 VC4_ENCODER_TYPE_DSI1
,
437 VC4_ENCODER_TYPE_SMI
,
438 VC4_ENCODER_TYPE_DPI
,
442 struct drm_encoder base
;
443 enum vc4_encoder_type type
;
446 void (*pre_crtc_configure
)(struct drm_encoder
*encoder
, struct drm_atomic_state
*state
);
447 void (*pre_crtc_enable
)(struct drm_encoder
*encoder
, struct drm_atomic_state
*state
);
448 void (*post_crtc_enable
)(struct drm_encoder
*encoder
, struct drm_atomic_state
*state
);
450 void (*post_crtc_disable
)(struct drm_encoder
*encoder
, struct drm_atomic_state
*state
);
451 void (*post_crtc_powerdown
)(struct drm_encoder
*encoder
, struct drm_atomic_state
*state
);
454 static inline struct vc4_encoder
*
455 to_vc4_encoder(struct drm_encoder
*encoder
)
457 return container_of(encoder
, struct vc4_encoder
, base
);
460 struct vc4_crtc_data
{
461 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
462 unsigned int hvs_available_channels
;
464 /* Which output of the HVS this pixelvalve sources from. */
469 struct vc4_crtc_data base
;
471 /* Depth of the PixelValve FIFO in bytes */
472 unsigned int fifo_depth
;
474 /* Number of pixels output per clock period */
477 enum vc4_encoder_type encoder_types
[4];
478 const char *debugfs_name
;
483 struct drm_crtc base
;
484 struct platform_device
*pdev
;
485 const struct vc4_crtc_data
*data
;
488 /* Timestamp at start of vblank irq - unaffected by lock delays. */
495 struct drm_pending_vblank_event
*event
;
497 struct debugfs_regset32 regset
;
500 * @feeds_txp: True if the CRTC feeds our writeback controller.
505 * @irq_lock: Spinlock protecting the resources shared between
506 * the atomic code and our vblank handler.
511 * @current_dlist: Start offset of the display list currently
512 * set in the HVS for that CRTC. Protected by @irq_lock, and
513 * copied in vc4_hvs_update_dlist() for the CRTC interrupt
514 * handler to have access to that value.
516 unsigned int current_dlist
;
519 * @current_hvs_channel: HVS channel currently assigned to the
520 * CRTC. Protected by @irq_lock, and copied in
521 * vc4_hvs_atomic_begin() for the CRTC interrupt handler to have
522 * access to that value.
524 unsigned int current_hvs_channel
;
527 static inline struct vc4_crtc
*
528 to_vc4_crtc(struct drm_crtc
*crtc
)
530 return container_of(crtc
, struct vc4_crtc
, base
);
533 static inline const struct vc4_crtc_data
*
534 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc
*crtc
)
539 static inline const struct vc4_pv_data
*
540 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc
*crtc
)
542 const struct vc4_crtc_data
*data
= vc4_crtc_to_vc4_crtc_data(crtc
);
544 return container_of(data
, struct vc4_pv_data
, base
);
547 struct drm_encoder
*vc4_get_crtc_encoder(struct drm_crtc
*crtc
,
548 struct drm_crtc_state
*state
);
550 struct vc4_crtc_state
{
551 struct drm_crtc_state base
;
552 /* Dlist area for this CRTC configuration. */
553 struct drm_mm_node mm
;
555 unsigned int assigned_channel
;
564 unsigned long hvs_load
;
566 /* Transitional state below, only valid during atomic commits */
570 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
572 static inline struct vc4_crtc_state
*
573 to_vc4_crtc_state(struct drm_crtc_state
*crtc_state
)
575 return container_of(crtc_state
, struct vc4_crtc_state
, base
);
578 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
579 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
580 #define HVS_READ(offset) readl(hvs->regs + offset)
581 #define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
583 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
585 struct vc4_exec_info
{
588 /* Sequence number for this bin/render job. */
591 /* Latest write_seqno of any BO that binning depends on. */
592 uint64_t bin_dep_seqno
;
594 struct dma_fence
*fence
;
596 /* Last current addresses the hardware was processing when the
597 * hangcheck timer checked on us.
599 uint32_t last_ct0ca
, last_ct1ca
;
601 /* Kernel-space copy of the ioctl arguments */
602 struct drm_vc4_submit_cl
*args
;
604 /* This is the array of BOs that were looked up at the start of exec.
605 * Command validation will use indices into this array.
607 struct drm_gem_cma_object
**bo
;
610 /* List of BOs that are being written by the RCL. Other than
611 * the binner temporary storage, this is all the BOs written
614 struct drm_gem_cma_object
*rcl_write_bo
[4];
615 uint32_t rcl_write_bo_count
;
617 /* Pointers for our position in vc4->job_list */
618 struct list_head head
;
620 /* List of other BOs used in the job that need to be released
621 * once the job is complete.
623 struct list_head unref_list
;
625 /* Current unvalidated indices into @bo loaded by the non-hardware
626 * VC4_PACKET_GEM_HANDLES.
628 uint32_t bo_index
[2];
630 /* This is the BO where we store the validated command lists, shader
631 * records, and uniforms.
633 struct drm_gem_cma_object
*exec_bo
;
636 * This tracks the per-shader-record state (packet 64) that
637 * determines the length of the shader record and the offset
638 * it's expected to be found at. It gets read in from the
641 struct vc4_shader_state
{
643 /* Maximum vertex index referenced by any primitive using this
649 /** How many shader states the user declared they were using. */
650 uint32_t shader_state_size
;
651 /** How many shader state records the validator has seen. */
652 uint32_t shader_state_count
;
654 bool found_tile_binning_mode_config_packet
;
655 bool found_start_tile_binning_packet
;
656 bool found_increment_semaphore_packet
;
658 uint8_t bin_tiles_x
, bin_tiles_y
;
659 /* Physical address of the start of the tile alloc array
660 * (where each tile's binned CL will start)
662 uint32_t tile_alloc_offset
;
663 /* Bitmask of which binner slots are freed when this job completes. */
667 * Computed addresses pointing into exec_bo where we start the
668 * bin thread (ct0) and render thread (ct1).
670 uint32_t ct0ca
, ct0ea
;
671 uint32_t ct1ca
, ct1ea
;
673 /* Pointer to the unvalidated bin CL (if present). */
676 /* Pointers to the shader recs. These paddr gets incremented as CL
677 * packets are relocated in validate_gl_shader_state, and the vaddrs
678 * (u and v) get incremented and size decremented as the shader recs
679 * themselves are validated.
683 uint32_t shader_rec_p
;
684 uint32_t shader_rec_size
;
686 /* Pointers to the uniform data. These pointers are incremented, and
687 * size decremented, as each batch of uniforms is uploaded.
692 uint32_t uniforms_size
;
694 /* Pointer to a performance monitor object if the user requested it,
697 struct vc4_perfmon
*perfmon
;
699 /* Whether the exec has taken a reference to the binner BO, which should
700 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
705 /* Per-open file private data. Any driver-specific resource that has to be
706 * released when the DRM file is closed should be placed here.
719 static inline struct vc4_exec_info
*
720 vc4_first_bin_job(struct vc4_dev
*vc4
)
722 return list_first_entry_or_null(&vc4
->bin_job_list
,
723 struct vc4_exec_info
, head
);
726 static inline struct vc4_exec_info
*
727 vc4_first_render_job(struct vc4_dev
*vc4
)
729 return list_first_entry_or_null(&vc4
->render_job_list
,
730 struct vc4_exec_info
, head
);
733 static inline struct vc4_exec_info
*
734 vc4_last_render_job(struct vc4_dev
*vc4
)
736 if (list_empty(&vc4
->render_job_list
))
738 return list_last_entry(&vc4
->render_job_list
,
739 struct vc4_exec_info
, head
);
743 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
746 * This will be used at draw time to relocate the reference to the texture
747 * contents in p0, and validate that the offset combined with
748 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
749 * Note that the hardware treats unprovided config parameters as 0, so not all
750 * of them need to be set up for every texure sample, and we'll store ~0 as
751 * the offset to mark the unused ones.
753 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
754 * Setup") for definitions of the texture parameters.
756 struct vc4_texture_sample_info
{
758 uint32_t p_offset
[4];
762 * struct vc4_validated_shader_info - information about validated shaders that
763 * needs to be used from command list validation.
765 * For a given shader, each time a shader state record references it, we need
766 * to verify that the shader doesn't read more uniforms than the shader state
767 * record's uniform BO pointer can provide, and we need to apply relocations
768 * and validate the shader state record's uniforms that define the texture
771 struct vc4_validated_shader_info
{
772 uint32_t uniforms_size
;
773 uint32_t uniforms_src_size
;
774 uint32_t num_texture_samples
;
775 struct vc4_texture_sample_info
*texture_samples
;
777 uint32_t num_uniform_addr_offsets
;
778 uint32_t *uniform_addr_offsets
;
784 * __wait_for - magic wait macro
786 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
787 * important that we check the condition again after having timed out, since the
788 * timeout could be due to preemption or similar and we've never had a chance to
789 * check the condition before the timeout.
791 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
792 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
793 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
797 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
799 /* Guarantee COND check prior to timeout */ \
806 ret__ = -ETIMEDOUT; \
809 usleep_range(wait__, wait__ * 2); \
810 if (wait__ < (Wmax)) \
816 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
818 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
821 struct drm_gem_object
*vc4_create_object(struct drm_device
*dev
, size_t size
);
822 struct vc4_bo
*vc4_bo_create(struct drm_device
*dev
, size_t size
,
823 bool from_cache
, enum vc4_kernel_bo_type type
);
824 int vc4_bo_dumb_create(struct drm_file
*file_priv
,
825 struct drm_device
*dev
,
826 struct drm_mode_create_dumb
*args
);
827 int vc4_create_bo_ioctl(struct drm_device
*dev
, void *data
,
828 struct drm_file
*file_priv
);
829 int vc4_create_shader_bo_ioctl(struct drm_device
*dev
, void *data
,
830 struct drm_file
*file_priv
);
831 int vc4_mmap_bo_ioctl(struct drm_device
*dev
, void *data
,
832 struct drm_file
*file_priv
);
833 int vc4_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
834 struct drm_file
*file_priv
);
835 int vc4_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
836 struct drm_file
*file_priv
);
837 int vc4_get_hang_state_ioctl(struct drm_device
*dev
, void *data
,
838 struct drm_file
*file_priv
);
839 int vc4_label_bo_ioctl(struct drm_device
*dev
, void *data
,
840 struct drm_file
*file_priv
);
841 int vc4_bo_cache_init(struct drm_device
*dev
);
842 int vc4_bo_inc_usecnt(struct vc4_bo
*bo
);
843 void vc4_bo_dec_usecnt(struct vc4_bo
*bo
);
844 void vc4_bo_add_to_purgeable_pool(struct vc4_bo
*bo
);
845 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo
*bo
);
848 extern struct platform_driver vc4_crtc_driver
;
849 int vc4_crtc_disable_at_boot(struct drm_crtc
*crtc
);
850 int vc4_crtc_init(struct drm_device
*drm
, struct vc4_crtc
*vc4_crtc
,
851 const struct drm_crtc_funcs
*crtc_funcs
,
852 const struct drm_crtc_helper_funcs
*crtc_helper_funcs
);
853 void vc4_crtc_destroy(struct drm_crtc
*crtc
);
854 int vc4_page_flip(struct drm_crtc
*crtc
,
855 struct drm_framebuffer
*fb
,
856 struct drm_pending_vblank_event
*event
,
858 struct drm_modeset_acquire_ctx
*ctx
);
859 struct drm_crtc_state
*vc4_crtc_duplicate_state(struct drm_crtc
*crtc
);
860 void vc4_crtc_destroy_state(struct drm_crtc
*crtc
,
861 struct drm_crtc_state
*state
);
862 void vc4_crtc_reset(struct drm_crtc
*crtc
);
863 void vc4_crtc_handle_vblank(struct vc4_crtc
*crtc
);
864 void vc4_crtc_get_margins(struct drm_crtc_state
*state
,
865 unsigned int *left
, unsigned int *right
,
866 unsigned int *top
, unsigned int *bottom
);
869 void vc4_debugfs_init(struct drm_minor
*minor
);
870 #ifdef CONFIG_DEBUG_FS
871 void vc4_debugfs_add_file(struct drm_device
*drm
,
872 const char *filename
,
873 int (*show
)(struct seq_file
*, void*),
875 void vc4_debugfs_add_regset32(struct drm_device
*drm
,
876 const char *filename
,
877 struct debugfs_regset32
*regset
);
879 static inline void vc4_debugfs_add_file(struct drm_device
*drm
,
880 const char *filename
,
881 int (*show
)(struct seq_file
*, void*),
886 static inline void vc4_debugfs_add_regset32(struct drm_device
*drm
,
887 const char *filename
,
888 struct debugfs_regset32
*regset
)
894 void __iomem
*vc4_ioremap_regs(struct platform_device
*dev
, int index
);
895 int vc4_dumb_fixup_args(struct drm_mode_create_dumb
*args
);
898 extern struct platform_driver vc4_dpi_driver
;
901 extern struct platform_driver vc4_dsi_driver
;
904 extern const struct dma_fence_ops vc4_fence_ops
;
907 int vc4_gem_init(struct drm_device
*dev
);
908 int vc4_submit_cl_ioctl(struct drm_device
*dev
, void *data
,
909 struct drm_file
*file_priv
);
910 int vc4_wait_seqno_ioctl(struct drm_device
*dev
, void *data
,
911 struct drm_file
*file_priv
);
912 int vc4_wait_bo_ioctl(struct drm_device
*dev
, void *data
,
913 struct drm_file
*file_priv
);
914 void vc4_submit_next_bin_job(struct drm_device
*dev
);
915 void vc4_submit_next_render_job(struct drm_device
*dev
);
916 void vc4_move_job_to_render(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
917 int vc4_wait_for_seqno(struct drm_device
*dev
, uint64_t seqno
,
918 uint64_t timeout_ns
, bool interruptible
);
919 void vc4_job_handle_completed(struct vc4_dev
*vc4
);
920 int vc4_queue_seqno_cb(struct drm_device
*dev
,
921 struct vc4_seqno_cb
*cb
, uint64_t seqno
,
922 void (*func
)(struct vc4_seqno_cb
*cb
));
923 int vc4_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
924 struct drm_file
*file_priv
);
927 extern struct platform_driver vc4_hdmi_driver
;
930 extern struct platform_driver vc4_vec_driver
;
933 extern struct platform_driver vc4_txp_driver
;
936 void vc4_irq_enable(struct drm_device
*dev
);
937 void vc4_irq_disable(struct drm_device
*dev
);
938 int vc4_irq_install(struct drm_device
*dev
, int irq
);
939 void vc4_irq_uninstall(struct drm_device
*dev
);
940 void vc4_irq_reset(struct drm_device
*dev
);
943 extern struct platform_driver vc4_hvs_driver
;
944 void vc4_hvs_stop_channel(struct vc4_hvs
*hvs
, unsigned int output
);
945 int vc4_hvs_get_fifo_from_output(struct vc4_hvs
*hvs
, unsigned int output
);
946 u8
vc4_hvs_get_fifo_frame_count(struct vc4_hvs
*hvs
, unsigned int fifo
);
947 int vc4_hvs_atomic_check(struct drm_crtc
*crtc
, struct drm_atomic_state
*state
);
948 void vc4_hvs_atomic_begin(struct drm_crtc
*crtc
, struct drm_atomic_state
*state
);
949 void vc4_hvs_atomic_enable(struct drm_crtc
*crtc
, struct drm_atomic_state
*state
);
950 void vc4_hvs_atomic_disable(struct drm_crtc
*crtc
, struct drm_atomic_state
*state
);
951 void vc4_hvs_atomic_flush(struct drm_crtc
*crtc
, struct drm_atomic_state
*state
);
952 void vc4_hvs_dump_state(struct vc4_hvs
*hvs
);
953 void vc4_hvs_unmask_underrun(struct vc4_hvs
*hvs
, int channel
);
954 void vc4_hvs_mask_underrun(struct vc4_hvs
*hvs
, int channel
);
957 int vc4_kms_load(struct drm_device
*dev
);
960 struct drm_plane
*vc4_plane_init(struct drm_device
*dev
,
961 enum drm_plane_type type
);
962 int vc4_plane_create_additional_planes(struct drm_device
*dev
);
963 u32
vc4_plane_write_dlist(struct drm_plane
*plane
, u32 __iomem
*dlist
);
964 u32
vc4_plane_dlist_size(const struct drm_plane_state
*state
);
965 void vc4_plane_async_set_fb(struct drm_plane
*plane
,
966 struct drm_framebuffer
*fb
);
969 extern struct platform_driver vc4_v3d_driver
;
970 extern const struct of_device_id vc4_v3d_dt_match
[];
971 int vc4_v3d_get_bin_slot(struct vc4_dev
*vc4
);
972 int vc4_v3d_bin_bo_get(struct vc4_dev
*vc4
, bool *used
);
973 void vc4_v3d_bin_bo_put(struct vc4_dev
*vc4
);
974 int vc4_v3d_pm_get(struct vc4_dev
*vc4
);
975 void vc4_v3d_pm_put(struct vc4_dev
*vc4
);
979 vc4_validate_bin_cl(struct drm_device
*dev
,
982 struct vc4_exec_info
*exec
);
985 vc4_validate_shader_recs(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
987 struct drm_gem_cma_object
*vc4_use_bo(struct vc4_exec_info
*exec
,
990 int vc4_get_rcl(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
992 bool vc4_check_tex_size(struct vc4_exec_info
*exec
,
993 struct drm_gem_cma_object
*fbo
,
994 uint32_t offset
, uint8_t tiling_format
,
995 uint32_t width
, uint32_t height
, uint8_t cpp
);
997 /* vc4_validate_shader.c */
998 struct vc4_validated_shader_info
*
999 vc4_validate_shader(struct drm_gem_cma_object
*shader_obj
);
1002 void vc4_perfmon_get(struct vc4_perfmon
*perfmon
);
1003 void vc4_perfmon_put(struct vc4_perfmon
*perfmon
);
1004 void vc4_perfmon_start(struct vc4_dev
*vc4
, struct vc4_perfmon
*perfmon
);
1005 void vc4_perfmon_stop(struct vc4_dev
*vc4
, struct vc4_perfmon
*perfmon
,
1007 struct vc4_perfmon
*vc4_perfmon_find(struct vc4_file
*vc4file
, int id
);
1008 void vc4_perfmon_open_file(struct vc4_file
*vc4file
);
1009 void vc4_perfmon_close_file(struct vc4_file
*vc4file
);
1010 int vc4_perfmon_create_ioctl(struct drm_device
*dev
, void *data
,
1011 struct drm_file
*file_priv
);
1012 int vc4_perfmon_destroy_ioctl(struct drm_device
*dev
, void *data
,
1013 struct drm_file
*file_priv
);
1014 int vc4_perfmon_get_values_ioctl(struct drm_device
*dev
, void *data
,
1015 struct drm_file
*file_priv
);
1017 #endif /* _VC4_DRV_H_ */