drivers/net/can/ti_hecc.c

   1 /*
   2  * TI HECC (CAN) device driver
   3  *
   4  * This driver supports TI's HECC (High End CAN Controller module) and the
   5  * specs for the same is available at <http://www.ti.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed as is WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 /*
  21  * Your platform definitions should specify module ram offsets and interrupt
  22  * number to use as follows:
  23  *
  24  * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
  25  *         .scc_hecc_offset        = 0,
  26  *         .scc_ram_offset         = 0x3000,
  27  *         .hecc_ram_offset        = 0x3000,
  28  *         .mbx_offset             = 0x2000,
  29  *         .int_line               = 0,
  30  *         .revision               = 1,
  31  *         .transceiver_switch     = hecc_phy_control,
  32  * };
  33  *
  34  * Please see include/linux/can/platform/ti_hecc.h for description of
  35  * above fields.
  36  *
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/types.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/errno.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/clk.h>
  48 #include <linux/io.h>
  49
  50 #include <linux/can/dev.h>
  51 #include <linux/can/error.h>
  52 #include <linux/can/led.h>
  53 #include <linux/can/platform/ti_hecc.h>
  54
  55 #define DRV_NAME "ti_hecc"
  56 #define HECC_MODULE_VERSION     "0.7"
  57 MODULE_VERSION(HECC_MODULE_VERSION);
  58 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
  59
  60 /* TX / RX Mailbox Configuration */
  61 #define HECC_MAX_MAILBOXES      32      /* hardware mailboxes - do not change */
  62 #define MAX_TX_PRIO             0x3F    /* hardware value - do not change */
  63
  64 /*
  65  * Important Note: TX mailbox configuration
  66  * TX mailboxes should be restricted to the number of SKB buffers to avoid
  67  * maintaining SKB buffers separately. TX mailboxes should be a power of 2
  68  * for the mailbox logic to work.  Top mailbox numbers are reserved for RX
  69  * and lower mailboxes for TX.
  70  *
  71  * HECC_MAX_TX_MBOX     HECC_MB_TX_SHIFT
  72  * 4 (default)          2
  73  * 8                    3
  74  * 16                   4
  75  */
  76 #define HECC_MB_TX_SHIFT        2 /* as per table above */
  77 #define HECC_MAX_TX_MBOX        BIT(HECC_MB_TX_SHIFT)
  78
  79 #define HECC_TX_PRIO_SHIFT      (HECC_MB_TX_SHIFT)
  80 #define HECC_TX_PRIO_MASK       (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
  81 #define HECC_TX_MB_MASK         (HECC_MAX_TX_MBOX - 1)
  82 #define HECC_TX_MASK            ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
  83 #define HECC_TX_MBOX_MASK       (~(BIT(HECC_MAX_TX_MBOX) - 1))
  84 #define HECC_DEF_NAPI_WEIGHT    HECC_MAX_RX_MBOX
  85
  86 /*
  87  * Important Note: RX mailbox configuration
  88  * RX mailboxes are further logically split into two - main and buffer
  89  * mailboxes. The goal is to get all packets into main mailboxes as
  90  * driven by mailbox number and receive priority (higher to lower) and
  91  * buffer mailboxes are used to receive pkts while main mailboxes are being
  92  * processed. This ensures in-order packet reception.
  93  *
  94  * Here are the recommended values for buffer mailbox. Note that RX mailboxes
  95  * start after TX mailboxes:
  96  *
  97  * HECC_MAX_RX_MBOX             HECC_RX_BUFFER_MBOX     No of buffer mailboxes
  98  * 28                           12                      8
  99  * 16                           20                      4
 100  */
 101
 102 #define HECC_MAX_RX_MBOX        (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
 103 #define HECC_RX_BUFFER_MBOX     12 /* as per table above */
 104 #define HECC_RX_FIRST_MBOX      (HECC_MAX_MAILBOXES - 1)
 105 #define HECC_RX_HIGH_MBOX_MASK  (~(BIT(HECC_RX_BUFFER_MBOX) - 1))
 106
 107 /* TI HECC module registers */
 108 #define HECC_CANME              0x0     /* Mailbox enable */
 109 #define HECC_CANMD              0x4     /* Mailbox direction */
 110 #define HECC_CANTRS             0x8     /* Transmit request set */
 111 #define HECC_CANTRR             0xC     /* Transmit request */
 112 #define HECC_CANTA              0x10    /* Transmission acknowledge */
 113 #define HECC_CANAA              0x14    /* Abort acknowledge */
 114 #define HECC_CANRMP             0x18    /* Receive message pending */
 115 #define HECC_CANRML             0x1C    /* Remote message lost */
 116 #define HECC_CANRFP             0x20    /* Remote frame pending */
 117 #define HECC_CANGAM             0x24    /* SECC only:Global acceptance mask */
 118 #define HECC_CANMC              0x28    /* Master control */
 119 #define HECC_CANBTC             0x2C    /* Bit timing configuration */
 120 #define HECC_CANES              0x30    /* Error and status */
 121 #define HECC_CANTEC             0x34    /* Transmit error counter */
 122 #define HECC_CANREC             0x38    /* Receive error counter */
 123 #define HECC_CANGIF0            0x3C    /* Global interrupt flag 0 */
 124 #define HECC_CANGIM             0x40    /* Global interrupt mask */
 125 #define HECC_CANGIF1            0x44    /* Global interrupt flag 1 */
 126 #define HECC_CANMIM             0x48    /* Mailbox interrupt mask */
 127 #define HECC_CANMIL             0x4C    /* Mailbox interrupt level */
 128 #define HECC_CANOPC             0x50    /* Overwrite protection control */
 129 #define HECC_CANTIOC            0x54    /* Transmit I/O control */
 130 #define HECC_CANRIOC            0x58    /* Receive I/O control */
 131 #define HECC_CANLNT             0x5C    /* HECC only: Local network time */
 132 #define HECC_CANTOC             0x60    /* HECC only: Time-out control */
 133 #define HECC_CANTOS             0x64    /* HECC only: Time-out status */
 134 #define HECC_CANTIOCE           0x68    /* SCC only:Enhanced TX I/O control */
 135 #define HECC_CANRIOCE           0x6C    /* SCC only:Enhanced RX I/O control */
 136
 137 /* Mailbox registers */
 138 #define HECC_CANMID             0x0
 139 #define HECC_CANMCF             0x4
 140 #define HECC_CANMDL             0x8
 141 #define HECC_CANMDH             0xC
 142
 143 #define HECC_SET_REG            0xFFFFFFFF
 144 #define HECC_CANID_MASK         0x3FF   /* 18 bits mask for extended id's */
 145 #define HECC_CCE_WAIT_COUNT     100     /* Wait for ~1 sec for CCE bit */
 146
 147 #define HECC_CANMC_SCM          BIT(13) /* SCC compat mode */
 148 #define HECC_CANMC_CCR          BIT(12) /* Change config request */
 149 #define HECC_CANMC_PDR          BIT(11) /* Local Power down - for sleep mode */
 150 #define HECC_CANMC_ABO          BIT(7)  /* Auto Bus On */
 151 #define HECC_CANMC_STM          BIT(6)  /* Self test mode - loopback */
 152 #define HECC_CANMC_SRES         BIT(5)  /* Software reset */
 153
 154 #define HECC_CANTIOC_EN         BIT(3)  /* Enable CAN TX I/O pin */
 155 #define HECC_CANRIOC_EN         BIT(3)  /* Enable CAN RX I/O pin */
 156
 157 #define HECC_CANMID_IDE         BIT(31) /* Extended frame format */
 158 #define HECC_CANMID_AME         BIT(30) /* Acceptance mask enable */
 159 #define HECC_CANMID_AAM         BIT(29) /* Auto answer mode */
 160
 161 #define HECC_CANES_FE           BIT(24) /* form error */
 162 #define HECC_CANES_BE           BIT(23) /* bit error */
 163 #define HECC_CANES_SA1          BIT(22) /* stuck at dominant error */
 164 #define HECC_CANES_CRCE         BIT(21) /* CRC error */
 165 #define HECC_CANES_SE           BIT(20) /* stuff bit error */
 166 #define HECC_CANES_ACKE         BIT(19) /* ack error */
 167 #define HECC_CANES_BO           BIT(18) /* Bus off status */
 168 #define HECC_CANES_EP           BIT(17) /* Error passive status */
 169 #define HECC_CANES_EW           BIT(16) /* Error warning status */
 170 #define HECC_CANES_SMA          BIT(5)  /* suspend mode ack */
 171 #define HECC_CANES_CCE          BIT(4)  /* Change config enabled */
 172 #define HECC_CANES_PDA          BIT(3)  /* Power down mode ack */
 173
 174 #define HECC_CANBTC_SAM         BIT(7)  /* sample points */
 175
 176 #define HECC_BUS_ERROR          (HECC_CANES_FE | HECC_CANES_BE |\
 177                                 HECC_CANES_CRCE | HECC_CANES_SE |\
 178                                 HECC_CANES_ACKE)
 179
 180 #define HECC_CANMCF_RTR         BIT(4)  /* Remote transmit request */
 181
 182 #define HECC_CANGIF_MAIF        BIT(17) /* Message alarm interrupt */
 183 #define HECC_CANGIF_TCOIF       BIT(16) /* Timer counter overflow int */
 184 #define HECC_CANGIF_GMIF        BIT(15) /* Global mailbox interrupt */
 185 #define HECC_CANGIF_AAIF        BIT(14) /* Abort ack interrupt */
 186 #define HECC_CANGIF_WDIF        BIT(13) /* Write denied interrupt */
 187 #define HECC_CANGIF_WUIF        BIT(12) /* Wake up interrupt */
 188 #define HECC_CANGIF_RMLIF       BIT(11) /* Receive message lost interrupt */
 189 #define HECC_CANGIF_BOIF        BIT(10) /* Bus off interrupt */
 190 #define HECC_CANGIF_EPIF        BIT(9)  /* Error passive interrupt */
 191 #define HECC_CANGIF_WLIF        BIT(8)  /* Warning level interrupt */
 192 #define HECC_CANGIF_MBOX_MASK   0x1F    /* Mailbox number mask */
 193 #define HECC_CANGIM_I1EN        BIT(1)  /* Int line 1 enable */
 194 #define HECC_CANGIM_I0EN        BIT(0)  /* Int line 0 enable */
 195 #define HECC_CANGIM_DEF_MASK    0x700   /* only busoff/warning/passive */
 196 #define HECC_CANGIM_SIL         BIT(2)  /* system interrupts to int line 1 */
 197
 198 /* CAN Bittiming constants as per HECC specs */
 199 static const struct can_bittiming_const ti_hecc_bittiming_const = {
 200         .name = DRV_NAME,
 201         .tseg1_min = 1,
 202         .tseg1_max = 16,
 203         .tseg2_min = 1,
 204         .tseg2_max = 8,
 205         .sjw_max = 4,
 206         .brp_min = 1,
 207         .brp_max = 256,
 208         .brp_inc = 1,
 209 };
 210
 211 struct ti_hecc_priv {
 212         struct can_priv can;    /* MUST be first member/field */
 213         struct napi_struct napi;
 214         struct net_device *ndev;
 215         struct clk *clk;
 216         void __iomem *base;
 217         u32 scc_ram_offset;
 218         u32 hecc_ram_offset;
 219         u32 mbx_offset;
 220         u32 int_line;
 221         spinlock_t mbx_lock; /* CANME register needs protection */
 222         u32 tx_head;
 223         u32 tx_tail;
 224         u32 rx_next;
 225         void (*transceiver_switch)(int);
 226 };
 227
 228 static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
 229 {
 230         return priv->tx_head & HECC_TX_MB_MASK;
 231 }
 232
 233 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
 234 {
 235         return priv->tx_tail & HECC_TX_MB_MASK;
 236 }
 237
 238 static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
 239 {
 240         return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
 241 }
 242
 243 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
 244 {
 245         __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);
 246 }
 247
 248 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
 249         u32 reg, u32 val)
 250 {
 251         __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +
 252                         reg);
 253 }
 254
 255 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
 256 {
 257         return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +
 258                         reg);
 259 }
 260
 261 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
 262 {
 263         __raw_writel(val, priv->base + reg);
 264 }
 265
 266 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
 267 {
 268         return __raw_readl(priv->base + reg);
 269 }
 270
 271 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
 272         u32 bit_mask)
 273 {
 274         hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
 275 }
 276
 277 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
 278         u32 bit_mask)
 279 {
 280         hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
 281 }
 282
 283 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
 284 {
 285         return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
 286 }
 287
 288 static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
 289 {
 290         struct can_bittiming *bit_timing = &priv->can.bittiming;
 291         u32 can_btc;
 292
 293         can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
 294         can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
 295                         & 0xF) << 3;
 296         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
 297                 if (bit_timing->brp > 4)
 298                         can_btc |= HECC_CANBTC_SAM;
 299                 else
 300                         netdev_warn(priv->ndev, "WARN: Triple"
 301                                 "sampling not set due to h/w limitations");
 302         }
 303         can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
 304         can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
 305
 306         /* ERM being set to 0 by default meaning resync at falling edge */
 307
 308         hecc_write(priv, HECC_CANBTC, can_btc);
 309         netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
 310
 311         return 0;
 312 }
 313
 314 static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
 315                                         int on)
 316 {
 317         if (priv->transceiver_switch)
 318                 priv->transceiver_switch(on);
 319 }
 320
 321 static void ti_hecc_reset(struct net_device *ndev)
 322 {
 323         u32 cnt;
 324         struct ti_hecc_priv *priv = netdev_priv(ndev);
 325
 326         netdev_dbg(ndev, "resetting hecc ...\n");
 327         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
 328
 329         /* Set change control request and wait till enabled */
 330         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 331
 332         /*
 333          * INFO: It has been observed that at times CCE bit may not be
 334          * set and hw seems to be ok even if this bit is not set so
 335          * timing out with a timing of 1ms to respect the specs
 336          */
 337         cnt = HECC_CCE_WAIT_COUNT;
 338         while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
 339                 --cnt;
 340                 udelay(10);
 341         }
 342
 343         /*
 344          * Note: On HECC, BTC can be programmed only in initialization mode, so
 345          * it is expected that the can bittiming parameters are set via ip
 346          * utility before the device is opened
 347          */
 348         ti_hecc_set_btc(priv);
 349
 350         /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
 351         hecc_write(priv, HECC_CANMC, 0);
 352
 353         /*
 354          * INFO: CAN net stack handles bus off and hence disabling auto-bus-on
 355          * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
 356          */
 357
 358         /*
 359          * INFO: It has been observed that at times CCE bit may not be
 360          * set and hw seems to be ok even if this bit is not set so
 361          */
 362         cnt = HECC_CCE_WAIT_COUNT;
 363         while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
 364                 --cnt;
 365                 udelay(10);
 366         }
 367
 368         /* Enable TX and RX I/O Control pins */
 369         hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
 370         hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
 371
 372         /* Clear registers for clean operation */
 373         hecc_write(priv, HECC_CANTA, HECC_SET_REG);
 374         hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
 375         hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
 376         hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
 377         hecc_write(priv, HECC_CANME, 0);
 378         hecc_write(priv, HECC_CANMD, 0);
 379
 380         /* SCC compat mode NOT supported (and not needed too) */
 381         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
 382 }
 383
 384 static void ti_hecc_start(struct net_device *ndev)
 385 {
 386         struct ti_hecc_priv *priv = netdev_priv(ndev);
 387         u32 cnt, mbxno, mbx_mask;
 388
 389         /* put HECC in initialization mode and set btc */
 390         ti_hecc_reset(ndev);
 391
 392         priv->tx_head = priv->tx_tail = HECC_TX_MASK;
 393         priv->rx_next = HECC_RX_FIRST_MBOX;
 394
 395         /* Enable local and global acceptance mask registers */
 396         hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
 397
 398         /* Prepare configured mailboxes to receive messages */
 399         for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
 400                 mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
 401                 mbx_mask = BIT(mbxno);
 402                 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
 403                 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
 404                 hecc_write_lam(priv, mbxno, HECC_SET_REG);
 405                 hecc_set_bit(priv, HECC_CANMD, mbx_mask);
 406                 hecc_set_bit(priv, HECC_CANME, mbx_mask);
 407                 hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
 408         }
 409
 410         /* Prevent message over-write & Enable interrupts */
 411         hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
 412         if (priv->int_line) {
 413                 hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
 414                 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
 415                         HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
 416         } else {
 417                 hecc_write(priv, HECC_CANMIL, 0);
 418                 hecc_write(priv, HECC_CANGIM,
 419                         HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
 420         }
 421         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 422 }
 423
 424 static void ti_hecc_stop(struct net_device *ndev)
 425 {
 426         struct ti_hecc_priv *priv = netdev_priv(ndev);
 427
 428         /* Disable interrupts and disable mailboxes */
 429         hecc_write(priv, HECC_CANGIM, 0);
 430         hecc_write(priv, HECC_CANMIM, 0);
 431         hecc_write(priv, HECC_CANME, 0);
 432         priv->can.state = CAN_STATE_STOPPED;
 433 }
 434
 435 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
 436 {
 437         int ret = 0;
 438
 439         switch (mode) {
 440         case CAN_MODE_START:
 441                 ti_hecc_start(ndev);
 442                 netif_wake_queue(ndev);
 443                 break;
 444         default:
 445                 ret = -EOPNOTSUPP;
 446                 break;
 447         }
 448
 449         return ret;
 450 }
 451
 452 static int ti_hecc_get_berr_counter(const struct net_device *ndev,
 453                                         struct can_berr_counter *bec)
 454 {
 455         struct ti_hecc_priv *priv = netdev_priv(ndev);
 456
 457         bec->txerr = hecc_read(priv, HECC_CANTEC);
 458         bec->rxerr = hecc_read(priv, HECC_CANREC);
 459
 460         return 0;
 461 }
 462
 463 /*
 464  * ti_hecc_xmit: HECC Transmit
 465  *
 466  * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
 467  * priority of the mailbox for tranmission is dependent upon priority setting
 468  * field in mailbox registers. The mailbox with highest value in priority field
 469  * is transmitted first. Only when two mailboxes have the same value in
 470  * priority field the highest numbered mailbox is transmitted first.
 471  *
 472  * To utilize the HECC priority feature as described above we start with the
 473  * highest numbered mailbox with highest priority level and move on to the next
 474  * mailbox with the same priority level and so on. Once we loop through all the
 475  * transmit mailboxes we choose the next priority level (lower) and so on
 476  * until we reach the lowest priority level on the lowest numbered mailbox
 477  * when we stop transmission until all mailboxes are transmitted and then
 478  * restart at highest numbered mailbox with highest priority.
 479  *
 480  * Two counters (head and tail) are used to track the next mailbox to transmit
 481  * and to track the echo buffer for already transmitted mailbox. The queue
 482  * is stopped when all the mailboxes are busy or when there is a priority
 483  * value roll-over happens.
 484  */
 485 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
 486 {
 487         struct ti_hecc_priv *priv = netdev_priv(ndev);
 488         struct can_frame *cf = (struct can_frame *)skb->data;
 489         u32 mbxno, mbx_mask, data;
 490         unsigned long flags;
 491
 492         if (can_dropped_invalid_skb(ndev, skb))
 493                 return NETDEV_TX_OK;
 494
 495         mbxno = get_tx_head_mb(priv);
 496         mbx_mask = BIT(mbxno);
 497         spin_lock_irqsave(&priv->mbx_lock, flags);
 498         if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
 499                 spin_unlock_irqrestore(&priv->mbx_lock, flags);
 500                 netif_stop_queue(ndev);
 501                 netdev_err(priv->ndev,
 502                         "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
 503                         priv->tx_head, priv->tx_tail);
 504                 return NETDEV_TX_BUSY;
 505         }
 506         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 507
 508         /* Prepare mailbox for transmission */
 509         data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
 510         if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
 511                 data |= HECC_CANMCF_RTR;
 512         hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
 513
 514         if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
 515                 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
 516         else /* Standard frame format */
 517                 data = (cf->can_id & CAN_SFF_MASK) << 18;
 518         hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
 519         hecc_write_mbx(priv, mbxno, HECC_CANMDL,
 520                 be32_to_cpu(*(__be32 *)(cf->data)));
 521         if (cf->can_dlc > 4)
 522                 hecc_write_mbx(priv, mbxno, HECC_CANMDH,
 523                         be32_to_cpu(*(__be32 *)(cf->data + 4)));
 524         else
 525                 *(u32 *)(cf->data + 4) = 0;
 526         can_put_echo_skb(skb, ndev, mbxno);
 527
 528         spin_lock_irqsave(&priv->mbx_lock, flags);
 529         --priv->tx_head;
 530         if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
 531                 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
 532                 netif_stop_queue(ndev);
 533         }
 534         hecc_set_bit(priv, HECC_CANME, mbx_mask);
 535         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 536
 537         hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
 538         hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
 539         hecc_write(priv, HECC_CANTRS, mbx_mask);
 540
 541         return NETDEV_TX_OK;
 542 }
 543
 544 static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno)
 545 {
 546         struct net_device_stats *stats = &priv->ndev->stats;
 547         struct can_frame *cf;
 548         struct sk_buff *skb;
 549         u32 data, mbx_mask;
 550         unsigned long flags;
 551
 552         skb = alloc_can_skb(priv->ndev, &cf);
 553         if (!skb) {
 554                 if (printk_ratelimit())
 555                         netdev_err(priv->ndev,
 556                                 "ti_hecc_rx_pkt: alloc_can_skb() failed\n");
 557                 return -ENOMEM;
 558         }
 559
 560         mbx_mask = BIT(mbxno);
 561         data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
 562         if (data & HECC_CANMID_IDE)
 563                 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
 564         else
 565                 cf->can_id = (data >> 18) & CAN_SFF_MASK;
 566         data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
 567         if (data & HECC_CANMCF_RTR)
 568                 cf->can_id |= CAN_RTR_FLAG;
 569         cf->can_dlc = get_can_dlc(data & 0xF);
 570         data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
 571         *(__be32 *)(cf->data) = cpu_to_be32(data);
 572         if (cf->can_dlc > 4) {
 573                 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
 574                 *(__be32 *)(cf->data + 4) = cpu_to_be32(data);
 575         }
 576         spin_lock_irqsave(&priv->mbx_lock, flags);
 577         hecc_clear_bit(priv, HECC_CANME, mbx_mask);
 578         hecc_write(priv, HECC_CANRMP, mbx_mask);
 579         /* enable mailbox only if it is part of rx buffer mailboxes */
 580         if (priv->rx_next < HECC_RX_BUFFER_MBOX)
 581                 hecc_set_bit(priv, HECC_CANME, mbx_mask);
 582         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 583
 584         stats->rx_bytes += cf->can_dlc;
 585         can_led_event(priv->ndev, CAN_LED_EVENT_RX);
 586         netif_receive_skb(skb);
 587         stats->rx_packets++;
 588
 589         return 0;
 590 }
 591
 592 /*
 593  * ti_hecc_rx_poll - HECC receive pkts
 594  *
 595  * The receive mailboxes start from highest numbered mailbox till last xmit
 596  * mailbox. On CAN frame reception the hardware places the data into highest
 597  * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes
 598  * have same filtering (ALL CAN frames) packets will arrive in the highest
 599  * available RX mailbox and we need to ensure in-order packet reception.
 600  *
 601  * To ensure the packets are received in the right order we logically divide
 602  * the RX mailboxes into main and buffer mailboxes. Packets are received as per
 603  * mailbox priotity (higher to lower) in the main bank and once it is full we
 604  * disable further reception into main mailboxes. While the main mailboxes are
 605  * processed in NAPI, further packets are received in buffer mailboxes.
 606  *
 607  * We maintain a RX next mailbox counter to process packets and once all main
 608  * mailboxe packets are passed to the upper stack we enable all of them but
 609  * continue to process packets received in buffer mailboxes. With each packet
 610  * received from buffer mailbox we enable it immediately so as to handle the
 611  * overflow from higher mailboxes.
 612  */
 613 static int ti_hecc_rx_poll(struct napi_struct *napi, int quota)
 614 {
 615         struct net_device *ndev = napi->dev;
 616         struct ti_hecc_priv *priv = netdev_priv(ndev);
 617         u32 num_pkts = 0;
 618         u32 mbx_mask;
 619         unsigned long pending_pkts, flags;
 620
 621         if (!netif_running(ndev))
 622                 return 0;
 623
 624         while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) &&
 625                 num_pkts < quota) {
 626                 mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */
 627                 if (mbx_mask & pending_pkts) {
 628                         if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0)
 629                                 return num_pkts;
 630                         ++num_pkts;
 631                 } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) {
 632                         break; /* pkt not received yet */
 633                 }
 634                 --priv->rx_next;
 635                 if (priv->rx_next == HECC_RX_BUFFER_MBOX) {
 636                         /* enable high bank mailboxes */
 637                         spin_lock_irqsave(&priv->mbx_lock, flags);
 638                         mbx_mask = hecc_read(priv, HECC_CANME);
 639                         mbx_mask |= HECC_RX_HIGH_MBOX_MASK;
 640                         hecc_write(priv, HECC_CANME, mbx_mask);
 641                         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 642                 } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) {
 643                         priv->rx_next = HECC_RX_FIRST_MBOX;
 644                         break;
 645                 }
 646         }
 647
 648         /* Enable packet interrupt if all pkts are handled */
 649         if (hecc_read(priv, HECC_CANRMP) == 0) {
 650                 napi_complete(napi);
 651                 /* Re-enable RX mailbox interrupts */
 652                 mbx_mask = hecc_read(priv, HECC_CANMIM);
 653                 mbx_mask |= HECC_TX_MBOX_MASK;
 654                 hecc_write(priv, HECC_CANMIM, mbx_mask);
 655         }
 656
 657         return num_pkts;
 658 }
 659
 660 static int ti_hecc_error(struct net_device *ndev, int int_status,
 661         int err_status)
 662 {
 663         struct ti_hecc_priv *priv = netdev_priv(ndev);
 664         struct net_device_stats *stats = &ndev->stats;
 665         struct can_frame *cf;
 666         struct sk_buff *skb;
 667
 668         /* propagate the error condition to the can stack */
 669         skb = alloc_can_err_skb(ndev, &cf);
 670         if (!skb) {
 671                 if (printk_ratelimit())
 672                         netdev_err(priv->ndev,
 673                                 "ti_hecc_error: alloc_can_err_skb() failed\n");
 674                 return -ENOMEM;
 675         }
 676
 677         if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
 678                 if ((int_status & HECC_CANGIF_BOIF) == 0) {
 679                         priv->can.state = CAN_STATE_ERROR_WARNING;
 680                         ++priv->can.can_stats.error_warning;
 681                         cf->can_id |= CAN_ERR_CRTL;
 682                         if (hecc_read(priv, HECC_CANTEC) > 96)
 683                                 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
 684                         if (hecc_read(priv, HECC_CANREC) > 96)
 685                                 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
 686                 }
 687                 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
 688                 netdev_dbg(priv->ndev, "Error Warning interrupt\n");
 689                 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 690         }
 691
 692         if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
 693                 if ((int_status & HECC_CANGIF_BOIF) == 0) {
 694                         priv->can.state = CAN_STATE_ERROR_PASSIVE;
 695                         ++priv->can.can_stats.error_passive;
 696                         cf->can_id |= CAN_ERR_CRTL;
 697                         if (hecc_read(priv, HECC_CANTEC) > 127)
 698                                 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 699                         if (hecc_read(priv, HECC_CANREC) > 127)
 700                                 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 701                 }
 702                 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
 703                 netdev_dbg(priv->ndev, "Error passive interrupt\n");
 704                 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 705         }
 706
 707         /*
 708          * Need to check busoff condition in error status register too to
 709          * ensure warning interrupts don't hog the system
 710          */
 711         if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
 712                 priv->can.state = CAN_STATE_BUS_OFF;
 713                 cf->can_id |= CAN_ERR_BUSOFF;
 714                 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
 715                 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 716                 /* Disable all interrupts in bus-off to avoid int hog */
 717                 hecc_write(priv, HECC_CANGIM, 0);
 718                 ++priv->can.can_stats.bus_off;
 719                 can_bus_off(ndev);
 720         }
 721
 722         if (err_status & HECC_BUS_ERROR) {
 723                 ++priv->can.can_stats.bus_error;
 724                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 725                 if (err_status & HECC_CANES_FE) {
 726                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
 727                         cf->data[2] |= CAN_ERR_PROT_FORM;
 728                 }
 729                 if (err_status & HECC_CANES_BE) {
 730                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
 731                         cf->data[2] |= CAN_ERR_PROT_BIT;
 732                 }
 733                 if (err_status & HECC_CANES_SE) {
 734                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
 735                         cf->data[2] |= CAN_ERR_PROT_STUFF;
 736                 }
 737                 if (err_status & HECC_CANES_CRCE) {
 738                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
 739                         cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 740                 }
 741                 if (err_status & HECC_CANES_ACKE) {
 742                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
 743                         cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 744                 }
 745         }
 746
 747         stats->rx_packets++;
 748         stats->rx_bytes += cf->can_dlc;
 749         netif_rx(skb);
 750
 751         return 0;
 752 }
 753
 754 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
 755 {
 756         struct net_device *ndev = (struct net_device *)dev_id;
 757         struct ti_hecc_priv *priv = netdev_priv(ndev);
 758         struct net_device_stats *stats = &ndev->stats;
 759         u32 mbxno, mbx_mask, int_status, err_status;
 760         unsigned long ack, flags;
 761
 762         int_status = hecc_read(priv,
 763                 (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);
 764
 765         if (!int_status)
 766                 return IRQ_NONE;
 767
 768         err_status = hecc_read(priv, HECC_CANES);
 769         if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
 770                 HECC_CANES_EP | HECC_CANES_EW))
 771                         ti_hecc_error(ndev, int_status, err_status);
 772
 773         if (int_status & HECC_CANGIF_GMIF) {
 774                 while (priv->tx_tail - priv->tx_head > 0) {
 775                         mbxno = get_tx_tail_mb(priv);
 776                         mbx_mask = BIT(mbxno);
 777                         if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
 778                                 break;
 779                         hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
 780                         hecc_write(priv, HECC_CANTA, mbx_mask);
 781                         spin_lock_irqsave(&priv->mbx_lock, flags);
 782                         hecc_clear_bit(priv, HECC_CANME, mbx_mask);
 783                         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 784                         stats->tx_bytes += hecc_read_mbx(priv, mbxno,
 785                                                 HECC_CANMCF) & 0xF;
 786                         stats->tx_packets++;
 787                         can_led_event(ndev, CAN_LED_EVENT_TX);
 788                         can_get_echo_skb(ndev, mbxno);
 789                         --priv->tx_tail;
 790                 }
 791
 792                 /* restart queue if wrap-up or if queue stalled on last pkt */
 793                 if (((priv->tx_head == priv->tx_tail) &&
 794                 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
 795                 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
 796                 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
 797                         netif_wake_queue(ndev);
 798
 799                 /* Disable RX mailbox interrupts and let NAPI reenable them */
 800                 if (hecc_read(priv, HECC_CANRMP)) {
 801                         ack = hecc_read(priv, HECC_CANMIM);
 802                         ack &= BIT(HECC_MAX_TX_MBOX) - 1;
 803                         hecc_write(priv, HECC_CANMIM, ack);
 804                         napi_schedule(&priv->napi);
 805                 }
 806         }
 807
 808         /* clear all interrupt conditions - read back to avoid spurious ints */
 809         if (priv->int_line) {
 810                 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
 811                 int_status = hecc_read(priv, HECC_CANGIF1);
 812         } else {
 813                 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
 814                 int_status = hecc_read(priv, HECC_CANGIF0);
 815         }
 816
 817         return IRQ_HANDLED;
 818 }
 819
 820 static int ti_hecc_open(struct net_device *ndev)
 821 {
 822         struct ti_hecc_priv *priv = netdev_priv(ndev);
 823         int err;
 824
 825         err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
 826                         ndev->name, ndev);
 827         if (err) {
 828                 netdev_err(ndev, "error requesting interrupt\n");
 829                 return err;
 830         }
 831
 832         ti_hecc_transceiver_switch(priv, 1);
 833
 834         /* Open common can device */
 835         err = open_candev(ndev);
 836         if (err) {
 837                 netdev_err(ndev, "open_candev() failed %d\n", err);
 838                 ti_hecc_transceiver_switch(priv, 0);
 839                 free_irq(ndev->irq, ndev);
 840                 return err;
 841         }
 842
 843         can_led_event(ndev, CAN_LED_EVENT_OPEN);
 844
 845         ti_hecc_start(ndev);
 846         napi_enable(&priv->napi);
 847         netif_start_queue(ndev);
 848
 849         return 0;
 850 }
 851
 852 static int ti_hecc_close(struct net_device *ndev)
 853 {
 854         struct ti_hecc_priv *priv = netdev_priv(ndev);
 855
 856         netif_stop_queue(ndev);
 857         napi_disable(&priv->napi);
 858         ti_hecc_stop(ndev);
 859         free_irq(ndev->irq, ndev);
 860         close_candev(ndev);
 861         ti_hecc_transceiver_switch(priv, 0);
 862
 863         can_led_event(ndev, CAN_LED_EVENT_STOP);
 864
 865         return 0;
 866 }
 867
 868 static const struct net_device_ops ti_hecc_netdev_ops = {
 869         .ndo_open               = ti_hecc_open,
 870         .ndo_stop               = ti_hecc_close,
 871         .ndo_start_xmit         = ti_hecc_xmit,
 872         .ndo_change_mtu         = can_change_mtu,
 873 };
 874
 875 static int ti_hecc_probe(struct platform_device *pdev)
 876 {
 877         struct net_device *ndev = (struct net_device *)0;
 878         struct ti_hecc_priv *priv;
 879         struct ti_hecc_platform_data *pdata;
 880         struct resource *mem, *irq;
 881         void __iomem *addr;
 882         int err = -ENODEV;
 883
 884         pdata = dev_get_platdata(&pdev->dev);
 885         if (!pdata) {
 886                 dev_err(&pdev->dev, "No platform data\n");
 887                 goto probe_exit;
 888         }
 889
 890         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 891         if (!mem) {
 892                 dev_err(&pdev->dev, "No mem resources\n");
 893                 goto probe_exit;
 894         }
 895         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 896         if (!irq) {
 897                 dev_err(&pdev->dev, "No irq resource\n");
 898                 goto probe_exit;
 899         }
 900         if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
 901                 dev_err(&pdev->dev, "HECC region already claimed\n");
 902                 err = -EBUSY;
 903                 goto probe_exit;
 904         }
 905         addr = ioremap(mem->start, resource_size(mem));
 906         if (!addr) {
 907                 dev_err(&pdev->dev, "ioremap failed\n");
 908                 err = -ENOMEM;
 909                 goto probe_exit_free_region;
 910         }
 911
 912         ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
 913         if (!ndev) {
 914                 dev_err(&pdev->dev, "alloc_candev failed\n");
 915                 err = -ENOMEM;
 916                 goto probe_exit_iounmap;
 917         }
 918
 919         priv = netdev_priv(ndev);
 920         priv->ndev = ndev;
 921         priv->base = addr;
 922         priv->scc_ram_offset = pdata->scc_ram_offset;
 923         priv->hecc_ram_offset = pdata->hecc_ram_offset;
 924         priv->mbx_offset = pdata->mbx_offset;
 925         priv->int_line = pdata->int_line;
 926         priv->transceiver_switch = pdata->transceiver_switch;
 927
 928         priv->can.bittiming_const = &ti_hecc_bittiming_const;
 929         priv->can.do_set_mode = ti_hecc_do_set_mode;
 930         priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
 931         priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
 932
 933         spin_lock_init(&priv->mbx_lock);
 934         ndev->irq = irq->start;
 935         ndev->flags |= IFF_ECHO;
 936         platform_set_drvdata(pdev, ndev);
 937         SET_NETDEV_DEV(ndev, &pdev->dev);
 938         ndev->netdev_ops = &ti_hecc_netdev_ops;
 939
 940         priv->clk = clk_get(&pdev->dev, "hecc_ck");
 941         if (IS_ERR(priv->clk)) {
 942                 dev_err(&pdev->dev, "No clock available\n");
 943                 err = PTR_ERR(priv->clk);
 944                 priv->clk = NULL;
 945                 goto probe_exit_candev;
 946         }
 947         priv->can.clock.freq = clk_get_rate(priv->clk);
 948         netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll,
 949                 HECC_DEF_NAPI_WEIGHT);
 950
 951         clk_enable(priv->clk);
 952         err = register_candev(ndev);
 953         if (err) {
 954                 dev_err(&pdev->dev, "register_candev() failed\n");
 955                 goto probe_exit_clk;
 956         }
 957
 958         devm_can_led_init(ndev);
 959
 960         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
 961                 priv->base, (u32) ndev->irq);
 962
 963         return 0;
 964
 965 probe_exit_clk:
 966         clk_put(priv->clk);
 967 probe_exit_candev:
 968         free_candev(ndev);
 969 probe_exit_iounmap:
 970         iounmap(addr);
 971 probe_exit_free_region:
 972         release_mem_region(mem->start, resource_size(mem));
 973 probe_exit:
 974         return err;
 975 }
 976
 977 static int ti_hecc_remove(struct platform_device *pdev)
 978 {
 979         struct resource *res;
 980         struct net_device *ndev = platform_get_drvdata(pdev);
 981         struct ti_hecc_priv *priv = netdev_priv(ndev);
 982
 983         unregister_candev(ndev);
 984         clk_disable(priv->clk);
 985         clk_put(priv->clk);
 986         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 987         iounmap(priv->base);
 988         release_mem_region(res->start, resource_size(res));
 989         free_candev(ndev);
 990
 991         return 0;
 992 }
 993
 994
 995 #ifdef CONFIG_PM
 996 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
 997 {
 998         struct net_device *dev = platform_get_drvdata(pdev);
 999         struct ti_hecc_priv *priv = netdev_priv(dev);
1000
1001         if (netif_running(dev)) {
1002                 netif_stop_queue(dev);
1003                 netif_device_detach(dev);
1004         }
1005
1006         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1007         priv->can.state = CAN_STATE_SLEEPING;
1008
1009         clk_disable(priv->clk);
1010
1011         return 0;
1012 }
1013
1014 static int ti_hecc_resume(struct platform_device *pdev)
1015 {
1016         struct net_device *dev = platform_get_drvdata(pdev);
1017         struct ti_hecc_priv *priv = netdev_priv(dev);
1018
1019         clk_enable(priv->clk);
1020
1021         hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1022         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1023
1024         if (netif_running(dev)) {
1025                 netif_device_attach(dev);
1026                 netif_start_queue(dev);
1027         }
1028
1029         return 0;
1030 }
1031 #else
1032 #define ti_hecc_suspend NULL
1033 #define ti_hecc_resume NULL
1034 #endif
1035
1036 /* TI HECC netdevice driver: platform driver structure */
1037 static struct platform_driver ti_hecc_driver = {
1038         .driver = {
1039                 .name    = DRV_NAME,
1040         },
1041         .probe = ti_hecc_probe,
1042         .remove = ti_hecc_remove,
1043         .suspend = ti_hecc_suspend,
1044         .resume = ti_hecc_resume,
1045 };
1046
1047 module_platform_driver(ti_hecc_driver);
1048
1049 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1050 MODULE_LICENSE("GPL v2");
1051 MODULE_DESCRIPTION(DRV_DESC);
1052 MODULE_ALIAS("platform:" DRV_NAME);