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[people/ms/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: QLogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
17 *
18 */
19
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
47 #include <net/ip.h>
48 #include <net/ipv6.h>
49 #include <net/tcp.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
58 #include <linux/io.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
62
63 #include "bnx2x.h"
64 #include "bnx2x_init.h"
65 #include "bnx2x_init_ops.h"
66 #include "bnx2x_cmn.h"
67 #include "bnx2x_vfpf.h"
68 #include "bnx2x_dcb.h"
69 #include "bnx2x_sp.h"
70 #include <linux/firmware.h>
71 #include "bnx2x_fw_file_hdr.h"
72 /* FW files */
73 #define FW_FILE_VERSION \
74 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
75 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
76 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
77 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
78 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
79 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
80 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
81
82 /* Time in jiffies before concluding the transmitter is hung */
83 #define TX_TIMEOUT (5*HZ)
84
85 static char version[] =
86 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
87 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
88
89 MODULE_AUTHOR("Eliezer Tamir");
90 MODULE_DESCRIPTION("QLogic "
91 "BCM57710/57711/57711E/"
92 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
93 "57840/57840_MF Driver");
94 MODULE_LICENSE("GPL");
95 MODULE_VERSION(DRV_MODULE_VERSION);
96 MODULE_FIRMWARE(FW_FILE_NAME_E1);
97 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
98 MODULE_FIRMWARE(FW_FILE_NAME_E2);
99
100 int bnx2x_num_queues;
101 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
102 MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
104
105 static int disable_tpa;
106 module_param(disable_tpa, int, S_IRUGO);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108
109 static int int_mode;
110 module_param(int_mode, int, S_IRUGO);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 "(1 INT#x; 2 MSI)");
113
114 static int dropless_fc;
115 module_param(dropless_fc, int, S_IRUGO);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117
118 static int mrrs = -1;
119 module_param(mrrs, int, S_IRUGO);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121
122 static int debug;
123 module_param(debug, int, S_IRUGO);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
125
126 static struct workqueue_struct *bnx2x_wq;
127 struct workqueue_struct *bnx2x_iov_wq;
128
129 struct bnx2x_mac_vals {
130 u32 xmac_addr;
131 u32 xmac_val;
132 u32 emac_addr;
133 u32 emac_val;
134 u32 umac_addr[2];
135 u32 umac_val[2];
136 u32 bmac_addr;
137 u32 bmac_val[2];
138 };
139
140 enum bnx2x_board_type {
141 BCM57710 = 0,
142 BCM57711,
143 BCM57711E,
144 BCM57712,
145 BCM57712_MF,
146 BCM57712_VF,
147 BCM57800,
148 BCM57800_MF,
149 BCM57800_VF,
150 BCM57810,
151 BCM57810_MF,
152 BCM57810_VF,
153 BCM57840_4_10,
154 BCM57840_2_20,
155 BCM57840_MF,
156 BCM57840_VF,
157 BCM57811,
158 BCM57811_MF,
159 BCM57840_O,
160 BCM57840_MFO,
161 BCM57811_VF
162 };
163
164 /* indexed by board_type, above */
165 static struct {
166 char *name;
167 } board_info[] = {
168 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
169 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
170 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
171 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
172 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
173 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
174 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
175 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
176 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
177 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
178 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
179 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
180 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
181 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
182 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
185 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
186 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
187 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
188 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
189 };
190
191 #ifndef PCI_DEVICE_ID_NX2_57710
192 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711
195 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57711E
198 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712
201 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
204 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
207 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800
210 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
213 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
216 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810
219 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
222 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57840_O
225 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
228 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
231 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
234 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
237 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
240 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
243 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811
246 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
249 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
250 #endif
251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
252 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
253 #endif
254
255 static const struct pci_device_id bnx2x_pci_tbl[] = {
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
269 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
274 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
276 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
280 { 0 }
281 };
282
283 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
284
285 /* Global resources for unloading a previously loaded device */
286 #define BNX2X_PREV_WAIT_NEEDED 1
287 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
288 static LIST_HEAD(bnx2x_prev_list);
289
290 /* Forward declaration */
291 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
292 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
293 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
294
295 /****************************************************************************
296 * General service functions
297 ****************************************************************************/
298
299 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
300
301 static void __storm_memset_dma_mapping(struct bnx2x *bp,
302 u32 addr, dma_addr_t mapping)
303 {
304 REG_WR(bp, addr, U64_LO(mapping));
305 REG_WR(bp, addr + 4, U64_HI(mapping));
306 }
307
308 static void storm_memset_spq_addr(struct bnx2x *bp,
309 dma_addr_t mapping, u16 abs_fid)
310 {
311 u32 addr = XSEM_REG_FAST_MEMORY +
312 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
313
314 __storm_memset_dma_mapping(bp, addr, mapping);
315 }
316
317 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
318 u16 pf_id)
319 {
320 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
321 pf_id);
322 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
323 pf_id);
324 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
325 pf_id);
326 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
327 pf_id);
328 }
329
330 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
331 u8 enable)
332 {
333 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
334 enable);
335 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
336 enable);
337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
338 enable);
339 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
340 enable);
341 }
342
343 static void storm_memset_eq_data(struct bnx2x *bp,
344 struct event_ring_data *eq_data,
345 u16 pfid)
346 {
347 size_t size = sizeof(struct event_ring_data);
348
349 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
350
351 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
352 }
353
354 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
355 u16 pfid)
356 {
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
358 REG_WR16(bp, addr, eq_prod);
359 }
360
361 /* used only at init
362 * locking is done by mcp
363 */
364 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
365 {
366 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
368 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
369 PCICFG_VENDOR_ID_OFFSET);
370 }
371
372 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
373 {
374 u32 val;
375
376 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
377 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
378 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
379 PCICFG_VENDOR_ID_OFFSET);
380
381 return val;
382 }
383
384 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
385 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
386 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
387 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
388 #define DMAE_DP_DST_NONE "dst_addr [none]"
389
390 static void bnx2x_dp_dmae(struct bnx2x *bp,
391 struct dmae_command *dmae, int msglvl)
392 {
393 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
394 int i;
395
396 switch (dmae->opcode & DMAE_COMMAND_DST) {
397 case DMAE_CMD_DST_PCI:
398 if (src_type == DMAE_CMD_SRC_PCI)
399 DP(msglvl, "DMAE: opcode 0x%08x\n"
400 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
401 "comp_addr [%x:%08x], comp_val 0x%08x\n",
402 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
403 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404 dmae->comp_addr_hi, dmae->comp_addr_lo,
405 dmae->comp_val);
406 else
407 DP(msglvl, "DMAE: opcode 0x%08x\n"
408 "src [%08x], len [%d*4], dst [%x:%08x]\n"
409 "comp_addr [%x:%08x], comp_val 0x%08x\n",
410 dmae->opcode, dmae->src_addr_lo >> 2,
411 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
412 dmae->comp_addr_hi, dmae->comp_addr_lo,
413 dmae->comp_val);
414 break;
415 case DMAE_CMD_DST_GRC:
416 if (src_type == DMAE_CMD_SRC_PCI)
417 DP(msglvl, "DMAE: opcode 0x%08x\n"
418 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
419 "comp_addr [%x:%08x], comp_val 0x%08x\n",
420 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
421 dmae->len, dmae->dst_addr_lo >> 2,
422 dmae->comp_addr_hi, dmae->comp_addr_lo,
423 dmae->comp_val);
424 else
425 DP(msglvl, "DMAE: opcode 0x%08x\n"
426 "src [%08x], len [%d*4], dst [%08x]\n"
427 "comp_addr [%x:%08x], comp_val 0x%08x\n",
428 dmae->opcode, dmae->src_addr_lo >> 2,
429 dmae->len, dmae->dst_addr_lo >> 2,
430 dmae->comp_addr_hi, dmae->comp_addr_lo,
431 dmae->comp_val);
432 break;
433 default:
434 if (src_type == DMAE_CMD_SRC_PCI)
435 DP(msglvl, "DMAE: opcode 0x%08x\n"
436 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
437 "comp_addr [%x:%08x] comp_val 0x%08x\n",
438 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
439 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
440 dmae->comp_val);
441 else
442 DP(msglvl, "DMAE: opcode 0x%08x\n"
443 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
444 "comp_addr [%x:%08x] comp_val 0x%08x\n",
445 dmae->opcode, dmae->src_addr_lo >> 2,
446 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
447 dmae->comp_val);
448 break;
449 }
450
451 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
452 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
453 i, *(((u32 *)dmae) + i));
454 }
455
456 /* copy command into DMAE command memory and set DMAE command go */
457 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
458 {
459 u32 cmd_offset;
460 int i;
461
462 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
463 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
464 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
465 }
466 REG_WR(bp, dmae_reg_go_c[idx], 1);
467 }
468
469 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
470 {
471 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
472 DMAE_CMD_C_ENABLE);
473 }
474
475 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
476 {
477 return opcode & ~DMAE_CMD_SRC_RESET;
478 }
479
480 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
481 bool with_comp, u8 comp_type)
482 {
483 u32 opcode = 0;
484
485 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
486 (dst_type << DMAE_COMMAND_DST_SHIFT));
487
488 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
489
490 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
491 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
492 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
493 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
494
495 #ifdef __BIG_ENDIAN
496 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
497 #else
498 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
499 #endif
500 if (with_comp)
501 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
502 return opcode;
503 }
504
505 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
506 struct dmae_command *dmae,
507 u8 src_type, u8 dst_type)
508 {
509 memset(dmae, 0, sizeof(struct dmae_command));
510
511 /* set the opcode */
512 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
513 true, DMAE_COMP_PCI);
514
515 /* fill in the completion parameters */
516 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
517 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
518 dmae->comp_val = DMAE_COMP_VAL;
519 }
520
521 /* issue a dmae command over the init-channel and wait for completion */
522 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
523 u32 *comp)
524 {
525 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
526 int rc = 0;
527
528 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
529
530 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
531 * as long as this code is called both from syscall context and
532 * from ndo_set_rx_mode() flow that may be called from BH.
533 */
534
535 spin_lock_bh(&bp->dmae_lock);
536
537 /* reset completion */
538 *comp = 0;
539
540 /* post the command on the channel used for initializations */
541 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
542
543 /* wait for completion */
544 udelay(5);
545 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
546
547 if (!cnt ||
548 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
549 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
550 BNX2X_ERR("DMAE timeout!\n");
551 rc = DMAE_TIMEOUT;
552 goto unlock;
553 }
554 cnt--;
555 udelay(50);
556 }
557 if (*comp & DMAE_PCI_ERR_FLAG) {
558 BNX2X_ERR("DMAE PCI error!\n");
559 rc = DMAE_PCI_ERROR;
560 }
561
562 unlock:
563
564 spin_unlock_bh(&bp->dmae_lock);
565
566 return rc;
567 }
568
569 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
570 u32 len32)
571 {
572 int rc;
573 struct dmae_command dmae;
574
575 if (!bp->dmae_ready) {
576 u32 *data = bnx2x_sp(bp, wb_data[0]);
577
578 if (CHIP_IS_E1(bp))
579 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
580 else
581 bnx2x_init_str_wr(bp, dst_addr, data, len32);
582 return;
583 }
584
585 /* set opcode and fixed command fields */
586 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
587
588 /* fill in addresses and len */
589 dmae.src_addr_lo = U64_LO(dma_addr);
590 dmae.src_addr_hi = U64_HI(dma_addr);
591 dmae.dst_addr_lo = dst_addr >> 2;
592 dmae.dst_addr_hi = 0;
593 dmae.len = len32;
594
595 /* issue the command and wait for completion */
596 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
597 if (rc) {
598 BNX2X_ERR("DMAE returned failure %d\n", rc);
599 #ifdef BNX2X_STOP_ON_ERROR
600 bnx2x_panic();
601 #endif
602 }
603 }
604
605 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
606 {
607 int rc;
608 struct dmae_command dmae;
609
610 if (!bp->dmae_ready) {
611 u32 *data = bnx2x_sp(bp, wb_data[0]);
612 int i;
613
614 if (CHIP_IS_E1(bp))
615 for (i = 0; i < len32; i++)
616 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
617 else
618 for (i = 0; i < len32; i++)
619 data[i] = REG_RD(bp, src_addr + i*4);
620
621 return;
622 }
623
624 /* set opcode and fixed command fields */
625 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
626
627 /* fill in addresses and len */
628 dmae.src_addr_lo = src_addr >> 2;
629 dmae.src_addr_hi = 0;
630 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
631 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
632 dmae.len = len32;
633
634 /* issue the command and wait for completion */
635 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
636 if (rc) {
637 BNX2X_ERR("DMAE returned failure %d\n", rc);
638 #ifdef BNX2X_STOP_ON_ERROR
639 bnx2x_panic();
640 #endif
641 }
642 }
643
644 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
645 u32 addr, u32 len)
646 {
647 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
648 int offset = 0;
649
650 while (len > dmae_wr_max) {
651 bnx2x_write_dmae(bp, phys_addr + offset,
652 addr + offset, dmae_wr_max);
653 offset += dmae_wr_max * 4;
654 len -= dmae_wr_max;
655 }
656
657 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
658 }
659
660 enum storms {
661 XSTORM,
662 TSTORM,
663 CSTORM,
664 USTORM,
665 MAX_STORMS
666 };
667
668 #define STORMS_NUM 4
669 #define REGS_IN_ENTRY 4
670
671 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
672 enum storms storm,
673 int entry)
674 {
675 switch (storm) {
676 case XSTORM:
677 return XSTORM_ASSERT_LIST_OFFSET(entry);
678 case TSTORM:
679 return TSTORM_ASSERT_LIST_OFFSET(entry);
680 case CSTORM:
681 return CSTORM_ASSERT_LIST_OFFSET(entry);
682 case USTORM:
683 return USTORM_ASSERT_LIST_OFFSET(entry);
684 case MAX_STORMS:
685 default:
686 BNX2X_ERR("unknown storm\n");
687 }
688 return -EINVAL;
689 }
690
691 static int bnx2x_mc_assert(struct bnx2x *bp)
692 {
693 char last_idx;
694 int i, j, rc = 0;
695 enum storms storm;
696 u32 regs[REGS_IN_ENTRY];
697 u32 bar_storm_intmem[STORMS_NUM] = {
698 BAR_XSTRORM_INTMEM,
699 BAR_TSTRORM_INTMEM,
700 BAR_CSTRORM_INTMEM,
701 BAR_USTRORM_INTMEM
702 };
703 u32 storm_assert_list_index[STORMS_NUM] = {
704 XSTORM_ASSERT_LIST_INDEX_OFFSET,
705 TSTORM_ASSERT_LIST_INDEX_OFFSET,
706 CSTORM_ASSERT_LIST_INDEX_OFFSET,
707 USTORM_ASSERT_LIST_INDEX_OFFSET
708 };
709 char *storms_string[STORMS_NUM] = {
710 "XSTORM",
711 "TSTORM",
712 "CSTORM",
713 "USTORM"
714 };
715
716 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
717 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
718 storm_assert_list_index[storm]);
719 if (last_idx)
720 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
721 storms_string[storm], last_idx);
722
723 /* print the asserts */
724 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
725 /* read a single assert entry */
726 for (j = 0; j < REGS_IN_ENTRY; j++)
727 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
728 bnx2x_get_assert_list_entry(bp,
729 storm,
730 i) +
731 sizeof(u32) * j);
732
733 /* log entry if it contains a valid assert */
734 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
735 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
736 storms_string[storm], i, regs[3],
737 regs[2], regs[1], regs[0]);
738 rc++;
739 } else {
740 break;
741 }
742 }
743 }
744
745 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
746 CHIP_IS_E1(bp) ? "everest1" :
747 CHIP_IS_E1H(bp) ? "everest1h" :
748 CHIP_IS_E2(bp) ? "everest2" : "everest3",
749 BCM_5710_FW_MAJOR_VERSION,
750 BCM_5710_FW_MINOR_VERSION,
751 BCM_5710_FW_REVISION_VERSION);
752
753 return rc;
754 }
755
756 #define MCPR_TRACE_BUFFER_SIZE (0x800)
757 #define SCRATCH_BUFFER_SIZE(bp) \
758 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
759
760 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
761 {
762 u32 addr, val;
763 u32 mark, offset;
764 __be32 data[9];
765 int word;
766 u32 trace_shmem_base;
767 if (BP_NOMCP(bp)) {
768 BNX2X_ERR("NO MCP - can not dump\n");
769 return;
770 }
771 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
772 (bp->common.bc_ver & 0xff0000) >> 16,
773 (bp->common.bc_ver & 0xff00) >> 8,
774 (bp->common.bc_ver & 0xff));
775
776 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
777 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
778 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
779
780 if (BP_PATH(bp) == 0)
781 trace_shmem_base = bp->common.shmem_base;
782 else
783 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
784
785 /* sanity */
786 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
787 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
788 SCRATCH_BUFFER_SIZE(bp)) {
789 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
790 trace_shmem_base);
791 return;
792 }
793
794 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
795
796 /* validate TRCB signature */
797 mark = REG_RD(bp, addr);
798 if (mark != MFW_TRACE_SIGNATURE) {
799 BNX2X_ERR("Trace buffer signature is missing.");
800 return ;
801 }
802
803 /* read cyclic buffer pointer */
804 addr += 4;
805 mark = REG_RD(bp, addr);
806 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
807 if (mark >= trace_shmem_base || mark < addr + 4) {
808 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
809 return;
810 }
811 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
812
813 printk("%s", lvl);
814
815 /* dump buffer after the mark */
816 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
817 for (word = 0; word < 8; word++)
818 data[word] = htonl(REG_RD(bp, offset + 4*word));
819 data[8] = 0x0;
820 pr_cont("%s", (char *)data);
821 }
822
823 /* dump buffer before the mark */
824 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
825 for (word = 0; word < 8; word++)
826 data[word] = htonl(REG_RD(bp, offset + 4*word));
827 data[8] = 0x0;
828 pr_cont("%s", (char *)data);
829 }
830 printk("%s" "end of fw dump\n", lvl);
831 }
832
833 static void bnx2x_fw_dump(struct bnx2x *bp)
834 {
835 bnx2x_fw_dump_lvl(bp, KERN_ERR);
836 }
837
838 static void bnx2x_hc_int_disable(struct bnx2x *bp)
839 {
840 int port = BP_PORT(bp);
841 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
842 u32 val = REG_RD(bp, addr);
843
844 /* in E1 we must use only PCI configuration space to disable
845 * MSI/MSIX capability
846 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
847 */
848 if (CHIP_IS_E1(bp)) {
849 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
850 * Use mask register to prevent from HC sending interrupts
851 * after we exit the function
852 */
853 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
854
855 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
856 HC_CONFIG_0_REG_INT_LINE_EN_0 |
857 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
858 } else
859 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
861 HC_CONFIG_0_REG_INT_LINE_EN_0 |
862 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
863
864 DP(NETIF_MSG_IFDOWN,
865 "write %x to HC %d (addr 0x%x)\n",
866 val, port, addr);
867
868 /* flush all outstanding writes */
869 mmiowb();
870
871 REG_WR(bp, addr, val);
872 if (REG_RD(bp, addr) != val)
873 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
874 }
875
876 static void bnx2x_igu_int_disable(struct bnx2x *bp)
877 {
878 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
879
880 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
881 IGU_PF_CONF_INT_LINE_EN |
882 IGU_PF_CONF_ATTN_BIT_EN);
883
884 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
885
886 /* flush all outstanding writes */
887 mmiowb();
888
889 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
890 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
891 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
892 }
893
894 static void bnx2x_int_disable(struct bnx2x *bp)
895 {
896 if (bp->common.int_block == INT_BLOCK_HC)
897 bnx2x_hc_int_disable(bp);
898 else
899 bnx2x_igu_int_disable(bp);
900 }
901
902 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
903 {
904 int i;
905 u16 j;
906 struct hc_sp_status_block_data sp_sb_data;
907 int func = BP_FUNC(bp);
908 #ifdef BNX2X_STOP_ON_ERROR
909 u16 start = 0, end = 0;
910 u8 cos;
911 #endif
912 if (IS_PF(bp) && disable_int)
913 bnx2x_int_disable(bp);
914
915 bp->stats_state = STATS_STATE_DISABLED;
916 bp->eth_stats.unrecoverable_error++;
917 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
918
919 BNX2X_ERR("begin crash dump -----------------\n");
920
921 /* Indices */
922 /* Common */
923 if (IS_PF(bp)) {
924 struct host_sp_status_block *def_sb = bp->def_status_blk;
925 int data_size, cstorm_offset;
926
927 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
928 bp->def_idx, bp->def_att_idx, bp->attn_state,
929 bp->spq_prod_idx, bp->stats_counter);
930 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
931 def_sb->atten_status_block.attn_bits,
932 def_sb->atten_status_block.attn_bits_ack,
933 def_sb->atten_status_block.status_block_id,
934 def_sb->atten_status_block.attn_bits_index);
935 BNX2X_ERR(" def (");
936 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
937 pr_cont("0x%x%s",
938 def_sb->sp_sb.index_values[i],
939 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
940
941 data_size = sizeof(struct hc_sp_status_block_data) /
942 sizeof(u32);
943 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
944 for (i = 0; i < data_size; i++)
945 *((u32 *)&sp_sb_data + i) =
946 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
947 i * sizeof(u32));
948
949 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
950 sp_sb_data.igu_sb_id,
951 sp_sb_data.igu_seg_id,
952 sp_sb_data.p_func.pf_id,
953 sp_sb_data.p_func.vnic_id,
954 sp_sb_data.p_func.vf_id,
955 sp_sb_data.p_func.vf_valid,
956 sp_sb_data.state);
957 }
958
959 for_each_eth_queue(bp, i) {
960 struct bnx2x_fastpath *fp = &bp->fp[i];
961 int loop;
962 struct hc_status_block_data_e2 sb_data_e2;
963 struct hc_status_block_data_e1x sb_data_e1x;
964 struct hc_status_block_sm *hc_sm_p =
965 CHIP_IS_E1x(bp) ?
966 sb_data_e1x.common.state_machine :
967 sb_data_e2.common.state_machine;
968 struct hc_index_data *hc_index_p =
969 CHIP_IS_E1x(bp) ?
970 sb_data_e1x.index_data :
971 sb_data_e2.index_data;
972 u8 data_size, cos;
973 u32 *sb_data_p;
974 struct bnx2x_fp_txdata txdata;
975
976 if (!bp->fp)
977 break;
978
979 if (!fp->rx_cons_sb)
980 continue;
981
982 /* Rx */
983 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
984 i, fp->rx_bd_prod, fp->rx_bd_cons,
985 fp->rx_comp_prod,
986 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
987 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
988 fp->rx_sge_prod, fp->last_max_sge,
989 le16_to_cpu(fp->fp_hc_idx));
990
991 /* Tx */
992 for_each_cos_in_tx_queue(fp, cos)
993 {
994 if (!fp->txdata_ptr[cos])
995 break;
996
997 txdata = *fp->txdata_ptr[cos];
998
999 if (!txdata.tx_cons_sb)
1000 continue;
1001
1002 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1003 i, txdata.tx_pkt_prod,
1004 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1005 txdata.tx_bd_cons,
1006 le16_to_cpu(*txdata.tx_cons_sb));
1007 }
1008
1009 loop = CHIP_IS_E1x(bp) ?
1010 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1011
1012 /* host sb data */
1013
1014 if (IS_FCOE_FP(fp))
1015 continue;
1016
1017 BNX2X_ERR(" run indexes (");
1018 for (j = 0; j < HC_SB_MAX_SM; j++)
1019 pr_cont("0x%x%s",
1020 fp->sb_running_index[j],
1021 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1022
1023 BNX2X_ERR(" indexes (");
1024 for (j = 0; j < loop; j++)
1025 pr_cont("0x%x%s",
1026 fp->sb_index_values[j],
1027 (j == loop - 1) ? ")" : " ");
1028
1029 /* VF cannot access FW refelection for status block */
1030 if (IS_VF(bp))
1031 continue;
1032
1033 /* fw sb data */
1034 data_size = CHIP_IS_E1x(bp) ?
1035 sizeof(struct hc_status_block_data_e1x) :
1036 sizeof(struct hc_status_block_data_e2);
1037 data_size /= sizeof(u32);
1038 sb_data_p = CHIP_IS_E1x(bp) ?
1039 (u32 *)&sb_data_e1x :
1040 (u32 *)&sb_data_e2;
1041 /* copy sb data in here */
1042 for (j = 0; j < data_size; j++)
1043 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1044 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1045 j * sizeof(u32));
1046
1047 if (!CHIP_IS_E1x(bp)) {
1048 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1049 sb_data_e2.common.p_func.pf_id,
1050 sb_data_e2.common.p_func.vf_id,
1051 sb_data_e2.common.p_func.vf_valid,
1052 sb_data_e2.common.p_func.vnic_id,
1053 sb_data_e2.common.same_igu_sb_1b,
1054 sb_data_e2.common.state);
1055 } else {
1056 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1057 sb_data_e1x.common.p_func.pf_id,
1058 sb_data_e1x.common.p_func.vf_id,
1059 sb_data_e1x.common.p_func.vf_valid,
1060 sb_data_e1x.common.p_func.vnic_id,
1061 sb_data_e1x.common.same_igu_sb_1b,
1062 sb_data_e1x.common.state);
1063 }
1064
1065 /* SB_SMs data */
1066 for (j = 0; j < HC_SB_MAX_SM; j++) {
1067 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1068 j, hc_sm_p[j].__flags,
1069 hc_sm_p[j].igu_sb_id,
1070 hc_sm_p[j].igu_seg_id,
1071 hc_sm_p[j].time_to_expire,
1072 hc_sm_p[j].timer_value);
1073 }
1074
1075 /* Indices data */
1076 for (j = 0; j < loop; j++) {
1077 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1078 hc_index_p[j].flags,
1079 hc_index_p[j].timeout);
1080 }
1081 }
1082
1083 #ifdef BNX2X_STOP_ON_ERROR
1084 if (IS_PF(bp)) {
1085 /* event queue */
1086 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1087 for (i = 0; i < NUM_EQ_DESC; i++) {
1088 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1089
1090 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1091 i, bp->eq_ring[i].message.opcode,
1092 bp->eq_ring[i].message.error);
1093 BNX2X_ERR("data: %x %x %x\n",
1094 data[0], data[1], data[2]);
1095 }
1096 }
1097
1098 /* Rings */
1099 /* Rx */
1100 for_each_valid_rx_queue(bp, i) {
1101 struct bnx2x_fastpath *fp = &bp->fp[i];
1102
1103 if (!bp->fp)
1104 break;
1105
1106 if (!fp->rx_cons_sb)
1107 continue;
1108
1109 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1110 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1111 for (j = start; j != end; j = RX_BD(j + 1)) {
1112 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1113 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1114
1115 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1116 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1117 }
1118
1119 start = RX_SGE(fp->rx_sge_prod);
1120 end = RX_SGE(fp->last_max_sge);
1121 for (j = start; j != end; j = RX_SGE(j + 1)) {
1122 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1123 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1124
1125 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1126 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1127 }
1128
1129 start = RCQ_BD(fp->rx_comp_cons - 10);
1130 end = RCQ_BD(fp->rx_comp_cons + 503);
1131 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1132 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1133
1134 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1135 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1136 }
1137 }
1138
1139 /* Tx */
1140 for_each_valid_tx_queue(bp, i) {
1141 struct bnx2x_fastpath *fp = &bp->fp[i];
1142
1143 if (!bp->fp)
1144 break;
1145
1146 for_each_cos_in_tx_queue(fp, cos) {
1147 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1148
1149 if (!fp->txdata_ptr[cos])
1150 break;
1151
1152 if (!txdata->tx_cons_sb)
1153 continue;
1154
1155 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1156 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1157 for (j = start; j != end; j = TX_BD(j + 1)) {
1158 struct sw_tx_bd *sw_bd =
1159 &txdata->tx_buf_ring[j];
1160
1161 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1162 i, cos, j, sw_bd->skb,
1163 sw_bd->first_bd);
1164 }
1165
1166 start = TX_BD(txdata->tx_bd_cons - 10);
1167 end = TX_BD(txdata->tx_bd_cons + 254);
1168 for (j = start; j != end; j = TX_BD(j + 1)) {
1169 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1170
1171 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1172 i, cos, j, tx_bd[0], tx_bd[1],
1173 tx_bd[2], tx_bd[3]);
1174 }
1175 }
1176 }
1177 #endif
1178 if (IS_PF(bp)) {
1179 bnx2x_fw_dump(bp);
1180 bnx2x_mc_assert(bp);
1181 }
1182 BNX2X_ERR("end crash dump -----------------\n");
1183 }
1184
1185 /*
1186 * FLR Support for E2
1187 *
1188 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1189 * initialization.
1190 */
1191 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1192 #define FLR_WAIT_INTERVAL 50 /* usec */
1193 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1194
1195 struct pbf_pN_buf_regs {
1196 int pN;
1197 u32 init_crd;
1198 u32 crd;
1199 u32 crd_freed;
1200 };
1201
1202 struct pbf_pN_cmd_regs {
1203 int pN;
1204 u32 lines_occup;
1205 u32 lines_freed;
1206 };
1207
1208 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1209 struct pbf_pN_buf_regs *regs,
1210 u32 poll_count)
1211 {
1212 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1213 u32 cur_cnt = poll_count;
1214
1215 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1216 crd = crd_start = REG_RD(bp, regs->crd);
1217 init_crd = REG_RD(bp, regs->init_crd);
1218
1219 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1220 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1221 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1222
1223 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1224 (init_crd - crd_start))) {
1225 if (cur_cnt--) {
1226 udelay(FLR_WAIT_INTERVAL);
1227 crd = REG_RD(bp, regs->crd);
1228 crd_freed = REG_RD(bp, regs->crd_freed);
1229 } else {
1230 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1231 regs->pN);
1232 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1233 regs->pN, crd);
1234 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1235 regs->pN, crd_freed);
1236 break;
1237 }
1238 }
1239 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1240 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1241 }
1242
1243 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1244 struct pbf_pN_cmd_regs *regs,
1245 u32 poll_count)
1246 {
1247 u32 occup, to_free, freed, freed_start;
1248 u32 cur_cnt = poll_count;
1249
1250 occup = to_free = REG_RD(bp, regs->lines_occup);
1251 freed = freed_start = REG_RD(bp, regs->lines_freed);
1252
1253 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1254 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1255
1256 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1257 if (cur_cnt--) {
1258 udelay(FLR_WAIT_INTERVAL);
1259 occup = REG_RD(bp, regs->lines_occup);
1260 freed = REG_RD(bp, regs->lines_freed);
1261 } else {
1262 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1263 regs->pN);
1264 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1265 regs->pN, occup);
1266 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1267 regs->pN, freed);
1268 break;
1269 }
1270 }
1271 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1272 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1273 }
1274
1275 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1276 u32 expected, u32 poll_count)
1277 {
1278 u32 cur_cnt = poll_count;
1279 u32 val;
1280
1281 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1282 udelay(FLR_WAIT_INTERVAL);
1283
1284 return val;
1285 }
1286
1287 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1288 char *msg, u32 poll_cnt)
1289 {
1290 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1291 if (val != 0) {
1292 BNX2X_ERR("%s usage count=%d\n", msg, val);
1293 return 1;
1294 }
1295 return 0;
1296 }
1297
1298 /* Common routines with VF FLR cleanup */
1299 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1300 {
1301 /* adjust polling timeout */
1302 if (CHIP_REV_IS_EMUL(bp))
1303 return FLR_POLL_CNT * 2000;
1304
1305 if (CHIP_REV_IS_FPGA(bp))
1306 return FLR_POLL_CNT * 120;
1307
1308 return FLR_POLL_CNT;
1309 }
1310
1311 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1312 {
1313 struct pbf_pN_cmd_regs cmd_regs[] = {
1314 {0, (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_OCCUPANCY_Q0 :
1316 PBF_REG_P0_TQ_OCCUPANCY,
1317 (CHIP_IS_E3B0(bp)) ?
1318 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1319 PBF_REG_P0_TQ_LINES_FREED_CNT},
1320 {1, (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_TQ_OCCUPANCY_Q1 :
1322 PBF_REG_P1_TQ_OCCUPANCY,
1323 (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1325 PBF_REG_P1_TQ_LINES_FREED_CNT},
1326 {4, (CHIP_IS_E3B0(bp)) ?
1327 PBF_REG_TQ_OCCUPANCY_LB_Q :
1328 PBF_REG_P4_TQ_OCCUPANCY,
1329 (CHIP_IS_E3B0(bp)) ?
1330 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1331 PBF_REG_P4_TQ_LINES_FREED_CNT}
1332 };
1333
1334 struct pbf_pN_buf_regs buf_regs[] = {
1335 {0, (CHIP_IS_E3B0(bp)) ?
1336 PBF_REG_INIT_CRD_Q0 :
1337 PBF_REG_P0_INIT_CRD ,
1338 (CHIP_IS_E3B0(bp)) ?
1339 PBF_REG_CREDIT_Q0 :
1340 PBF_REG_P0_CREDIT,
1341 (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1343 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1344 {1, (CHIP_IS_E3B0(bp)) ?
1345 PBF_REG_INIT_CRD_Q1 :
1346 PBF_REG_P1_INIT_CRD,
1347 (CHIP_IS_E3B0(bp)) ?
1348 PBF_REG_CREDIT_Q1 :
1349 PBF_REG_P1_CREDIT,
1350 (CHIP_IS_E3B0(bp)) ?
1351 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1352 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1353 {4, (CHIP_IS_E3B0(bp)) ?
1354 PBF_REG_INIT_CRD_LB_Q :
1355 PBF_REG_P4_INIT_CRD,
1356 (CHIP_IS_E3B0(bp)) ?
1357 PBF_REG_CREDIT_LB_Q :
1358 PBF_REG_P4_CREDIT,
1359 (CHIP_IS_E3B0(bp)) ?
1360 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1361 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1362 };
1363
1364 int i;
1365
1366 /* Verify the command queues are flushed P0, P1, P4 */
1367 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1368 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1369
1370 /* Verify the transmission buffers are flushed P0, P1, P4 */
1371 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1372 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1373 }
1374
1375 #define OP_GEN_PARAM(param) \
1376 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1377
1378 #define OP_GEN_TYPE(type) \
1379 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1380
1381 #define OP_GEN_AGG_VECT(index) \
1382 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1383
1384 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1385 {
1386 u32 op_gen_command = 0;
1387 u32 comp_addr = BAR_CSTRORM_INTMEM +
1388 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1389 int ret = 0;
1390
1391 if (REG_RD(bp, comp_addr)) {
1392 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1393 return 1;
1394 }
1395
1396 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1397 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1398 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1399 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1400
1401 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1402 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1403
1404 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1405 BNX2X_ERR("FW final cleanup did not succeed\n");
1406 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1407 (REG_RD(bp, comp_addr)));
1408 bnx2x_panic();
1409 return 1;
1410 }
1411 /* Zero completion for next FLR */
1412 REG_WR(bp, comp_addr, 0);
1413
1414 return ret;
1415 }
1416
1417 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1418 {
1419 u16 status;
1420
1421 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1422 return status & PCI_EXP_DEVSTA_TRPND;
1423 }
1424
1425 /* PF FLR specific routines
1426 */
1427 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1428 {
1429 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1430 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1431 CFC_REG_NUM_LCIDS_INSIDE_PF,
1432 "CFC PF usage counter timed out",
1433 poll_cnt))
1434 return 1;
1435
1436 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1437 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438 DORQ_REG_PF_USAGE_CNT,
1439 "DQ PF usage counter timed out",
1440 poll_cnt))
1441 return 1;
1442
1443 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1444 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1446 "QM PF usage counter timed out",
1447 poll_cnt))
1448 return 1;
1449
1450 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1453 "Timers VNIC usage counter timed out",
1454 poll_cnt))
1455 return 1;
1456 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1457 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1458 "Timers NUM_SCANS usage counter timed out",
1459 poll_cnt))
1460 return 1;
1461
1462 /* Wait DMAE PF usage counter to zero */
1463 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1464 dmae_reg_go_c[INIT_DMAE_C(bp)],
1465 "DMAE command register timed out",
1466 poll_cnt))
1467 return 1;
1468
1469 return 0;
1470 }
1471
1472 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1473 {
1474 u32 val;
1475
1476 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1477 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1478
1479 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1480 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1481
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1483 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1484
1485 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1486 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1487
1488 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1489 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1490
1491 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1492 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1493
1494 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1495 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1496
1497 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1498 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1499 val);
1500 }
1501
1502 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1503 {
1504 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1505
1506 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1507
1508 /* Re-enable PF target read access */
1509 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1510
1511 /* Poll HW usage counters */
1512 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1513 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1514 return -EBUSY;
1515
1516 /* Zero the igu 'trailing edge' and 'leading edge' */
1517
1518 /* Send the FW cleanup command */
1519 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1520 return -EBUSY;
1521
1522 /* ATC cleanup */
1523
1524 /* Verify TX hw is flushed */
1525 bnx2x_tx_hw_flushed(bp, poll_cnt);
1526
1527 /* Wait 100ms (not adjusted according to platform) */
1528 msleep(100);
1529
1530 /* Verify no pending pci transactions */
1531 if (bnx2x_is_pcie_pending(bp->pdev))
1532 BNX2X_ERR("PCIE Transactions still pending\n");
1533
1534 /* Debug */
1535 bnx2x_hw_enable_status(bp);
1536
1537 /*
1538 * Master enable - Due to WB DMAE writes performed before this
1539 * register is re-initialized as part of the regular function init
1540 */
1541 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1542
1543 return 0;
1544 }
1545
1546 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1547 {
1548 int port = BP_PORT(bp);
1549 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1550 u32 val = REG_RD(bp, addr);
1551 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1552 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1553 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1554
1555 if (msix) {
1556 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1557 HC_CONFIG_0_REG_INT_LINE_EN_0);
1558 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1559 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1560 if (single_msix)
1561 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1562 } else if (msi) {
1563 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1564 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1565 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1566 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567 } else {
1568 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1571 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1572
1573 if (!CHIP_IS_E1(bp)) {
1574 DP(NETIF_MSG_IFUP,
1575 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1576
1577 REG_WR(bp, addr, val);
1578
1579 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1580 }
1581 }
1582
1583 if (CHIP_IS_E1(bp))
1584 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1585
1586 DP(NETIF_MSG_IFUP,
1587 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1588 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1589
1590 REG_WR(bp, addr, val);
1591 /*
1592 * Ensure that HC_CONFIG is written before leading/trailing edge config
1593 */
1594 mmiowb();
1595 barrier();
1596
1597 if (!CHIP_IS_E1(bp)) {
1598 /* init leading/trailing edge */
1599 if (IS_MF(bp)) {
1600 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1601 if (bp->port.pmf)
1602 /* enable nig and gpio3 attention */
1603 val |= 0x1100;
1604 } else
1605 val = 0xffff;
1606
1607 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1608 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1609 }
1610
1611 /* Make sure that interrupts are indeed enabled from here on */
1612 mmiowb();
1613 }
1614
1615 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1616 {
1617 u32 val;
1618 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1619 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1620 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1621
1622 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1623
1624 if (msix) {
1625 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1626 IGU_PF_CONF_SINGLE_ISR_EN);
1627 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1628 IGU_PF_CONF_ATTN_BIT_EN);
1629
1630 if (single_msix)
1631 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1632 } else if (msi) {
1633 val &= ~IGU_PF_CONF_INT_LINE_EN;
1634 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1635 IGU_PF_CONF_ATTN_BIT_EN |
1636 IGU_PF_CONF_SINGLE_ISR_EN);
1637 } else {
1638 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1639 val |= (IGU_PF_CONF_INT_LINE_EN |
1640 IGU_PF_CONF_ATTN_BIT_EN |
1641 IGU_PF_CONF_SINGLE_ISR_EN);
1642 }
1643
1644 /* Clean previous status - need to configure igu prior to ack*/
1645 if ((!msix) || single_msix) {
1646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1647 bnx2x_ack_int(bp);
1648 }
1649
1650 val |= IGU_PF_CONF_FUNC_EN;
1651
1652 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1653 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1654
1655 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1656
1657 if (val & IGU_PF_CONF_INT_LINE_EN)
1658 pci_intx(bp->pdev, true);
1659
1660 barrier();
1661
1662 /* init leading/trailing edge */
1663 if (IS_MF(bp)) {
1664 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1665 if (bp->port.pmf)
1666 /* enable nig and gpio3 attention */
1667 val |= 0x1100;
1668 } else
1669 val = 0xffff;
1670
1671 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1672 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1673
1674 /* Make sure that interrupts are indeed enabled from here on */
1675 mmiowb();
1676 }
1677
1678 void bnx2x_int_enable(struct bnx2x *bp)
1679 {
1680 if (bp->common.int_block == INT_BLOCK_HC)
1681 bnx2x_hc_int_enable(bp);
1682 else
1683 bnx2x_igu_int_enable(bp);
1684 }
1685
1686 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1687 {
1688 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1689 int i, offset;
1690
1691 if (disable_hw)
1692 /* prevent the HW from sending interrupts */
1693 bnx2x_int_disable(bp);
1694
1695 /* make sure all ISRs are done */
1696 if (msix) {
1697 synchronize_irq(bp->msix_table[0].vector);
1698 offset = 1;
1699 if (CNIC_SUPPORT(bp))
1700 offset++;
1701 for_each_eth_queue(bp, i)
1702 synchronize_irq(bp->msix_table[offset++].vector);
1703 } else
1704 synchronize_irq(bp->pdev->irq);
1705
1706 /* make sure sp_task is not running */
1707 cancel_delayed_work(&bp->sp_task);
1708 cancel_delayed_work(&bp->period_task);
1709 flush_workqueue(bnx2x_wq);
1710 }
1711
1712 /* fast path */
1713
1714 /*
1715 * General service functions
1716 */
1717
1718 /* Return true if succeeded to acquire the lock */
1719 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1720 {
1721 u32 lock_status;
1722 u32 resource_bit = (1 << resource);
1723 int func = BP_FUNC(bp);
1724 u32 hw_lock_control_reg;
1725
1726 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727 "Trying to take a lock on resource %d\n", resource);
1728
1729 /* Validating that the resource is within range */
1730 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1731 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1732 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1733 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1734 return false;
1735 }
1736
1737 if (func <= 5)
1738 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1739 else
1740 hw_lock_control_reg =
1741 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1742
1743 /* Try to acquire the lock */
1744 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1745 lock_status = REG_RD(bp, hw_lock_control_reg);
1746 if (lock_status & resource_bit)
1747 return true;
1748
1749 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1750 "Failed to get a lock on resource %d\n", resource);
1751 return false;
1752 }
1753
1754 /**
1755 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1756 *
1757 * @bp: driver handle
1758 *
1759 * Returns the recovery leader resource id according to the engine this function
1760 * belongs to. Currently only only 2 engines is supported.
1761 */
1762 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1763 {
1764 if (BP_PATH(bp))
1765 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1766 else
1767 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1768 }
1769
1770 /**
1771 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1772 *
1773 * @bp: driver handle
1774 *
1775 * Tries to acquire a leader lock for current engine.
1776 */
1777 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1778 {
1779 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1780 }
1781
1782 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1783
1784 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1785 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1786 {
1787 /* Set the interrupt occurred bit for the sp-task to recognize it
1788 * must ack the interrupt and transition according to the IGU
1789 * state machine.
1790 */
1791 atomic_set(&bp->interrupt_occurred, 1);
1792
1793 /* The sp_task must execute only after this bit
1794 * is set, otherwise we will get out of sync and miss all
1795 * further interrupts. Hence, the barrier.
1796 */
1797 smp_wmb();
1798
1799 /* schedule sp_task to workqueue */
1800 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1801 }
1802
1803 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1804 {
1805 struct bnx2x *bp = fp->bp;
1806 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1807 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1808 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1809 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1810
1811 DP(BNX2X_MSG_SP,
1812 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1813 fp->index, cid, command, bp->state,
1814 rr_cqe->ramrod_cqe.ramrod_type);
1815
1816 /* If cid is within VF range, replace the slowpath object with the
1817 * one corresponding to this VF
1818 */
1819 if (cid >= BNX2X_FIRST_VF_CID &&
1820 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1821 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1822
1823 switch (command) {
1824 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1825 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1826 drv_cmd = BNX2X_Q_CMD_UPDATE;
1827 break;
1828
1829 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1830 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1831 drv_cmd = BNX2X_Q_CMD_SETUP;
1832 break;
1833
1834 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1835 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1836 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1837 break;
1838
1839 case (RAMROD_CMD_ID_ETH_HALT):
1840 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1841 drv_cmd = BNX2X_Q_CMD_HALT;
1842 break;
1843
1844 case (RAMROD_CMD_ID_ETH_TERMINATE):
1845 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1846 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1847 break;
1848
1849 case (RAMROD_CMD_ID_ETH_EMPTY):
1850 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1851 drv_cmd = BNX2X_Q_CMD_EMPTY;
1852 break;
1853
1854 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1855 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1856 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1857 break;
1858
1859 default:
1860 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1861 command, fp->index);
1862 return;
1863 }
1864
1865 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1866 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1867 /* q_obj->complete_cmd() failure means that this was
1868 * an unexpected completion.
1869 *
1870 * In this case we don't want to increase the bp->spq_left
1871 * because apparently we haven't sent this command the first
1872 * place.
1873 */
1874 #ifdef BNX2X_STOP_ON_ERROR
1875 bnx2x_panic();
1876 #else
1877 return;
1878 #endif
1879
1880 smp_mb__before_atomic();
1881 atomic_inc(&bp->cq_spq_left);
1882 /* push the change in bp->spq_left and towards the memory */
1883 smp_mb__after_atomic();
1884
1885 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1886
1887 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1888 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1889 /* if Q update ramrod is completed for last Q in AFEX vif set
1890 * flow, then ACK MCP at the end
1891 *
1892 * mark pending ACK to MCP bit.
1893 * prevent case that both bits are cleared.
1894 * At the end of load/unload driver checks that
1895 * sp_state is cleared, and this order prevents
1896 * races
1897 */
1898 smp_mb__before_atomic();
1899 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1900 wmb();
1901 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1902 smp_mb__after_atomic();
1903
1904 /* schedule the sp task as mcp ack is required */
1905 bnx2x_schedule_sp_task(bp);
1906 }
1907
1908 return;
1909 }
1910
1911 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1912 {
1913 struct bnx2x *bp = netdev_priv(dev_instance);
1914 u16 status = bnx2x_ack_int(bp);
1915 u16 mask;
1916 int i;
1917 u8 cos;
1918
1919 /* Return here if interrupt is shared and it's not for us */
1920 if (unlikely(status == 0)) {
1921 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1922 return IRQ_NONE;
1923 }
1924 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1925
1926 #ifdef BNX2X_STOP_ON_ERROR
1927 if (unlikely(bp->panic))
1928 return IRQ_HANDLED;
1929 #endif
1930
1931 for_each_eth_queue(bp, i) {
1932 struct bnx2x_fastpath *fp = &bp->fp[i];
1933
1934 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1935 if (status & mask) {
1936 /* Handle Rx or Tx according to SB id */
1937 for_each_cos_in_tx_queue(fp, cos)
1938 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1939 prefetch(&fp->sb_running_index[SM_RX_ID]);
1940 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1941 status &= ~mask;
1942 }
1943 }
1944
1945 if (CNIC_SUPPORT(bp)) {
1946 mask = 0x2;
1947 if (status & (mask | 0x1)) {
1948 struct cnic_ops *c_ops = NULL;
1949
1950 rcu_read_lock();
1951 c_ops = rcu_dereference(bp->cnic_ops);
1952 if (c_ops && (bp->cnic_eth_dev.drv_state &
1953 CNIC_DRV_STATE_HANDLES_IRQ))
1954 c_ops->cnic_handler(bp->cnic_data, NULL);
1955 rcu_read_unlock();
1956
1957 status &= ~mask;
1958 }
1959 }
1960
1961 if (unlikely(status & 0x1)) {
1962
1963 /* schedule sp task to perform default status block work, ack
1964 * attentions and enable interrupts.
1965 */
1966 bnx2x_schedule_sp_task(bp);
1967
1968 status &= ~0x1;
1969 if (!status)
1970 return IRQ_HANDLED;
1971 }
1972
1973 if (unlikely(status))
1974 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1975 status);
1976
1977 return IRQ_HANDLED;
1978 }
1979
1980 /* Link */
1981
1982 /*
1983 * General service functions
1984 */
1985
1986 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1987 {
1988 u32 lock_status;
1989 u32 resource_bit = (1 << resource);
1990 int func = BP_FUNC(bp);
1991 u32 hw_lock_control_reg;
1992 int cnt;
1993
1994 /* Validating that the resource is within range */
1995 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1996 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1997 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1998 return -EINVAL;
1999 }
2000
2001 if (func <= 5) {
2002 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2003 } else {
2004 hw_lock_control_reg =
2005 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2006 }
2007
2008 /* Validating that the resource is not already taken */
2009 lock_status = REG_RD(bp, hw_lock_control_reg);
2010 if (lock_status & resource_bit) {
2011 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2012 lock_status, resource_bit);
2013 return -EEXIST;
2014 }
2015
2016 /* Try for 5 second every 5ms */
2017 for (cnt = 0; cnt < 1000; cnt++) {
2018 /* Try to acquire the lock */
2019 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2020 lock_status = REG_RD(bp, hw_lock_control_reg);
2021 if (lock_status & resource_bit)
2022 return 0;
2023
2024 usleep_range(5000, 10000);
2025 }
2026 BNX2X_ERR("Timeout\n");
2027 return -EAGAIN;
2028 }
2029
2030 int bnx2x_release_leader_lock(struct bnx2x *bp)
2031 {
2032 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2033 }
2034
2035 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2036 {
2037 u32 lock_status;
2038 u32 resource_bit = (1 << resource);
2039 int func = BP_FUNC(bp);
2040 u32 hw_lock_control_reg;
2041
2042 /* Validating that the resource is within range */
2043 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2044 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2045 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2046 return -EINVAL;
2047 }
2048
2049 if (func <= 5) {
2050 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2051 } else {
2052 hw_lock_control_reg =
2053 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2054 }
2055
2056 /* Validating that the resource is currently taken */
2057 lock_status = REG_RD(bp, hw_lock_control_reg);
2058 if (!(lock_status & resource_bit)) {
2059 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2060 lock_status, resource_bit);
2061 return -EFAULT;
2062 }
2063
2064 REG_WR(bp, hw_lock_control_reg, resource_bit);
2065 return 0;
2066 }
2067
2068 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2069 {
2070 /* The GPIO should be swapped if swap register is set and active */
2071 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2072 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2073 int gpio_shift = gpio_num +
2074 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2075 u32 gpio_mask = (1 << gpio_shift);
2076 u32 gpio_reg;
2077 int value;
2078
2079 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2080 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2081 return -EINVAL;
2082 }
2083
2084 /* read GPIO value */
2085 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2086
2087 /* get the requested pin value */
2088 if ((gpio_reg & gpio_mask) == gpio_mask)
2089 value = 1;
2090 else
2091 value = 0;
2092
2093 return value;
2094 }
2095
2096 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2097 {
2098 /* The GPIO should be swapped if swap register is set and active */
2099 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2100 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2101 int gpio_shift = gpio_num +
2102 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2103 u32 gpio_mask = (1 << gpio_shift);
2104 u32 gpio_reg;
2105
2106 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2107 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2108 return -EINVAL;
2109 }
2110
2111 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2112 /* read GPIO and mask except the float bits */
2113 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2114
2115 switch (mode) {
2116 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2117 DP(NETIF_MSG_LINK,
2118 "Set GPIO %d (shift %d) -> output low\n",
2119 gpio_num, gpio_shift);
2120 /* clear FLOAT and set CLR */
2121 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2122 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2123 break;
2124
2125 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2126 DP(NETIF_MSG_LINK,
2127 "Set GPIO %d (shift %d) -> output high\n",
2128 gpio_num, gpio_shift);
2129 /* clear FLOAT and set SET */
2130 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2131 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2132 break;
2133
2134 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2135 DP(NETIF_MSG_LINK,
2136 "Set GPIO %d (shift %d) -> input\n",
2137 gpio_num, gpio_shift);
2138 /* set FLOAT */
2139 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2140 break;
2141
2142 default:
2143 break;
2144 }
2145
2146 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2147 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2148
2149 return 0;
2150 }
2151
2152 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2153 {
2154 u32 gpio_reg = 0;
2155 int rc = 0;
2156
2157 /* Any port swapping should be handled by caller. */
2158
2159 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2160 /* read GPIO and mask except the float bits */
2161 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2162 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2163 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2164 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2165
2166 switch (mode) {
2167 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2168 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2169 /* set CLR */
2170 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2171 break;
2172
2173 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2174 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2175 /* set SET */
2176 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2177 break;
2178
2179 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2180 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2181 /* set FLOAT */
2182 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2183 break;
2184
2185 default:
2186 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2187 rc = -EINVAL;
2188 break;
2189 }
2190
2191 if (rc == 0)
2192 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2193
2194 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2195
2196 return rc;
2197 }
2198
2199 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2200 {
2201 /* The GPIO should be swapped if swap register is set and active */
2202 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2203 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2204 int gpio_shift = gpio_num +
2205 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2206 u32 gpio_mask = (1 << gpio_shift);
2207 u32 gpio_reg;
2208
2209 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2210 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2211 return -EINVAL;
2212 }
2213
2214 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2215 /* read GPIO int */
2216 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2217
2218 switch (mode) {
2219 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2220 DP(NETIF_MSG_LINK,
2221 "Clear GPIO INT %d (shift %d) -> output low\n",
2222 gpio_num, gpio_shift);
2223 /* clear SET and set CLR */
2224 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2225 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2226 break;
2227
2228 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2229 DP(NETIF_MSG_LINK,
2230 "Set GPIO INT %d (shift %d) -> output high\n",
2231 gpio_num, gpio_shift);
2232 /* clear CLR and set SET */
2233 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2234 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2235 break;
2236
2237 default:
2238 break;
2239 }
2240
2241 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2242 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2243
2244 return 0;
2245 }
2246
2247 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2248 {
2249 u32 spio_reg;
2250
2251 /* Only 2 SPIOs are configurable */
2252 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2253 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2254 return -EINVAL;
2255 }
2256
2257 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2258 /* read SPIO and mask except the float bits */
2259 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2260
2261 switch (mode) {
2262 case MISC_SPIO_OUTPUT_LOW:
2263 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2264 /* clear FLOAT and set CLR */
2265 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2266 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2267 break;
2268
2269 case MISC_SPIO_OUTPUT_HIGH:
2270 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2271 /* clear FLOAT and set SET */
2272 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2273 spio_reg |= (spio << MISC_SPIO_SET_POS);
2274 break;
2275
2276 case MISC_SPIO_INPUT_HI_Z:
2277 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2278 /* set FLOAT */
2279 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2280 break;
2281
2282 default:
2283 break;
2284 }
2285
2286 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2287 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2288
2289 return 0;
2290 }
2291
2292 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2293 {
2294 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2295
2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2297 ADVERTISED_Pause);
2298 switch (bp->link_vars.ieee_fc &
2299 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2300 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2301 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2302 ADVERTISED_Pause);
2303 break;
2304
2305 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2306 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2307 break;
2308
2309 default:
2310 break;
2311 }
2312 }
2313
2314 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2315 {
2316 /* Initialize link parameters structure variables
2317 * It is recommended to turn off RX FC for jumbo frames
2318 * for better performance
2319 */
2320 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2322 else
2323 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2324 }
2325
2326 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2327 {
2328 u32 pause_enabled = 0;
2329
2330 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2331 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2332 pause_enabled = 1;
2333
2334 REG_WR(bp, BAR_USTRORM_INTMEM +
2335 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2336 pause_enabled);
2337 }
2338
2339 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2340 pause_enabled ? "enabled" : "disabled");
2341 }
2342
2343 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2344 {
2345 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2346 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2347
2348 if (!BP_NOMCP(bp)) {
2349 bnx2x_set_requested_fc(bp);
2350 bnx2x_acquire_phy_lock(bp);
2351
2352 if (load_mode == LOAD_DIAG) {
2353 struct link_params *lp = &bp->link_params;
2354 lp->loopback_mode = LOOPBACK_XGXS;
2355 /* Prefer doing PHY loopback at highest speed */
2356 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2357 if (lp->speed_cap_mask[cfx_idx] &
2358 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2359 lp->req_line_speed[cfx_idx] =
2360 SPEED_20000;
2361 else if (lp->speed_cap_mask[cfx_idx] &
2362 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2363 lp->req_line_speed[cfx_idx] =
2364 SPEED_10000;
2365 else
2366 lp->req_line_speed[cfx_idx] =
2367 SPEED_1000;
2368 }
2369 }
2370
2371 if (load_mode == LOAD_LOOPBACK_EXT) {
2372 struct link_params *lp = &bp->link_params;
2373 lp->loopback_mode = LOOPBACK_EXT;
2374 }
2375
2376 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2377
2378 bnx2x_release_phy_lock(bp);
2379
2380 bnx2x_init_dropless_fc(bp);
2381
2382 bnx2x_calc_fc_adv(bp);
2383
2384 if (bp->link_vars.link_up) {
2385 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2386 bnx2x_link_report(bp);
2387 }
2388 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2389 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2390 return rc;
2391 }
2392 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2393 return -EINVAL;
2394 }
2395
2396 void bnx2x_link_set(struct bnx2x *bp)
2397 {
2398 if (!BP_NOMCP(bp)) {
2399 bnx2x_acquire_phy_lock(bp);
2400 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2401 bnx2x_release_phy_lock(bp);
2402
2403 bnx2x_init_dropless_fc(bp);
2404
2405 bnx2x_calc_fc_adv(bp);
2406 } else
2407 BNX2X_ERR("Bootcode is missing - can not set link\n");
2408 }
2409
2410 static void bnx2x__link_reset(struct bnx2x *bp)
2411 {
2412 if (!BP_NOMCP(bp)) {
2413 bnx2x_acquire_phy_lock(bp);
2414 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2415 bnx2x_release_phy_lock(bp);
2416 } else
2417 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2418 }
2419
2420 void bnx2x_force_link_reset(struct bnx2x *bp)
2421 {
2422 bnx2x_acquire_phy_lock(bp);
2423 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2424 bnx2x_release_phy_lock(bp);
2425 }
2426
2427 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2428 {
2429 u8 rc = 0;
2430
2431 if (!BP_NOMCP(bp)) {
2432 bnx2x_acquire_phy_lock(bp);
2433 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2434 is_serdes);
2435 bnx2x_release_phy_lock(bp);
2436 } else
2437 BNX2X_ERR("Bootcode is missing - can not test link\n");
2438
2439 return rc;
2440 }
2441
2442 /* Calculates the sum of vn_min_rates.
2443 It's needed for further normalizing of the min_rates.
2444 Returns:
2445 sum of vn_min_rates.
2446 or
2447 0 - if all the min_rates are 0.
2448 In the later case fairness algorithm should be deactivated.
2449 If not all min_rates are zero then those that are zeroes will be set to 1.
2450 */
2451 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2452 struct cmng_init_input *input)
2453 {
2454 int all_zero = 1;
2455 int vn;
2456
2457 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2458 u32 vn_cfg = bp->mf_config[vn];
2459 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2460 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2461
2462 /* Skip hidden vns */
2463 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2464 vn_min_rate = 0;
2465 /* If min rate is zero - set it to 1 */
2466 else if (!vn_min_rate)
2467 vn_min_rate = DEF_MIN_RATE;
2468 else
2469 all_zero = 0;
2470
2471 input->vnic_min_rate[vn] = vn_min_rate;
2472 }
2473
2474 /* if ETS or all min rates are zeros - disable fairness */
2475 if (BNX2X_IS_ETS_ENABLED(bp)) {
2476 input->flags.cmng_enables &=
2477 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2478 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2479 } else if (all_zero) {
2480 input->flags.cmng_enables &=
2481 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 DP(NETIF_MSG_IFUP,
2483 "All MIN values are zeroes fairness will be disabled\n");
2484 } else
2485 input->flags.cmng_enables |=
2486 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2487 }
2488
2489 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2490 struct cmng_init_input *input)
2491 {
2492 u16 vn_max_rate;
2493 u32 vn_cfg = bp->mf_config[vn];
2494
2495 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2496 vn_max_rate = 0;
2497 else {
2498 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2499
2500 if (IS_MF_PERCENT_BW(bp)) {
2501 /* maxCfg in percents of linkspeed */
2502 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2503 } else /* SD modes */
2504 /* maxCfg is absolute in 100Mb units */
2505 vn_max_rate = maxCfg * 100;
2506 }
2507
2508 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2509
2510 input->vnic_max_rate[vn] = vn_max_rate;
2511 }
2512
2513 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2514 {
2515 if (CHIP_REV_IS_SLOW(bp))
2516 return CMNG_FNS_NONE;
2517 if (IS_MF(bp))
2518 return CMNG_FNS_MINMAX;
2519
2520 return CMNG_FNS_NONE;
2521 }
2522
2523 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2524 {
2525 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2526
2527 if (BP_NOMCP(bp))
2528 return; /* what should be the default value in this case */
2529
2530 /* For 2 port configuration the absolute function number formula
2531 * is:
2532 * abs_func = 2 * vn + BP_PORT + BP_PATH
2533 *
2534 * and there are 4 functions per port
2535 *
2536 * For 4 port configuration it is
2537 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2538 *
2539 * and there are 2 functions per port
2540 */
2541 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2542 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2543
2544 if (func >= E1H_FUNC_MAX)
2545 break;
2546
2547 bp->mf_config[vn] =
2548 MF_CFG_RD(bp, func_mf_config[func].config);
2549 }
2550 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2551 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2552 bp->flags |= MF_FUNC_DIS;
2553 } else {
2554 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2555 bp->flags &= ~MF_FUNC_DIS;
2556 }
2557 }
2558
2559 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2560 {
2561 struct cmng_init_input input;
2562 memset(&input, 0, sizeof(struct cmng_init_input));
2563
2564 input.port_rate = bp->link_vars.line_speed;
2565
2566 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2567 int vn;
2568
2569 /* read mf conf from shmem */
2570 if (read_cfg)
2571 bnx2x_read_mf_cfg(bp);
2572
2573 /* vn_weight_sum and enable fairness if not 0 */
2574 bnx2x_calc_vn_min(bp, &input);
2575
2576 /* calculate and set min-max rate for each vn */
2577 if (bp->port.pmf)
2578 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2579 bnx2x_calc_vn_max(bp, vn, &input);
2580
2581 /* always enable rate shaping and fairness */
2582 input.flags.cmng_enables |=
2583 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2584
2585 bnx2x_init_cmng(&input, &bp->cmng);
2586 return;
2587 }
2588
2589 /* rate shaping and fairness are disabled */
2590 DP(NETIF_MSG_IFUP,
2591 "rate shaping and fairness are disabled\n");
2592 }
2593
2594 static void storm_memset_cmng(struct bnx2x *bp,
2595 struct cmng_init *cmng,
2596 u8 port)
2597 {
2598 int vn;
2599 size_t size = sizeof(struct cmng_struct_per_port);
2600
2601 u32 addr = BAR_XSTRORM_INTMEM +
2602 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2603
2604 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2605
2606 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2607 int func = func_by_vn(bp, vn);
2608
2609 addr = BAR_XSTRORM_INTMEM +
2610 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2611 size = sizeof(struct rate_shaping_vars_per_vn);
2612 __storm_memset_struct(bp, addr, size,
2613 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2614
2615 addr = BAR_XSTRORM_INTMEM +
2616 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2617 size = sizeof(struct fairness_vars_per_vn);
2618 __storm_memset_struct(bp, addr, size,
2619 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2620 }
2621 }
2622
2623 /* init cmng mode in HW according to local configuration */
2624 void bnx2x_set_local_cmng(struct bnx2x *bp)
2625 {
2626 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2627
2628 if (cmng_fns != CMNG_FNS_NONE) {
2629 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2630 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2631 } else {
2632 /* rate shaping and fairness are disabled */
2633 DP(NETIF_MSG_IFUP,
2634 "single function mode without fairness\n");
2635 }
2636 }
2637
2638 /* This function is called upon link interrupt */
2639 static void bnx2x_link_attn(struct bnx2x *bp)
2640 {
2641 /* Make sure that we are synced with the current statistics */
2642 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2643
2644 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2645
2646 bnx2x_init_dropless_fc(bp);
2647
2648 if (bp->link_vars.link_up) {
2649
2650 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2651 struct host_port_stats *pstats;
2652
2653 pstats = bnx2x_sp(bp, port_stats);
2654 /* reset old mac stats */
2655 memset(&(pstats->mac_stx[0]), 0,
2656 sizeof(struct mac_stx));
2657 }
2658 if (bp->state == BNX2X_STATE_OPEN)
2659 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2660 }
2661
2662 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2663 bnx2x_set_local_cmng(bp);
2664
2665 __bnx2x_link_report(bp);
2666
2667 if (IS_MF(bp))
2668 bnx2x_link_sync_notify(bp);
2669 }
2670
2671 void bnx2x__link_status_update(struct bnx2x *bp)
2672 {
2673 if (bp->state != BNX2X_STATE_OPEN)
2674 return;
2675
2676 /* read updated dcb configuration */
2677 if (IS_PF(bp)) {
2678 bnx2x_dcbx_pmf_update(bp);
2679 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2680 if (bp->link_vars.link_up)
2681 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2682 else
2683 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2684 /* indicate link status */
2685 bnx2x_link_report(bp);
2686
2687 } else { /* VF */
2688 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2689 SUPPORTED_10baseT_Full |
2690 SUPPORTED_100baseT_Half |
2691 SUPPORTED_100baseT_Full |
2692 SUPPORTED_1000baseT_Full |
2693 SUPPORTED_2500baseX_Full |
2694 SUPPORTED_10000baseT_Full |
2695 SUPPORTED_TP |
2696 SUPPORTED_FIBRE |
2697 SUPPORTED_Autoneg |
2698 SUPPORTED_Pause |
2699 SUPPORTED_Asym_Pause);
2700 bp->port.advertising[0] = bp->port.supported[0];
2701
2702 bp->link_params.bp = bp;
2703 bp->link_params.port = BP_PORT(bp);
2704 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2705 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2706 bp->link_params.req_line_speed[0] = SPEED_10000;
2707 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2708 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2709 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2710 bp->link_vars.line_speed = SPEED_10000;
2711 bp->link_vars.link_status =
2712 (LINK_STATUS_LINK_UP |
2713 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2714 bp->link_vars.link_up = 1;
2715 bp->link_vars.duplex = DUPLEX_FULL;
2716 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2717 __bnx2x_link_report(bp);
2718
2719 bnx2x_sample_bulletin(bp);
2720
2721 /* if bulletin board did not have an update for link status
2722 * __bnx2x_link_report will report current status
2723 * but it will NOT duplicate report in case of already reported
2724 * during sampling bulletin board.
2725 */
2726 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2727 }
2728 }
2729
2730 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2731 u16 vlan_val, u8 allowed_prio)
2732 {
2733 struct bnx2x_func_state_params func_params = {NULL};
2734 struct bnx2x_func_afex_update_params *f_update_params =
2735 &func_params.params.afex_update;
2736
2737 func_params.f_obj = &bp->func_obj;
2738 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2739
2740 /* no need to wait for RAMROD completion, so don't
2741 * set RAMROD_COMP_WAIT flag
2742 */
2743
2744 f_update_params->vif_id = vifid;
2745 f_update_params->afex_default_vlan = vlan_val;
2746 f_update_params->allowed_priorities = allowed_prio;
2747
2748 /* if ramrod can not be sent, response to MCP immediately */
2749 if (bnx2x_func_state_change(bp, &func_params) < 0)
2750 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2751
2752 return 0;
2753 }
2754
2755 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2756 u16 vif_index, u8 func_bit_map)
2757 {
2758 struct bnx2x_func_state_params func_params = {NULL};
2759 struct bnx2x_func_afex_viflists_params *update_params =
2760 &func_params.params.afex_viflists;
2761 int rc;
2762 u32 drv_msg_code;
2763
2764 /* validate only LIST_SET and LIST_GET are received from switch */
2765 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2766 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2767 cmd_type);
2768
2769 func_params.f_obj = &bp->func_obj;
2770 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2771
2772 /* set parameters according to cmd_type */
2773 update_params->afex_vif_list_command = cmd_type;
2774 update_params->vif_list_index = vif_index;
2775 update_params->func_bit_map =
2776 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2777 update_params->func_to_clear = 0;
2778 drv_msg_code =
2779 (cmd_type == VIF_LIST_RULE_GET) ?
2780 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2781 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2782
2783 /* if ramrod can not be sent, respond to MCP immediately for
2784 * SET and GET requests (other are not triggered from MCP)
2785 */
2786 rc = bnx2x_func_state_change(bp, &func_params);
2787 if (rc < 0)
2788 bnx2x_fw_command(bp, drv_msg_code, 0);
2789
2790 return 0;
2791 }
2792
2793 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2794 {
2795 struct afex_stats afex_stats;
2796 u32 func = BP_ABS_FUNC(bp);
2797 u32 mf_config;
2798 u16 vlan_val;
2799 u32 vlan_prio;
2800 u16 vif_id;
2801 u8 allowed_prio;
2802 u8 vlan_mode;
2803 u32 addr_to_write, vifid, addrs, stats_type, i;
2804
2805 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2806 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2807 DP(BNX2X_MSG_MCP,
2808 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2809 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2810 }
2811
2812 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2813 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2814 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2815 DP(BNX2X_MSG_MCP,
2816 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2817 vifid, addrs);
2818 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2819 addrs);
2820 }
2821
2822 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2823 addr_to_write = SHMEM2_RD(bp,
2824 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2825 stats_type = SHMEM2_RD(bp,
2826 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2827
2828 DP(BNX2X_MSG_MCP,
2829 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2830 addr_to_write);
2831
2832 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2833
2834 /* write response to scratchpad, for MCP */
2835 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2836 REG_WR(bp, addr_to_write + i*sizeof(u32),
2837 *(((u32 *)(&afex_stats))+i));
2838
2839 /* send ack message to MCP */
2840 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2841 }
2842
2843 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2844 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2845 bp->mf_config[BP_VN(bp)] = mf_config;
2846 DP(BNX2X_MSG_MCP,
2847 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2848 mf_config);
2849
2850 /* if VIF_SET is "enabled" */
2851 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2852 /* set rate limit directly to internal RAM */
2853 struct cmng_init_input cmng_input;
2854 struct rate_shaping_vars_per_vn m_rs_vn;
2855 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2856 u32 addr = BAR_XSTRORM_INTMEM +
2857 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2858
2859 bp->mf_config[BP_VN(bp)] = mf_config;
2860
2861 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2862 m_rs_vn.vn_counter.rate =
2863 cmng_input.vnic_max_rate[BP_VN(bp)];
2864 m_rs_vn.vn_counter.quota =
2865 (m_rs_vn.vn_counter.rate *
2866 RS_PERIODIC_TIMEOUT_USEC) / 8;
2867
2868 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2869
2870 /* read relevant values from mf_cfg struct in shmem */
2871 vif_id =
2872 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2873 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2874 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2875 vlan_val =
2876 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2878 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2879 vlan_prio = (mf_config &
2880 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2881 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2882 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2883 vlan_mode =
2884 (MF_CFG_RD(bp,
2885 func_mf_config[func].afex_config) &
2886 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2887 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2888 allowed_prio =
2889 (MF_CFG_RD(bp,
2890 func_mf_config[func].afex_config) &
2891 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2892 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2893
2894 /* send ramrod to FW, return in case of failure */
2895 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2896 allowed_prio))
2897 return;
2898
2899 bp->afex_def_vlan_tag = vlan_val;
2900 bp->afex_vlan_mode = vlan_mode;
2901 } else {
2902 /* notify link down because BP->flags is disabled */
2903 bnx2x_link_report(bp);
2904
2905 /* send INVALID VIF ramrod to FW */
2906 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2907
2908 /* Reset the default afex VLAN */
2909 bp->afex_def_vlan_tag = -1;
2910 }
2911 }
2912 }
2913
2914 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2915 {
2916 struct bnx2x_func_switch_update_params *switch_update_params;
2917 struct bnx2x_func_state_params func_params;
2918
2919 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2920 switch_update_params = &func_params.params.switch_update;
2921 func_params.f_obj = &bp->func_obj;
2922 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2923
2924 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2925 int func = BP_ABS_FUNC(bp);
2926 u32 val;
2927
2928 /* Re-learn the S-tag from shmem */
2929 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2930 FUNC_MF_CFG_E1HOV_TAG_MASK;
2931 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2932 bp->mf_ov = val;
2933 } else {
2934 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2935 goto fail;
2936 }
2937
2938 /* Configure new S-tag in LLH */
2939 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2940 bp->mf_ov);
2941
2942 /* Send Ramrod to update FW of change */
2943 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2944 &switch_update_params->changes);
2945 switch_update_params->vlan = bp->mf_ov;
2946
2947 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2948 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2949 bp->mf_ov);
2950 goto fail;
2951 } else {
2952 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2953 bp->mf_ov);
2954 }
2955 } else {
2956 goto fail;
2957 }
2958
2959 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2960 return;
2961 fail:
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2963 }
2964
2965 static void bnx2x_pmf_update(struct bnx2x *bp)
2966 {
2967 int port = BP_PORT(bp);
2968 u32 val;
2969
2970 bp->port.pmf = 1;
2971 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2972
2973 /*
2974 * We need the mb() to ensure the ordering between the writing to
2975 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2976 */
2977 smp_mb();
2978
2979 /* queue a periodic task */
2980 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2981
2982 bnx2x_dcbx_pmf_update(bp);
2983
2984 /* enable nig attention */
2985 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2986 if (bp->common.int_block == INT_BLOCK_HC) {
2987 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2988 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2989 } else if (!CHIP_IS_E1x(bp)) {
2990 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2991 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2992 }
2993
2994 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2995 }
2996
2997 /* end of Link */
2998
2999 /* slow path */
3000
3001 /*
3002 * General service functions
3003 */
3004
3005 /* send the MCP a request, block until there is a reply */
3006 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3007 {
3008 int mb_idx = BP_FW_MB_IDX(bp);
3009 u32 seq;
3010 u32 rc = 0;
3011 u32 cnt = 1;
3012 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3013
3014 mutex_lock(&bp->fw_mb_mutex);
3015 seq = ++bp->fw_seq;
3016 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3017 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3018
3019 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3020 (command | seq), param);
3021
3022 do {
3023 /* let the FW do it's magic ... */
3024 msleep(delay);
3025
3026 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3027
3028 /* Give the FW up to 5 second (500*10ms) */
3029 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3030
3031 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3032 cnt*delay, rc, seq);
3033
3034 /* is this a reply to our command? */
3035 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3036 rc &= FW_MSG_CODE_MASK;
3037 else {
3038 /* FW BUG! */
3039 BNX2X_ERR("FW failed to respond!\n");
3040 bnx2x_fw_dump(bp);
3041 rc = 0;
3042 }
3043 mutex_unlock(&bp->fw_mb_mutex);
3044
3045 return rc;
3046 }
3047
3048 static void storm_memset_func_cfg(struct bnx2x *bp,
3049 struct tstorm_eth_function_common_config *tcfg,
3050 u16 abs_fid)
3051 {
3052 size_t size = sizeof(struct tstorm_eth_function_common_config);
3053
3054 u32 addr = BAR_TSTRORM_INTMEM +
3055 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3056
3057 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3058 }
3059
3060 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3061 {
3062 if (CHIP_IS_E1x(bp)) {
3063 struct tstorm_eth_function_common_config tcfg = {0};
3064
3065 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3066 }
3067
3068 /* Enable the function in the FW */
3069 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3070 storm_memset_func_en(bp, p->func_id, 1);
3071
3072 /* spq */
3073 if (p->spq_active) {
3074 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3075 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3076 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3077 }
3078 }
3079
3080 /**
3081 * bnx2x_get_common_flags - Return common flags
3082 *
3083 * @bp device handle
3084 * @fp queue handle
3085 * @zero_stats TRUE if statistics zeroing is needed
3086 *
3087 * Return the flags that are common for the Tx-only and not normal connections.
3088 */
3089 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3090 struct bnx2x_fastpath *fp,
3091 bool zero_stats)
3092 {
3093 unsigned long flags = 0;
3094
3095 /* PF driver will always initialize the Queue to an ACTIVE state */
3096 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3097
3098 /* tx only connections collect statistics (on the same index as the
3099 * parent connection). The statistics are zeroed when the parent
3100 * connection is initialized.
3101 */
3102
3103 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3104 if (zero_stats)
3105 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3106
3107 if (bp->flags & TX_SWITCHING)
3108 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3109
3110 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3111 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3112
3113 #ifdef BNX2X_STOP_ON_ERROR
3114 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3115 #endif
3116
3117 return flags;
3118 }
3119
3120 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3121 struct bnx2x_fastpath *fp,
3122 bool leading)
3123 {
3124 unsigned long flags = 0;
3125
3126 /* calculate other queue flags */
3127 if (IS_MF_SD(bp))
3128 __set_bit(BNX2X_Q_FLG_OV, &flags);
3129
3130 if (IS_FCOE_FP(fp)) {
3131 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3132 /* For FCoE - force usage of default priority (for afex) */
3133 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3134 }
3135
3136 if (fp->mode != TPA_MODE_DISABLED) {
3137 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3138 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3139 if (fp->mode == TPA_MODE_GRO)
3140 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3141 }
3142
3143 if (leading) {
3144 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3145 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3146 }
3147
3148 /* Always set HW VLAN stripping */
3149 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3150
3151 /* configure silent vlan removal */
3152 if (IS_MF_AFEX(bp))
3153 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3154
3155 return flags | bnx2x_get_common_flags(bp, fp, true);
3156 }
3157
3158 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3159 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3160 u8 cos)
3161 {
3162 gen_init->stat_id = bnx2x_stats_id(fp);
3163 gen_init->spcl_id = fp->cl_id;
3164
3165 /* Always use mini-jumbo MTU for FCoE L2 ring */
3166 if (IS_FCOE_FP(fp))
3167 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3168 else
3169 gen_init->mtu = bp->dev->mtu;
3170
3171 gen_init->cos = cos;
3172
3173 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3174 }
3175
3176 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3177 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3178 struct bnx2x_rxq_setup_params *rxq_init)
3179 {
3180 u8 max_sge = 0;
3181 u16 sge_sz = 0;
3182 u16 tpa_agg_size = 0;
3183
3184 if (fp->mode != TPA_MODE_DISABLED) {
3185 pause->sge_th_lo = SGE_TH_LO(bp);
3186 pause->sge_th_hi = SGE_TH_HI(bp);
3187
3188 /* validate SGE ring has enough to cross high threshold */
3189 WARN_ON(bp->dropless_fc &&
3190 pause->sge_th_hi + FW_PREFETCH_CNT >
3191 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3192
3193 tpa_agg_size = TPA_AGG_SIZE;
3194 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3195 SGE_PAGE_SHIFT;
3196 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3197 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3198 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3199 }
3200
3201 /* pause - not for e1 */
3202 if (!CHIP_IS_E1(bp)) {
3203 pause->bd_th_lo = BD_TH_LO(bp);
3204 pause->bd_th_hi = BD_TH_HI(bp);
3205
3206 pause->rcq_th_lo = RCQ_TH_LO(bp);
3207 pause->rcq_th_hi = RCQ_TH_HI(bp);
3208 /*
3209 * validate that rings have enough entries to cross
3210 * high thresholds
3211 */
3212 WARN_ON(bp->dropless_fc &&
3213 pause->bd_th_hi + FW_PREFETCH_CNT >
3214 bp->rx_ring_size);
3215 WARN_ON(bp->dropless_fc &&
3216 pause->rcq_th_hi + FW_PREFETCH_CNT >
3217 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3218
3219 pause->pri_map = 1;
3220 }
3221
3222 /* rxq setup */
3223 rxq_init->dscr_map = fp->rx_desc_mapping;
3224 rxq_init->sge_map = fp->rx_sge_mapping;
3225 rxq_init->rcq_map = fp->rx_comp_mapping;
3226 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3227
3228 /* This should be a maximum number of data bytes that may be
3229 * placed on the BD (not including paddings).
3230 */
3231 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3232 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3233
3234 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3235 rxq_init->tpa_agg_sz = tpa_agg_size;
3236 rxq_init->sge_buf_sz = sge_sz;
3237 rxq_init->max_sges_pkt = max_sge;
3238 rxq_init->rss_engine_id = BP_FUNC(bp);
3239 rxq_init->mcast_engine_id = BP_FUNC(bp);
3240
3241 /* Maximum number or simultaneous TPA aggregation for this Queue.
3242 *
3243 * For PF Clients it should be the maximum available number.
3244 * VF driver(s) may want to define it to a smaller value.
3245 */
3246 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3247
3248 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3249 rxq_init->fw_sb_id = fp->fw_sb_id;
3250
3251 if (IS_FCOE_FP(fp))
3252 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3253 else
3254 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3255 /* configure silent vlan removal
3256 * if multi function mode is afex, then mask default vlan
3257 */
3258 if (IS_MF_AFEX(bp)) {
3259 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3260 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3261 }
3262 }
3263
3264 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3265 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3266 u8 cos)
3267 {
3268 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3269 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3270 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3271 txq_init->fw_sb_id = fp->fw_sb_id;
3272
3273 /*
3274 * set the tss leading client id for TX classification ==
3275 * leading RSS client id
3276 */
3277 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3278
3279 if (IS_FCOE_FP(fp)) {
3280 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3281 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3282 }
3283 }
3284
3285 static void bnx2x_pf_init(struct bnx2x *bp)
3286 {
3287 struct bnx2x_func_init_params func_init = {0};
3288 struct event_ring_data eq_data = { {0} };
3289
3290 if (!CHIP_IS_E1x(bp)) {
3291 /* reset IGU PF statistics: MSIX + ATTN */
3292 /* PF */
3293 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3294 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3295 (CHIP_MODE_IS_4_PORT(bp) ?
3296 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297 /* ATTN */
3298 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3299 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3300 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3301 (CHIP_MODE_IS_4_PORT(bp) ?
3302 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3303 }
3304
3305 func_init.spq_active = true;
3306 func_init.pf_id = BP_FUNC(bp);
3307 func_init.func_id = BP_FUNC(bp);
3308 func_init.spq_map = bp->spq_mapping;
3309 func_init.spq_prod = bp->spq_prod_idx;
3310
3311 bnx2x_func_init(bp, &func_init);
3312
3313 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3314
3315 /*
3316 * Congestion management values depend on the link rate
3317 * There is no active link so initial link rate is set to 10 Gbps.
3318 * When the link comes up The congestion management values are
3319 * re-calculated according to the actual link rate.
3320 */
3321 bp->link_vars.line_speed = SPEED_10000;
3322 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3323
3324 /* Only the PMF sets the HW */
3325 if (bp->port.pmf)
3326 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3327
3328 /* init Event Queue - PCI bus guarantees correct endianity*/
3329 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3330 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3331 eq_data.producer = bp->eq_prod;
3332 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3333 eq_data.sb_id = DEF_SB_ID;
3334 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3335 }
3336
3337 static void bnx2x_e1h_disable(struct bnx2x *bp)
3338 {
3339 int port = BP_PORT(bp);
3340
3341 bnx2x_tx_disable(bp);
3342
3343 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3344 }
3345
3346 static void bnx2x_e1h_enable(struct bnx2x *bp)
3347 {
3348 int port = BP_PORT(bp);
3349
3350 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3352
3353 /* Tx queue should be only re-enabled */
3354 netif_tx_wake_all_queues(bp->dev);
3355
3356 /*
3357 * Should not call netif_carrier_on since it will be called if the link
3358 * is up when checking for link state
3359 */
3360 }
3361
3362 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3363
3364 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3365 {
3366 struct eth_stats_info *ether_stat =
3367 &bp->slowpath->drv_info_to_mcp.ether_stat;
3368 struct bnx2x_vlan_mac_obj *mac_obj =
3369 &bp->sp_objs->mac_obj;
3370 int i;
3371
3372 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3373 ETH_STAT_INFO_VERSION_LEN);
3374
3375 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3376 * mac_local field in ether_stat struct. The base address is offset by 2
3377 * bytes to account for the field being 8 bytes but a mac address is
3378 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3379 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3380 * allocated by the ether_stat struct, so the macs will land in their
3381 * proper positions.
3382 */
3383 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3384 memset(ether_stat->mac_local + i, 0,
3385 sizeof(ether_stat->mac_local[0]));
3386 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3387 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3388 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3389 ETH_ALEN);
3390 ether_stat->mtu_size = bp->dev->mtu;
3391 if (bp->dev->features & NETIF_F_RXCSUM)
3392 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3393 if (bp->dev->features & NETIF_F_TSO)
3394 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3395 ether_stat->feature_flags |= bp->common.boot_mode;
3396
3397 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3398
3399 ether_stat->txq_size = bp->tx_ring_size;
3400 ether_stat->rxq_size = bp->rx_ring_size;
3401
3402 #ifdef CONFIG_BNX2X_SRIOV
3403 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3404 #endif
3405 }
3406
3407 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3408 {
3409 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3410 struct fcoe_stats_info *fcoe_stat =
3411 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3412
3413 if (!CNIC_LOADED(bp))
3414 return;
3415
3416 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3417
3418 fcoe_stat->qos_priority =
3419 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3420
3421 /* insert FCoE stats from ramrod response */
3422 if (!NO_FCOE(bp)) {
3423 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3424 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3425 tstorm_queue_statistics;
3426
3427 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429 xstorm_queue_statistics;
3430
3431 struct fcoe_statistics_params *fw_fcoe_stat =
3432 &bp->fw_stats_data->fcoe;
3433
3434 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3435 fcoe_stat->rx_bytes_lo,
3436 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3437
3438 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3440 fcoe_stat->rx_bytes_lo,
3441 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3442
3443 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3445 fcoe_stat->rx_bytes_lo,
3446 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3447
3448 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3449 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3450 fcoe_stat->rx_bytes_lo,
3451 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3452
3453 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3454 fcoe_stat->rx_frames_lo,
3455 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3456
3457 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458 fcoe_stat->rx_frames_lo,
3459 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3460
3461 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462 fcoe_stat->rx_frames_lo,
3463 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3464
3465 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466 fcoe_stat->rx_frames_lo,
3467 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3468
3469 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3470 fcoe_stat->tx_bytes_lo,
3471 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3472
3473 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3475 fcoe_stat->tx_bytes_lo,
3476 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3477
3478 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3480 fcoe_stat->tx_bytes_lo,
3481 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3482
3483 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3484 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3485 fcoe_stat->tx_bytes_lo,
3486 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3487
3488 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3489 fcoe_stat->tx_frames_lo,
3490 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3491
3492 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493 fcoe_stat->tx_frames_lo,
3494 fcoe_q_xstorm_stats->ucast_pkts_sent);
3495
3496 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497 fcoe_stat->tx_frames_lo,
3498 fcoe_q_xstorm_stats->bcast_pkts_sent);
3499
3500 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501 fcoe_stat->tx_frames_lo,
3502 fcoe_q_xstorm_stats->mcast_pkts_sent);
3503 }
3504
3505 /* ask L5 driver to add data to the struct */
3506 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3507 }
3508
3509 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3510 {
3511 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3512 struct iscsi_stats_info *iscsi_stat =
3513 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3514
3515 if (!CNIC_LOADED(bp))
3516 return;
3517
3518 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3519 ETH_ALEN);
3520
3521 iscsi_stat->qos_priority =
3522 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3523
3524 /* ask L5 driver to add data to the struct */
3525 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3526 }
3527
3528 /* called due to MCP event (on pmf):
3529 * reread new bandwidth configuration
3530 * configure FW
3531 * notify others function about the change
3532 */
3533 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3534 {
3535 if (bp->link_vars.link_up) {
3536 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3537 bnx2x_link_sync_notify(bp);
3538 }
3539 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3540 }
3541
3542 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3543 {
3544 bnx2x_config_mf_bw(bp);
3545 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3546 }
3547
3548 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3549 {
3550 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3551 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3552 }
3553
3554 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3555 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3556
3557 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3558 {
3559 enum drv_info_opcode op_code;
3560 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3561 bool release = false;
3562 int wait;
3563
3564 /* if drv_info version supported by MFW doesn't match - send NACK */
3565 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3566 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3567 return;
3568 }
3569
3570 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3571 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3572
3573 /* Must prevent other flows from accessing drv_info_to_mcp */
3574 mutex_lock(&bp->drv_info_mutex);
3575
3576 memset(&bp->slowpath->drv_info_to_mcp, 0,
3577 sizeof(union drv_info_to_mcp));
3578
3579 switch (op_code) {
3580 case ETH_STATS_OPCODE:
3581 bnx2x_drv_info_ether_stat(bp);
3582 break;
3583 case FCOE_STATS_OPCODE:
3584 bnx2x_drv_info_fcoe_stat(bp);
3585 break;
3586 case ISCSI_STATS_OPCODE:
3587 bnx2x_drv_info_iscsi_stat(bp);
3588 break;
3589 default:
3590 /* if op code isn't supported - send NACK */
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3592 goto out;
3593 }
3594
3595 /* if we got drv_info attn from MFW then these fields are defined in
3596 * shmem2 for sure
3597 */
3598 SHMEM2_WR(bp, drv_info_host_addr_lo,
3599 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600 SHMEM2_WR(bp, drv_info_host_addr_hi,
3601 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3602
3603 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3604
3605 /* Since possible management wants both this and get_driver_version
3606 * need to wait until management notifies us it finished utilizing
3607 * the buffer.
3608 */
3609 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3610 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3611 } else if (!bp->drv_info_mng_owner) {
3612 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3613
3614 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3615 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3616
3617 /* Management is done; need to clear indication */
3618 if (indication & bit) {
3619 SHMEM2_WR(bp, mfw_drv_indication,
3620 indication & ~bit);
3621 release = true;
3622 break;
3623 }
3624
3625 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3626 }
3627 }
3628 if (!release) {
3629 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3630 bp->drv_info_mng_owner = true;
3631 }
3632
3633 out:
3634 mutex_unlock(&bp->drv_info_mutex);
3635 }
3636
3637 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3638 {
3639 u8 vals[4];
3640 int i = 0;
3641
3642 if (bnx2x_format) {
3643 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3644 &vals[0], &vals[1], &vals[2], &vals[3]);
3645 if (i > 0)
3646 vals[0] -= '0';
3647 } else {
3648 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3649 &vals[0], &vals[1], &vals[2], &vals[3]);
3650 }
3651
3652 while (i < 4)
3653 vals[i++] = 0;
3654
3655 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3656 }
3657
3658 void bnx2x_update_mng_version(struct bnx2x *bp)
3659 {
3660 u32 iscsiver = DRV_VER_NOT_LOADED;
3661 u32 fcoever = DRV_VER_NOT_LOADED;
3662 u32 ethver = DRV_VER_NOT_LOADED;
3663 int idx = BP_FW_MB_IDX(bp);
3664 u8 *version;
3665
3666 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3667 return;
3668
3669 mutex_lock(&bp->drv_info_mutex);
3670 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3671 if (bp->drv_info_mng_owner)
3672 goto out;
3673
3674 if (bp->state != BNX2X_STATE_OPEN)
3675 goto out;
3676
3677 /* Parse ethernet driver version */
3678 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3679 if (!CNIC_LOADED(bp))
3680 goto out;
3681
3682 /* Try getting storage driver version via cnic */
3683 memset(&bp->slowpath->drv_info_to_mcp, 0,
3684 sizeof(union drv_info_to_mcp));
3685 bnx2x_drv_info_iscsi_stat(bp);
3686 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3687 iscsiver = bnx2x_update_mng_version_utility(version, false);
3688
3689 memset(&bp->slowpath->drv_info_to_mcp, 0,
3690 sizeof(union drv_info_to_mcp));
3691 bnx2x_drv_info_fcoe_stat(bp);
3692 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3693 fcoever = bnx2x_update_mng_version_utility(version, false);
3694
3695 out:
3696 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3697 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3699
3700 mutex_unlock(&bp->drv_info_mutex);
3701
3702 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3703 ethver, iscsiver, fcoever);
3704 }
3705
3706 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3707 {
3708 u32 drv_ver;
3709 u32 valid_dump;
3710
3711 if (!SHMEM2_HAS(bp, drv_info))
3712 return;
3713
3714 /* Update Driver load time, possibly broken in y2038 */
3715 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3716
3717 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3718 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3719
3720 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3721
3722 /* Check & notify On-Chip dump. */
3723 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3724
3725 if (valid_dump & FIRST_DUMP_VALID)
3726 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3727
3728 if (valid_dump & SECOND_DUMP_VALID)
3729 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3730 }
3731
3732 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3733 {
3734 u32 cmd_ok, cmd_fail;
3735
3736 /* sanity */
3737 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3738 event & DRV_STATUS_OEM_EVENT_MASK) {
3739 BNX2X_ERR("Received simultaneous events %08x\n", event);
3740 return;
3741 }
3742
3743 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3744 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3745 cmd_ok = DRV_MSG_CODE_DCC_OK;
3746 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3747 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3748 cmd_ok = DRV_MSG_CODE_OEM_OK;
3749 }
3750
3751 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3752
3753 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3754 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3755 /* This is the only place besides the function initialization
3756 * where the bp->flags can change so it is done without any
3757 * locks
3758 */
3759 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3760 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3761 bp->flags |= MF_FUNC_DIS;
3762
3763 bnx2x_e1h_disable(bp);
3764 } else {
3765 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3766 bp->flags &= ~MF_FUNC_DIS;
3767
3768 bnx2x_e1h_enable(bp);
3769 }
3770 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3771 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3772 }
3773
3774 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3775 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3776 bnx2x_config_mf_bw(bp);
3777 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3778 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3779 }
3780
3781 /* Report results to MCP */
3782 if (event)
3783 bnx2x_fw_command(bp, cmd_fail, 0);
3784 else
3785 bnx2x_fw_command(bp, cmd_ok, 0);
3786 }
3787
3788 /* must be called under the spq lock */
3789 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3790 {
3791 struct eth_spe *next_spe = bp->spq_prod_bd;
3792
3793 if (bp->spq_prod_bd == bp->spq_last_bd) {
3794 bp->spq_prod_bd = bp->spq;
3795 bp->spq_prod_idx = 0;
3796 DP(BNX2X_MSG_SP, "end of spq\n");
3797 } else {
3798 bp->spq_prod_bd++;
3799 bp->spq_prod_idx++;
3800 }
3801 return next_spe;
3802 }
3803
3804 /* must be called under the spq lock */
3805 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3806 {
3807 int func = BP_FUNC(bp);
3808
3809 /*
3810 * Make sure that BD data is updated before writing the producer:
3811 * BD data is written to the memory, the producer is read from the
3812 * memory, thus we need a full memory barrier to ensure the ordering.
3813 */
3814 mb();
3815
3816 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3817 bp->spq_prod_idx);
3818 mmiowb();
3819 }
3820
3821 /**
3822 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3823 *
3824 * @cmd: command to check
3825 * @cmd_type: command type
3826 */
3827 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3828 {
3829 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3830 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3831 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3832 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3833 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3834 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3835 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3836 return true;
3837 else
3838 return false;
3839 }
3840
3841 /**
3842 * bnx2x_sp_post - place a single command on an SP ring
3843 *
3844 * @bp: driver handle
3845 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3846 * @cid: SW CID the command is related to
3847 * @data_hi: command private data address (high 32 bits)
3848 * @data_lo: command private data address (low 32 bits)
3849 * @cmd_type: command type (e.g. NONE, ETH)
3850 *
3851 * SP data is handled as if it's always an address pair, thus data fields are
3852 * not swapped to little endian in upper functions. Instead this function swaps
3853 * data as if it's two u32 fields.
3854 */
3855 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3856 u32 data_hi, u32 data_lo, int cmd_type)
3857 {
3858 struct eth_spe *spe;
3859 u16 type;
3860 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3861
3862 #ifdef BNX2X_STOP_ON_ERROR
3863 if (unlikely(bp->panic)) {
3864 BNX2X_ERR("Can't post SP when there is panic\n");
3865 return -EIO;
3866 }
3867 #endif
3868
3869 spin_lock_bh(&bp->spq_lock);
3870
3871 if (common) {
3872 if (!atomic_read(&bp->eq_spq_left)) {
3873 BNX2X_ERR("BUG! EQ ring full!\n");
3874 spin_unlock_bh(&bp->spq_lock);
3875 bnx2x_panic();
3876 return -EBUSY;
3877 }
3878 } else if (!atomic_read(&bp->cq_spq_left)) {
3879 BNX2X_ERR("BUG! SPQ ring full!\n");
3880 spin_unlock_bh(&bp->spq_lock);
3881 bnx2x_panic();
3882 return -EBUSY;
3883 }
3884
3885 spe = bnx2x_sp_get_next(bp);
3886
3887 /* CID needs port number to be encoded int it */
3888 spe->hdr.conn_and_cmd_data =
3889 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3890 HW_CID(bp, cid));
3891
3892 /* In some cases, type may already contain the func-id
3893 * mainly in SRIOV related use cases, so we add it here only
3894 * if it's not already set.
3895 */
3896 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3897 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3898 SPE_HDR_CONN_TYPE;
3899 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3900 SPE_HDR_FUNCTION_ID);
3901 } else {
3902 type = cmd_type;
3903 }
3904
3905 spe->hdr.type = cpu_to_le16(type);
3906
3907 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3908 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3909
3910 /*
3911 * It's ok if the actual decrement is issued towards the memory
3912 * somewhere between the spin_lock and spin_unlock. Thus no
3913 * more explicit memory barrier is needed.
3914 */
3915 if (common)
3916 atomic_dec(&bp->eq_spq_left);
3917 else
3918 atomic_dec(&bp->cq_spq_left);
3919
3920 DP(BNX2X_MSG_SP,
3921 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3922 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3923 (u32)(U64_LO(bp->spq_mapping) +
3924 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3925 HW_CID(bp, cid), data_hi, data_lo, type,
3926 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3927
3928 bnx2x_sp_prod_update(bp);
3929 spin_unlock_bh(&bp->spq_lock);
3930 return 0;
3931 }
3932
3933 /* acquire split MCP access lock register */
3934 static int bnx2x_acquire_alr(struct bnx2x *bp)
3935 {
3936 u32 j, val;
3937 int rc = 0;
3938
3939 might_sleep();
3940 for (j = 0; j < 1000; j++) {
3941 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3942 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3943 if (val & MCPR_ACCESS_LOCK_LOCK)
3944 break;
3945
3946 usleep_range(5000, 10000);
3947 }
3948 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3949 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3950 rc = -EBUSY;
3951 }
3952
3953 return rc;
3954 }
3955
3956 /* release split MCP access lock register */
3957 static void bnx2x_release_alr(struct bnx2x *bp)
3958 {
3959 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3960 }
3961
3962 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3963 #define BNX2X_DEF_SB_IDX 0x0002
3964
3965 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3966 {
3967 struct host_sp_status_block *def_sb = bp->def_status_blk;
3968 u16 rc = 0;
3969
3970 barrier(); /* status block is written to by the chip */
3971 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3972 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3973 rc |= BNX2X_DEF_SB_ATT_IDX;
3974 }
3975
3976 if (bp->def_idx != def_sb->sp_sb.running_index) {
3977 bp->def_idx = def_sb->sp_sb.running_index;
3978 rc |= BNX2X_DEF_SB_IDX;
3979 }
3980
3981 /* Do not reorder: indices reading should complete before handling */
3982 barrier();
3983 return rc;
3984 }
3985
3986 /*
3987 * slow path service functions
3988 */
3989
3990 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3991 {
3992 int port = BP_PORT(bp);
3993 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3994 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3995 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3996 NIG_REG_MASK_INTERRUPT_PORT0;
3997 u32 aeu_mask;
3998 u32 nig_mask = 0;
3999 u32 reg_addr;
4000
4001 if (bp->attn_state & asserted)
4002 BNX2X_ERR("IGU ERROR\n");
4003
4004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4005 aeu_mask = REG_RD(bp, aeu_addr);
4006
4007 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
4008 aeu_mask, asserted);
4009 aeu_mask &= ~(asserted & 0x3ff);
4010 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4011
4012 REG_WR(bp, aeu_addr, aeu_mask);
4013 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4014
4015 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4016 bp->attn_state |= asserted;
4017 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4018
4019 if (asserted & ATTN_HARD_WIRED_MASK) {
4020 if (asserted & ATTN_NIG_FOR_FUNC) {
4021
4022 bnx2x_acquire_phy_lock(bp);
4023
4024 /* save nig interrupt mask */
4025 nig_mask = REG_RD(bp, nig_int_mask_addr);
4026
4027 /* If nig_mask is not set, no need to call the update
4028 * function.
4029 */
4030 if (nig_mask) {
4031 REG_WR(bp, nig_int_mask_addr, 0);
4032
4033 bnx2x_link_attn(bp);
4034 }
4035
4036 /* handle unicore attn? */
4037 }
4038 if (asserted & ATTN_SW_TIMER_4_FUNC)
4039 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4040
4041 if (asserted & GPIO_2_FUNC)
4042 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4043
4044 if (asserted & GPIO_3_FUNC)
4045 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4046
4047 if (asserted & GPIO_4_FUNC)
4048 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4049
4050 if (port == 0) {
4051 if (asserted & ATTN_GENERAL_ATTN_1) {
4052 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4053 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4054 }
4055 if (asserted & ATTN_GENERAL_ATTN_2) {
4056 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4057 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4058 }
4059 if (asserted & ATTN_GENERAL_ATTN_3) {
4060 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4061 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4062 }
4063 } else {
4064 if (asserted & ATTN_GENERAL_ATTN_4) {
4065 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4066 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4067 }
4068 if (asserted & ATTN_GENERAL_ATTN_5) {
4069 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4070 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4071 }
4072 if (asserted & ATTN_GENERAL_ATTN_6) {
4073 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4074 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4075 }
4076 }
4077
4078 } /* if hardwired */
4079
4080 if (bp->common.int_block == INT_BLOCK_HC)
4081 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4082 COMMAND_REG_ATTN_BITS_SET);
4083 else
4084 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4085
4086 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4087 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4088 REG_WR(bp, reg_addr, asserted);
4089
4090 /* now set back the mask */
4091 if (asserted & ATTN_NIG_FOR_FUNC) {
4092 /* Verify that IGU ack through BAR was written before restoring
4093 * NIG mask. This loop should exit after 2-3 iterations max.
4094 */
4095 if (bp->common.int_block != INT_BLOCK_HC) {
4096 u32 cnt = 0, igu_acked;
4097 do {
4098 igu_acked = REG_RD(bp,
4099 IGU_REG_ATTENTION_ACK_BITS);
4100 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4101 (++cnt < MAX_IGU_ATTN_ACK_TO));
4102 if (!igu_acked)
4103 DP(NETIF_MSG_HW,
4104 "Failed to verify IGU ack on time\n");
4105 barrier();
4106 }
4107 REG_WR(bp, nig_int_mask_addr, nig_mask);
4108 bnx2x_release_phy_lock(bp);
4109 }
4110 }
4111
4112 static void bnx2x_fan_failure(struct bnx2x *bp)
4113 {
4114 int port = BP_PORT(bp);
4115 u32 ext_phy_config;
4116 /* mark the failure */
4117 ext_phy_config =
4118 SHMEM_RD(bp,
4119 dev_info.port_hw_config[port].external_phy_config);
4120
4121 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4122 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4123 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4124 ext_phy_config);
4125
4126 /* log the failure */
4127 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4128 "Please contact OEM Support for assistance\n");
4129
4130 /* Schedule device reset (unload)
4131 * This is due to some boards consuming sufficient power when driver is
4132 * up to overheat if fan fails.
4133 */
4134 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4135 }
4136
4137 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4138 {
4139 int port = BP_PORT(bp);
4140 int reg_offset;
4141 u32 val;
4142
4143 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4144 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4145
4146 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4147
4148 val = REG_RD(bp, reg_offset);
4149 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4150 REG_WR(bp, reg_offset, val);
4151
4152 BNX2X_ERR("SPIO5 hw attention\n");
4153
4154 /* Fan failure attention */
4155 bnx2x_hw_reset_phy(&bp->link_params);
4156 bnx2x_fan_failure(bp);
4157 }
4158
4159 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4160 bnx2x_acquire_phy_lock(bp);
4161 bnx2x_handle_module_detect_int(&bp->link_params);
4162 bnx2x_release_phy_lock(bp);
4163 }
4164
4165 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4166
4167 val = REG_RD(bp, reg_offset);
4168 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4169 REG_WR(bp, reg_offset, val);
4170
4171 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4172 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4173 bnx2x_panic();
4174 }
4175 }
4176
4177 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4178 {
4179 u32 val;
4180
4181 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4182
4183 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4184 BNX2X_ERR("DB hw attention 0x%x\n", val);
4185 /* DORQ discard attention */
4186 if (val & 0x2)
4187 BNX2X_ERR("FATAL error from DORQ\n");
4188 }
4189
4190 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4191
4192 int port = BP_PORT(bp);
4193 int reg_offset;
4194
4195 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4196 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4197
4198 val = REG_RD(bp, reg_offset);
4199 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4200 REG_WR(bp, reg_offset, val);
4201
4202 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4203 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4204 bnx2x_panic();
4205 }
4206 }
4207
4208 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4209 {
4210 u32 val;
4211
4212 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4213
4214 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4215 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4216 /* CFC error attention */
4217 if (val & 0x2)
4218 BNX2X_ERR("FATAL error from CFC\n");
4219 }
4220
4221 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4222 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4223 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4224 /* RQ_USDMDP_FIFO_OVERFLOW */
4225 if (val & 0x18000)
4226 BNX2X_ERR("FATAL error from PXP\n");
4227
4228 if (!CHIP_IS_E1x(bp)) {
4229 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4230 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4231 }
4232 }
4233
4234 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4235
4236 int port = BP_PORT(bp);
4237 int reg_offset;
4238
4239 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4240 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4241
4242 val = REG_RD(bp, reg_offset);
4243 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4244 REG_WR(bp, reg_offset, val);
4245
4246 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4247 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4248 bnx2x_panic();
4249 }
4250 }
4251
4252 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4253 {
4254 u32 val;
4255
4256 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4257
4258 if (attn & BNX2X_PMF_LINK_ASSERT) {
4259 int func = BP_FUNC(bp);
4260
4261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4262 bnx2x_read_mf_cfg(bp);
4263 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4264 func_mf_config[BP_ABS_FUNC(bp)].config);
4265 val = SHMEM_RD(bp,
4266 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4267
4268 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4269 DRV_STATUS_OEM_EVENT_MASK))
4270 bnx2x_oem_event(bp,
4271 (val & (DRV_STATUS_DCC_EVENT_MASK |
4272 DRV_STATUS_OEM_EVENT_MASK)));
4273
4274 if (val & DRV_STATUS_SET_MF_BW)
4275 bnx2x_set_mf_bw(bp);
4276
4277 if (val & DRV_STATUS_DRV_INFO_REQ)
4278 bnx2x_handle_drv_info_req(bp);
4279
4280 if (val & DRV_STATUS_VF_DISABLED)
4281 bnx2x_schedule_iov_task(bp,
4282 BNX2X_IOV_HANDLE_FLR);
4283
4284 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4285 bnx2x_pmf_update(bp);
4286
4287 if (bp->port.pmf &&
4288 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4289 bp->dcbx_enabled > 0)
4290 /* start dcbx state machine */
4291 bnx2x_dcbx_set_params(bp,
4292 BNX2X_DCBX_STATE_NEG_RECEIVED);
4293 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4294 bnx2x_handle_afex_cmd(bp,
4295 val & DRV_STATUS_AFEX_EVENT_MASK);
4296 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4297 bnx2x_handle_eee_event(bp);
4298
4299 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4300 bnx2x_handle_update_svid_cmd(bp);
4301
4302 if (bp->link_vars.periodic_flags &
4303 PERIODIC_FLAGS_LINK_EVENT) {
4304 /* sync with link */
4305 bnx2x_acquire_phy_lock(bp);
4306 bp->link_vars.periodic_flags &=
4307 ~PERIODIC_FLAGS_LINK_EVENT;
4308 bnx2x_release_phy_lock(bp);
4309 if (IS_MF(bp))
4310 bnx2x_link_sync_notify(bp);
4311 bnx2x_link_report(bp);
4312 }
4313 /* Always call it here: bnx2x_link_report() will
4314 * prevent the link indication duplication.
4315 */
4316 bnx2x__link_status_update(bp);
4317 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4318
4319 BNX2X_ERR("MC assert!\n");
4320 bnx2x_mc_assert(bp);
4321 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4322 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4323 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4324 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4325 bnx2x_panic();
4326
4327 } else if (attn & BNX2X_MCP_ASSERT) {
4328
4329 BNX2X_ERR("MCP assert!\n");
4330 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4331 bnx2x_fw_dump(bp);
4332
4333 } else
4334 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4335 }
4336
4337 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4338 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4339 if (attn & BNX2X_GRC_TIMEOUT) {
4340 val = CHIP_IS_E1(bp) ? 0 :
4341 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4342 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4343 }
4344 if (attn & BNX2X_GRC_RSV) {
4345 val = CHIP_IS_E1(bp) ? 0 :
4346 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4347 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4348 }
4349 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4350 }
4351 }
4352
4353 /*
4354 * Bits map:
4355 * 0-7 - Engine0 load counter.
4356 * 8-15 - Engine1 load counter.
4357 * 16 - Engine0 RESET_IN_PROGRESS bit.
4358 * 17 - Engine1 RESET_IN_PROGRESS bit.
4359 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4360 * on the engine
4361 * 19 - Engine1 ONE_IS_LOADED.
4362 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4363 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4364 * just the one belonging to its engine).
4365 *
4366 */
4367 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4368
4369 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4370 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4371 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4372 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4373 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4374 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4375 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4376
4377 /*
4378 * Set the GLOBAL_RESET bit.
4379 *
4380 * Should be run under rtnl lock
4381 */
4382 void bnx2x_set_reset_global(struct bnx2x *bp)
4383 {
4384 u32 val;
4385 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4386 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4387 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4388 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4389 }
4390
4391 /*
4392 * Clear the GLOBAL_RESET bit.
4393 *
4394 * Should be run under rtnl lock
4395 */
4396 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4397 {
4398 u32 val;
4399 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4401 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4402 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4403 }
4404
4405 /*
4406 * Checks the GLOBAL_RESET bit.
4407 *
4408 * should be run under rtnl lock
4409 */
4410 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4411 {
4412 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4413
4414 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4415 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4416 }
4417
4418 /*
4419 * Clear RESET_IN_PROGRESS bit for the current engine.
4420 *
4421 * Should be run under rtnl lock
4422 */
4423 static void bnx2x_set_reset_done(struct bnx2x *bp)
4424 {
4425 u32 val;
4426 u32 bit = BP_PATH(bp) ?
4427 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4428 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4430
4431 /* Clear the bit */
4432 val &= ~bit;
4433 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4434
4435 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4436 }
4437
4438 /*
4439 * Set RESET_IN_PROGRESS for the current engine.
4440 *
4441 * should be run under rtnl lock
4442 */
4443 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4444 {
4445 u32 val;
4446 u32 bit = BP_PATH(bp) ?
4447 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4448 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4449 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4450
4451 /* Set the bit */
4452 val |= bit;
4453 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4454 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4455 }
4456
4457 /*
4458 * Checks the RESET_IN_PROGRESS bit for the given engine.
4459 * should be run under rtnl lock
4460 */
4461 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4462 {
4463 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4464 u32 bit = engine ?
4465 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4466
4467 /* return false if bit is set */
4468 return (val & bit) ? false : true;
4469 }
4470
4471 /*
4472 * set pf load for the current pf.
4473 *
4474 * should be run under rtnl lock
4475 */
4476 void bnx2x_set_pf_load(struct bnx2x *bp)
4477 {
4478 u32 val1, val;
4479 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4480 BNX2X_PATH0_LOAD_CNT_MASK;
4481 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4482 BNX2X_PATH0_LOAD_CNT_SHIFT;
4483
4484 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4485 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4486
4487 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4488
4489 /* get the current counter value */
4490 val1 = (val & mask) >> shift;
4491
4492 /* set bit of that PF */
4493 val1 |= (1 << bp->pf_num);
4494
4495 /* clear the old value */
4496 val &= ~mask;
4497
4498 /* set the new one */
4499 val |= ((val1 << shift) & mask);
4500
4501 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4502 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4503 }
4504
4505 /**
4506 * bnx2x_clear_pf_load - clear pf load mark
4507 *
4508 * @bp: driver handle
4509 *
4510 * Should be run under rtnl lock.
4511 * Decrements the load counter for the current engine. Returns
4512 * whether other functions are still loaded
4513 */
4514 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4515 {
4516 u32 val1, val;
4517 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4518 BNX2X_PATH0_LOAD_CNT_MASK;
4519 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4520 BNX2X_PATH0_LOAD_CNT_SHIFT;
4521
4522 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4523 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4524 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4525
4526 /* get the current counter value */
4527 val1 = (val & mask) >> shift;
4528
4529 /* clear bit of that PF */
4530 val1 &= ~(1 << bp->pf_num);
4531
4532 /* clear the old value */
4533 val &= ~mask;
4534
4535 /* set the new one */
4536 val |= ((val1 << shift) & mask);
4537
4538 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4539 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4540 return val1 != 0;
4541 }
4542
4543 /*
4544 * Read the load status for the current engine.
4545 *
4546 * should be run under rtnl lock
4547 */
4548 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4549 {
4550 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4551 BNX2X_PATH0_LOAD_CNT_MASK);
4552 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4553 BNX2X_PATH0_LOAD_CNT_SHIFT);
4554 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4555
4556 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4557
4558 val = (val & mask) >> shift;
4559
4560 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4561 engine, val);
4562
4563 return val != 0;
4564 }
4565
4566 static void _print_parity(struct bnx2x *bp, u32 reg)
4567 {
4568 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4569 }
4570
4571 static void _print_next_block(int idx, const char *blk)
4572 {
4573 pr_cont("%s%s", idx ? ", " : "", blk);
4574 }
4575
4576 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4577 int *par_num, bool print)
4578 {
4579 u32 cur_bit;
4580 bool res;
4581 int i;
4582
4583 res = false;
4584
4585 for (i = 0; sig; i++) {
4586 cur_bit = (0x1UL << i);
4587 if (sig & cur_bit) {
4588 res |= true; /* Each bit is real error! */
4589
4590 if (print) {
4591 switch (cur_bit) {
4592 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4593 _print_next_block((*par_num)++, "BRB");
4594 _print_parity(bp,
4595 BRB1_REG_BRB1_PRTY_STS);
4596 break;
4597 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4598 _print_next_block((*par_num)++,
4599 "PARSER");
4600 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4601 break;
4602 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4603 _print_next_block((*par_num)++, "TSDM");
4604 _print_parity(bp,
4605 TSDM_REG_TSDM_PRTY_STS);
4606 break;
4607 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4608 _print_next_block((*par_num)++,
4609 "SEARCHER");
4610 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4611 break;
4612 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4613 _print_next_block((*par_num)++, "TCM");
4614 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4615 break;
4616 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4617 _print_next_block((*par_num)++,
4618 "TSEMI");
4619 _print_parity(bp,
4620 TSEM_REG_TSEM_PRTY_STS_0);
4621 _print_parity(bp,
4622 TSEM_REG_TSEM_PRTY_STS_1);
4623 break;
4624 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4625 _print_next_block((*par_num)++, "XPB");
4626 _print_parity(bp, GRCBASE_XPB +
4627 PB_REG_PB_PRTY_STS);
4628 break;
4629 }
4630 }
4631
4632 /* Clear the bit */
4633 sig &= ~cur_bit;
4634 }
4635 }
4636
4637 return res;
4638 }
4639
4640 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4641 int *par_num, bool *global,
4642 bool print)
4643 {
4644 u32 cur_bit;
4645 bool res;
4646 int i;
4647
4648 res = false;
4649
4650 for (i = 0; sig; i++) {
4651 cur_bit = (0x1UL << i);
4652 if (sig & cur_bit) {
4653 res |= true; /* Each bit is real error! */
4654 switch (cur_bit) {
4655 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4656 if (print) {
4657 _print_next_block((*par_num)++, "PBF");
4658 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4659 }
4660 break;
4661 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4662 if (print) {
4663 _print_next_block((*par_num)++, "QM");
4664 _print_parity(bp, QM_REG_QM_PRTY_STS);
4665 }
4666 break;
4667 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4668 if (print) {
4669 _print_next_block((*par_num)++, "TM");
4670 _print_parity(bp, TM_REG_TM_PRTY_STS);
4671 }
4672 break;
4673 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4674 if (print) {
4675 _print_next_block((*par_num)++, "XSDM");
4676 _print_parity(bp,
4677 XSDM_REG_XSDM_PRTY_STS);
4678 }
4679 break;
4680 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4681 if (print) {
4682 _print_next_block((*par_num)++, "XCM");
4683 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4684 }
4685 break;
4686 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4687 if (print) {
4688 _print_next_block((*par_num)++,
4689 "XSEMI");
4690 _print_parity(bp,
4691 XSEM_REG_XSEM_PRTY_STS_0);
4692 _print_parity(bp,
4693 XSEM_REG_XSEM_PRTY_STS_1);
4694 }
4695 break;
4696 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4697 if (print) {
4698 _print_next_block((*par_num)++,
4699 "DOORBELLQ");
4700 _print_parity(bp,
4701 DORQ_REG_DORQ_PRTY_STS);
4702 }
4703 break;
4704 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4705 if (print) {
4706 _print_next_block((*par_num)++, "NIG");
4707 if (CHIP_IS_E1x(bp)) {
4708 _print_parity(bp,
4709 NIG_REG_NIG_PRTY_STS);
4710 } else {
4711 _print_parity(bp,
4712 NIG_REG_NIG_PRTY_STS_0);
4713 _print_parity(bp,
4714 NIG_REG_NIG_PRTY_STS_1);
4715 }
4716 }
4717 break;
4718 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4719 if (print)
4720 _print_next_block((*par_num)++,
4721 "VAUX PCI CORE");
4722 *global = true;
4723 break;
4724 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4725 if (print) {
4726 _print_next_block((*par_num)++,
4727 "DEBUG");
4728 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4729 }
4730 break;
4731 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4732 if (print) {
4733 _print_next_block((*par_num)++, "USDM");
4734 _print_parity(bp,
4735 USDM_REG_USDM_PRTY_STS);
4736 }
4737 break;
4738 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4739 if (print) {
4740 _print_next_block((*par_num)++, "UCM");
4741 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4742 }
4743 break;
4744 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4745 if (print) {
4746 _print_next_block((*par_num)++,
4747 "USEMI");
4748 _print_parity(bp,
4749 USEM_REG_USEM_PRTY_STS_0);
4750 _print_parity(bp,
4751 USEM_REG_USEM_PRTY_STS_1);
4752 }
4753 break;
4754 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4755 if (print) {
4756 _print_next_block((*par_num)++, "UPB");
4757 _print_parity(bp, GRCBASE_UPB +
4758 PB_REG_PB_PRTY_STS);
4759 }
4760 break;
4761 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4762 if (print) {
4763 _print_next_block((*par_num)++, "CSDM");
4764 _print_parity(bp,
4765 CSDM_REG_CSDM_PRTY_STS);
4766 }
4767 break;
4768 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4769 if (print) {
4770 _print_next_block((*par_num)++, "CCM");
4771 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4772 }
4773 break;
4774 }
4775
4776 /* Clear the bit */
4777 sig &= ~cur_bit;
4778 }
4779 }
4780
4781 return res;
4782 }
4783
4784 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4785 int *par_num, bool print)
4786 {
4787 u32 cur_bit;
4788 bool res;
4789 int i;
4790
4791 res = false;
4792
4793 for (i = 0; sig; i++) {
4794 cur_bit = (0x1UL << i);
4795 if (sig & cur_bit) {
4796 res = true; /* Each bit is real error! */
4797 if (print) {
4798 switch (cur_bit) {
4799 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4800 _print_next_block((*par_num)++,
4801 "CSEMI");
4802 _print_parity(bp,
4803 CSEM_REG_CSEM_PRTY_STS_0);
4804 _print_parity(bp,
4805 CSEM_REG_CSEM_PRTY_STS_1);
4806 break;
4807 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4808 _print_next_block((*par_num)++, "PXP");
4809 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4810 _print_parity(bp,
4811 PXP2_REG_PXP2_PRTY_STS_0);
4812 _print_parity(bp,
4813 PXP2_REG_PXP2_PRTY_STS_1);
4814 break;
4815 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4816 _print_next_block((*par_num)++,
4817 "PXPPCICLOCKCLIENT");
4818 break;
4819 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4820 _print_next_block((*par_num)++, "CFC");
4821 _print_parity(bp,
4822 CFC_REG_CFC_PRTY_STS);
4823 break;
4824 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4825 _print_next_block((*par_num)++, "CDU");
4826 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4827 break;
4828 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4829 _print_next_block((*par_num)++, "DMAE");
4830 _print_parity(bp,
4831 DMAE_REG_DMAE_PRTY_STS);
4832 break;
4833 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4834 _print_next_block((*par_num)++, "IGU");
4835 if (CHIP_IS_E1x(bp))
4836 _print_parity(bp,
4837 HC_REG_HC_PRTY_STS);
4838 else
4839 _print_parity(bp,
4840 IGU_REG_IGU_PRTY_STS);
4841 break;
4842 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4843 _print_next_block((*par_num)++, "MISC");
4844 _print_parity(bp,
4845 MISC_REG_MISC_PRTY_STS);
4846 break;
4847 }
4848 }
4849
4850 /* Clear the bit */
4851 sig &= ~cur_bit;
4852 }
4853 }
4854
4855 return res;
4856 }
4857
4858 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4859 int *par_num, bool *global,
4860 bool print)
4861 {
4862 bool res = false;
4863 u32 cur_bit;
4864 int i;
4865
4866 for (i = 0; sig; i++) {
4867 cur_bit = (0x1UL << i);
4868 if (sig & cur_bit) {
4869 switch (cur_bit) {
4870 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4871 if (print)
4872 _print_next_block((*par_num)++,
4873 "MCP ROM");
4874 *global = true;
4875 res = true;
4876 break;
4877 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4878 if (print)
4879 _print_next_block((*par_num)++,
4880 "MCP UMP RX");
4881 *global = true;
4882 res = true;
4883 break;
4884 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4885 if (print)
4886 _print_next_block((*par_num)++,
4887 "MCP UMP TX");
4888 *global = true;
4889 res = true;
4890 break;
4891 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4892 (*par_num)++;
4893 /* clear latched SCPAD PATIRY from MCP */
4894 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4895 1UL << 10);
4896 break;
4897 }
4898
4899 /* Clear the bit */
4900 sig &= ~cur_bit;
4901 }
4902 }
4903
4904 return res;
4905 }
4906
4907 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4908 int *par_num, bool print)
4909 {
4910 u32 cur_bit;
4911 bool res;
4912 int i;
4913
4914 res = false;
4915
4916 for (i = 0; sig; i++) {
4917 cur_bit = (0x1UL << i);
4918 if (sig & cur_bit) {
4919 res = true; /* Each bit is real error! */
4920 if (print) {
4921 switch (cur_bit) {
4922 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4923 _print_next_block((*par_num)++,
4924 "PGLUE_B");
4925 _print_parity(bp,
4926 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4927 break;
4928 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4929 _print_next_block((*par_num)++, "ATC");
4930 _print_parity(bp,
4931 ATC_REG_ATC_PRTY_STS);
4932 break;
4933 }
4934 }
4935 /* Clear the bit */
4936 sig &= ~cur_bit;
4937 }
4938 }
4939
4940 return res;
4941 }
4942
4943 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4944 u32 *sig)
4945 {
4946 bool res = false;
4947
4948 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4949 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4950 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4951 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4952 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4953 int par_num = 0;
4954
4955 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4956 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4957 sig[0] & HW_PRTY_ASSERT_SET_0,
4958 sig[1] & HW_PRTY_ASSERT_SET_1,
4959 sig[2] & HW_PRTY_ASSERT_SET_2,
4960 sig[3] & HW_PRTY_ASSERT_SET_3,
4961 sig[4] & HW_PRTY_ASSERT_SET_4);
4962 if (print) {
4963 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4964 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4965 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4966 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4967 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4968 netdev_err(bp->dev,
4969 "Parity errors detected in blocks: ");
4970 } else {
4971 print = false;
4972 }
4973 }
4974 res |= bnx2x_check_blocks_with_parity0(bp,
4975 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4976 res |= bnx2x_check_blocks_with_parity1(bp,
4977 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4978 res |= bnx2x_check_blocks_with_parity2(bp,
4979 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4980 res |= bnx2x_check_blocks_with_parity3(bp,
4981 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4982 res |= bnx2x_check_blocks_with_parity4(bp,
4983 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4984
4985 if (print)
4986 pr_cont("\n");
4987 }
4988
4989 return res;
4990 }
4991
4992 /**
4993 * bnx2x_chk_parity_attn - checks for parity attentions.
4994 *
4995 * @bp: driver handle
4996 * @global: true if there was a global attention
4997 * @print: show parity attention in syslog
4998 */
4999 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5000 {
5001 struct attn_route attn = { {0} };
5002 int port = BP_PORT(bp);
5003
5004 attn.sig[0] = REG_RD(bp,
5005 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5006 port*4);
5007 attn.sig[1] = REG_RD(bp,
5008 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5009 port*4);
5010 attn.sig[2] = REG_RD(bp,
5011 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5012 port*4);
5013 attn.sig[3] = REG_RD(bp,
5014 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5015 port*4);
5016 /* Since MCP attentions can't be disabled inside the block, we need to
5017 * read AEU registers to see whether they're currently disabled
5018 */
5019 attn.sig[3] &= ((REG_RD(bp,
5020 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5021 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5022 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5023 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5024
5025 if (!CHIP_IS_E1x(bp))
5026 attn.sig[4] = REG_RD(bp,
5027 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5028 port*4);
5029
5030 return bnx2x_parity_attn(bp, global, print, attn.sig);
5031 }
5032
5033 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5034 {
5035 u32 val;
5036 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5037
5038 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5039 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5040 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5041 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5042 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5043 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5044 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5046 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5048 if (val &
5049 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5050 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5051 if (val &
5052 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5053 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5054 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5056 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5058 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5060 }
5061 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5062 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5063 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5064 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5065 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5066 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5067 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5068 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5070 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5072 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5074 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5076 }
5077
5078 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5079 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5080 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5081 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5082 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5083 }
5084 }
5085
5086 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5087 {
5088 struct attn_route attn, *group_mask;
5089 int port = BP_PORT(bp);
5090 int index;
5091 u32 reg_addr;
5092 u32 val;
5093 u32 aeu_mask;
5094 bool global = false;
5095
5096 /* need to take HW lock because MCP or other port might also
5097 try to handle this event */
5098 bnx2x_acquire_alr(bp);
5099
5100 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5101 #ifndef BNX2X_STOP_ON_ERROR
5102 bp->recovery_state = BNX2X_RECOVERY_INIT;
5103 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5104 /* Disable HW interrupts */
5105 bnx2x_int_disable(bp);
5106 /* In case of parity errors don't handle attentions so that
5107 * other function would "see" parity errors.
5108 */
5109 #else
5110 bnx2x_panic();
5111 #endif
5112 bnx2x_release_alr(bp);
5113 return;
5114 }
5115
5116 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5117 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5118 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5119 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5120 if (!CHIP_IS_E1x(bp))
5121 attn.sig[4] =
5122 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5123 else
5124 attn.sig[4] = 0;
5125
5126 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5127 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5128
5129 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5130 if (deasserted & (1 << index)) {
5131 group_mask = &bp->attn_group[index];
5132
5133 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5134 index,
5135 group_mask->sig[0], group_mask->sig[1],
5136 group_mask->sig[2], group_mask->sig[3],
5137 group_mask->sig[4]);
5138
5139 bnx2x_attn_int_deasserted4(bp,
5140 attn.sig[4] & group_mask->sig[4]);
5141 bnx2x_attn_int_deasserted3(bp,
5142 attn.sig[3] & group_mask->sig[3]);
5143 bnx2x_attn_int_deasserted1(bp,
5144 attn.sig[1] & group_mask->sig[1]);
5145 bnx2x_attn_int_deasserted2(bp,
5146 attn.sig[2] & group_mask->sig[2]);
5147 bnx2x_attn_int_deasserted0(bp,
5148 attn.sig[0] & group_mask->sig[0]);
5149 }
5150 }
5151
5152 bnx2x_release_alr(bp);
5153
5154 if (bp->common.int_block == INT_BLOCK_HC)
5155 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5156 COMMAND_REG_ATTN_BITS_CLR);
5157 else
5158 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5159
5160 val = ~deasserted;
5161 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5162 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5163 REG_WR(bp, reg_addr, val);
5164
5165 if (~bp->attn_state & deasserted)
5166 BNX2X_ERR("IGU ERROR\n");
5167
5168 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5169 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5170
5171 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5172 aeu_mask = REG_RD(bp, reg_addr);
5173
5174 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5175 aeu_mask, deasserted);
5176 aeu_mask |= (deasserted & 0x3ff);
5177 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5178
5179 REG_WR(bp, reg_addr, aeu_mask);
5180 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5181
5182 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5183 bp->attn_state &= ~deasserted;
5184 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5185 }
5186
5187 static void bnx2x_attn_int(struct bnx2x *bp)
5188 {
5189 /* read local copy of bits */
5190 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5191 attn_bits);
5192 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5193 attn_bits_ack);
5194 u32 attn_state = bp->attn_state;
5195
5196 /* look for changed bits */
5197 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5198 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5199
5200 DP(NETIF_MSG_HW,
5201 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5202 attn_bits, attn_ack, asserted, deasserted);
5203
5204 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5205 BNX2X_ERR("BAD attention state\n");
5206
5207 /* handle bits that were raised */
5208 if (asserted)
5209 bnx2x_attn_int_asserted(bp, asserted);
5210
5211 if (deasserted)
5212 bnx2x_attn_int_deasserted(bp, deasserted);
5213 }
5214
5215 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5216 u16 index, u8 op, u8 update)
5217 {
5218 u32 igu_addr = bp->igu_base_addr;
5219 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5220 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5221 igu_addr);
5222 }
5223
5224 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5225 {
5226 /* No memory barriers */
5227 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5228 mmiowb(); /* keep prod updates ordered */
5229 }
5230
5231 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5232 union event_ring_elem *elem)
5233 {
5234 u8 err = elem->message.error;
5235
5236 if (!bp->cnic_eth_dev.starting_cid ||
5237 (cid < bp->cnic_eth_dev.starting_cid &&
5238 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5239 return 1;
5240
5241 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5242
5243 if (unlikely(err)) {
5244
5245 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5246 cid);
5247 bnx2x_panic_dump(bp, false);
5248 }
5249 bnx2x_cnic_cfc_comp(bp, cid, err);
5250 return 0;
5251 }
5252
5253 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5254 {
5255 struct bnx2x_mcast_ramrod_params rparam;
5256 int rc;
5257
5258 memset(&rparam, 0, sizeof(rparam));
5259
5260 rparam.mcast_obj = &bp->mcast_obj;
5261
5262 netif_addr_lock_bh(bp->dev);
5263
5264 /* Clear pending state for the last command */
5265 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5266
5267 /* If there are pending mcast commands - send them */
5268 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5269 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5270 if (rc < 0)
5271 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5272 rc);
5273 }
5274
5275 netif_addr_unlock_bh(bp->dev);
5276 }
5277
5278 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5279 union event_ring_elem *elem)
5280 {
5281 unsigned long ramrod_flags = 0;
5282 int rc = 0;
5283 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5284 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5285
5286 /* Always push next commands out, don't wait here */
5287 __set_bit(RAMROD_CONT, &ramrod_flags);
5288
5289 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5290 >> BNX2X_SWCID_SHIFT) {
5291 case BNX2X_FILTER_MAC_PENDING:
5292 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5293 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5294 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5295 else
5296 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5297
5298 break;
5299 case BNX2X_FILTER_VLAN_PENDING:
5300 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5301 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5302 break;
5303 case BNX2X_FILTER_MCAST_PENDING:
5304 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5305 /* This is only relevant for 57710 where multicast MACs are
5306 * configured as unicast MACs using the same ramrod.
5307 */
5308 bnx2x_handle_mcast_eqe(bp);
5309 return;
5310 default:
5311 BNX2X_ERR("Unsupported classification command: %d\n",
5312 elem->message.data.eth_event.echo);
5313 return;
5314 }
5315
5316 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5317
5318 if (rc < 0)
5319 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5320 else if (rc > 0)
5321 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5322 }
5323
5324 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5325
5326 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5327 {
5328 netif_addr_lock_bh(bp->dev);
5329
5330 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5331
5332 /* Send rx_mode command again if was requested */
5333 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5334 bnx2x_set_storm_rx_mode(bp);
5335 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5336 &bp->sp_state))
5337 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5338 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5339 &bp->sp_state))
5340 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5341
5342 netif_addr_unlock_bh(bp->dev);
5343 }
5344
5345 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5346 union event_ring_elem *elem)
5347 {
5348 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5349 DP(BNX2X_MSG_SP,
5350 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5351 elem->message.data.vif_list_event.func_bit_map);
5352 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5353 elem->message.data.vif_list_event.func_bit_map);
5354 } else if (elem->message.data.vif_list_event.echo ==
5355 VIF_LIST_RULE_SET) {
5356 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5357 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5358 }
5359 }
5360
5361 /* called with rtnl_lock */
5362 static void bnx2x_after_function_update(struct bnx2x *bp)
5363 {
5364 int q, rc;
5365 struct bnx2x_fastpath *fp;
5366 struct bnx2x_queue_state_params queue_params = {NULL};
5367 struct bnx2x_queue_update_params *q_update_params =
5368 &queue_params.params.update;
5369
5370 /* Send Q update command with afex vlan removal values for all Qs */
5371 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5372
5373 /* set silent vlan removal values according to vlan mode */
5374 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5375 &q_update_params->update_flags);
5376 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5377 &q_update_params->update_flags);
5378 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5379
5380 /* in access mode mark mask and value are 0 to strip all vlans */
5381 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5382 q_update_params->silent_removal_value = 0;
5383 q_update_params->silent_removal_mask = 0;
5384 } else {
5385 q_update_params->silent_removal_value =
5386 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5387 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5388 }
5389
5390 for_each_eth_queue(bp, q) {
5391 /* Set the appropriate Queue object */
5392 fp = &bp->fp[q];
5393 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5394
5395 /* send the ramrod */
5396 rc = bnx2x_queue_state_change(bp, &queue_params);
5397 if (rc < 0)
5398 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5399 q);
5400 }
5401
5402 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5403 fp = &bp->fp[FCOE_IDX(bp)];
5404 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5405
5406 /* clear pending completion bit */
5407 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5408
5409 /* mark latest Q bit */
5410 smp_mb__before_atomic();
5411 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5412 smp_mb__after_atomic();
5413
5414 /* send Q update ramrod for FCoE Q */
5415 rc = bnx2x_queue_state_change(bp, &queue_params);
5416 if (rc < 0)
5417 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5418 q);
5419 } else {
5420 /* If no FCoE ring - ACK MCP now */
5421 bnx2x_link_report(bp);
5422 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5423 }
5424 }
5425
5426 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5427 struct bnx2x *bp, u32 cid)
5428 {
5429 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5430
5431 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5432 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5433 else
5434 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5435 }
5436
5437 static void bnx2x_eq_int(struct bnx2x *bp)
5438 {
5439 u16 hw_cons, sw_cons, sw_prod;
5440 union event_ring_elem *elem;
5441 u8 echo;
5442 u32 cid;
5443 u8 opcode;
5444 int rc, spqe_cnt = 0;
5445 struct bnx2x_queue_sp_obj *q_obj;
5446 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5447 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5448
5449 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5450
5451 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5452 * when we get the next-page we need to adjust so the loop
5453 * condition below will be met. The next element is the size of a
5454 * regular element and hence incrementing by 1
5455 */
5456 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5457 hw_cons++;
5458
5459 /* This function may never run in parallel with itself for a
5460 * specific bp, thus there is no need in "paired" read memory
5461 * barrier here.
5462 */
5463 sw_cons = bp->eq_cons;
5464 sw_prod = bp->eq_prod;
5465
5466 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5467 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5468
5469 for (; sw_cons != hw_cons;
5470 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5471
5472 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5473
5474 rc = bnx2x_iov_eq_sp_event(bp, elem);
5475 if (!rc) {
5476 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5477 rc);
5478 goto next_spqe;
5479 }
5480
5481 /* elem CID originates from FW; actually LE */
5482 cid = SW_CID((__force __le32)
5483 elem->message.data.cfc_del_event.cid);
5484 opcode = elem->message.opcode;
5485
5486 /* handle eq element */
5487 switch (opcode) {
5488 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5489 bnx2x_vf_mbx_schedule(bp,
5490 &elem->message.data.vf_pf_event);
5491 continue;
5492
5493 case EVENT_RING_OPCODE_STAT_QUERY:
5494 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5495 "got statistics comp event %d\n",
5496 bp->stats_comp++);
5497 /* nothing to do with stats comp */
5498 goto next_spqe;
5499
5500 case EVENT_RING_OPCODE_CFC_DEL:
5501 /* handle according to cid range */
5502 /*
5503 * we may want to verify here that the bp state is
5504 * HALTING
5505 */
5506 DP(BNX2X_MSG_SP,
5507 "got delete ramrod for MULTI[%d]\n", cid);
5508
5509 if (CNIC_LOADED(bp) &&
5510 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5511 goto next_spqe;
5512
5513 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5514
5515 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5516 break;
5517
5518 goto next_spqe;
5519
5520 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5521 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5522 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5523 if (f_obj->complete_cmd(bp, f_obj,
5524 BNX2X_F_CMD_TX_STOP))
5525 break;
5526 goto next_spqe;
5527
5528 case EVENT_RING_OPCODE_START_TRAFFIC:
5529 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5530 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5531 if (f_obj->complete_cmd(bp, f_obj,
5532 BNX2X_F_CMD_TX_START))
5533 break;
5534 goto next_spqe;
5535
5536 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5537 echo = elem->message.data.function_update_event.echo;
5538 if (echo == SWITCH_UPDATE) {
5539 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5540 "got FUNC_SWITCH_UPDATE ramrod\n");
5541 if (f_obj->complete_cmd(
5542 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5543 break;
5544
5545 } else {
5546 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5547
5548 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5549 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5550 f_obj->complete_cmd(bp, f_obj,
5551 BNX2X_F_CMD_AFEX_UPDATE);
5552
5553 /* We will perform the Queues update from
5554 * sp_rtnl task as all Queue SP operations
5555 * should run under rtnl_lock.
5556 */
5557 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5558 }
5559
5560 goto next_spqe;
5561
5562 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5563 f_obj->complete_cmd(bp, f_obj,
5564 BNX2X_F_CMD_AFEX_VIFLISTS);
5565 bnx2x_after_afex_vif_lists(bp, elem);
5566 goto next_spqe;
5567 case EVENT_RING_OPCODE_FUNCTION_START:
5568 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5569 "got FUNC_START ramrod\n");
5570 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5571 break;
5572
5573 goto next_spqe;
5574
5575 case EVENT_RING_OPCODE_FUNCTION_STOP:
5576 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5577 "got FUNC_STOP ramrod\n");
5578 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5579 break;
5580
5581 goto next_spqe;
5582
5583 case EVENT_RING_OPCODE_SET_TIMESYNC:
5584 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5585 "got set_timesync ramrod completion\n");
5586 if (f_obj->complete_cmd(bp, f_obj,
5587 BNX2X_F_CMD_SET_TIMESYNC))
5588 break;
5589 goto next_spqe;
5590 }
5591
5592 switch (opcode | bp->state) {
5593 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5594 BNX2X_STATE_OPEN):
5595 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5596 BNX2X_STATE_OPENING_WAIT4_PORT):
5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598 BNX2X_STATE_CLOSING_WAIT4_HALT):
5599 cid = elem->message.data.eth_event.echo &
5600 BNX2X_SWCID_MASK;
5601 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5602 cid);
5603 rss_raw->clear_pending(rss_raw);
5604 break;
5605
5606 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5607 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5608 case (EVENT_RING_OPCODE_SET_MAC |
5609 BNX2X_STATE_CLOSING_WAIT4_HALT):
5610 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5611 BNX2X_STATE_OPEN):
5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613 BNX2X_STATE_DIAG):
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615 BNX2X_STATE_CLOSING_WAIT4_HALT):
5616 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5617 bnx2x_handle_classification_eqe(bp, elem);
5618 break;
5619
5620 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5621 BNX2X_STATE_OPEN):
5622 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623 BNX2X_STATE_DIAG):
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625 BNX2X_STATE_CLOSING_WAIT4_HALT):
5626 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5627 bnx2x_handle_mcast_eqe(bp);
5628 break;
5629
5630 case (EVENT_RING_OPCODE_FILTERS_RULES |
5631 BNX2X_STATE_OPEN):
5632 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633 BNX2X_STATE_DIAG):
5634 case (EVENT_RING_OPCODE_FILTERS_RULES |
5635 BNX2X_STATE_CLOSING_WAIT4_HALT):
5636 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5637 bnx2x_handle_rx_mode_eqe(bp);
5638 break;
5639 default:
5640 /* unknown event log error and continue */
5641 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5642 elem->message.opcode, bp->state);
5643 }
5644 next_spqe:
5645 spqe_cnt++;
5646 } /* for */
5647
5648 smp_mb__before_atomic();
5649 atomic_add(spqe_cnt, &bp->eq_spq_left);
5650
5651 bp->eq_cons = sw_cons;
5652 bp->eq_prod = sw_prod;
5653 /* Make sure that above mem writes were issued towards the memory */
5654 smp_wmb();
5655
5656 /* update producer */
5657 bnx2x_update_eq_prod(bp, bp->eq_prod);
5658 }
5659
5660 static void bnx2x_sp_task(struct work_struct *work)
5661 {
5662 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5663
5664 DP(BNX2X_MSG_SP, "sp task invoked\n");
5665
5666 /* make sure the atomic interrupt_occurred has been written */
5667 smp_rmb();
5668 if (atomic_read(&bp->interrupt_occurred)) {
5669
5670 /* what work needs to be performed? */
5671 u16 status = bnx2x_update_dsb_idx(bp);
5672
5673 DP(BNX2X_MSG_SP, "status %x\n", status);
5674 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5675 atomic_set(&bp->interrupt_occurred, 0);
5676
5677 /* HW attentions */
5678 if (status & BNX2X_DEF_SB_ATT_IDX) {
5679 bnx2x_attn_int(bp);
5680 status &= ~BNX2X_DEF_SB_ATT_IDX;
5681 }
5682
5683 /* SP events: STAT_QUERY and others */
5684 if (status & BNX2X_DEF_SB_IDX) {
5685 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5686
5687 if (FCOE_INIT(bp) &&
5688 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5689 /* Prevent local bottom-halves from running as
5690 * we are going to change the local NAPI list.
5691 */
5692 local_bh_disable();
5693 napi_schedule(&bnx2x_fcoe(bp, napi));
5694 local_bh_enable();
5695 }
5696
5697 /* Handle EQ completions */
5698 bnx2x_eq_int(bp);
5699 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5700 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5701
5702 status &= ~BNX2X_DEF_SB_IDX;
5703 }
5704
5705 /* if status is non zero then perhaps something went wrong */
5706 if (unlikely(status))
5707 DP(BNX2X_MSG_SP,
5708 "got an unknown interrupt! (status 0x%x)\n", status);
5709
5710 /* ack status block only if something was actually handled */
5711 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5712 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5713 }
5714
5715 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5716 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5717 &bp->sp_state)) {
5718 bnx2x_link_report(bp);
5719 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5720 }
5721 }
5722
5723 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5724 {
5725 struct net_device *dev = dev_instance;
5726 struct bnx2x *bp = netdev_priv(dev);
5727
5728 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5729 IGU_INT_DISABLE, 0);
5730
5731 #ifdef BNX2X_STOP_ON_ERROR
5732 if (unlikely(bp->panic))
5733 return IRQ_HANDLED;
5734 #endif
5735
5736 if (CNIC_LOADED(bp)) {
5737 struct cnic_ops *c_ops;
5738
5739 rcu_read_lock();
5740 c_ops = rcu_dereference(bp->cnic_ops);
5741 if (c_ops)
5742 c_ops->cnic_handler(bp->cnic_data, NULL);
5743 rcu_read_unlock();
5744 }
5745
5746 /* schedule sp task to perform default status block work, ack
5747 * attentions and enable interrupts.
5748 */
5749 bnx2x_schedule_sp_task(bp);
5750
5751 return IRQ_HANDLED;
5752 }
5753
5754 /* end of slow path */
5755
5756 void bnx2x_drv_pulse(struct bnx2x *bp)
5757 {
5758 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5759 bp->fw_drv_pulse_wr_seq);
5760 }
5761
5762 static void bnx2x_timer(unsigned long data)
5763 {
5764 struct bnx2x *bp = (struct bnx2x *) data;
5765
5766 if (!netif_running(bp->dev))
5767 return;
5768
5769 if (IS_PF(bp) &&
5770 !BP_NOMCP(bp)) {
5771 int mb_idx = BP_FW_MB_IDX(bp);
5772 u16 drv_pulse;
5773 u16 mcp_pulse;
5774
5775 ++bp->fw_drv_pulse_wr_seq;
5776 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5777 drv_pulse = bp->fw_drv_pulse_wr_seq;
5778 bnx2x_drv_pulse(bp);
5779
5780 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5781 MCP_PULSE_SEQ_MASK);
5782 /* The delta between driver pulse and mcp response
5783 * should not get too big. If the MFW is more than 5 pulses
5784 * behind, we should worry about it enough to generate an error
5785 * log.
5786 */
5787 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5788 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5789 drv_pulse, mcp_pulse);
5790 }
5791
5792 if (bp->state == BNX2X_STATE_OPEN)
5793 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5794
5795 /* sample pf vf bulletin board for new posts from pf */
5796 if (IS_VF(bp))
5797 bnx2x_timer_sriov(bp);
5798
5799 mod_timer(&bp->timer, jiffies + bp->current_interval);
5800 }
5801
5802 /* end of Statistics */
5803
5804 /* nic init */
5805
5806 /*
5807 * nic init service functions
5808 */
5809
5810 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5811 {
5812 u32 i;
5813 if (!(len%4) && !(addr%4))
5814 for (i = 0; i < len; i += 4)
5815 REG_WR(bp, addr + i, fill);
5816 else
5817 for (i = 0; i < len; i++)
5818 REG_WR8(bp, addr + i, fill);
5819 }
5820
5821 /* helper: writes FP SP data to FW - data_size in dwords */
5822 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5823 int fw_sb_id,
5824 u32 *sb_data_p,
5825 u32 data_size)
5826 {
5827 int index;
5828 for (index = 0; index < data_size; index++)
5829 REG_WR(bp, BAR_CSTRORM_INTMEM +
5830 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5831 sizeof(u32)*index,
5832 *(sb_data_p + index));
5833 }
5834
5835 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5836 {
5837 u32 *sb_data_p;
5838 u32 data_size = 0;
5839 struct hc_status_block_data_e2 sb_data_e2;
5840 struct hc_status_block_data_e1x sb_data_e1x;
5841
5842 /* disable the function first */
5843 if (!CHIP_IS_E1x(bp)) {
5844 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5845 sb_data_e2.common.state = SB_DISABLED;
5846 sb_data_e2.common.p_func.vf_valid = false;
5847 sb_data_p = (u32 *)&sb_data_e2;
5848 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5849 } else {
5850 memset(&sb_data_e1x, 0,
5851 sizeof(struct hc_status_block_data_e1x));
5852 sb_data_e1x.common.state = SB_DISABLED;
5853 sb_data_e1x.common.p_func.vf_valid = false;
5854 sb_data_p = (u32 *)&sb_data_e1x;
5855 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5856 }
5857 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5858
5859 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5860 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5861 CSTORM_STATUS_BLOCK_SIZE);
5862 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5863 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5864 CSTORM_SYNC_BLOCK_SIZE);
5865 }
5866
5867 /* helper: writes SP SB data to FW */
5868 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5869 struct hc_sp_status_block_data *sp_sb_data)
5870 {
5871 int func = BP_FUNC(bp);
5872 int i;
5873 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5874 REG_WR(bp, BAR_CSTRORM_INTMEM +
5875 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5876 i*sizeof(u32),
5877 *((u32 *)sp_sb_data + i));
5878 }
5879
5880 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5881 {
5882 int func = BP_FUNC(bp);
5883 struct hc_sp_status_block_data sp_sb_data;
5884 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5885
5886 sp_sb_data.state = SB_DISABLED;
5887 sp_sb_data.p_func.vf_valid = false;
5888
5889 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5890
5891 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5892 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5893 CSTORM_SP_STATUS_BLOCK_SIZE);
5894 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5895 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5896 CSTORM_SP_SYNC_BLOCK_SIZE);
5897 }
5898
5899 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5900 int igu_sb_id, int igu_seg_id)
5901 {
5902 hc_sm->igu_sb_id = igu_sb_id;
5903 hc_sm->igu_seg_id = igu_seg_id;
5904 hc_sm->timer_value = 0xFF;
5905 hc_sm->time_to_expire = 0xFFFFFFFF;
5906 }
5907
5908 /* allocates state machine ids. */
5909 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5910 {
5911 /* zero out state machine indices */
5912 /* rx indices */
5913 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5914
5915 /* tx indices */
5916 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5917 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5918 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5919 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5920
5921 /* map indices */
5922 /* rx indices */
5923 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5924 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5925
5926 /* tx indices */
5927 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5928 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5930 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5932 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5934 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935 }
5936
5937 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5938 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5939 {
5940 int igu_seg_id;
5941
5942 struct hc_status_block_data_e2 sb_data_e2;
5943 struct hc_status_block_data_e1x sb_data_e1x;
5944 struct hc_status_block_sm *hc_sm_p;
5945 int data_size;
5946 u32 *sb_data_p;
5947
5948 if (CHIP_INT_MODE_IS_BC(bp))
5949 igu_seg_id = HC_SEG_ACCESS_NORM;
5950 else
5951 igu_seg_id = IGU_SEG_ACCESS_NORM;
5952
5953 bnx2x_zero_fp_sb(bp, fw_sb_id);
5954
5955 if (!CHIP_IS_E1x(bp)) {
5956 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5957 sb_data_e2.common.state = SB_ENABLED;
5958 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5959 sb_data_e2.common.p_func.vf_id = vfid;
5960 sb_data_e2.common.p_func.vf_valid = vf_valid;
5961 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5962 sb_data_e2.common.same_igu_sb_1b = true;
5963 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5964 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5965 hc_sm_p = sb_data_e2.common.state_machine;
5966 sb_data_p = (u32 *)&sb_data_e2;
5967 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5968 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5969 } else {
5970 memset(&sb_data_e1x, 0,
5971 sizeof(struct hc_status_block_data_e1x));
5972 sb_data_e1x.common.state = SB_ENABLED;
5973 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5974 sb_data_e1x.common.p_func.vf_id = 0xff;
5975 sb_data_e1x.common.p_func.vf_valid = false;
5976 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5977 sb_data_e1x.common.same_igu_sb_1b = true;
5978 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5979 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5980 hc_sm_p = sb_data_e1x.common.state_machine;
5981 sb_data_p = (u32 *)&sb_data_e1x;
5982 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5983 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5984 }
5985
5986 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5987 igu_sb_id, igu_seg_id);
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5989 igu_sb_id, igu_seg_id);
5990
5991 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5992
5993 /* write indices to HW - PCI guarantees endianity of regpairs */
5994 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5995 }
5996
5997 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5998 u16 tx_usec, u16 rx_usec)
5999 {
6000 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6001 false, rx_usec);
6002 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6003 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6004 tx_usec);
6005 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6006 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6007 tx_usec);
6008 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6009 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6010 tx_usec);
6011 }
6012
6013 static void bnx2x_init_def_sb(struct bnx2x *bp)
6014 {
6015 struct host_sp_status_block *def_sb = bp->def_status_blk;
6016 dma_addr_t mapping = bp->def_status_blk_mapping;
6017 int igu_sp_sb_index;
6018 int igu_seg_id;
6019 int port = BP_PORT(bp);
6020 int func = BP_FUNC(bp);
6021 int reg_offset, reg_offset_en5;
6022 u64 section;
6023 int index;
6024 struct hc_sp_status_block_data sp_sb_data;
6025 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6026
6027 if (CHIP_INT_MODE_IS_BC(bp)) {
6028 igu_sp_sb_index = DEF_SB_IGU_ID;
6029 igu_seg_id = HC_SEG_ACCESS_DEF;
6030 } else {
6031 igu_sp_sb_index = bp->igu_dsb_id;
6032 igu_seg_id = IGU_SEG_ACCESS_DEF;
6033 }
6034
6035 /* ATTN */
6036 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6037 atten_status_block);
6038 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6039
6040 bp->attn_state = 0;
6041
6042 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6043 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6044 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6045 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6046 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6047 int sindex;
6048 /* take care of sig[0]..sig[4] */
6049 for (sindex = 0; sindex < 4; sindex++)
6050 bp->attn_group[index].sig[sindex] =
6051 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6052
6053 if (!CHIP_IS_E1x(bp))
6054 /*
6055 * enable5 is separate from the rest of the registers,
6056 * and therefore the address skip is 4
6057 * and not 16 between the different groups
6058 */
6059 bp->attn_group[index].sig[4] = REG_RD(bp,
6060 reg_offset_en5 + 0x4*index);
6061 else
6062 bp->attn_group[index].sig[4] = 0;
6063 }
6064
6065 if (bp->common.int_block == INT_BLOCK_HC) {
6066 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6067 HC_REG_ATTN_MSG0_ADDR_L);
6068
6069 REG_WR(bp, reg_offset, U64_LO(section));
6070 REG_WR(bp, reg_offset + 4, U64_HI(section));
6071 } else if (!CHIP_IS_E1x(bp)) {
6072 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6073 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6074 }
6075
6076 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6077 sp_sb);
6078
6079 bnx2x_zero_sp_sb(bp);
6080
6081 /* PCI guarantees endianity of regpairs */
6082 sp_sb_data.state = SB_ENABLED;
6083 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6084 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6085 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6086 sp_sb_data.igu_seg_id = igu_seg_id;
6087 sp_sb_data.p_func.pf_id = func;
6088 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6089 sp_sb_data.p_func.vf_id = 0xff;
6090
6091 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6092
6093 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6094 }
6095
6096 void bnx2x_update_coalesce(struct bnx2x *bp)
6097 {
6098 int i;
6099
6100 for_each_eth_queue(bp, i)
6101 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6102 bp->tx_ticks, bp->rx_ticks);
6103 }
6104
6105 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6106 {
6107 spin_lock_init(&bp->spq_lock);
6108 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6109
6110 bp->spq_prod_idx = 0;
6111 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6112 bp->spq_prod_bd = bp->spq;
6113 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6114 }
6115
6116 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6117 {
6118 int i;
6119 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6120 union event_ring_elem *elem =
6121 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6122
6123 elem->next_page.addr.hi =
6124 cpu_to_le32(U64_HI(bp->eq_mapping +
6125 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6126 elem->next_page.addr.lo =
6127 cpu_to_le32(U64_LO(bp->eq_mapping +
6128 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6129 }
6130 bp->eq_cons = 0;
6131 bp->eq_prod = NUM_EQ_DESC;
6132 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6133 /* we want a warning message before it gets wrought... */
6134 atomic_set(&bp->eq_spq_left,
6135 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6136 }
6137
6138 /* called with netif_addr_lock_bh() */
6139 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6140 unsigned long rx_mode_flags,
6141 unsigned long rx_accept_flags,
6142 unsigned long tx_accept_flags,
6143 unsigned long ramrod_flags)
6144 {
6145 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6146 int rc;
6147
6148 memset(&ramrod_param, 0, sizeof(ramrod_param));
6149
6150 /* Prepare ramrod parameters */
6151 ramrod_param.cid = 0;
6152 ramrod_param.cl_id = cl_id;
6153 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6154 ramrod_param.func_id = BP_FUNC(bp);
6155
6156 ramrod_param.pstate = &bp->sp_state;
6157 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6158
6159 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6160 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6161
6162 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6163
6164 ramrod_param.ramrod_flags = ramrod_flags;
6165 ramrod_param.rx_mode_flags = rx_mode_flags;
6166
6167 ramrod_param.rx_accept_flags = rx_accept_flags;
6168 ramrod_param.tx_accept_flags = tx_accept_flags;
6169
6170 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6171 if (rc < 0) {
6172 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6173 return rc;
6174 }
6175
6176 return 0;
6177 }
6178
6179 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6180 unsigned long *rx_accept_flags,
6181 unsigned long *tx_accept_flags)
6182 {
6183 /* Clear the flags first */
6184 *rx_accept_flags = 0;
6185 *tx_accept_flags = 0;
6186
6187 switch (rx_mode) {
6188 case BNX2X_RX_MODE_NONE:
6189 /*
6190 * 'drop all' supersedes any accept flags that may have been
6191 * passed to the function.
6192 */
6193 break;
6194 case BNX2X_RX_MODE_NORMAL:
6195 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6196 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6197 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6198
6199 /* internal switching mode */
6200 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6201 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6202 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6203
6204 if (bp->accept_any_vlan) {
6205 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6206 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6207 }
6208
6209 break;
6210 case BNX2X_RX_MODE_ALLMULTI:
6211 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6212 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6213 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6214
6215 /* internal switching mode */
6216 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6217 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6218 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6219
6220 if (bp->accept_any_vlan) {
6221 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6222 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6223 }
6224
6225 break;
6226 case BNX2X_RX_MODE_PROMISC:
6227 /* According to definition of SI mode, iface in promisc mode
6228 * should receive matched and unmatched (in resolution of port)
6229 * unicast packets.
6230 */
6231 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6232 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6233 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6234 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6235
6236 /* internal switching mode */
6237 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6238 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6239
6240 if (IS_MF_SI(bp))
6241 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6242 else
6243 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6244
6245 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6246 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6247
6248 break;
6249 default:
6250 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6251 return -EINVAL;
6252 }
6253
6254 return 0;
6255 }
6256
6257 /* called with netif_addr_lock_bh() */
6258 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6259 {
6260 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6261 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6262 int rc;
6263
6264 if (!NO_FCOE(bp))
6265 /* Configure rx_mode of FCoE Queue */
6266 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6267
6268 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6269 &tx_accept_flags);
6270 if (rc)
6271 return rc;
6272
6273 __set_bit(RAMROD_RX, &ramrod_flags);
6274 __set_bit(RAMROD_TX, &ramrod_flags);
6275
6276 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6277 rx_accept_flags, tx_accept_flags,
6278 ramrod_flags);
6279 }
6280
6281 static void bnx2x_init_internal_common(struct bnx2x *bp)
6282 {
6283 int i;
6284
6285 /* Zero this manually as its initialization is
6286 currently missing in the initTool */
6287 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6288 REG_WR(bp, BAR_USTRORM_INTMEM +
6289 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6290 if (!CHIP_IS_E1x(bp)) {
6291 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6292 CHIP_INT_MODE_IS_BC(bp) ?
6293 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6294 }
6295 }
6296
6297 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6298 {
6299 switch (load_code) {
6300 case FW_MSG_CODE_DRV_LOAD_COMMON:
6301 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6302 bnx2x_init_internal_common(bp);
6303 /* no break */
6304
6305 case FW_MSG_CODE_DRV_LOAD_PORT:
6306 /* nothing to do */
6307 /* no break */
6308
6309 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6310 /* internal memory per function is
6311 initialized inside bnx2x_pf_init */
6312 break;
6313
6314 default:
6315 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6316 break;
6317 }
6318 }
6319
6320 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6321 {
6322 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6323 }
6324
6325 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6326 {
6327 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6328 }
6329
6330 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6331 {
6332 if (CHIP_IS_E1x(fp->bp))
6333 return BP_L_ID(fp->bp) + fp->index;
6334 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6335 return bnx2x_fp_igu_sb_id(fp);
6336 }
6337
6338 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6339 {
6340 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6341 u8 cos;
6342 unsigned long q_type = 0;
6343 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6344 fp->rx_queue = fp_idx;
6345 fp->cid = fp_idx;
6346 fp->cl_id = bnx2x_fp_cl_id(fp);
6347 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6348 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6349 /* qZone id equals to FW (per path) client id */
6350 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6351
6352 /* init shortcut */
6353 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6354
6355 /* Setup SB indices */
6356 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6357
6358 /* Configure Queue State object */
6359 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6360 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6361
6362 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6363
6364 /* init tx data */
6365 for_each_cos_in_tx_queue(fp, cos) {
6366 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6367 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6368 FP_COS_TO_TXQ(fp, cos, bp),
6369 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6370 cids[cos] = fp->txdata_ptr[cos]->cid;
6371 }
6372
6373 /* nothing more for vf to do here */
6374 if (IS_VF(bp))
6375 return;
6376
6377 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6378 fp->fw_sb_id, fp->igu_sb_id);
6379 bnx2x_update_fpsb_idx(fp);
6380 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6381 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6382 bnx2x_sp_mapping(bp, q_rdata), q_type);
6383
6384 /**
6385 * Configure classification DBs: Always enable Tx switching
6386 */
6387 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6388
6389 DP(NETIF_MSG_IFUP,
6390 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6391 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6392 fp->igu_sb_id);
6393 }
6394
6395 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6396 {
6397 int i;
6398
6399 for (i = 1; i <= NUM_TX_RINGS; i++) {
6400 struct eth_tx_next_bd *tx_next_bd =
6401 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6402
6403 tx_next_bd->addr_hi =
6404 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6405 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6406 tx_next_bd->addr_lo =
6407 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6408 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6409 }
6410
6411 *txdata->tx_cons_sb = cpu_to_le16(0);
6412
6413 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6414 txdata->tx_db.data.zero_fill1 = 0;
6415 txdata->tx_db.data.prod = 0;
6416
6417 txdata->tx_pkt_prod = 0;
6418 txdata->tx_pkt_cons = 0;
6419 txdata->tx_bd_prod = 0;
6420 txdata->tx_bd_cons = 0;
6421 txdata->tx_pkt = 0;
6422 }
6423
6424 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6425 {
6426 int i;
6427
6428 for_each_tx_queue_cnic(bp, i)
6429 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6430 }
6431
6432 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6433 {
6434 int i;
6435 u8 cos;
6436
6437 for_each_eth_queue(bp, i)
6438 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6439 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6440 }
6441
6442 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6443 {
6444 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6445 unsigned long q_type = 0;
6446
6447 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6448 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6449 BNX2X_FCOE_ETH_CL_ID_IDX);
6450 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6451 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6452 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6453 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6454 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6455 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6456 fp);
6457
6458 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6459
6460 /* qZone id equals to FW (per path) client id */
6461 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6462 /* init shortcut */
6463 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6464 bnx2x_rx_ustorm_prods_offset(fp);
6465
6466 /* Configure Queue State object */
6467 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6468 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6469
6470 /* No multi-CoS for FCoE L2 client */
6471 BUG_ON(fp->max_cos != 1);
6472
6473 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6474 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6475 bnx2x_sp_mapping(bp, q_rdata), q_type);
6476
6477 DP(NETIF_MSG_IFUP,
6478 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6479 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6480 fp->igu_sb_id);
6481 }
6482
6483 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6484 {
6485 if (!NO_FCOE(bp))
6486 bnx2x_init_fcoe_fp(bp);
6487
6488 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6489 BNX2X_VF_ID_INVALID, false,
6490 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6491
6492 /* ensure status block indices were read */
6493 rmb();
6494 bnx2x_init_rx_rings_cnic(bp);
6495 bnx2x_init_tx_rings_cnic(bp);
6496
6497 /* flush all */
6498 mb();
6499 mmiowb();
6500 }
6501
6502 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6503 {
6504 int i;
6505
6506 /* Setup NIC internals and enable interrupts */
6507 for_each_eth_queue(bp, i)
6508 bnx2x_init_eth_fp(bp, i);
6509
6510 /* ensure status block indices were read */
6511 rmb();
6512 bnx2x_init_rx_rings(bp);
6513 bnx2x_init_tx_rings(bp);
6514
6515 if (IS_PF(bp)) {
6516 /* Initialize MOD_ABS interrupts */
6517 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6518 bp->common.shmem_base,
6519 bp->common.shmem2_base, BP_PORT(bp));
6520
6521 /* initialize the default status block and sp ring */
6522 bnx2x_init_def_sb(bp);
6523 bnx2x_update_dsb_idx(bp);
6524 bnx2x_init_sp_ring(bp);
6525 } else {
6526 bnx2x_memset_stats(bp);
6527 }
6528 }
6529
6530 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6531 {
6532 bnx2x_init_eq_ring(bp);
6533 bnx2x_init_internal(bp, load_code);
6534 bnx2x_pf_init(bp);
6535 bnx2x_stats_init(bp);
6536
6537 /* flush all before enabling interrupts */
6538 mb();
6539 mmiowb();
6540
6541 bnx2x_int_enable(bp);
6542
6543 /* Check for SPIO5 */
6544 bnx2x_attn_int_deasserted0(bp,
6545 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6546 AEU_INPUTS_ATTN_BITS_SPIO5);
6547 }
6548
6549 /* gzip service functions */
6550 static int bnx2x_gunzip_init(struct bnx2x *bp)
6551 {
6552 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6553 &bp->gunzip_mapping, GFP_KERNEL);
6554 if (bp->gunzip_buf == NULL)
6555 goto gunzip_nomem1;
6556
6557 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6558 if (bp->strm == NULL)
6559 goto gunzip_nomem2;
6560
6561 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6562 if (bp->strm->workspace == NULL)
6563 goto gunzip_nomem3;
6564
6565 return 0;
6566
6567 gunzip_nomem3:
6568 kfree(bp->strm);
6569 bp->strm = NULL;
6570
6571 gunzip_nomem2:
6572 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6573 bp->gunzip_mapping);
6574 bp->gunzip_buf = NULL;
6575
6576 gunzip_nomem1:
6577 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6578 return -ENOMEM;
6579 }
6580
6581 static void bnx2x_gunzip_end(struct bnx2x *bp)
6582 {
6583 if (bp->strm) {
6584 vfree(bp->strm->workspace);
6585 kfree(bp->strm);
6586 bp->strm = NULL;
6587 }
6588
6589 if (bp->gunzip_buf) {
6590 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6591 bp->gunzip_mapping);
6592 bp->gunzip_buf = NULL;
6593 }
6594 }
6595
6596 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6597 {
6598 int n, rc;
6599
6600 /* check gzip header */
6601 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6602 BNX2X_ERR("Bad gzip header\n");
6603 return -EINVAL;
6604 }
6605
6606 n = 10;
6607
6608 #define FNAME 0x8
6609
6610 if (zbuf[3] & FNAME)
6611 while ((zbuf[n++] != 0) && (n < len));
6612
6613 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6614 bp->strm->avail_in = len - n;
6615 bp->strm->next_out = bp->gunzip_buf;
6616 bp->strm->avail_out = FW_BUF_SIZE;
6617
6618 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6619 if (rc != Z_OK)
6620 return rc;
6621
6622 rc = zlib_inflate(bp->strm, Z_FINISH);
6623 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6624 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6625 bp->strm->msg);
6626
6627 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6628 if (bp->gunzip_outlen & 0x3)
6629 netdev_err(bp->dev,
6630 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6631 bp->gunzip_outlen);
6632 bp->gunzip_outlen >>= 2;
6633
6634 zlib_inflateEnd(bp->strm);
6635
6636 if (rc == Z_STREAM_END)
6637 return 0;
6638
6639 return rc;
6640 }
6641
6642 /* nic load/unload */
6643
6644 /*
6645 * General service functions
6646 */
6647
6648 /* send a NIG loopback debug packet */
6649 static void bnx2x_lb_pckt(struct bnx2x *bp)
6650 {
6651 u32 wb_write[3];
6652
6653 /* Ethernet source and destination addresses */
6654 wb_write[0] = 0x55555555;
6655 wb_write[1] = 0x55555555;
6656 wb_write[2] = 0x20; /* SOP */
6657 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6658
6659 /* NON-IP protocol */
6660 wb_write[0] = 0x09000000;
6661 wb_write[1] = 0x55555555;
6662 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6663 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6664 }
6665
6666 /* some of the internal memories
6667 * are not directly readable from the driver
6668 * to test them we send debug packets
6669 */
6670 static int bnx2x_int_mem_test(struct bnx2x *bp)
6671 {
6672 int factor;
6673 int count, i;
6674 u32 val = 0;
6675
6676 if (CHIP_REV_IS_FPGA(bp))
6677 factor = 120;
6678 else if (CHIP_REV_IS_EMUL(bp))
6679 factor = 200;
6680 else
6681 factor = 1;
6682
6683 /* Disable inputs of parser neighbor blocks */
6684 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6685 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6686 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6687 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6688
6689 /* Write 0 to parser credits for CFC search request */
6690 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6691
6692 /* send Ethernet packet */
6693 bnx2x_lb_pckt(bp);
6694
6695 /* TODO do i reset NIG statistic? */
6696 /* Wait until NIG register shows 1 packet of size 0x10 */
6697 count = 1000 * factor;
6698 while (count) {
6699
6700 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6701 val = *bnx2x_sp(bp, wb_data[0]);
6702 if (val == 0x10)
6703 break;
6704
6705 usleep_range(10000, 20000);
6706 count--;
6707 }
6708 if (val != 0x10) {
6709 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6710 return -1;
6711 }
6712
6713 /* Wait until PRS register shows 1 packet */
6714 count = 1000 * factor;
6715 while (count) {
6716 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6717 if (val == 1)
6718 break;
6719
6720 usleep_range(10000, 20000);
6721 count--;
6722 }
6723 if (val != 0x1) {
6724 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6725 return -2;
6726 }
6727
6728 /* Reset and init BRB, PRS */
6729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6730 msleep(50);
6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6732 msleep(50);
6733 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6734 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6735
6736 DP(NETIF_MSG_HW, "part2\n");
6737
6738 /* Disable inputs of parser neighbor blocks */
6739 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6740 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6741 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6742 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6743
6744 /* Write 0 to parser credits for CFC search request */
6745 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6746
6747 /* send 10 Ethernet packets */
6748 for (i = 0; i < 10; i++)
6749 bnx2x_lb_pckt(bp);
6750
6751 /* Wait until NIG register shows 10 + 1
6752 packets of size 11*0x10 = 0xb0 */
6753 count = 1000 * factor;
6754 while (count) {
6755
6756 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6757 val = *bnx2x_sp(bp, wb_data[0]);
6758 if (val == 0xb0)
6759 break;
6760
6761 usleep_range(10000, 20000);
6762 count--;
6763 }
6764 if (val != 0xb0) {
6765 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6766 return -3;
6767 }
6768
6769 /* Wait until PRS register shows 2 packets */
6770 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6771 if (val != 2)
6772 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6773
6774 /* Write 1 to parser credits for CFC search request */
6775 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6776
6777 /* Wait until PRS register shows 3 packets */
6778 msleep(10 * factor);
6779 /* Wait until NIG register shows 1 packet of size 0x10 */
6780 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6781 if (val != 3)
6782 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6783
6784 /* clear NIG EOP FIFO */
6785 for (i = 0; i < 11; i++)
6786 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6787 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6788 if (val != 1) {
6789 BNX2X_ERR("clear of NIG failed\n");
6790 return -4;
6791 }
6792
6793 /* Reset and init BRB, PRS, NIG */
6794 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6795 msleep(50);
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6797 msleep(50);
6798 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6799 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6800 if (!CNIC_SUPPORT(bp))
6801 /* set NIC mode */
6802 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6803
6804 /* Enable inputs of parser neighbor blocks */
6805 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6806 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6807 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6808 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6809
6810 DP(NETIF_MSG_HW, "done\n");
6811
6812 return 0; /* OK */
6813 }
6814
6815 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6816 {
6817 u32 val;
6818
6819 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6820 if (!CHIP_IS_E1x(bp))
6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6822 else
6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6824 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6825 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6826 /*
6827 * mask read length error interrupts in brb for parser
6828 * (parsing unit and 'checksum and crc' unit)
6829 * these errors are legal (PU reads fixed length and CAC can cause
6830 * read length error on truncated packets)
6831 */
6832 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6833 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6834 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6835 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6836 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6837 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6838 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6839 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6840 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6841 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6842 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6843 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6844 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6845 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6846 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6847 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6848 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6849 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6850 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6851
6852 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6853 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6854 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6855 if (!CHIP_IS_E1x(bp))
6856 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6857 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6858 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6859
6860 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6861 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6862 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6863 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6864
6865 if (!CHIP_IS_E1x(bp))
6866 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6867 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6868
6869 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6870 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6871 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6872 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6873 }
6874
6875 static void bnx2x_reset_common(struct bnx2x *bp)
6876 {
6877 u32 val = 0x1400;
6878
6879 /* reset_common */
6880 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6881 0xd3ffff7f);
6882
6883 if (CHIP_IS_E3(bp)) {
6884 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6885 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6886 }
6887
6888 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6889 }
6890
6891 static void bnx2x_setup_dmae(struct bnx2x *bp)
6892 {
6893 bp->dmae_ready = 0;
6894 spin_lock_init(&bp->dmae_lock);
6895 }
6896
6897 static void bnx2x_init_pxp(struct bnx2x *bp)
6898 {
6899 u16 devctl;
6900 int r_order, w_order;
6901
6902 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6903 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6904 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6905 if (bp->mrrs == -1)
6906 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6907 else {
6908 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6909 r_order = bp->mrrs;
6910 }
6911
6912 bnx2x_init_pxp_arb(bp, r_order, w_order);
6913 }
6914
6915 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6916 {
6917 int is_required;
6918 u32 val;
6919 int port;
6920
6921 if (BP_NOMCP(bp))
6922 return;
6923
6924 is_required = 0;
6925 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6926 SHARED_HW_CFG_FAN_FAILURE_MASK;
6927
6928 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6929 is_required = 1;
6930
6931 /*
6932 * The fan failure mechanism is usually related to the PHY type since
6933 * the power consumption of the board is affected by the PHY. Currently,
6934 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6935 */
6936 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6937 for (port = PORT_0; port < PORT_MAX; port++) {
6938 is_required |=
6939 bnx2x_fan_failure_det_req(
6940 bp,
6941 bp->common.shmem_base,
6942 bp->common.shmem2_base,
6943 port);
6944 }
6945
6946 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6947
6948 if (is_required == 0)
6949 return;
6950
6951 /* Fan failure is indicated by SPIO 5 */
6952 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6953
6954 /* set to active low mode */
6955 val = REG_RD(bp, MISC_REG_SPIO_INT);
6956 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6957 REG_WR(bp, MISC_REG_SPIO_INT, val);
6958
6959 /* enable interrupt to signal the IGU */
6960 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6961 val |= MISC_SPIO_SPIO5;
6962 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6963 }
6964
6965 void bnx2x_pf_disable(struct bnx2x *bp)
6966 {
6967 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6968 val &= ~IGU_PF_CONF_FUNC_EN;
6969
6970 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6971 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6972 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6973 }
6974
6975 static void bnx2x__common_init_phy(struct bnx2x *bp)
6976 {
6977 u32 shmem_base[2], shmem2_base[2];
6978 /* Avoid common init in case MFW supports LFA */
6979 if (SHMEM2_RD(bp, size) >
6980 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6981 return;
6982 shmem_base[0] = bp->common.shmem_base;
6983 shmem2_base[0] = bp->common.shmem2_base;
6984 if (!CHIP_IS_E1x(bp)) {
6985 shmem_base[1] =
6986 SHMEM2_RD(bp, other_shmem_base_addr);
6987 shmem2_base[1] =
6988 SHMEM2_RD(bp, other_shmem2_base_addr);
6989 }
6990 bnx2x_acquire_phy_lock(bp);
6991 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6992 bp->common.chip_id);
6993 bnx2x_release_phy_lock(bp);
6994 }
6995
6996 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6997 {
6998 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6999 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7000 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7001 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7002 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7003
7004 /* make sure this value is 0 */
7005 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7006
7007 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7008 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7009 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7010 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7011 }
7012
7013 static void bnx2x_set_endianity(struct bnx2x *bp)
7014 {
7015 #ifdef __BIG_ENDIAN
7016 bnx2x_config_endianity(bp, 1);
7017 #else
7018 bnx2x_config_endianity(bp, 0);
7019 #endif
7020 }
7021
7022 static void bnx2x_reset_endianity(struct bnx2x *bp)
7023 {
7024 bnx2x_config_endianity(bp, 0);
7025 }
7026
7027 /**
7028 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7029 *
7030 * @bp: driver handle
7031 */
7032 static int bnx2x_init_hw_common(struct bnx2x *bp)
7033 {
7034 u32 val;
7035
7036 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
7037
7038 /*
7039 * take the RESET lock to protect undi_unload flow from accessing
7040 * registers while we're resetting the chip
7041 */
7042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7043
7044 bnx2x_reset_common(bp);
7045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7046
7047 val = 0xfffc;
7048 if (CHIP_IS_E3(bp)) {
7049 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7050 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7051 }
7052 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7053
7054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7055
7056 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7057
7058 if (!CHIP_IS_E1x(bp)) {
7059 u8 abs_func_id;
7060
7061 /**
7062 * 4-port mode or 2-port mode we need to turn of master-enable
7063 * for everyone, after that, turn it back on for self.
7064 * so, we disregard multi-function or not, and always disable
7065 * for all functions on the given path, this means 0,2,4,6 for
7066 * path 0 and 1,3,5,7 for path 1
7067 */
7068 for (abs_func_id = BP_PATH(bp);
7069 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7070 if (abs_func_id == BP_ABS_FUNC(bp)) {
7071 REG_WR(bp,
7072 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7073 1);
7074 continue;
7075 }
7076
7077 bnx2x_pretend_func(bp, abs_func_id);
7078 /* clear pf enable */
7079 bnx2x_pf_disable(bp);
7080 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7081 }
7082 }
7083
7084 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7085 if (CHIP_IS_E1(bp)) {
7086 /* enable HW interrupt from PXP on USDM overflow
7087 bit 16 on INT_MASK_0 */
7088 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7089 }
7090
7091 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7092 bnx2x_init_pxp(bp);
7093 bnx2x_set_endianity(bp);
7094 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7095
7096 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7097 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7098
7099 /* let the HW do it's magic ... */
7100 msleep(100);
7101 /* finish PXP init */
7102 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7103 if (val != 1) {
7104 BNX2X_ERR("PXP2 CFG failed\n");
7105 return -EBUSY;
7106 }
7107 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7108 if (val != 1) {
7109 BNX2X_ERR("PXP2 RD_INIT failed\n");
7110 return -EBUSY;
7111 }
7112
7113 /* Timers bug workaround E2 only. We need to set the entire ILT to
7114 * have entries with value "0" and valid bit on.
7115 * This needs to be done by the first PF that is loaded in a path
7116 * (i.e. common phase)
7117 */
7118 if (!CHIP_IS_E1x(bp)) {
7119 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7120 * (i.e. vnic3) to start even if it is marked as "scan-off".
7121 * This occurs when a different function (func2,3) is being marked
7122 * as "scan-off". Real-life scenario for example: if a driver is being
7123 * load-unloaded while func6,7 are down. This will cause the timer to access
7124 * the ilt, translate to a logical address and send a request to read/write.
7125 * Since the ilt for the function that is down is not valid, this will cause
7126 * a translation error which is unrecoverable.
7127 * The Workaround is intended to make sure that when this happens nothing fatal
7128 * will occur. The workaround:
7129 * 1. First PF driver which loads on a path will:
7130 * a. After taking the chip out of reset, by using pretend,
7131 * it will write "0" to the following registers of
7132 * the other vnics.
7133 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7134 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7135 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7136 * And for itself it will write '1' to
7137 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7138 * dmae-operations (writing to pram for example.)
7139 * note: can be done for only function 6,7 but cleaner this
7140 * way.
7141 * b. Write zero+valid to the entire ILT.
7142 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7143 * VNIC3 (of that port). The range allocated will be the
7144 * entire ILT. This is needed to prevent ILT range error.
7145 * 2. Any PF driver load flow:
7146 * a. ILT update with the physical addresses of the allocated
7147 * logical pages.
7148 * b. Wait 20msec. - note that this timeout is needed to make
7149 * sure there are no requests in one of the PXP internal
7150 * queues with "old" ILT addresses.
7151 * c. PF enable in the PGLC.
7152 * d. Clear the was_error of the PF in the PGLC. (could have
7153 * occurred while driver was down)
7154 * e. PF enable in the CFC (WEAK + STRONG)
7155 * f. Timers scan enable
7156 * 3. PF driver unload flow:
7157 * a. Clear the Timers scan_en.
7158 * b. Polling for scan_on=0 for that PF.
7159 * c. Clear the PF enable bit in the PXP.
7160 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7161 * e. Write zero+valid to all ILT entries (The valid bit must
7162 * stay set)
7163 * f. If this is VNIC 3 of a port then also init
7164 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7165 * to the last entry in the ILT.
7166 *
7167 * Notes:
7168 * Currently the PF error in the PGLC is non recoverable.
7169 * In the future the there will be a recovery routine for this error.
7170 * Currently attention is masked.
7171 * Having an MCP lock on the load/unload process does not guarantee that
7172 * there is no Timer disable during Func6/7 enable. This is because the
7173 * Timers scan is currently being cleared by the MCP on FLR.
7174 * Step 2.d can be done only for PF6/7 and the driver can also check if
7175 * there is error before clearing it. But the flow above is simpler and
7176 * more general.
7177 * All ILT entries are written by zero+valid and not just PF6/7
7178 * ILT entries since in the future the ILT entries allocation for
7179 * PF-s might be dynamic.
7180 */
7181 struct ilt_client_info ilt_cli;
7182 struct bnx2x_ilt ilt;
7183 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7184 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7185
7186 /* initialize dummy TM client */
7187 ilt_cli.start = 0;
7188 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7189 ilt_cli.client_num = ILT_CLIENT_TM;
7190
7191 /* Step 1: set zeroes to all ilt page entries with valid bit on
7192 * Step 2: set the timers first/last ilt entry to point
7193 * to the entire range to prevent ILT range error for 3rd/4th
7194 * vnic (this code assumes existence of the vnic)
7195 *
7196 * both steps performed by call to bnx2x_ilt_client_init_op()
7197 * with dummy TM client
7198 *
7199 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7200 * and his brother are split registers
7201 */
7202 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7203 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7204 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7205
7206 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7207 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7209 }
7210
7211 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7212 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7213
7214 if (!CHIP_IS_E1x(bp)) {
7215 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7216 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7217 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7218
7219 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7220
7221 /* let the HW do it's magic ... */
7222 do {
7223 msleep(200);
7224 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7225 } while (factor-- && (val != 1));
7226
7227 if (val != 1) {
7228 BNX2X_ERR("ATC_INIT failed\n");
7229 return -EBUSY;
7230 }
7231 }
7232
7233 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7234
7235 bnx2x_iov_init_dmae(bp);
7236
7237 /* clean the DMAE memory */
7238 bp->dmae_ready = 1;
7239 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7240
7241 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7242
7243 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7244
7245 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7246
7247 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7248
7249 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7250 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7251 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7252 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7253
7254 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7255
7256 /* QM queues pointers table */
7257 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7258
7259 /* soft reset pulse */
7260 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7261 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7262
7263 if (CNIC_SUPPORT(bp))
7264 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7265
7266 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7267
7268 if (!CHIP_REV_IS_SLOW(bp))
7269 /* enable hw interrupt from doorbell Q */
7270 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7271
7272 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7273
7274 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7275 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7276
7277 if (!CHIP_IS_E1(bp))
7278 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7279
7280 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7281 if (IS_MF_AFEX(bp)) {
7282 /* configure that VNTag and VLAN headers must be
7283 * received in afex mode
7284 */
7285 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7286 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7288 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7289 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7290 } else {
7291 /* Bit-map indicating which L2 hdrs may appear
7292 * after the basic Ethernet header
7293 */
7294 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7295 bp->path_has_ovlan ? 7 : 6);
7296 }
7297 }
7298
7299 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7300 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7301 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7302 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7303
7304 if (!CHIP_IS_E1x(bp)) {
7305 /* reset VFC memories */
7306 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7307 VFC_MEMORIES_RST_REG_CAM_RST |
7308 VFC_MEMORIES_RST_REG_RAM_RST);
7309 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7310 VFC_MEMORIES_RST_REG_CAM_RST |
7311 VFC_MEMORIES_RST_REG_RAM_RST);
7312
7313 msleep(20);
7314 }
7315
7316 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7317 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7318 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7319 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7320
7321 /* sync semi rtc */
7322 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7323 0x80000000);
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7325 0x80000000);
7326
7327 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7328 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7329 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7330
7331 if (!CHIP_IS_E1x(bp)) {
7332 if (IS_MF_AFEX(bp)) {
7333 /* configure that VNTag and VLAN headers must be
7334 * sent in afex mode
7335 */
7336 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7337 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7339 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7340 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7341 } else {
7342 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7343 bp->path_has_ovlan ? 7 : 6);
7344 }
7345 }
7346
7347 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7348
7349 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7350
7351 if (CNIC_SUPPORT(bp)) {
7352 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7353 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7354 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7355 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7356 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7357 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7358 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7359 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7360 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7361 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7362 }
7363 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7364
7365 if (sizeof(union cdu_context) != 1024)
7366 /* we currently assume that a context is 1024 bytes */
7367 dev_alert(&bp->pdev->dev,
7368 "please adjust the size of cdu_context(%ld)\n",
7369 (long)sizeof(union cdu_context));
7370
7371 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7372 val = (4 << 24) + (0 << 12) + 1024;
7373 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7374
7375 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7376 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7377 /* enable context validation interrupt from CFC */
7378 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7379
7380 /* set the thresholds to prevent CFC/CDU race */
7381 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7382
7383 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7384
7385 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7386 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7387
7388 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7389 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7390
7391 /* Reset PCIE errors for debug */
7392 REG_WR(bp, 0x2814, 0xffffffff);
7393 REG_WR(bp, 0x3820, 0xffffffff);
7394
7395 if (!CHIP_IS_E1x(bp)) {
7396 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7397 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7398 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7399 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7400 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7401 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7402 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7403 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7404 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7405 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7406 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7407 }
7408
7409 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7410 if (!CHIP_IS_E1(bp)) {
7411 /* in E3 this done in per-port section */
7412 if (!CHIP_IS_E3(bp))
7413 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7414 }
7415 if (CHIP_IS_E1H(bp))
7416 /* not applicable for E2 (and above ...) */
7417 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7418
7419 if (CHIP_REV_IS_SLOW(bp))
7420 msleep(200);
7421
7422 /* finish CFC init */
7423 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7424 if (val != 1) {
7425 BNX2X_ERR("CFC LL_INIT failed\n");
7426 return -EBUSY;
7427 }
7428 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7429 if (val != 1) {
7430 BNX2X_ERR("CFC AC_INIT failed\n");
7431 return -EBUSY;
7432 }
7433 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7434 if (val != 1) {
7435 BNX2X_ERR("CFC CAM_INIT failed\n");
7436 return -EBUSY;
7437 }
7438 REG_WR(bp, CFC_REG_DEBUG0, 0);
7439
7440 if (CHIP_IS_E1(bp)) {
7441 /* read NIG statistic
7442 to see if this is our first up since powerup */
7443 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7444 val = *bnx2x_sp(bp, wb_data[0]);
7445
7446 /* do internal memory self test */
7447 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7448 BNX2X_ERR("internal mem self test failed\n");
7449 return -EBUSY;
7450 }
7451 }
7452
7453 bnx2x_setup_fan_failure_detection(bp);
7454
7455 /* clear PXP2 attentions */
7456 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7457
7458 bnx2x_enable_blocks_attention(bp);
7459 bnx2x_enable_blocks_parity(bp);
7460
7461 if (!BP_NOMCP(bp)) {
7462 if (CHIP_IS_E1x(bp))
7463 bnx2x__common_init_phy(bp);
7464 } else
7465 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7466
7467 if (SHMEM2_HAS(bp, netproc_fw_ver))
7468 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7469
7470 return 0;
7471 }
7472
7473 /**
7474 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7475 *
7476 * @bp: driver handle
7477 */
7478 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7479 {
7480 int rc = bnx2x_init_hw_common(bp);
7481
7482 if (rc)
7483 return rc;
7484
7485 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7486 if (!BP_NOMCP(bp))
7487 bnx2x__common_init_phy(bp);
7488
7489 return 0;
7490 }
7491
7492 static int bnx2x_init_hw_port(struct bnx2x *bp)
7493 {
7494 int port = BP_PORT(bp);
7495 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7496 u32 low, high;
7497 u32 val, reg;
7498
7499 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7500
7501 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7502
7503 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7504 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7505 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7506
7507 /* Timers bug workaround: disables the pf_master bit in pglue at
7508 * common phase, we need to enable it here before any dmae access are
7509 * attempted. Therefore we manually added the enable-master to the
7510 * port phase (it also happens in the function phase)
7511 */
7512 if (!CHIP_IS_E1x(bp))
7513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7514
7515 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7516 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7517 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7518 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7519
7520 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7521 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7522 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7523 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7524
7525 /* QM cid (connection) count */
7526 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7527
7528 if (CNIC_SUPPORT(bp)) {
7529 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7530 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7531 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7532 }
7533
7534 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7535
7536 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7537
7538 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7539
7540 if (IS_MF(bp))
7541 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7542 else if (bp->dev->mtu > 4096) {
7543 if (bp->flags & ONE_PORT_FLAG)
7544 low = 160;
7545 else {
7546 val = bp->dev->mtu;
7547 /* (24*1024 + val*4)/256 */
7548 low = 96 + (val/64) +
7549 ((val % 64) ? 1 : 0);
7550 }
7551 } else
7552 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7553 high = low + 56; /* 14*1024/256 */
7554 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7555 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7556 }
7557
7558 if (CHIP_MODE_IS_4_PORT(bp))
7559 REG_WR(bp, (BP_PORT(bp) ?
7560 BRB1_REG_MAC_GUARANTIED_1 :
7561 BRB1_REG_MAC_GUARANTIED_0), 40);
7562
7563 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7564 if (CHIP_IS_E3B0(bp)) {
7565 if (IS_MF_AFEX(bp)) {
7566 /* configure headers for AFEX mode */
7567 REG_WR(bp, BP_PORT(bp) ?
7568 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7569 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7570 REG_WR(bp, BP_PORT(bp) ?
7571 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7572 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7573 REG_WR(bp, BP_PORT(bp) ?
7574 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7575 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7576 } else {
7577 /* Ovlan exists only if we are in multi-function +
7578 * switch-dependent mode, in switch-independent there
7579 * is no ovlan headers
7580 */
7581 REG_WR(bp, BP_PORT(bp) ?
7582 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7583 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7584 (bp->path_has_ovlan ? 7 : 6));
7585 }
7586 }
7587
7588 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7589 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7590 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7591 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7592
7593 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7594 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7595 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7596 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7597
7598 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7599 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7600
7601 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7602
7603 if (CHIP_IS_E1x(bp)) {
7604 /* configure PBF to work without PAUSE mtu 9000 */
7605 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7606
7607 /* update threshold */
7608 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7609 /* update init credit */
7610 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7611
7612 /* probe changes */
7613 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7614 udelay(50);
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7616 }
7617
7618 if (CNIC_SUPPORT(bp))
7619 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7620
7621 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7622 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7623
7624 if (CHIP_IS_E1(bp)) {
7625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7626 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7627 }
7628 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7629
7630 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7631
7632 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7633 /* init aeu_mask_attn_func_0/1:
7634 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7635 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7636 * bits 4-7 are used for "per vn group attention" */
7637 val = IS_MF(bp) ? 0xF7 : 0x7;
7638 /* Enable DCBX attention for all but E1 */
7639 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7640 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7641
7642 /* SCPAD_PARITY should NOT trigger close the gates */
7643 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7644 REG_WR(bp, reg,
7645 REG_RD(bp, reg) &
7646 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7647
7648 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7649 REG_WR(bp, reg,
7650 REG_RD(bp, reg) &
7651 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7652
7653 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7654
7655 if (!CHIP_IS_E1x(bp)) {
7656 /* Bit-map indicating which L2 hdrs may appear after the
7657 * basic Ethernet header
7658 */
7659 if (IS_MF_AFEX(bp))
7660 REG_WR(bp, BP_PORT(bp) ?
7661 NIG_REG_P1_HDRS_AFTER_BASIC :
7662 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7663 else
7664 REG_WR(bp, BP_PORT(bp) ?
7665 NIG_REG_P1_HDRS_AFTER_BASIC :
7666 NIG_REG_P0_HDRS_AFTER_BASIC,
7667 IS_MF_SD(bp) ? 7 : 6);
7668
7669 if (CHIP_IS_E3(bp))
7670 REG_WR(bp, BP_PORT(bp) ?
7671 NIG_REG_LLH1_MF_MODE :
7672 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7673 }
7674 if (!CHIP_IS_E3(bp))
7675 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7676
7677 if (!CHIP_IS_E1(bp)) {
7678 /* 0x2 disable mf_ov, 0x1 enable */
7679 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7680 (IS_MF_SD(bp) ? 0x1 : 0x2));
7681
7682 if (!CHIP_IS_E1x(bp)) {
7683 val = 0;
7684 switch (bp->mf_mode) {
7685 case MULTI_FUNCTION_SD:
7686 val = 1;
7687 break;
7688 case MULTI_FUNCTION_SI:
7689 case MULTI_FUNCTION_AFEX:
7690 val = 2;
7691 break;
7692 }
7693
7694 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7695 NIG_REG_LLH0_CLS_TYPE), val);
7696 }
7697 {
7698 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7699 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7700 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7701 }
7702 }
7703
7704 /* If SPIO5 is set to generate interrupts, enable it for this port */
7705 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7706 if (val & MISC_SPIO_SPIO5) {
7707 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7708 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7709 val = REG_RD(bp, reg_addr);
7710 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7711 REG_WR(bp, reg_addr, val);
7712 }
7713
7714 return 0;
7715 }
7716
7717 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7718 {
7719 int reg;
7720 u32 wb_write[2];
7721
7722 if (CHIP_IS_E1(bp))
7723 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7724 else
7725 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7726
7727 wb_write[0] = ONCHIP_ADDR1(addr);
7728 wb_write[1] = ONCHIP_ADDR2(addr);
7729 REG_WR_DMAE(bp, reg, wb_write, 2);
7730 }
7731
7732 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7733 {
7734 u32 data, ctl, cnt = 100;
7735 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7736 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7737 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7738 u32 sb_bit = 1 << (idu_sb_id%32);
7739 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7740 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7741
7742 /* Not supported in BC mode */
7743 if (CHIP_INT_MODE_IS_BC(bp))
7744 return;
7745
7746 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7747 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7748 IGU_REGULAR_CLEANUP_SET |
7749 IGU_REGULAR_BCLEANUP;
7750
7751 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7752 func_encode << IGU_CTRL_REG_FID_SHIFT |
7753 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7754
7755 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7756 data, igu_addr_data);
7757 REG_WR(bp, igu_addr_data, data);
7758 mmiowb();
7759 barrier();
7760 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7761 ctl, igu_addr_ctl);
7762 REG_WR(bp, igu_addr_ctl, ctl);
7763 mmiowb();
7764 barrier();
7765
7766 /* wait for clean up to finish */
7767 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7768 msleep(20);
7769
7770 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7771 DP(NETIF_MSG_HW,
7772 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7773 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7774 }
7775 }
7776
7777 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7778 {
7779 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7780 }
7781
7782 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7783 {
7784 u32 i, base = FUNC_ILT_BASE(func);
7785 for (i = base; i < base + ILT_PER_FUNC; i++)
7786 bnx2x_ilt_wr(bp, i, 0);
7787 }
7788
7789 static void bnx2x_init_searcher(struct bnx2x *bp)
7790 {
7791 int port = BP_PORT(bp);
7792 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7793 /* T1 hash bits value determines the T1 number of entries */
7794 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7795 }
7796
7797 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7798 {
7799 int rc;
7800 struct bnx2x_func_state_params func_params = {NULL};
7801 struct bnx2x_func_switch_update_params *switch_update_params =
7802 &func_params.params.switch_update;
7803
7804 /* Prepare parameters for function state transitions */
7805 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7806 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7807
7808 func_params.f_obj = &bp->func_obj;
7809 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7810
7811 /* Function parameters */
7812 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7813 &switch_update_params->changes);
7814 if (suspend)
7815 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7816 &switch_update_params->changes);
7817
7818 rc = bnx2x_func_state_change(bp, &func_params);
7819
7820 return rc;
7821 }
7822
7823 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7824 {
7825 int rc, i, port = BP_PORT(bp);
7826 int vlan_en = 0, mac_en[NUM_MACS];
7827
7828 /* Close input from network */
7829 if (bp->mf_mode == SINGLE_FUNCTION) {
7830 bnx2x_set_rx_filter(&bp->link_params, 0);
7831 } else {
7832 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7833 NIG_REG_LLH0_FUNC_EN);
7834 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7835 NIG_REG_LLH0_FUNC_EN, 0);
7836 for (i = 0; i < NUM_MACS; i++) {
7837 mac_en[i] = REG_RD(bp, port ?
7838 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7839 4 * i) :
7840 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7841 4 * i));
7842 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7843 4 * i) :
7844 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7845 }
7846 }
7847
7848 /* Close BMC to host */
7849 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7850 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7851
7852 /* Suspend Tx switching to the PF. Completion of this ramrod
7853 * further guarantees that all the packets of that PF / child
7854 * VFs in BRB were processed by the Parser, so it is safe to
7855 * change the NIC_MODE register.
7856 */
7857 rc = bnx2x_func_switch_update(bp, 1);
7858 if (rc) {
7859 BNX2X_ERR("Can't suspend tx-switching!\n");
7860 return rc;
7861 }
7862
7863 /* Change NIC_MODE register */
7864 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7865
7866 /* Open input from network */
7867 if (bp->mf_mode == SINGLE_FUNCTION) {
7868 bnx2x_set_rx_filter(&bp->link_params, 1);
7869 } else {
7870 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7871 NIG_REG_LLH0_FUNC_EN, vlan_en);
7872 for (i = 0; i < NUM_MACS; i++) {
7873 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7874 4 * i) :
7875 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7876 mac_en[i]);
7877 }
7878 }
7879
7880 /* Enable BMC to host */
7881 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7882 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7883
7884 /* Resume Tx switching to the PF */
7885 rc = bnx2x_func_switch_update(bp, 0);
7886 if (rc) {
7887 BNX2X_ERR("Can't resume tx-switching!\n");
7888 return rc;
7889 }
7890
7891 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7892 return 0;
7893 }
7894
7895 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7896 {
7897 int rc;
7898
7899 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7900
7901 if (CONFIGURE_NIC_MODE(bp)) {
7902 /* Configure searcher as part of function hw init */
7903 bnx2x_init_searcher(bp);
7904
7905 /* Reset NIC mode */
7906 rc = bnx2x_reset_nic_mode(bp);
7907 if (rc)
7908 BNX2X_ERR("Can't change NIC mode!\n");
7909 return rc;
7910 }
7911
7912 return 0;
7913 }
7914
7915 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7916 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7917 * the addresses of the transaction, resulting in was-error bit set in the pci
7918 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7919 * to clear the interrupt which detected this from the pglueb and the was done
7920 * bit
7921 */
7922 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7923 {
7924 if (!CHIP_IS_E1x(bp))
7925 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7926 1 << BP_ABS_FUNC(bp));
7927 }
7928
7929 static int bnx2x_init_hw_func(struct bnx2x *bp)
7930 {
7931 int port = BP_PORT(bp);
7932 int func = BP_FUNC(bp);
7933 int init_phase = PHASE_PF0 + func;
7934 struct bnx2x_ilt *ilt = BP_ILT(bp);
7935 u16 cdu_ilt_start;
7936 u32 addr, val;
7937 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7938 int i, main_mem_width, rc;
7939
7940 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7941
7942 /* FLR cleanup - hmmm */
7943 if (!CHIP_IS_E1x(bp)) {
7944 rc = bnx2x_pf_flr_clnup(bp);
7945 if (rc) {
7946 bnx2x_fw_dump(bp);
7947 return rc;
7948 }
7949 }
7950
7951 /* set MSI reconfigure capability */
7952 if (bp->common.int_block == INT_BLOCK_HC) {
7953 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7954 val = REG_RD(bp, addr);
7955 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7956 REG_WR(bp, addr, val);
7957 }
7958
7959 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7960 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7961
7962 ilt = BP_ILT(bp);
7963 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7964
7965 if (IS_SRIOV(bp))
7966 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7967 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7968
7969 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7970 * those of the VFs, so start line should be reset
7971 */
7972 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7973 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7974 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7975 ilt->lines[cdu_ilt_start + i].page_mapping =
7976 bp->context[i].cxt_mapping;
7977 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7978 }
7979
7980 bnx2x_ilt_init_op(bp, INITOP_SET);
7981
7982 if (!CONFIGURE_NIC_MODE(bp)) {
7983 bnx2x_init_searcher(bp);
7984 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7985 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7986 } else {
7987 /* Set NIC mode */
7988 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7989 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7990 }
7991
7992 if (!CHIP_IS_E1x(bp)) {
7993 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7994
7995 /* Turn on a single ISR mode in IGU if driver is going to use
7996 * INT#x or MSI
7997 */
7998 if (!(bp->flags & USING_MSIX_FLAG))
7999 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8000 /*
8001 * Timers workaround bug: function init part.
8002 * Need to wait 20msec after initializing ILT,
8003 * needed to make sure there are no requests in
8004 * one of the PXP internal queues with "old" ILT addresses
8005 */
8006 msleep(20);
8007 /*
8008 * Master enable - Due to WB DMAE writes performed before this
8009 * register is re-initialized as part of the regular function
8010 * init
8011 */
8012 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8013 /* Enable the function in IGU */
8014 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8015 }
8016
8017 bp->dmae_ready = 1;
8018
8019 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8020
8021 bnx2x_clean_pglue_errors(bp);
8022
8023 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8024 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8025 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8026 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8027 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8028 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8029 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8030 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8031 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8032 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8033 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8034 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8035 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8036
8037 if (!CHIP_IS_E1x(bp))
8038 REG_WR(bp, QM_REG_PF_EN, 1);
8039
8040 if (!CHIP_IS_E1x(bp)) {
8041 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8042 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8043 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8045 }
8046 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8047
8048 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8049 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8050 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8051
8052 bnx2x_iov_init_dq(bp);
8053
8054 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8055 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8056 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8057 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8058 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8059 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8060 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8061 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8062 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8063 if (!CHIP_IS_E1x(bp))
8064 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8065
8066 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8067
8068 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8069
8070 if (!CHIP_IS_E1x(bp))
8071 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8072
8073 if (IS_MF(bp)) {
8074 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8076 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8077 bp->mf_ov);
8078 }
8079 }
8080
8081 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8082
8083 /* HC init per function */
8084 if (bp->common.int_block == INT_BLOCK_HC) {
8085 if (CHIP_IS_E1H(bp)) {
8086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8087
8088 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8089 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8090 }
8091 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8092
8093 } else {
8094 int num_segs, sb_idx, prod_offset;
8095
8096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8097
8098 if (!CHIP_IS_E1x(bp)) {
8099 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8100 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8101 }
8102
8103 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8104
8105 if (!CHIP_IS_E1x(bp)) {
8106 int dsb_idx = 0;
8107 /**
8108 * Producer memory:
8109 * E2 mode: address 0-135 match to the mapping memory;
8110 * 136 - PF0 default prod; 137 - PF1 default prod;
8111 * 138 - PF2 default prod; 139 - PF3 default prod;
8112 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8113 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8114 * 144-147 reserved.
8115 *
8116 * E1.5 mode - In backward compatible mode;
8117 * for non default SB; each even line in the memory
8118 * holds the U producer and each odd line hold
8119 * the C producer. The first 128 producers are for
8120 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8121 * producers are for the DSB for each PF.
8122 * Each PF has five segments: (the order inside each
8123 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8124 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8125 * 144-147 attn prods;
8126 */
8127 /* non-default-status-blocks */
8128 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8129 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8130 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8131 prod_offset = (bp->igu_base_sb + sb_idx) *
8132 num_segs;
8133
8134 for (i = 0; i < num_segs; i++) {
8135 addr = IGU_REG_PROD_CONS_MEMORY +
8136 (prod_offset + i) * 4;
8137 REG_WR(bp, addr, 0);
8138 }
8139 /* send consumer update with value 0 */
8140 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8141 USTORM_ID, 0, IGU_INT_NOP, 1);
8142 bnx2x_igu_clear_sb(bp,
8143 bp->igu_base_sb + sb_idx);
8144 }
8145
8146 /* default-status-blocks */
8147 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8148 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8149
8150 if (CHIP_MODE_IS_4_PORT(bp))
8151 dsb_idx = BP_FUNC(bp);
8152 else
8153 dsb_idx = BP_VN(bp);
8154
8155 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8156 IGU_BC_BASE_DSB_PROD + dsb_idx :
8157 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8158
8159 /*
8160 * igu prods come in chunks of E1HVN_MAX (4) -
8161 * does not matters what is the current chip mode
8162 */
8163 for (i = 0; i < (num_segs * E1HVN_MAX);
8164 i += E1HVN_MAX) {
8165 addr = IGU_REG_PROD_CONS_MEMORY +
8166 (prod_offset + i)*4;
8167 REG_WR(bp, addr, 0);
8168 }
8169 /* send consumer update with 0 */
8170 if (CHIP_INT_MODE_IS_BC(bp)) {
8171 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8172 USTORM_ID, 0, IGU_INT_NOP, 1);
8173 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174 CSTORM_ID, 0, IGU_INT_NOP, 1);
8175 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176 XSTORM_ID, 0, IGU_INT_NOP, 1);
8177 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8178 TSTORM_ID, 0, IGU_INT_NOP, 1);
8179 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8180 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8181 } else {
8182 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8183 USTORM_ID, 0, IGU_INT_NOP, 1);
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8186 }
8187 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8188
8189 /* !!! These should become driver const once
8190 rf-tool supports split-68 const */
8191 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8192 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8193 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8194 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8195 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8196 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8197 }
8198 }
8199
8200 /* Reset PCIE errors for debug */
8201 REG_WR(bp, 0x2114, 0xffffffff);
8202 REG_WR(bp, 0x2120, 0xffffffff);
8203
8204 if (CHIP_IS_E1x(bp)) {
8205 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8206 main_mem_base = HC_REG_MAIN_MEMORY +
8207 BP_PORT(bp) * (main_mem_size * 4);
8208 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8209 main_mem_width = 8;
8210
8211 val = REG_RD(bp, main_mem_prty_clr);
8212 if (val)
8213 DP(NETIF_MSG_HW,
8214 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8215 val);
8216
8217 /* Clear "false" parity errors in MSI-X table */
8218 for (i = main_mem_base;
8219 i < main_mem_base + main_mem_size * 4;
8220 i += main_mem_width) {
8221 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8222 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8223 i, main_mem_width / 4);
8224 }
8225 /* Clear HC parity attention */
8226 REG_RD(bp, main_mem_prty_clr);
8227 }
8228
8229 #ifdef BNX2X_STOP_ON_ERROR
8230 /* Enable STORMs SP logging */
8231 REG_WR8(bp, BAR_USTRORM_INTMEM +
8232 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8233 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8234 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8235 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8236 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8237 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8238 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8239 #endif
8240
8241 bnx2x_phy_probe(&bp->link_params);
8242
8243 return 0;
8244 }
8245
8246 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8247 {
8248 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8249
8250 if (!CHIP_IS_E1x(bp))
8251 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8252 sizeof(struct host_hc_status_block_e2));
8253 else
8254 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8255 sizeof(struct host_hc_status_block_e1x));
8256
8257 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8258 }
8259
8260 void bnx2x_free_mem(struct bnx2x *bp)
8261 {
8262 int i;
8263
8264 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8265 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8266
8267 if (IS_VF(bp))
8268 return;
8269
8270 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8271 sizeof(struct host_sp_status_block));
8272
8273 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8274 sizeof(struct bnx2x_slowpath));
8275
8276 for (i = 0; i < L2_ILT_LINES(bp); i++)
8277 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8278 bp->context[i].size);
8279 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8280
8281 BNX2X_FREE(bp->ilt->lines);
8282
8283 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8284
8285 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8286 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8287
8288 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8289
8290 bnx2x_iov_free_mem(bp);
8291 }
8292
8293 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8294 {
8295 if (!CHIP_IS_E1x(bp)) {
8296 /* size = the status block + ramrod buffers */
8297 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8298 sizeof(struct host_hc_status_block_e2));
8299 if (!bp->cnic_sb.e2_sb)
8300 goto alloc_mem_err;
8301 } else {
8302 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8303 sizeof(struct host_hc_status_block_e1x));
8304 if (!bp->cnic_sb.e1x_sb)
8305 goto alloc_mem_err;
8306 }
8307
8308 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8309 /* allocate searcher T2 table, as it wasn't allocated before */
8310 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8311 if (!bp->t2)
8312 goto alloc_mem_err;
8313 }
8314
8315 /* write address to which L5 should insert its values */
8316 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8317 &bp->slowpath->drv_info_to_mcp;
8318
8319 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8320 goto alloc_mem_err;
8321
8322 return 0;
8323
8324 alloc_mem_err:
8325 bnx2x_free_mem_cnic(bp);
8326 BNX2X_ERR("Can't allocate memory\n");
8327 return -ENOMEM;
8328 }
8329
8330 int bnx2x_alloc_mem(struct bnx2x *bp)
8331 {
8332 int i, allocated, context_size;
8333
8334 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8335 /* allocate searcher T2 table */
8336 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8337 if (!bp->t2)
8338 goto alloc_mem_err;
8339 }
8340
8341 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8342 sizeof(struct host_sp_status_block));
8343 if (!bp->def_status_blk)
8344 goto alloc_mem_err;
8345
8346 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8347 sizeof(struct bnx2x_slowpath));
8348 if (!bp->slowpath)
8349 goto alloc_mem_err;
8350
8351 /* Allocate memory for CDU context:
8352 * This memory is allocated separately and not in the generic ILT
8353 * functions because CDU differs in few aspects:
8354 * 1. There are multiple entities allocating memory for context -
8355 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8356 * its own ILT lines.
8357 * 2. Since CDU page-size is not a single 4KB page (which is the case
8358 * for the other ILT clients), to be efficient we want to support
8359 * allocation of sub-page-size in the last entry.
8360 * 3. Context pointers are used by the driver to pass to FW / update
8361 * the context (for the other ILT clients the pointers are used just to
8362 * free the memory during unload).
8363 */
8364 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8365
8366 for (i = 0, allocated = 0; allocated < context_size; i++) {
8367 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8368 (context_size - allocated));
8369 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8370 bp->context[i].size);
8371 if (!bp->context[i].vcxt)
8372 goto alloc_mem_err;
8373 allocated += bp->context[i].size;
8374 }
8375 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8376 GFP_KERNEL);
8377 if (!bp->ilt->lines)
8378 goto alloc_mem_err;
8379
8380 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8381 goto alloc_mem_err;
8382
8383 if (bnx2x_iov_alloc_mem(bp))
8384 goto alloc_mem_err;
8385
8386 /* Slow path ring */
8387 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8388 if (!bp->spq)
8389 goto alloc_mem_err;
8390
8391 /* EQ */
8392 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8393 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8394 if (!bp->eq_ring)
8395 goto alloc_mem_err;
8396
8397 return 0;
8398
8399 alloc_mem_err:
8400 bnx2x_free_mem(bp);
8401 BNX2X_ERR("Can't allocate memory\n");
8402 return -ENOMEM;
8403 }
8404
8405 /*
8406 * Init service functions
8407 */
8408
8409 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8410 struct bnx2x_vlan_mac_obj *obj, bool set,
8411 int mac_type, unsigned long *ramrod_flags)
8412 {
8413 int rc;
8414 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8415
8416 memset(&ramrod_param, 0, sizeof(ramrod_param));
8417
8418 /* Fill general parameters */
8419 ramrod_param.vlan_mac_obj = obj;
8420 ramrod_param.ramrod_flags = *ramrod_flags;
8421
8422 /* Fill a user request section if needed */
8423 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8424 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8425
8426 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8427
8428 /* Set the command: ADD or DEL */
8429 if (set)
8430 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8431 else
8432 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8433 }
8434
8435 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8436
8437 if (rc == -EEXIST) {
8438 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8439 /* do not treat adding same MAC as error */
8440 rc = 0;
8441 } else if (rc < 0)
8442 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8443
8444 return rc;
8445 }
8446
8447 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8448 struct bnx2x_vlan_mac_obj *obj, bool set,
8449 unsigned long *ramrod_flags)
8450 {
8451 int rc;
8452 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8453
8454 memset(&ramrod_param, 0, sizeof(ramrod_param));
8455
8456 /* Fill general parameters */
8457 ramrod_param.vlan_mac_obj = obj;
8458 ramrod_param.ramrod_flags = *ramrod_flags;
8459
8460 /* Fill a user request section if needed */
8461 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8462 ramrod_param.user_req.u.vlan.vlan = vlan;
8463 /* Set the command: ADD or DEL */
8464 if (set)
8465 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8466 else
8467 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8468 }
8469
8470 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8471
8472 if (rc == -EEXIST) {
8473 /* Do not treat adding same vlan as error. */
8474 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8475 rc = 0;
8476 } else if (rc < 0) {
8477 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8478 }
8479
8480 return rc;
8481 }
8482
8483 int bnx2x_del_all_macs(struct bnx2x *bp,
8484 struct bnx2x_vlan_mac_obj *mac_obj,
8485 int mac_type, bool wait_for_comp)
8486 {
8487 int rc;
8488 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8489
8490 /* Wait for completion of requested */
8491 if (wait_for_comp)
8492 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8493
8494 /* Set the mac type of addresses we want to clear */
8495 __set_bit(mac_type, &vlan_mac_flags);
8496
8497 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8498 if (rc < 0)
8499 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8500
8501 return rc;
8502 }
8503
8504 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8505 {
8506 if (IS_PF(bp)) {
8507 unsigned long ramrod_flags = 0;
8508
8509 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8510 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8511 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8512 &bp->sp_objs->mac_obj, set,
8513 BNX2X_ETH_MAC, &ramrod_flags);
8514 } else { /* vf */
8515 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8516 bp->fp->index, set);
8517 }
8518 }
8519
8520 int bnx2x_setup_leading(struct bnx2x *bp)
8521 {
8522 if (IS_PF(bp))
8523 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8524 else /* VF */
8525 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8526 }
8527
8528 /**
8529 * bnx2x_set_int_mode - configure interrupt mode
8530 *
8531 * @bp: driver handle
8532 *
8533 * In case of MSI-X it will also try to enable MSI-X.
8534 */
8535 int bnx2x_set_int_mode(struct bnx2x *bp)
8536 {
8537 int rc = 0;
8538
8539 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8540 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8541 return -EINVAL;
8542 }
8543
8544 switch (int_mode) {
8545 case BNX2X_INT_MODE_MSIX:
8546 /* attempt to enable msix */
8547 rc = bnx2x_enable_msix(bp);
8548
8549 /* msix attained */
8550 if (!rc)
8551 return 0;
8552
8553 /* vfs use only msix */
8554 if (rc && IS_VF(bp))
8555 return rc;
8556
8557 /* failed to enable multiple MSI-X */
8558 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8559 bp->num_queues,
8560 1 + bp->num_cnic_queues);
8561
8562 /* falling through... */
8563 case BNX2X_INT_MODE_MSI:
8564 bnx2x_enable_msi(bp);
8565
8566 /* falling through... */
8567 case BNX2X_INT_MODE_INTX:
8568 bp->num_ethernet_queues = 1;
8569 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8570 BNX2X_DEV_INFO("set number of queues to 1\n");
8571 break;
8572 default:
8573 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8574 return -EINVAL;
8575 }
8576 return 0;
8577 }
8578
8579 /* must be called prior to any HW initializations */
8580 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8581 {
8582 if (IS_SRIOV(bp))
8583 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8584 return L2_ILT_LINES(bp);
8585 }
8586
8587 void bnx2x_ilt_set_info(struct bnx2x *bp)
8588 {
8589 struct ilt_client_info *ilt_client;
8590 struct bnx2x_ilt *ilt = BP_ILT(bp);
8591 u16 line = 0;
8592
8593 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8594 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8595
8596 /* CDU */
8597 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8598 ilt_client->client_num = ILT_CLIENT_CDU;
8599 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8600 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8601 ilt_client->start = line;
8602 line += bnx2x_cid_ilt_lines(bp);
8603
8604 if (CNIC_SUPPORT(bp))
8605 line += CNIC_ILT_LINES;
8606 ilt_client->end = line - 1;
8607
8608 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8609 ilt_client->start,
8610 ilt_client->end,
8611 ilt_client->page_size,
8612 ilt_client->flags,
8613 ilog2(ilt_client->page_size >> 12));
8614
8615 /* QM */
8616 if (QM_INIT(bp->qm_cid_count)) {
8617 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8618 ilt_client->client_num = ILT_CLIENT_QM;
8619 ilt_client->page_size = QM_ILT_PAGE_SZ;
8620 ilt_client->flags = 0;
8621 ilt_client->start = line;
8622
8623 /* 4 bytes for each cid */
8624 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8625 QM_ILT_PAGE_SZ);
8626
8627 ilt_client->end = line - 1;
8628
8629 DP(NETIF_MSG_IFUP,
8630 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8631 ilt_client->start,
8632 ilt_client->end,
8633 ilt_client->page_size,
8634 ilt_client->flags,
8635 ilog2(ilt_client->page_size >> 12));
8636 }
8637
8638 if (CNIC_SUPPORT(bp)) {
8639 /* SRC */
8640 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8641 ilt_client->client_num = ILT_CLIENT_SRC;
8642 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8643 ilt_client->flags = 0;
8644 ilt_client->start = line;
8645 line += SRC_ILT_LINES;
8646 ilt_client->end = line - 1;
8647
8648 DP(NETIF_MSG_IFUP,
8649 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8650 ilt_client->start,
8651 ilt_client->end,
8652 ilt_client->page_size,
8653 ilt_client->flags,
8654 ilog2(ilt_client->page_size >> 12));
8655
8656 /* TM */
8657 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8658 ilt_client->client_num = ILT_CLIENT_TM;
8659 ilt_client->page_size = TM_ILT_PAGE_SZ;
8660 ilt_client->flags = 0;
8661 ilt_client->start = line;
8662 line += TM_ILT_LINES;
8663 ilt_client->end = line - 1;
8664
8665 DP(NETIF_MSG_IFUP,
8666 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8667 ilt_client->start,
8668 ilt_client->end,
8669 ilt_client->page_size,
8670 ilt_client->flags,
8671 ilog2(ilt_client->page_size >> 12));
8672 }
8673
8674 BUG_ON(line > ILT_MAX_LINES);
8675 }
8676
8677 /**
8678 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8679 *
8680 * @bp: driver handle
8681 * @fp: pointer to fastpath
8682 * @init_params: pointer to parameters structure
8683 *
8684 * parameters configured:
8685 * - HC configuration
8686 * - Queue's CDU context
8687 */
8688 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8689 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8690 {
8691 u8 cos;
8692 int cxt_index, cxt_offset;
8693
8694 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8695 if (!IS_FCOE_FP(fp)) {
8696 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8697 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8698
8699 /* If HC is supported, enable host coalescing in the transition
8700 * to INIT state.
8701 */
8702 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8703 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8704
8705 /* HC rate */
8706 init_params->rx.hc_rate = bp->rx_ticks ?
8707 (1000000 / bp->rx_ticks) : 0;
8708 init_params->tx.hc_rate = bp->tx_ticks ?
8709 (1000000 / bp->tx_ticks) : 0;
8710
8711 /* FW SB ID */
8712 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8713 fp->fw_sb_id;
8714
8715 /*
8716 * CQ index among the SB indices: FCoE clients uses the default
8717 * SB, therefore it's different.
8718 */
8719 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8720 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8721 }
8722
8723 /* set maximum number of COSs supported by this queue */
8724 init_params->max_cos = fp->max_cos;
8725
8726 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8727 fp->index, init_params->max_cos);
8728
8729 /* set the context pointers queue object */
8730 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8731 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8732 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8733 ILT_PAGE_CIDS);
8734 init_params->cxts[cos] =
8735 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8736 }
8737 }
8738
8739 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8740 struct bnx2x_queue_state_params *q_params,
8741 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8742 int tx_index, bool leading)
8743 {
8744 memset(tx_only_params, 0, sizeof(*tx_only_params));
8745
8746 /* Set the command */
8747 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8748
8749 /* Set tx-only QUEUE flags: don't zero statistics */
8750 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8751
8752 /* choose the index of the cid to send the slow path on */
8753 tx_only_params->cid_index = tx_index;
8754
8755 /* Set general TX_ONLY_SETUP parameters */
8756 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8757
8758 /* Set Tx TX_ONLY_SETUP parameters */
8759 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8760
8761 DP(NETIF_MSG_IFUP,
8762 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8763 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8764 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8765 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8766
8767 /* send the ramrod */
8768 return bnx2x_queue_state_change(bp, q_params);
8769 }
8770
8771 /**
8772 * bnx2x_setup_queue - setup queue
8773 *
8774 * @bp: driver handle
8775 * @fp: pointer to fastpath
8776 * @leading: is leading
8777 *
8778 * This function performs 2 steps in a Queue state machine
8779 * actually: 1) RESET->INIT 2) INIT->SETUP
8780 */
8781
8782 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8783 bool leading)
8784 {
8785 struct bnx2x_queue_state_params q_params = {NULL};
8786 struct bnx2x_queue_setup_params *setup_params =
8787 &q_params.params.setup;
8788 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8789 &q_params.params.tx_only;
8790 int rc;
8791 u8 tx_index;
8792
8793 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8794
8795 /* reset IGU state skip FCoE L2 queue */
8796 if (!IS_FCOE_FP(fp))
8797 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8798 IGU_INT_ENABLE, 0);
8799
8800 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8801 /* We want to wait for completion in this context */
8802 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8803
8804 /* Prepare the INIT parameters */
8805 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8806
8807 /* Set the command */
8808 q_params.cmd = BNX2X_Q_CMD_INIT;
8809
8810 /* Change the state to INIT */
8811 rc = bnx2x_queue_state_change(bp, &q_params);
8812 if (rc) {
8813 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8814 return rc;
8815 }
8816
8817 DP(NETIF_MSG_IFUP, "init complete\n");
8818
8819 /* Now move the Queue to the SETUP state... */
8820 memset(setup_params, 0, sizeof(*setup_params));
8821
8822 /* Set QUEUE flags */
8823 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8824
8825 /* Set general SETUP parameters */
8826 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8827 FIRST_TX_COS_INDEX);
8828
8829 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8830 &setup_params->rxq_params);
8831
8832 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8833 FIRST_TX_COS_INDEX);
8834
8835 /* Set the command */
8836 q_params.cmd = BNX2X_Q_CMD_SETUP;
8837
8838 if (IS_FCOE_FP(fp))
8839 bp->fcoe_init = true;
8840
8841 /* Change the state to SETUP */
8842 rc = bnx2x_queue_state_change(bp, &q_params);
8843 if (rc) {
8844 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8845 return rc;
8846 }
8847
8848 /* loop through the relevant tx-only indices */
8849 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8850 tx_index < fp->max_cos;
8851 tx_index++) {
8852
8853 /* prepare and send tx-only ramrod*/
8854 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8855 tx_only_params, tx_index, leading);
8856 if (rc) {
8857 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8858 fp->index, tx_index);
8859 return rc;
8860 }
8861 }
8862
8863 return rc;
8864 }
8865
8866 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8867 {
8868 struct bnx2x_fastpath *fp = &bp->fp[index];
8869 struct bnx2x_fp_txdata *txdata;
8870 struct bnx2x_queue_state_params q_params = {NULL};
8871 int rc, tx_index;
8872
8873 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8874
8875 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8876 /* We want to wait for completion in this context */
8877 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8878
8879 /* close tx-only connections */
8880 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8881 tx_index < fp->max_cos;
8882 tx_index++){
8883
8884 /* ascertain this is a normal queue*/
8885 txdata = fp->txdata_ptr[tx_index];
8886
8887 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8888 txdata->txq_index);
8889
8890 /* send halt terminate on tx-only connection */
8891 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8892 memset(&q_params.params.terminate, 0,
8893 sizeof(q_params.params.terminate));
8894 q_params.params.terminate.cid_index = tx_index;
8895
8896 rc = bnx2x_queue_state_change(bp, &q_params);
8897 if (rc)
8898 return rc;
8899
8900 /* send halt terminate on tx-only connection */
8901 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8902 memset(&q_params.params.cfc_del, 0,
8903 sizeof(q_params.params.cfc_del));
8904 q_params.params.cfc_del.cid_index = tx_index;
8905 rc = bnx2x_queue_state_change(bp, &q_params);
8906 if (rc)
8907 return rc;
8908 }
8909 /* Stop the primary connection: */
8910 /* ...halt the connection */
8911 q_params.cmd = BNX2X_Q_CMD_HALT;
8912 rc = bnx2x_queue_state_change(bp, &q_params);
8913 if (rc)
8914 return rc;
8915
8916 /* ...terminate the connection */
8917 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8918 memset(&q_params.params.terminate, 0,
8919 sizeof(q_params.params.terminate));
8920 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8921 rc = bnx2x_queue_state_change(bp, &q_params);
8922 if (rc)
8923 return rc;
8924 /* ...delete cfc entry */
8925 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8926 memset(&q_params.params.cfc_del, 0,
8927 sizeof(q_params.params.cfc_del));
8928 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8929 return bnx2x_queue_state_change(bp, &q_params);
8930 }
8931
8932 static void bnx2x_reset_func(struct bnx2x *bp)
8933 {
8934 int port = BP_PORT(bp);
8935 int func = BP_FUNC(bp);
8936 int i;
8937
8938 /* Disable the function in the FW */
8939 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8940 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8941 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8942 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8943
8944 /* FP SBs */
8945 for_each_eth_queue(bp, i) {
8946 struct bnx2x_fastpath *fp = &bp->fp[i];
8947 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8948 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8949 SB_DISABLED);
8950 }
8951
8952 if (CNIC_LOADED(bp))
8953 /* CNIC SB */
8954 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8955 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8956 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8957
8958 /* SP SB */
8959 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8960 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8961 SB_DISABLED);
8962
8963 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8964 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8965 0);
8966
8967 /* Configure IGU */
8968 if (bp->common.int_block == INT_BLOCK_HC) {
8969 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8970 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8971 } else {
8972 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8973 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8974 }
8975
8976 if (CNIC_LOADED(bp)) {
8977 /* Disable Timer scan */
8978 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8979 /*
8980 * Wait for at least 10ms and up to 2 second for the timers
8981 * scan to complete
8982 */
8983 for (i = 0; i < 200; i++) {
8984 usleep_range(10000, 20000);
8985 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8986 break;
8987 }
8988 }
8989 /* Clear ILT */
8990 bnx2x_clear_func_ilt(bp, func);
8991
8992 /* Timers workaround bug for E2: if this is vnic-3,
8993 * we need to set the entire ilt range for this timers.
8994 */
8995 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8996 struct ilt_client_info ilt_cli;
8997 /* use dummy TM client */
8998 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8999 ilt_cli.start = 0;
9000 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9001 ilt_cli.client_num = ILT_CLIENT_TM;
9002
9003 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9004 }
9005
9006 /* this assumes that reset_port() called before reset_func()*/
9007 if (!CHIP_IS_E1x(bp))
9008 bnx2x_pf_disable(bp);
9009
9010 bp->dmae_ready = 0;
9011 }
9012
9013 static void bnx2x_reset_port(struct bnx2x *bp)
9014 {
9015 int port = BP_PORT(bp);
9016 u32 val;
9017
9018 /* Reset physical Link */
9019 bnx2x__link_reset(bp);
9020
9021 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9022
9023 /* Do not rcv packets to BRB */
9024 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9025 /* Do not direct rcv packets that are not for MCP to the BRB */
9026 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9027 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9028
9029 /* Configure AEU */
9030 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9031
9032 msleep(100);
9033 /* Check for BRB port occupancy */
9034 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9035 if (val)
9036 DP(NETIF_MSG_IFDOWN,
9037 "BRB1 is not empty %d blocks are occupied\n", val);
9038
9039 /* TODO: Close Doorbell port? */
9040 }
9041
9042 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9043 {
9044 struct bnx2x_func_state_params func_params = {NULL};
9045
9046 /* Prepare parameters for function state transitions */
9047 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9048
9049 func_params.f_obj = &bp->func_obj;
9050 func_params.cmd = BNX2X_F_CMD_HW_RESET;
9051
9052 func_params.params.hw_init.load_phase = load_code;
9053
9054 return bnx2x_func_state_change(bp, &func_params);
9055 }
9056
9057 static int bnx2x_func_stop(struct bnx2x *bp)
9058 {
9059 struct bnx2x_func_state_params func_params = {NULL};
9060 int rc;
9061
9062 /* Prepare parameters for function state transitions */
9063 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9064 func_params.f_obj = &bp->func_obj;
9065 func_params.cmd = BNX2X_F_CMD_STOP;
9066
9067 /*
9068 * Try to stop the function the 'good way'. If fails (in case
9069 * of a parity error during bnx2x_chip_cleanup()) and we are
9070 * not in a debug mode, perform a state transaction in order to
9071 * enable further HW_RESET transaction.
9072 */
9073 rc = bnx2x_func_state_change(bp, &func_params);
9074 if (rc) {
9075 #ifdef BNX2X_STOP_ON_ERROR
9076 return rc;
9077 #else
9078 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9079 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9080 return bnx2x_func_state_change(bp, &func_params);
9081 #endif
9082 }
9083
9084 return 0;
9085 }
9086
9087 /**
9088 * bnx2x_send_unload_req - request unload mode from the MCP.
9089 *
9090 * @bp: driver handle
9091 * @unload_mode: requested function's unload mode
9092 *
9093 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9094 */
9095 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9096 {
9097 u32 reset_code = 0;
9098 int port = BP_PORT(bp);
9099
9100 /* Select the UNLOAD request mode */
9101 if (unload_mode == UNLOAD_NORMAL)
9102 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9103
9104 else if (bp->flags & NO_WOL_FLAG)
9105 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9106
9107 else if (bp->wol) {
9108 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9109 u8 *mac_addr = bp->dev->dev_addr;
9110 struct pci_dev *pdev = bp->pdev;
9111 u32 val;
9112 u16 pmc;
9113
9114 /* The mac address is written to entries 1-4 to
9115 * preserve entry 0 which is used by the PMF
9116 */
9117 u8 entry = (BP_VN(bp) + 1)*8;
9118
9119 val = (mac_addr[0] << 8) | mac_addr[1];
9120 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9121
9122 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9123 (mac_addr[4] << 8) | mac_addr[5];
9124 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9125
9126 /* Enable the PME and clear the status */
9127 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9128 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9129 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9130
9131 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9132
9133 } else
9134 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9135
9136 /* Send the request to the MCP */
9137 if (!BP_NOMCP(bp))
9138 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9139 else {
9140 int path = BP_PATH(bp);
9141
9142 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9143 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9144 bnx2x_load_count[path][2]);
9145 bnx2x_load_count[path][0]--;
9146 bnx2x_load_count[path][1 + port]--;
9147 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9148 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9149 bnx2x_load_count[path][2]);
9150 if (bnx2x_load_count[path][0] == 0)
9151 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9152 else if (bnx2x_load_count[path][1 + port] == 0)
9153 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9154 else
9155 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9156 }
9157
9158 return reset_code;
9159 }
9160
9161 /**
9162 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9163 *
9164 * @bp: driver handle
9165 * @keep_link: true iff link should be kept up
9166 */
9167 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9168 {
9169 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9170
9171 /* Report UNLOAD_DONE to MCP */
9172 if (!BP_NOMCP(bp))
9173 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9174 }
9175
9176 static int bnx2x_func_wait_started(struct bnx2x *bp)
9177 {
9178 int tout = 50;
9179 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9180
9181 if (!bp->port.pmf)
9182 return 0;
9183
9184 /*
9185 * (assumption: No Attention from MCP at this stage)
9186 * PMF probably in the middle of TX disable/enable transaction
9187 * 1. Sync IRS for default SB
9188 * 2. Sync SP queue - this guarantees us that attention handling started
9189 * 3. Wait, that TX disable/enable transaction completes
9190 *
9191 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9192 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9193 * received completion for the transaction the state is TX_STOPPED.
9194 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9195 * transaction.
9196 */
9197
9198 /* make sure default SB ISR is done */
9199 if (msix)
9200 synchronize_irq(bp->msix_table[0].vector);
9201 else
9202 synchronize_irq(bp->pdev->irq);
9203
9204 flush_workqueue(bnx2x_wq);
9205 flush_workqueue(bnx2x_iov_wq);
9206
9207 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9208 BNX2X_F_STATE_STARTED && tout--)
9209 msleep(20);
9210
9211 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9212 BNX2X_F_STATE_STARTED) {
9213 #ifdef BNX2X_STOP_ON_ERROR
9214 BNX2X_ERR("Wrong function state\n");
9215 return -EBUSY;
9216 #else
9217 /*
9218 * Failed to complete the transaction in a "good way"
9219 * Force both transactions with CLR bit
9220 */
9221 struct bnx2x_func_state_params func_params = {NULL};
9222
9223 DP(NETIF_MSG_IFDOWN,
9224 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9225
9226 func_params.f_obj = &bp->func_obj;
9227 __set_bit(RAMROD_DRV_CLR_ONLY,
9228 &func_params.ramrod_flags);
9229
9230 /* STARTED-->TX_ST0PPED */
9231 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9232 bnx2x_func_state_change(bp, &func_params);
9233
9234 /* TX_ST0PPED-->STARTED */
9235 func_params.cmd = BNX2X_F_CMD_TX_START;
9236 return bnx2x_func_state_change(bp, &func_params);
9237 #endif
9238 }
9239
9240 return 0;
9241 }
9242
9243 static void bnx2x_disable_ptp(struct bnx2x *bp)
9244 {
9245 int port = BP_PORT(bp);
9246
9247 /* Disable sending PTP packets to host */
9248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9249 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9250
9251 /* Reset PTP event detection rules */
9252 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9253 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9255 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9256 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9257 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9259 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9260
9261 /* Disable the PTP feature */
9262 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9263 NIG_REG_P0_PTP_EN, 0x0);
9264 }
9265
9266 /* Called during unload, to stop PTP-related stuff */
9267 static void bnx2x_stop_ptp(struct bnx2x *bp)
9268 {
9269 /* Cancel PTP work queue. Should be done after the Tx queues are
9270 * drained to prevent additional scheduling.
9271 */
9272 cancel_work_sync(&bp->ptp_task);
9273
9274 if (bp->ptp_tx_skb) {
9275 dev_kfree_skb_any(bp->ptp_tx_skb);
9276 bp->ptp_tx_skb = NULL;
9277 }
9278
9279 /* Disable PTP in HW */
9280 bnx2x_disable_ptp(bp);
9281
9282 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9283 }
9284
9285 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9286 {
9287 int port = BP_PORT(bp);
9288 int i, rc = 0;
9289 u8 cos;
9290 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9291 u32 reset_code;
9292
9293 /* Wait until tx fastpath tasks complete */
9294 for_each_tx_queue(bp, i) {
9295 struct bnx2x_fastpath *fp = &bp->fp[i];
9296
9297 for_each_cos_in_tx_queue(fp, cos)
9298 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9299 #ifdef BNX2X_STOP_ON_ERROR
9300 if (rc)
9301 return;
9302 #endif
9303 }
9304
9305 /* Give HW time to discard old tx messages */
9306 usleep_range(1000, 2000);
9307
9308 /* Clean all ETH MACs */
9309 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9310 false);
9311 if (rc < 0)
9312 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9313
9314 /* Clean up UC list */
9315 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9316 true);
9317 if (rc < 0)
9318 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9319 rc);
9320
9321 /* Disable LLH */
9322 if (!CHIP_IS_E1(bp))
9323 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9324
9325 /* Set "drop all" (stop Rx).
9326 * We need to take a netif_addr_lock() here in order to prevent
9327 * a race between the completion code and this code.
9328 */
9329 netif_addr_lock_bh(bp->dev);
9330 /* Schedule the rx_mode command */
9331 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9332 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9333 else
9334 bnx2x_set_storm_rx_mode(bp);
9335
9336 /* Cleanup multicast configuration */
9337 rparam.mcast_obj = &bp->mcast_obj;
9338 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9339 if (rc < 0)
9340 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9341
9342 netif_addr_unlock_bh(bp->dev);
9343
9344 bnx2x_iov_chip_cleanup(bp);
9345
9346 /*
9347 * Send the UNLOAD_REQUEST to the MCP. This will return if
9348 * this function should perform FUNC, PORT or COMMON HW
9349 * reset.
9350 */
9351 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9352
9353 /*
9354 * (assumption: No Attention from MCP at this stage)
9355 * PMF probably in the middle of TX disable/enable transaction
9356 */
9357 rc = bnx2x_func_wait_started(bp);
9358 if (rc) {
9359 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9360 #ifdef BNX2X_STOP_ON_ERROR
9361 return;
9362 #endif
9363 }
9364
9365 /* Close multi and leading connections
9366 * Completions for ramrods are collected in a synchronous way
9367 */
9368 for_each_eth_queue(bp, i)
9369 if (bnx2x_stop_queue(bp, i))
9370 #ifdef BNX2X_STOP_ON_ERROR
9371 return;
9372 #else
9373 goto unload_error;
9374 #endif
9375
9376 if (CNIC_LOADED(bp)) {
9377 for_each_cnic_queue(bp, i)
9378 if (bnx2x_stop_queue(bp, i))
9379 #ifdef BNX2X_STOP_ON_ERROR
9380 return;
9381 #else
9382 goto unload_error;
9383 #endif
9384 }
9385
9386 /* If SP settings didn't get completed so far - something
9387 * very wrong has happen.
9388 */
9389 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9390 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9391
9392 #ifndef BNX2X_STOP_ON_ERROR
9393 unload_error:
9394 #endif
9395 rc = bnx2x_func_stop(bp);
9396 if (rc) {
9397 BNX2X_ERR("Function stop failed!\n");
9398 #ifdef BNX2X_STOP_ON_ERROR
9399 return;
9400 #endif
9401 }
9402
9403 /* stop_ptp should be after the Tx queues are drained to prevent
9404 * scheduling to the cancelled PTP work queue. It should also be after
9405 * function stop ramrod is sent, since as part of this ramrod FW access
9406 * PTP registers.
9407 */
9408 if (bp->flags & PTP_SUPPORTED)
9409 bnx2x_stop_ptp(bp);
9410
9411 /* Disable HW interrupts, NAPI */
9412 bnx2x_netif_stop(bp, 1);
9413 /* Delete all NAPI objects */
9414 bnx2x_del_all_napi(bp);
9415 if (CNIC_LOADED(bp))
9416 bnx2x_del_all_napi_cnic(bp);
9417
9418 /* Release IRQs */
9419 bnx2x_free_irq(bp);
9420
9421 /* Reset the chip */
9422 rc = bnx2x_reset_hw(bp, reset_code);
9423 if (rc)
9424 BNX2X_ERR("HW_RESET failed\n");
9425
9426 /* Report UNLOAD_DONE to MCP */
9427 bnx2x_send_unload_done(bp, keep_link);
9428 }
9429
9430 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9431 {
9432 u32 val;
9433
9434 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9435
9436 if (CHIP_IS_E1(bp)) {
9437 int port = BP_PORT(bp);
9438 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9439 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9440
9441 val = REG_RD(bp, addr);
9442 val &= ~(0x300);
9443 REG_WR(bp, addr, val);
9444 } else {
9445 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9446 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9447 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9448 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9449 }
9450 }
9451
9452 /* Close gates #2, #3 and #4: */
9453 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9454 {
9455 u32 val;
9456
9457 /* Gates #2 and #4a are closed/opened for "not E1" only */
9458 if (!CHIP_IS_E1(bp)) {
9459 /* #4 */
9460 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9461 /* #2 */
9462 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9463 }
9464
9465 /* #3 */
9466 if (CHIP_IS_E1x(bp)) {
9467 /* Prevent interrupts from HC on both ports */
9468 val = REG_RD(bp, HC_REG_CONFIG_1);
9469 REG_WR(bp, HC_REG_CONFIG_1,
9470 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9471 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9472
9473 val = REG_RD(bp, HC_REG_CONFIG_0);
9474 REG_WR(bp, HC_REG_CONFIG_0,
9475 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9476 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9477 } else {
9478 /* Prevent incoming interrupts in IGU */
9479 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9480
9481 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9482 (!close) ?
9483 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9484 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9485 }
9486
9487 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9488 close ? "closing" : "opening");
9489 mmiowb();
9490 }
9491
9492 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9493
9494 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9495 {
9496 /* Do some magic... */
9497 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9498 *magic_val = val & SHARED_MF_CLP_MAGIC;
9499 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9500 }
9501
9502 /**
9503 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9504 *
9505 * @bp: driver handle
9506 * @magic_val: old value of the `magic' bit.
9507 */
9508 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9509 {
9510 /* Restore the `magic' bit value... */
9511 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9512 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9513 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9514 }
9515
9516 /**
9517 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9518 *
9519 * @bp: driver handle
9520 * @magic_val: old value of 'magic' bit.
9521 *
9522 * Takes care of CLP configurations.
9523 */
9524 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9525 {
9526 u32 shmem;
9527 u32 validity_offset;
9528
9529 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9530
9531 /* Set `magic' bit in order to save MF config */
9532 if (!CHIP_IS_E1(bp))
9533 bnx2x_clp_reset_prep(bp, magic_val);
9534
9535 /* Get shmem offset */
9536 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9537 validity_offset =
9538 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9539
9540 /* Clear validity map flags */
9541 if (shmem > 0)
9542 REG_WR(bp, shmem + validity_offset, 0);
9543 }
9544
9545 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9546 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9547
9548 /**
9549 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9550 *
9551 * @bp: driver handle
9552 */
9553 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9554 {
9555 /* special handling for emulation and FPGA,
9556 wait 10 times longer */
9557 if (CHIP_REV_IS_SLOW(bp))
9558 msleep(MCP_ONE_TIMEOUT*10);
9559 else
9560 msleep(MCP_ONE_TIMEOUT);
9561 }
9562
9563 /*
9564 * initializes bp->common.shmem_base and waits for validity signature to appear
9565 */
9566 static int bnx2x_init_shmem(struct bnx2x *bp)
9567 {
9568 int cnt = 0;
9569 u32 val = 0;
9570
9571 do {
9572 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9573 if (bp->common.shmem_base) {
9574 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9575 if (val & SHR_MEM_VALIDITY_MB)
9576 return 0;
9577 }
9578
9579 bnx2x_mcp_wait_one(bp);
9580
9581 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9582
9583 BNX2X_ERR("BAD MCP validity signature\n");
9584
9585 return -ENODEV;
9586 }
9587
9588 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9589 {
9590 int rc = bnx2x_init_shmem(bp);
9591
9592 /* Restore the `magic' bit value */
9593 if (!CHIP_IS_E1(bp))
9594 bnx2x_clp_reset_done(bp, magic_val);
9595
9596 return rc;
9597 }
9598
9599 static void bnx2x_pxp_prep(struct bnx2x *bp)
9600 {
9601 if (!CHIP_IS_E1(bp)) {
9602 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9603 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9604 mmiowb();
9605 }
9606 }
9607
9608 /*
9609 * Reset the whole chip except for:
9610 * - PCIE core
9611 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9612 * one reset bit)
9613 * - IGU
9614 * - MISC (including AEU)
9615 * - GRC
9616 * - RBCN, RBCP
9617 */
9618 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9619 {
9620 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9621 u32 global_bits2, stay_reset2;
9622
9623 /*
9624 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9625 * (per chip) blocks.
9626 */
9627 global_bits2 =
9628 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9629 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9630
9631 /* Don't reset the following blocks.
9632 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9633 * reset, as in 4 port device they might still be owned
9634 * by the MCP (there is only one leader per path).
9635 */
9636 not_reset_mask1 =
9637 MISC_REGISTERS_RESET_REG_1_RST_HC |
9638 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9639 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9640
9641 not_reset_mask2 =
9642 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9643 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9644 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9645 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9646 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9647 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9648 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9649 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9650 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9651 MISC_REGISTERS_RESET_REG_2_PGLC |
9652 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9653 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9654 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9655 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9656 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9657 MISC_REGISTERS_RESET_REG_2_UMAC1;
9658
9659 /*
9660 * Keep the following blocks in reset:
9661 * - all xxMACs are handled by the bnx2x_link code.
9662 */
9663 stay_reset2 =
9664 MISC_REGISTERS_RESET_REG_2_XMAC |
9665 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9666
9667 /* Full reset masks according to the chip */
9668 reset_mask1 = 0xffffffff;
9669
9670 if (CHIP_IS_E1(bp))
9671 reset_mask2 = 0xffff;
9672 else if (CHIP_IS_E1H(bp))
9673 reset_mask2 = 0x1ffff;
9674 else if (CHIP_IS_E2(bp))
9675 reset_mask2 = 0xfffff;
9676 else /* CHIP_IS_E3 */
9677 reset_mask2 = 0x3ffffff;
9678
9679 /* Don't reset global blocks unless we need to */
9680 if (!global)
9681 reset_mask2 &= ~global_bits2;
9682
9683 /*
9684 * In case of attention in the QM, we need to reset PXP
9685 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9686 * because otherwise QM reset would release 'close the gates' shortly
9687 * before resetting the PXP, then the PSWRQ would send a write
9688 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9689 * read the payload data from PSWWR, but PSWWR would not
9690 * respond. The write queue in PGLUE would stuck, dmae commands
9691 * would not return. Therefore it's important to reset the second
9692 * reset register (containing the
9693 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9694 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9695 * bit).
9696 */
9697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9698 reset_mask2 & (~not_reset_mask2));
9699
9700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9701 reset_mask1 & (~not_reset_mask1));
9702
9703 barrier();
9704 mmiowb();
9705
9706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9707 reset_mask2 & (~stay_reset2));
9708
9709 barrier();
9710 mmiowb();
9711
9712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9713 mmiowb();
9714 }
9715
9716 /**
9717 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9718 * It should get cleared in no more than 1s.
9719 *
9720 * @bp: driver handle
9721 *
9722 * It should get cleared in no more than 1s. Returns 0 if
9723 * pending writes bit gets cleared.
9724 */
9725 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9726 {
9727 u32 cnt = 1000;
9728 u32 pend_bits = 0;
9729
9730 do {
9731 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9732
9733 if (pend_bits == 0)
9734 break;
9735
9736 usleep_range(1000, 2000);
9737 } while (cnt-- > 0);
9738
9739 if (cnt <= 0) {
9740 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9741 pend_bits);
9742 return -EBUSY;
9743 }
9744
9745 return 0;
9746 }
9747
9748 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9749 {
9750 int cnt = 1000;
9751 u32 val = 0;
9752 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9753 u32 tags_63_32 = 0;
9754
9755 /* Empty the Tetris buffer, wait for 1s */
9756 do {
9757 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9758 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9759 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9760 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9761 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9762 if (CHIP_IS_E3(bp))
9763 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9764
9765 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9766 ((port_is_idle_0 & 0x1) == 0x1) &&
9767 ((port_is_idle_1 & 0x1) == 0x1) &&
9768 (pgl_exp_rom2 == 0xffffffff) &&
9769 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9770 break;
9771 usleep_range(1000, 2000);
9772 } while (cnt-- > 0);
9773
9774 if (cnt <= 0) {
9775 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9776 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9777 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9778 pgl_exp_rom2);
9779 return -EAGAIN;
9780 }
9781
9782 barrier();
9783
9784 /* Close gates #2, #3 and #4 */
9785 bnx2x_set_234_gates(bp, true);
9786
9787 /* Poll for IGU VQs for 57712 and newer chips */
9788 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9789 return -EAGAIN;
9790
9791 /* TBD: Indicate that "process kill" is in progress to MCP */
9792
9793 /* Clear "unprepared" bit */
9794 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9795 barrier();
9796
9797 /* Make sure all is written to the chip before the reset */
9798 mmiowb();
9799
9800 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9801 * PSWHST, GRC and PSWRD Tetris buffer.
9802 */
9803 usleep_range(1000, 2000);
9804
9805 /* Prepare to chip reset: */
9806 /* MCP */
9807 if (global)
9808 bnx2x_reset_mcp_prep(bp, &val);
9809
9810 /* PXP */
9811 bnx2x_pxp_prep(bp);
9812 barrier();
9813
9814 /* reset the chip */
9815 bnx2x_process_kill_chip_reset(bp, global);
9816 barrier();
9817
9818 /* clear errors in PGB */
9819 if (!CHIP_IS_E1x(bp))
9820 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9821
9822 /* Recover after reset: */
9823 /* MCP */
9824 if (global && bnx2x_reset_mcp_comp(bp, val))
9825 return -EAGAIN;
9826
9827 /* TBD: Add resetting the NO_MCP mode DB here */
9828
9829 /* Open the gates #2, #3 and #4 */
9830 bnx2x_set_234_gates(bp, false);
9831
9832 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9833 * reset state, re-enable attentions. */
9834
9835 return 0;
9836 }
9837
9838 static int bnx2x_leader_reset(struct bnx2x *bp)
9839 {
9840 int rc = 0;
9841 bool global = bnx2x_reset_is_global(bp);
9842 u32 load_code;
9843
9844 /* if not going to reset MCP - load "fake" driver to reset HW while
9845 * driver is owner of the HW
9846 */
9847 if (!global && !BP_NOMCP(bp)) {
9848 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9849 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9850 if (!load_code) {
9851 BNX2X_ERR("MCP response failure, aborting\n");
9852 rc = -EAGAIN;
9853 goto exit_leader_reset;
9854 }
9855 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9856 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9857 BNX2X_ERR("MCP unexpected resp, aborting\n");
9858 rc = -EAGAIN;
9859 goto exit_leader_reset2;
9860 }
9861 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9862 if (!load_code) {
9863 BNX2X_ERR("MCP response failure, aborting\n");
9864 rc = -EAGAIN;
9865 goto exit_leader_reset2;
9866 }
9867 }
9868
9869 /* Try to recover after the failure */
9870 if (bnx2x_process_kill(bp, global)) {
9871 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9872 BP_PATH(bp));
9873 rc = -EAGAIN;
9874 goto exit_leader_reset2;
9875 }
9876
9877 /*
9878 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9879 * state.
9880 */
9881 bnx2x_set_reset_done(bp);
9882 if (global)
9883 bnx2x_clear_reset_global(bp);
9884
9885 exit_leader_reset2:
9886 /* unload "fake driver" if it was loaded */
9887 if (!global && !BP_NOMCP(bp)) {
9888 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9889 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9890 }
9891 exit_leader_reset:
9892 bp->is_leader = 0;
9893 bnx2x_release_leader_lock(bp);
9894 smp_mb();
9895 return rc;
9896 }
9897
9898 static void bnx2x_recovery_failed(struct bnx2x *bp)
9899 {
9900 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9901
9902 /* Disconnect this device */
9903 netif_device_detach(bp->dev);
9904
9905 /*
9906 * Block ifup for all function on this engine until "process kill"
9907 * or power cycle.
9908 */
9909 bnx2x_set_reset_in_progress(bp);
9910
9911 /* Shut down the power */
9912 bnx2x_set_power_state(bp, PCI_D3hot);
9913
9914 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9915
9916 smp_mb();
9917 }
9918
9919 /*
9920 * Assumption: runs under rtnl lock. This together with the fact
9921 * that it's called only from bnx2x_sp_rtnl() ensure that it
9922 * will never be called when netif_running(bp->dev) is false.
9923 */
9924 static void bnx2x_parity_recover(struct bnx2x *bp)
9925 {
9926 bool global = false;
9927 u32 error_recovered, error_unrecovered;
9928 bool is_parity;
9929
9930 DP(NETIF_MSG_HW, "Handling parity\n");
9931 while (1) {
9932 switch (bp->recovery_state) {
9933 case BNX2X_RECOVERY_INIT:
9934 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9935 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9936 WARN_ON(!is_parity);
9937
9938 /* Try to get a LEADER_LOCK HW lock */
9939 if (bnx2x_trylock_leader_lock(bp)) {
9940 bnx2x_set_reset_in_progress(bp);
9941 /*
9942 * Check if there is a global attention and if
9943 * there was a global attention, set the global
9944 * reset bit.
9945 */
9946
9947 if (global)
9948 bnx2x_set_reset_global(bp);
9949
9950 bp->is_leader = 1;
9951 }
9952
9953 /* Stop the driver */
9954 /* If interface has been removed - break */
9955 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9956 return;
9957
9958 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9959
9960 /* Ensure "is_leader", MCP command sequence and
9961 * "recovery_state" update values are seen on other
9962 * CPUs.
9963 */
9964 smp_mb();
9965 break;
9966
9967 case BNX2X_RECOVERY_WAIT:
9968 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9969 if (bp->is_leader) {
9970 int other_engine = BP_PATH(bp) ? 0 : 1;
9971 bool other_load_status =
9972 bnx2x_get_load_status(bp, other_engine);
9973 bool load_status =
9974 bnx2x_get_load_status(bp, BP_PATH(bp));
9975 global = bnx2x_reset_is_global(bp);
9976
9977 /*
9978 * In case of a parity in a global block, let
9979 * the first leader that performs a
9980 * leader_reset() reset the global blocks in
9981 * order to clear global attentions. Otherwise
9982 * the gates will remain closed for that
9983 * engine.
9984 */
9985 if (load_status ||
9986 (global && other_load_status)) {
9987 /* Wait until all other functions get
9988 * down.
9989 */
9990 schedule_delayed_work(&bp->sp_rtnl_task,
9991 HZ/10);
9992 return;
9993 } else {
9994 /* If all other functions got down -
9995 * try to bring the chip back to
9996 * normal. In any case it's an exit
9997 * point for a leader.
9998 */
9999 if (bnx2x_leader_reset(bp)) {
10000 bnx2x_recovery_failed(bp);
10001 return;
10002 }
10003
10004 /* If we are here, means that the
10005 * leader has succeeded and doesn't
10006 * want to be a leader any more. Try
10007 * to continue as a none-leader.
10008 */
10009 break;
10010 }
10011 } else { /* non-leader */
10012 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10013 /* Try to get a LEADER_LOCK HW lock as
10014 * long as a former leader may have
10015 * been unloaded by the user or
10016 * released a leadership by another
10017 * reason.
10018 */
10019 if (bnx2x_trylock_leader_lock(bp)) {
10020 /* I'm a leader now! Restart a
10021 * switch case.
10022 */
10023 bp->is_leader = 1;
10024 break;
10025 }
10026
10027 schedule_delayed_work(&bp->sp_rtnl_task,
10028 HZ/10);
10029 return;
10030
10031 } else {
10032 /*
10033 * If there was a global attention, wait
10034 * for it to be cleared.
10035 */
10036 if (bnx2x_reset_is_global(bp)) {
10037 schedule_delayed_work(
10038 &bp->sp_rtnl_task,
10039 HZ/10);
10040 return;
10041 }
10042
10043 error_recovered =
10044 bp->eth_stats.recoverable_error;
10045 error_unrecovered =
10046 bp->eth_stats.unrecoverable_error;
10047 bp->recovery_state =
10048 BNX2X_RECOVERY_NIC_LOADING;
10049 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10050 error_unrecovered++;
10051 netdev_err(bp->dev,
10052 "Recovery failed. Power cycle needed\n");
10053 /* Disconnect this device */
10054 netif_device_detach(bp->dev);
10055 /* Shut down the power */
10056 bnx2x_set_power_state(
10057 bp, PCI_D3hot);
10058 smp_mb();
10059 } else {
10060 bp->recovery_state =
10061 BNX2X_RECOVERY_DONE;
10062 error_recovered++;
10063 smp_mb();
10064 }
10065 bp->eth_stats.recoverable_error =
10066 error_recovered;
10067 bp->eth_stats.unrecoverable_error =
10068 error_unrecovered;
10069
10070 return;
10071 }
10072 }
10073 default:
10074 return;
10075 }
10076 }
10077 }
10078
10079 #ifdef CONFIG_BNX2X_VXLAN
10080 static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port)
10081 {
10082 struct bnx2x_func_switch_update_params *switch_update_params;
10083 struct bnx2x_func_state_params func_params = {NULL};
10084 int rc;
10085
10086 switch_update_params = &func_params.params.switch_update;
10087
10088 /* Prepare parameters for function state transitions */
10089 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10090 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10091
10092 func_params.f_obj = &bp->func_obj;
10093 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10094
10095 /* Function parameters */
10096 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10097 &switch_update_params->changes);
10098 switch_update_params->vxlan_dst_port = port;
10099 rc = bnx2x_func_state_change(bp, &func_params);
10100 if (rc)
10101 BNX2X_ERR("failed to change vxlan dst port to %d (rc = 0x%x)\n",
10102 port, rc);
10103 return rc;
10104 }
10105
10106 static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port)
10107 {
10108 if (!netif_running(bp->dev))
10109 return;
10110
10111 if (bp->vxlan_dst_port_count && bp->vxlan_dst_port == port) {
10112 bp->vxlan_dst_port_count++;
10113 return;
10114 }
10115
10116 if (bp->vxlan_dst_port_count || !IS_PF(bp)) {
10117 DP(BNX2X_MSG_SP, "Vxlan destination port limit reached\n");
10118 return;
10119 }
10120
10121 bp->vxlan_dst_port = port;
10122 bp->vxlan_dst_port_count = 1;
10123 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0);
10124 }
10125
10126 static void bnx2x_add_vxlan_port(struct net_device *netdev,
10127 sa_family_t sa_family, __be16 port)
10128 {
10129 struct bnx2x *bp = netdev_priv(netdev);
10130 u16 t_port = ntohs(port);
10131
10132 __bnx2x_add_vxlan_port(bp, t_port);
10133 }
10134
10135 static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port)
10136 {
10137 if (!bp->vxlan_dst_port_count || bp->vxlan_dst_port != port ||
10138 !IS_PF(bp)) {
10139 DP(BNX2X_MSG_SP, "Invalid vxlan port\n");
10140 return;
10141 }
10142 bp->vxlan_dst_port--;
10143 if (bp->vxlan_dst_port)
10144 return;
10145
10146 if (netif_running(bp->dev)) {
10147 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0);
10148 } else {
10149 bp->vxlan_dst_port = 0;
10150 netdev_info(bp->dev, "Deleted vxlan dest port %d", port);
10151 }
10152 }
10153
10154 static void bnx2x_del_vxlan_port(struct net_device *netdev,
10155 sa_family_t sa_family, __be16 port)
10156 {
10157 struct bnx2x *bp = netdev_priv(netdev);
10158 u16 t_port = ntohs(port);
10159
10160 __bnx2x_del_vxlan_port(bp, t_port);
10161 }
10162 #endif
10163
10164 static int bnx2x_close(struct net_device *dev);
10165
10166 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10167 * scheduled on a general queue in order to prevent a dead lock.
10168 */
10169 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10170 {
10171 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10172 #ifdef CONFIG_BNX2X_VXLAN
10173 u16 port;
10174 #endif
10175
10176 rtnl_lock();
10177
10178 if (!netif_running(bp->dev)) {
10179 rtnl_unlock();
10180 return;
10181 }
10182
10183 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10184 #ifdef BNX2X_STOP_ON_ERROR
10185 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10186 "you will need to reboot when done\n");
10187 goto sp_rtnl_not_reset;
10188 #endif
10189 /*
10190 * Clear all pending SP commands as we are going to reset the
10191 * function anyway.
10192 */
10193 bp->sp_rtnl_state = 0;
10194 smp_mb();
10195
10196 bnx2x_parity_recover(bp);
10197
10198 rtnl_unlock();
10199 return;
10200 }
10201
10202 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10203 #ifdef BNX2X_STOP_ON_ERROR
10204 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10205 "you will need to reboot when done\n");
10206 goto sp_rtnl_not_reset;
10207 #endif
10208
10209 /*
10210 * Clear all pending SP commands as we are going to reset the
10211 * function anyway.
10212 */
10213 bp->sp_rtnl_state = 0;
10214 smp_mb();
10215
10216 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10217 bnx2x_nic_load(bp, LOAD_NORMAL);
10218
10219 rtnl_unlock();
10220 return;
10221 }
10222 #ifdef BNX2X_STOP_ON_ERROR
10223 sp_rtnl_not_reset:
10224 #endif
10225 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10226 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10227 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10228 bnx2x_after_function_update(bp);
10229 /*
10230 * in case of fan failure we need to reset id if the "stop on error"
10231 * debug flag is set, since we trying to prevent permanent overheating
10232 * damage
10233 */
10234 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10235 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10236 netif_device_detach(bp->dev);
10237 bnx2x_close(bp->dev);
10238 rtnl_unlock();
10239 return;
10240 }
10241
10242 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10243 DP(BNX2X_MSG_SP,
10244 "sending set mcast vf pf channel message from rtnl sp-task\n");
10245 bnx2x_vfpf_set_mcast(bp->dev);
10246 }
10247 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10248 &bp->sp_rtnl_state)){
10249 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10250 bnx2x_tx_disable(bp);
10251 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10252 }
10253 }
10254
10255 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10256 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10257 bnx2x_set_rx_mode_inner(bp);
10258 }
10259
10260 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10261 &bp->sp_rtnl_state))
10262 bnx2x_pf_set_vfs_vlan(bp);
10263
10264 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10265 bnx2x_dcbx_stop_hw_tx(bp);
10266 bnx2x_dcbx_resume_hw_tx(bp);
10267 }
10268
10269 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10270 &bp->sp_rtnl_state))
10271 bnx2x_update_mng_version(bp);
10272
10273 #ifdef CONFIG_BNX2X_VXLAN
10274 port = bp->vxlan_dst_port;
10275 if (test_and_clear_bit(BNX2X_SP_RTNL_ADD_VXLAN_PORT,
10276 &bp->sp_rtnl_state)) {
10277 if (!bnx2x_vxlan_port_update(bp, port))
10278 netdev_info(bp->dev, "Added vxlan dest port %d", port);
10279 else
10280 bp->vxlan_dst_port = 0;
10281 }
10282
10283 if (test_and_clear_bit(BNX2X_SP_RTNL_DEL_VXLAN_PORT,
10284 &bp->sp_rtnl_state)) {
10285 if (!bnx2x_vxlan_port_update(bp, 0)) {
10286 netdev_info(bp->dev,
10287 "Deleted vxlan dest port %d", port);
10288 bp->vxlan_dst_port = 0;
10289 vxlan_get_rx_port(bp->dev);
10290 }
10291 }
10292 #endif
10293
10294 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10295 * can be called from other contexts as well)
10296 */
10297 rtnl_unlock();
10298
10299 /* enable SR-IOV if applicable */
10300 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10301 &bp->sp_rtnl_state)) {
10302 bnx2x_disable_sriov(bp);
10303 bnx2x_enable_sriov(bp);
10304 }
10305 }
10306
10307 static void bnx2x_period_task(struct work_struct *work)
10308 {
10309 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10310
10311 if (!netif_running(bp->dev))
10312 goto period_task_exit;
10313
10314 if (CHIP_REV_IS_SLOW(bp)) {
10315 BNX2X_ERR("period task called on emulation, ignoring\n");
10316 goto period_task_exit;
10317 }
10318
10319 bnx2x_acquire_phy_lock(bp);
10320 /*
10321 * The barrier is needed to ensure the ordering between the writing to
10322 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10323 * the reading here.
10324 */
10325 smp_mb();
10326 if (bp->port.pmf) {
10327 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10328
10329 /* Re-queue task in 1 sec */
10330 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10331 }
10332
10333 bnx2x_release_phy_lock(bp);
10334 period_task_exit:
10335 return;
10336 }
10337
10338 /*
10339 * Init service functions
10340 */
10341
10342 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10343 {
10344 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10345 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10346 return base + (BP_ABS_FUNC(bp)) * stride;
10347 }
10348
10349 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10350 u8 port, u32 reset_reg,
10351 struct bnx2x_mac_vals *vals)
10352 {
10353 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10354 u32 base_addr;
10355
10356 if (!(mask & reset_reg))
10357 return false;
10358
10359 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10360 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10361 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10362 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10363 REG_WR(bp, vals->umac_addr[port], 0);
10364
10365 return true;
10366 }
10367
10368 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10369 struct bnx2x_mac_vals *vals)
10370 {
10371 u32 val, base_addr, offset, mask, reset_reg;
10372 bool mac_stopped = false;
10373 u8 port = BP_PORT(bp);
10374
10375 /* reset addresses as they also mark which values were changed */
10376 memset(vals, 0, sizeof(*vals));
10377
10378 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10379
10380 if (!CHIP_IS_E3(bp)) {
10381 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10382 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10383 if ((mask & reset_reg) && val) {
10384 u32 wb_data[2];
10385 BNX2X_DEV_INFO("Disable bmac Rx\n");
10386 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10387 : NIG_REG_INGRESS_BMAC0_MEM;
10388 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10389 : BIGMAC_REGISTER_BMAC_CONTROL;
10390
10391 /*
10392 * use rd/wr since we cannot use dmae. This is safe
10393 * since MCP won't access the bus due to the request
10394 * to unload, and no function on the path can be
10395 * loaded at this time.
10396 */
10397 wb_data[0] = REG_RD(bp, base_addr + offset);
10398 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10399 vals->bmac_addr = base_addr + offset;
10400 vals->bmac_val[0] = wb_data[0];
10401 vals->bmac_val[1] = wb_data[1];
10402 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10403 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10404 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10405 }
10406 BNX2X_DEV_INFO("Disable emac Rx\n");
10407 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10408 vals->emac_val = REG_RD(bp, vals->emac_addr);
10409 REG_WR(bp, vals->emac_addr, 0);
10410 mac_stopped = true;
10411 } else {
10412 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10413 BNX2X_DEV_INFO("Disable xmac Rx\n");
10414 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10415 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10416 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10417 val & ~(1 << 1));
10418 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10419 val | (1 << 1));
10420 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10421 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10422 REG_WR(bp, vals->xmac_addr, 0);
10423 mac_stopped = true;
10424 }
10425
10426 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10427 reset_reg, vals);
10428 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10429 reset_reg, vals);
10430 }
10431
10432 if (mac_stopped)
10433 msleep(20);
10434 }
10435
10436 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10437 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10438 0x1848 + ((f) << 4))
10439 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10440 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10441 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10442
10443 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10444 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10445 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10446
10447 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10448 {
10449 /* UNDI marks its presence in DORQ -
10450 * it initializes CID offset for normal bell to 0x7
10451 */
10452 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10453 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10454 return false;
10455
10456 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10457 BNX2X_DEV_INFO("UNDI previously loaded\n");
10458 return true;
10459 }
10460
10461 return false;
10462 }
10463
10464 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10465 {
10466 u16 rcq, bd;
10467 u32 addr, tmp_reg;
10468
10469 if (BP_FUNC(bp) < 2)
10470 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10471 else
10472 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10473
10474 tmp_reg = REG_RD(bp, addr);
10475 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10476 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10477
10478 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10479 REG_WR(bp, addr, tmp_reg);
10480
10481 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10482 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10483 }
10484
10485 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10486 {
10487 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10488 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10489 if (!rc) {
10490 BNX2X_ERR("MCP response failure, aborting\n");
10491 return -EBUSY;
10492 }
10493
10494 return 0;
10495 }
10496
10497 static struct bnx2x_prev_path_list *
10498 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10499 {
10500 struct bnx2x_prev_path_list *tmp_list;
10501
10502 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10503 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10504 bp->pdev->bus->number == tmp_list->bus &&
10505 BP_PATH(bp) == tmp_list->path)
10506 return tmp_list;
10507
10508 return NULL;
10509 }
10510
10511 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10512 {
10513 struct bnx2x_prev_path_list *tmp_list;
10514 int rc;
10515
10516 rc = down_interruptible(&bnx2x_prev_sem);
10517 if (rc) {
10518 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10519 return rc;
10520 }
10521
10522 tmp_list = bnx2x_prev_path_get_entry(bp);
10523 if (tmp_list) {
10524 tmp_list->aer = 1;
10525 rc = 0;
10526 } else {
10527 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10528 BP_PATH(bp));
10529 }
10530
10531 up(&bnx2x_prev_sem);
10532
10533 return rc;
10534 }
10535
10536 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10537 {
10538 struct bnx2x_prev_path_list *tmp_list;
10539 bool rc = false;
10540
10541 if (down_trylock(&bnx2x_prev_sem))
10542 return false;
10543
10544 tmp_list = bnx2x_prev_path_get_entry(bp);
10545 if (tmp_list) {
10546 if (tmp_list->aer) {
10547 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10548 BP_PATH(bp));
10549 } else {
10550 rc = true;
10551 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10552 BP_PATH(bp));
10553 }
10554 }
10555
10556 up(&bnx2x_prev_sem);
10557
10558 return rc;
10559 }
10560
10561 bool bnx2x_port_after_undi(struct bnx2x *bp)
10562 {
10563 struct bnx2x_prev_path_list *entry;
10564 bool val;
10565
10566 down(&bnx2x_prev_sem);
10567
10568 entry = bnx2x_prev_path_get_entry(bp);
10569 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10570
10571 up(&bnx2x_prev_sem);
10572
10573 return val;
10574 }
10575
10576 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10577 {
10578 struct bnx2x_prev_path_list *tmp_list;
10579 int rc;
10580
10581 rc = down_interruptible(&bnx2x_prev_sem);
10582 if (rc) {
10583 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10584 return rc;
10585 }
10586
10587 /* Check whether the entry for this path already exists */
10588 tmp_list = bnx2x_prev_path_get_entry(bp);
10589 if (tmp_list) {
10590 if (!tmp_list->aer) {
10591 BNX2X_ERR("Re-Marking the path.\n");
10592 } else {
10593 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10594 BP_PATH(bp));
10595 tmp_list->aer = 0;
10596 }
10597 up(&bnx2x_prev_sem);
10598 return 0;
10599 }
10600 up(&bnx2x_prev_sem);
10601
10602 /* Create an entry for this path and add it */
10603 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10604 if (!tmp_list) {
10605 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10606 return -ENOMEM;
10607 }
10608
10609 tmp_list->bus = bp->pdev->bus->number;
10610 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10611 tmp_list->path = BP_PATH(bp);
10612 tmp_list->aer = 0;
10613 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10614
10615 rc = down_interruptible(&bnx2x_prev_sem);
10616 if (rc) {
10617 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10618 kfree(tmp_list);
10619 } else {
10620 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10621 BP_PATH(bp));
10622 list_add(&tmp_list->list, &bnx2x_prev_list);
10623 up(&bnx2x_prev_sem);
10624 }
10625
10626 return rc;
10627 }
10628
10629 static int bnx2x_do_flr(struct bnx2x *bp)
10630 {
10631 struct pci_dev *dev = bp->pdev;
10632
10633 if (CHIP_IS_E1x(bp)) {
10634 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10635 return -EINVAL;
10636 }
10637
10638 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10639 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10640 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10641 bp->common.bc_ver);
10642 return -EINVAL;
10643 }
10644
10645 if (!pci_wait_for_pending_transaction(dev))
10646 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10647
10648 BNX2X_DEV_INFO("Initiating FLR\n");
10649 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10650
10651 return 0;
10652 }
10653
10654 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10655 {
10656 int rc;
10657
10658 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10659
10660 /* Test if previous unload process was already finished for this path */
10661 if (bnx2x_prev_is_path_marked(bp))
10662 return bnx2x_prev_mcp_done(bp);
10663
10664 BNX2X_DEV_INFO("Path is unmarked\n");
10665
10666 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10667 if (bnx2x_prev_is_after_undi(bp))
10668 goto out;
10669
10670 /* If function has FLR capabilities, and existing FW version matches
10671 * the one required, then FLR will be sufficient to clean any residue
10672 * left by previous driver
10673 */
10674 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10675
10676 if (!rc) {
10677 /* fw version is good */
10678 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10679 rc = bnx2x_do_flr(bp);
10680 }
10681
10682 if (!rc) {
10683 /* FLR was performed */
10684 BNX2X_DEV_INFO("FLR successful\n");
10685 return 0;
10686 }
10687
10688 BNX2X_DEV_INFO("Could not FLR\n");
10689
10690 out:
10691 /* Close the MCP request, return failure*/
10692 rc = bnx2x_prev_mcp_done(bp);
10693 if (!rc)
10694 rc = BNX2X_PREV_WAIT_NEEDED;
10695
10696 return rc;
10697 }
10698
10699 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10700 {
10701 u32 reset_reg, tmp_reg = 0, rc;
10702 bool prev_undi = false;
10703 struct bnx2x_mac_vals mac_vals;
10704
10705 /* It is possible a previous function received 'common' answer,
10706 * but hasn't loaded yet, therefore creating a scenario of
10707 * multiple functions receiving 'common' on the same path.
10708 */
10709 BNX2X_DEV_INFO("Common unload Flow\n");
10710
10711 memset(&mac_vals, 0, sizeof(mac_vals));
10712
10713 if (bnx2x_prev_is_path_marked(bp))
10714 return bnx2x_prev_mcp_done(bp);
10715
10716 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10717
10718 /* Reset should be performed after BRB is emptied */
10719 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10720 u32 timer_count = 1000;
10721
10722 /* Close the MAC Rx to prevent BRB from filling up */
10723 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10724
10725 /* close LLH filters for both ports towards the BRB */
10726 bnx2x_set_rx_filter(&bp->link_params, 0);
10727 bp->link_params.port ^= 1;
10728 bnx2x_set_rx_filter(&bp->link_params, 0);
10729 bp->link_params.port ^= 1;
10730
10731 /* Check if the UNDI driver was previously loaded */
10732 if (bnx2x_prev_is_after_undi(bp)) {
10733 prev_undi = true;
10734 /* clear the UNDI indication */
10735 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10736 /* clear possible idle check errors */
10737 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10738 }
10739 if (!CHIP_IS_E1x(bp))
10740 /* block FW from writing to host */
10741 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10742
10743 /* wait until BRB is empty */
10744 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10745 while (timer_count) {
10746 u32 prev_brb = tmp_reg;
10747
10748 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10749 if (!tmp_reg)
10750 break;
10751
10752 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10753
10754 /* reset timer as long as BRB actually gets emptied */
10755 if (prev_brb > tmp_reg)
10756 timer_count = 1000;
10757 else
10758 timer_count--;
10759
10760 /* If UNDI resides in memory, manually increment it */
10761 if (prev_undi)
10762 bnx2x_prev_unload_undi_inc(bp, 1);
10763
10764 udelay(10);
10765 }
10766
10767 if (!timer_count)
10768 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10769 }
10770
10771 /* No packets are in the pipeline, path is ready for reset */
10772 bnx2x_reset_common(bp);
10773
10774 if (mac_vals.xmac_addr)
10775 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10776 if (mac_vals.umac_addr[0])
10777 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10778 if (mac_vals.umac_addr[1])
10779 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10780 if (mac_vals.emac_addr)
10781 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10782 if (mac_vals.bmac_addr) {
10783 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10784 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10785 }
10786
10787 rc = bnx2x_prev_mark_path(bp, prev_undi);
10788 if (rc) {
10789 bnx2x_prev_mcp_done(bp);
10790 return rc;
10791 }
10792
10793 return bnx2x_prev_mcp_done(bp);
10794 }
10795
10796 static int bnx2x_prev_unload(struct bnx2x *bp)
10797 {
10798 int time_counter = 10;
10799 u32 rc, fw, hw_lock_reg, hw_lock_val;
10800 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10801
10802 /* clear hw from errors which may have resulted from an interrupted
10803 * dmae transaction.
10804 */
10805 bnx2x_clean_pglue_errors(bp);
10806
10807 /* Release previously held locks */
10808 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10809 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10810 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10811
10812 hw_lock_val = REG_RD(bp, hw_lock_reg);
10813 if (hw_lock_val) {
10814 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10815 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10816 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10817 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10818 }
10819
10820 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10821 REG_WR(bp, hw_lock_reg, 0xffffffff);
10822 } else
10823 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10824
10825 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10826 BNX2X_DEV_INFO("Release previously held alr\n");
10827 bnx2x_release_alr(bp);
10828 }
10829
10830 do {
10831 int aer = 0;
10832 /* Lock MCP using an unload request */
10833 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10834 if (!fw) {
10835 BNX2X_ERR("MCP response failure, aborting\n");
10836 rc = -EBUSY;
10837 break;
10838 }
10839
10840 rc = down_interruptible(&bnx2x_prev_sem);
10841 if (rc) {
10842 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10843 rc);
10844 } else {
10845 /* If Path is marked by EEH, ignore unload status */
10846 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10847 bnx2x_prev_path_get_entry(bp)->aer);
10848 up(&bnx2x_prev_sem);
10849 }
10850
10851 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10852 rc = bnx2x_prev_unload_common(bp);
10853 break;
10854 }
10855
10856 /* non-common reply from MCP might require looping */
10857 rc = bnx2x_prev_unload_uncommon(bp);
10858 if (rc != BNX2X_PREV_WAIT_NEEDED)
10859 break;
10860
10861 msleep(20);
10862 } while (--time_counter);
10863
10864 if (!time_counter || rc) {
10865 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10866 rc = -EPROBE_DEFER;
10867 }
10868
10869 /* Mark function if its port was used to boot from SAN */
10870 if (bnx2x_port_after_undi(bp))
10871 bp->link_params.feature_config_flags |=
10872 FEATURE_CONFIG_BOOT_FROM_SAN;
10873
10874 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10875
10876 return rc;
10877 }
10878
10879 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10880 {
10881 u32 val, val2, val3, val4, id, boot_mode;
10882 u16 pmc;
10883
10884 /* Get the chip revision id and number. */
10885 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10886 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10887 id = ((val & 0xffff) << 16);
10888 val = REG_RD(bp, MISC_REG_CHIP_REV);
10889 id |= ((val & 0xf) << 12);
10890
10891 /* Metal is read from PCI regs, but we can't access >=0x400 from
10892 * the configuration space (so we need to reg_rd)
10893 */
10894 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10895 id |= (((val >> 24) & 0xf) << 4);
10896 val = REG_RD(bp, MISC_REG_BOND_ID);
10897 id |= (val & 0xf);
10898 bp->common.chip_id = id;
10899
10900 /* force 57811 according to MISC register */
10901 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10902 if (CHIP_IS_57810(bp))
10903 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10904 (bp->common.chip_id & 0x0000FFFF);
10905 else if (CHIP_IS_57810_MF(bp))
10906 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10907 (bp->common.chip_id & 0x0000FFFF);
10908 bp->common.chip_id |= 0x1;
10909 }
10910
10911 /* Set doorbell size */
10912 bp->db_size = (1 << BNX2X_DB_SHIFT);
10913
10914 if (!CHIP_IS_E1x(bp)) {
10915 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10916 if ((val & 1) == 0)
10917 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10918 else
10919 val = (val >> 1) & 1;
10920 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10921 "2_PORT_MODE");
10922 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10923 CHIP_2_PORT_MODE;
10924
10925 if (CHIP_MODE_IS_4_PORT(bp))
10926 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10927 else
10928 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10929 } else {
10930 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10931 bp->pfid = bp->pf_num; /* 0..7 */
10932 }
10933
10934 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10935
10936 bp->link_params.chip_id = bp->common.chip_id;
10937 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10938
10939 val = (REG_RD(bp, 0x2874) & 0x55);
10940 if ((bp->common.chip_id & 0x1) ||
10941 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10942 bp->flags |= ONE_PORT_FLAG;
10943 BNX2X_DEV_INFO("single port device\n");
10944 }
10945
10946 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10947 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10948 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10949 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10950 bp->common.flash_size, bp->common.flash_size);
10951
10952 bnx2x_init_shmem(bp);
10953
10954 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10955 MISC_REG_GENERIC_CR_1 :
10956 MISC_REG_GENERIC_CR_0));
10957
10958 bp->link_params.shmem_base = bp->common.shmem_base;
10959 bp->link_params.shmem2_base = bp->common.shmem2_base;
10960 if (SHMEM2_RD(bp, size) >
10961 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10962 bp->link_params.lfa_base =
10963 REG_RD(bp, bp->common.shmem2_base +
10964 (u32)offsetof(struct shmem2_region,
10965 lfa_host_addr[BP_PORT(bp)]));
10966 else
10967 bp->link_params.lfa_base = 0;
10968 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10969 bp->common.shmem_base, bp->common.shmem2_base);
10970
10971 if (!bp->common.shmem_base) {
10972 BNX2X_DEV_INFO("MCP not active\n");
10973 bp->flags |= NO_MCP_FLAG;
10974 return;
10975 }
10976
10977 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10978 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10979
10980 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10981 SHARED_HW_CFG_LED_MODE_MASK) >>
10982 SHARED_HW_CFG_LED_MODE_SHIFT);
10983
10984 bp->link_params.feature_config_flags = 0;
10985 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10986 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10987 bp->link_params.feature_config_flags |=
10988 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10989 else
10990 bp->link_params.feature_config_flags &=
10991 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10992
10993 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10994 bp->common.bc_ver = val;
10995 BNX2X_DEV_INFO("bc_ver %X\n", val);
10996 if (val < BNX2X_BC_VER) {
10997 /* for now only warn
10998 * later we might need to enforce this */
10999 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11000 BNX2X_BC_VER, val);
11001 }
11002 bp->link_params.feature_config_flags |=
11003 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11004 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11005
11006 bp->link_params.feature_config_flags |=
11007 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11008 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11009 bp->link_params.feature_config_flags |=
11010 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11011 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11012 bp->link_params.feature_config_flags |=
11013 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11014 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11015
11016 bp->link_params.feature_config_flags |=
11017 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11018 FEATURE_CONFIG_MT_SUPPORT : 0;
11019
11020 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11021 BC_SUPPORTS_PFC_STATS : 0;
11022
11023 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11024 BC_SUPPORTS_FCOE_FEATURES : 0;
11025
11026 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11027 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11028
11029 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11030 BC_SUPPORTS_RMMOD_CMD : 0;
11031
11032 boot_mode = SHMEM_RD(bp,
11033 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11034 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11035 switch (boot_mode) {
11036 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11037 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11038 break;
11039 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11040 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11041 break;
11042 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11043 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11044 break;
11045 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11046 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11047 break;
11048 }
11049
11050 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11051 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11052
11053 BNX2X_DEV_INFO("%sWoL capable\n",
11054 (bp->flags & NO_WOL_FLAG) ? "not " : "");
11055
11056 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11057 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11058 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11059 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11060
11061 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11062 val, val2, val3, val4);
11063 }
11064
11065 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11066 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11067
11068 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11069 {
11070 int pfid = BP_FUNC(bp);
11071 int igu_sb_id;
11072 u32 val;
11073 u8 fid, igu_sb_cnt = 0;
11074
11075 bp->igu_base_sb = 0xff;
11076 if (CHIP_INT_MODE_IS_BC(bp)) {
11077 int vn = BP_VN(bp);
11078 igu_sb_cnt = bp->igu_sb_cnt;
11079 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11080 FP_SB_MAX_E1x;
11081
11082 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11083 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11084
11085 return 0;
11086 }
11087
11088 /* IGU in normal mode - read CAM */
11089 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11090 igu_sb_id++) {
11091 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11092 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11093 continue;
11094 fid = IGU_FID(val);
11095 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11096 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11097 continue;
11098 if (IGU_VEC(val) == 0)
11099 /* default status block */
11100 bp->igu_dsb_id = igu_sb_id;
11101 else {
11102 if (bp->igu_base_sb == 0xff)
11103 bp->igu_base_sb = igu_sb_id;
11104 igu_sb_cnt++;
11105 }
11106 }
11107 }
11108
11109 #ifdef CONFIG_PCI_MSI
11110 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11111 * optional that number of CAM entries will not be equal to the value
11112 * advertised in PCI.
11113 * Driver should use the minimal value of both as the actual status
11114 * block count
11115 */
11116 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11117 #endif
11118
11119 if (igu_sb_cnt == 0) {
11120 BNX2X_ERR("CAM configuration error\n");
11121 return -EINVAL;
11122 }
11123
11124 return 0;
11125 }
11126
11127 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11128 {
11129 int cfg_size = 0, idx, port = BP_PORT(bp);
11130
11131 /* Aggregation of supported attributes of all external phys */
11132 bp->port.supported[0] = 0;
11133 bp->port.supported[1] = 0;
11134 switch (bp->link_params.num_phys) {
11135 case 1:
11136 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11137 cfg_size = 1;
11138 break;
11139 case 2:
11140 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11141 cfg_size = 1;
11142 break;
11143 case 3:
11144 if (bp->link_params.multi_phy_config &
11145 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11146 bp->port.supported[1] =
11147 bp->link_params.phy[EXT_PHY1].supported;
11148 bp->port.supported[0] =
11149 bp->link_params.phy[EXT_PHY2].supported;
11150 } else {
11151 bp->port.supported[0] =
11152 bp->link_params.phy[EXT_PHY1].supported;
11153 bp->port.supported[1] =
11154 bp->link_params.phy[EXT_PHY2].supported;
11155 }
11156 cfg_size = 2;
11157 break;
11158 }
11159
11160 if (!(bp->port.supported[0] || bp->port.supported[1])) {
11161 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11162 SHMEM_RD(bp,
11163 dev_info.port_hw_config[port].external_phy_config),
11164 SHMEM_RD(bp,
11165 dev_info.port_hw_config[port].external_phy_config2));
11166 return;
11167 }
11168
11169 if (CHIP_IS_E3(bp))
11170 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11171 else {
11172 switch (switch_cfg) {
11173 case SWITCH_CFG_1G:
11174 bp->port.phy_addr = REG_RD(
11175 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11176 break;
11177 case SWITCH_CFG_10G:
11178 bp->port.phy_addr = REG_RD(
11179 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11180 break;
11181 default:
11182 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11183 bp->port.link_config[0]);
11184 return;
11185 }
11186 }
11187 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11188 /* mask what we support according to speed_cap_mask per configuration */
11189 for (idx = 0; idx < cfg_size; idx++) {
11190 if (!(bp->link_params.speed_cap_mask[idx] &
11191 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11192 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11193
11194 if (!(bp->link_params.speed_cap_mask[idx] &
11195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11196 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11197
11198 if (!(bp->link_params.speed_cap_mask[idx] &
11199 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11200 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11201
11202 if (!(bp->link_params.speed_cap_mask[idx] &
11203 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11204 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11205
11206 if (!(bp->link_params.speed_cap_mask[idx] &
11207 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11208 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11209 SUPPORTED_1000baseT_Full);
11210
11211 if (!(bp->link_params.speed_cap_mask[idx] &
11212 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11213 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11214
11215 if (!(bp->link_params.speed_cap_mask[idx] &
11216 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11217 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11218
11219 if (!(bp->link_params.speed_cap_mask[idx] &
11220 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11221 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11222 }
11223
11224 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11225 bp->port.supported[1]);
11226 }
11227
11228 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11229 {
11230 u32 link_config, idx, cfg_size = 0;
11231 bp->port.advertising[0] = 0;
11232 bp->port.advertising[1] = 0;
11233 switch (bp->link_params.num_phys) {
11234 case 1:
11235 case 2:
11236 cfg_size = 1;
11237 break;
11238 case 3:
11239 cfg_size = 2;
11240 break;
11241 }
11242 for (idx = 0; idx < cfg_size; idx++) {
11243 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11244 link_config = bp->port.link_config[idx];
11245 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11246 case PORT_FEATURE_LINK_SPEED_AUTO:
11247 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11248 bp->link_params.req_line_speed[idx] =
11249 SPEED_AUTO_NEG;
11250 bp->port.advertising[idx] |=
11251 bp->port.supported[idx];
11252 if (bp->link_params.phy[EXT_PHY1].type ==
11253 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11254 bp->port.advertising[idx] |=
11255 (SUPPORTED_100baseT_Half |
11256 SUPPORTED_100baseT_Full);
11257 } else {
11258 /* force 10G, no AN */
11259 bp->link_params.req_line_speed[idx] =
11260 SPEED_10000;
11261 bp->port.advertising[idx] |=
11262 (ADVERTISED_10000baseT_Full |
11263 ADVERTISED_FIBRE);
11264 continue;
11265 }
11266 break;
11267
11268 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11269 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11270 bp->link_params.req_line_speed[idx] =
11271 SPEED_10;
11272 bp->port.advertising[idx] |=
11273 (ADVERTISED_10baseT_Full |
11274 ADVERTISED_TP);
11275 } else {
11276 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11277 link_config,
11278 bp->link_params.speed_cap_mask[idx]);
11279 return;
11280 }
11281 break;
11282
11283 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11284 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11285 bp->link_params.req_line_speed[idx] =
11286 SPEED_10;
11287 bp->link_params.req_duplex[idx] =
11288 DUPLEX_HALF;
11289 bp->port.advertising[idx] |=
11290 (ADVERTISED_10baseT_Half |
11291 ADVERTISED_TP);
11292 } else {
11293 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11294 link_config,
11295 bp->link_params.speed_cap_mask[idx]);
11296 return;
11297 }
11298 break;
11299
11300 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11301 if (bp->port.supported[idx] &
11302 SUPPORTED_100baseT_Full) {
11303 bp->link_params.req_line_speed[idx] =
11304 SPEED_100;
11305 bp->port.advertising[idx] |=
11306 (ADVERTISED_100baseT_Full |
11307 ADVERTISED_TP);
11308 } else {
11309 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11310 link_config,
11311 bp->link_params.speed_cap_mask[idx]);
11312 return;
11313 }
11314 break;
11315
11316 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11317 if (bp->port.supported[idx] &
11318 SUPPORTED_100baseT_Half) {
11319 bp->link_params.req_line_speed[idx] =
11320 SPEED_100;
11321 bp->link_params.req_duplex[idx] =
11322 DUPLEX_HALF;
11323 bp->port.advertising[idx] |=
11324 (ADVERTISED_100baseT_Half |
11325 ADVERTISED_TP);
11326 } else {
11327 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11328 link_config,
11329 bp->link_params.speed_cap_mask[idx]);
11330 return;
11331 }
11332 break;
11333
11334 case PORT_FEATURE_LINK_SPEED_1G:
11335 if (bp->port.supported[idx] &
11336 SUPPORTED_1000baseT_Full) {
11337 bp->link_params.req_line_speed[idx] =
11338 SPEED_1000;
11339 bp->port.advertising[idx] |=
11340 (ADVERTISED_1000baseT_Full |
11341 ADVERTISED_TP);
11342 } else if (bp->port.supported[idx] &
11343 SUPPORTED_1000baseKX_Full) {
11344 bp->link_params.req_line_speed[idx] =
11345 SPEED_1000;
11346 bp->port.advertising[idx] |=
11347 ADVERTISED_1000baseKX_Full;
11348 } else {
11349 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11350 link_config,
11351 bp->link_params.speed_cap_mask[idx]);
11352 return;
11353 }
11354 break;
11355
11356 case PORT_FEATURE_LINK_SPEED_2_5G:
11357 if (bp->port.supported[idx] &
11358 SUPPORTED_2500baseX_Full) {
11359 bp->link_params.req_line_speed[idx] =
11360 SPEED_2500;
11361 bp->port.advertising[idx] |=
11362 (ADVERTISED_2500baseX_Full |
11363 ADVERTISED_TP);
11364 } else {
11365 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11366 link_config,
11367 bp->link_params.speed_cap_mask[idx]);
11368 return;
11369 }
11370 break;
11371
11372 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11373 if (bp->port.supported[idx] &
11374 SUPPORTED_10000baseT_Full) {
11375 bp->link_params.req_line_speed[idx] =
11376 SPEED_10000;
11377 bp->port.advertising[idx] |=
11378 (ADVERTISED_10000baseT_Full |
11379 ADVERTISED_FIBRE);
11380 } else if (bp->port.supported[idx] &
11381 SUPPORTED_10000baseKR_Full) {
11382 bp->link_params.req_line_speed[idx] =
11383 SPEED_10000;
11384 bp->port.advertising[idx] |=
11385 (ADVERTISED_10000baseKR_Full |
11386 ADVERTISED_FIBRE);
11387 } else {
11388 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11389 link_config,
11390 bp->link_params.speed_cap_mask[idx]);
11391 return;
11392 }
11393 break;
11394 case PORT_FEATURE_LINK_SPEED_20G:
11395 bp->link_params.req_line_speed[idx] = SPEED_20000;
11396
11397 break;
11398 default:
11399 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11400 link_config);
11401 bp->link_params.req_line_speed[idx] =
11402 SPEED_AUTO_NEG;
11403 bp->port.advertising[idx] =
11404 bp->port.supported[idx];
11405 break;
11406 }
11407
11408 bp->link_params.req_flow_ctrl[idx] = (link_config &
11409 PORT_FEATURE_FLOW_CONTROL_MASK);
11410 if (bp->link_params.req_flow_ctrl[idx] ==
11411 BNX2X_FLOW_CTRL_AUTO) {
11412 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11413 bp->link_params.req_flow_ctrl[idx] =
11414 BNX2X_FLOW_CTRL_NONE;
11415 else
11416 bnx2x_set_requested_fc(bp);
11417 }
11418
11419 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11420 bp->link_params.req_line_speed[idx],
11421 bp->link_params.req_duplex[idx],
11422 bp->link_params.req_flow_ctrl[idx],
11423 bp->port.advertising[idx]);
11424 }
11425 }
11426
11427 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11428 {
11429 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11430 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11431 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11432 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11433 }
11434
11435 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11436 {
11437 int port = BP_PORT(bp);
11438 u32 config;
11439 u32 ext_phy_type, ext_phy_config, eee_mode;
11440
11441 bp->link_params.bp = bp;
11442 bp->link_params.port = port;
11443
11444 bp->link_params.lane_config =
11445 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11446
11447 bp->link_params.speed_cap_mask[0] =
11448 SHMEM_RD(bp,
11449 dev_info.port_hw_config[port].speed_capability_mask) &
11450 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11451 bp->link_params.speed_cap_mask[1] =
11452 SHMEM_RD(bp,
11453 dev_info.port_hw_config[port].speed_capability_mask2) &
11454 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11455 bp->port.link_config[0] =
11456 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11457
11458 bp->port.link_config[1] =
11459 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11460
11461 bp->link_params.multi_phy_config =
11462 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11463 /* If the device is capable of WoL, set the default state according
11464 * to the HW
11465 */
11466 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11467 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11468 (config & PORT_FEATURE_WOL_ENABLED));
11469
11470 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11471 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11472 bp->flags |= NO_ISCSI_FLAG;
11473 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11474 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11475 bp->flags |= NO_FCOE_FLAG;
11476
11477 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11478 bp->link_params.lane_config,
11479 bp->link_params.speed_cap_mask[0],
11480 bp->port.link_config[0]);
11481
11482 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11483 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11484 bnx2x_phy_probe(&bp->link_params);
11485 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11486
11487 bnx2x_link_settings_requested(bp);
11488
11489 /*
11490 * If connected directly, work with the internal PHY, otherwise, work
11491 * with the external PHY
11492 */
11493 ext_phy_config =
11494 SHMEM_RD(bp,
11495 dev_info.port_hw_config[port].external_phy_config);
11496 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11497 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11498 bp->mdio.prtad = bp->port.phy_addr;
11499
11500 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11501 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11502 bp->mdio.prtad =
11503 XGXS_EXT_PHY_ADDR(ext_phy_config);
11504
11505 /* Configure link feature according to nvram value */
11506 eee_mode = (((SHMEM_RD(bp, dev_info.
11507 port_feature_config[port].eee_power_mode)) &
11508 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11509 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11510 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11511 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11512 EEE_MODE_ENABLE_LPI |
11513 EEE_MODE_OUTPUT_TIME;
11514 } else {
11515 bp->link_params.eee_mode = 0;
11516 }
11517 }
11518
11519 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11520 {
11521 u32 no_flags = NO_ISCSI_FLAG;
11522 int port = BP_PORT(bp);
11523 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11524 drv_lic_key[port].max_iscsi_conn);
11525
11526 if (!CNIC_SUPPORT(bp)) {
11527 bp->flags |= no_flags;
11528 return;
11529 }
11530
11531 /* Get the number of maximum allowed iSCSI connections */
11532 bp->cnic_eth_dev.max_iscsi_conn =
11533 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11534 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11535
11536 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11537 bp->cnic_eth_dev.max_iscsi_conn);
11538
11539 /*
11540 * If maximum allowed number of connections is zero -
11541 * disable the feature.
11542 */
11543 if (!bp->cnic_eth_dev.max_iscsi_conn)
11544 bp->flags |= no_flags;
11545 }
11546
11547 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11548 {
11549 /* Port info */
11550 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11551 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11552 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11553 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11554
11555 /* Node info */
11556 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11557 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11558 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11559 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11560 }
11561
11562 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11563 {
11564 u8 count = 0;
11565
11566 if (IS_MF(bp)) {
11567 u8 fid;
11568
11569 /* iterate over absolute function ids for this path: */
11570 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11571 if (IS_MF_SD(bp)) {
11572 u32 cfg = MF_CFG_RD(bp,
11573 func_mf_config[fid].config);
11574
11575 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11576 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11577 FUNC_MF_CFG_PROTOCOL_FCOE))
11578 count++;
11579 } else {
11580 u32 cfg = MF_CFG_RD(bp,
11581 func_ext_config[fid].
11582 func_cfg);
11583
11584 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11585 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11586 count++;
11587 }
11588 }
11589 } else { /* SF */
11590 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11591
11592 for (port = 0; port < port_cnt; port++) {
11593 u32 lic = SHMEM_RD(bp,
11594 drv_lic_key[port].max_fcoe_conn) ^
11595 FW_ENCODE_32BIT_PATTERN;
11596 if (lic)
11597 count++;
11598 }
11599 }
11600
11601 return count;
11602 }
11603
11604 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11605 {
11606 int port = BP_PORT(bp);
11607 int func = BP_ABS_FUNC(bp);
11608 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11609 drv_lic_key[port].max_fcoe_conn);
11610 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11611
11612 if (!CNIC_SUPPORT(bp)) {
11613 bp->flags |= NO_FCOE_FLAG;
11614 return;
11615 }
11616
11617 /* Get the number of maximum allowed FCoE connections */
11618 bp->cnic_eth_dev.max_fcoe_conn =
11619 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11620 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11621
11622 /* Calculate the number of maximum allowed FCoE tasks */
11623 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11624
11625 /* check if FCoE resources must be shared between different functions */
11626 if (num_fcoe_func)
11627 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11628
11629 /* Read the WWN: */
11630 if (!IS_MF(bp)) {
11631 /* Port info */
11632 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11633 SHMEM_RD(bp,
11634 dev_info.port_hw_config[port].
11635 fcoe_wwn_port_name_upper);
11636 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11637 SHMEM_RD(bp,
11638 dev_info.port_hw_config[port].
11639 fcoe_wwn_port_name_lower);
11640
11641 /* Node info */
11642 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11643 SHMEM_RD(bp,
11644 dev_info.port_hw_config[port].
11645 fcoe_wwn_node_name_upper);
11646 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11647 SHMEM_RD(bp,
11648 dev_info.port_hw_config[port].
11649 fcoe_wwn_node_name_lower);
11650 } else if (!IS_MF_SD(bp)) {
11651 /* Read the WWN info only if the FCoE feature is enabled for
11652 * this function.
11653 */
11654 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11655 bnx2x_get_ext_wwn_info(bp, func);
11656 } else {
11657 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11658 bnx2x_get_ext_wwn_info(bp, func);
11659 }
11660
11661 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11662
11663 /*
11664 * If maximum allowed number of connections is zero -
11665 * disable the feature.
11666 */
11667 if (!bp->cnic_eth_dev.max_fcoe_conn)
11668 bp->flags |= NO_FCOE_FLAG;
11669 }
11670
11671 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11672 {
11673 /*
11674 * iSCSI may be dynamically disabled but reading
11675 * info here we will decrease memory usage by driver
11676 * if the feature is disabled for good
11677 */
11678 bnx2x_get_iscsi_info(bp);
11679 bnx2x_get_fcoe_info(bp);
11680 }
11681
11682 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11683 {
11684 u32 val, val2;
11685 int func = BP_ABS_FUNC(bp);
11686 int port = BP_PORT(bp);
11687 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11688 u8 *fip_mac = bp->fip_mac;
11689
11690 if (IS_MF(bp)) {
11691 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11692 * FCoE MAC then the appropriate feature should be disabled.
11693 * In non SD mode features configuration comes from struct
11694 * func_ext_config.
11695 */
11696 if (!IS_MF_SD(bp)) {
11697 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11698 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11699 val2 = MF_CFG_RD(bp, func_ext_config[func].
11700 iscsi_mac_addr_upper);
11701 val = MF_CFG_RD(bp, func_ext_config[func].
11702 iscsi_mac_addr_lower);
11703 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11704 BNX2X_DEV_INFO
11705 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11706 } else {
11707 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11708 }
11709
11710 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11711 val2 = MF_CFG_RD(bp, func_ext_config[func].
11712 fcoe_mac_addr_upper);
11713 val = MF_CFG_RD(bp, func_ext_config[func].
11714 fcoe_mac_addr_lower);
11715 bnx2x_set_mac_buf(fip_mac, val, val2);
11716 BNX2X_DEV_INFO
11717 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11718 } else {
11719 bp->flags |= NO_FCOE_FLAG;
11720 }
11721
11722 bp->mf_ext_config = cfg;
11723
11724 } else { /* SD MODE */
11725 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11726 /* use primary mac as iscsi mac */
11727 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11728
11729 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11730 BNX2X_DEV_INFO
11731 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11732 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11733 /* use primary mac as fip mac */
11734 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11735 BNX2X_DEV_INFO("SD FCoE MODE\n");
11736 BNX2X_DEV_INFO
11737 ("Read FIP MAC: %pM\n", fip_mac);
11738 }
11739 }
11740
11741 /* If this is a storage-only interface, use SAN mac as
11742 * primary MAC. Notice that for SD this is already the case,
11743 * as the SAN mac was copied from the primary MAC.
11744 */
11745 if (IS_MF_FCOE_AFEX(bp))
11746 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11747 } else {
11748 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11749 iscsi_mac_upper);
11750 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11751 iscsi_mac_lower);
11752 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11753
11754 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11755 fcoe_fip_mac_upper);
11756 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11757 fcoe_fip_mac_lower);
11758 bnx2x_set_mac_buf(fip_mac, val, val2);
11759 }
11760
11761 /* Disable iSCSI OOO if MAC configuration is invalid. */
11762 if (!is_valid_ether_addr(iscsi_mac)) {
11763 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11764 eth_zero_addr(iscsi_mac);
11765 }
11766
11767 /* Disable FCoE if MAC configuration is invalid. */
11768 if (!is_valid_ether_addr(fip_mac)) {
11769 bp->flags |= NO_FCOE_FLAG;
11770 eth_zero_addr(bp->fip_mac);
11771 }
11772 }
11773
11774 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11775 {
11776 u32 val, val2;
11777 int func = BP_ABS_FUNC(bp);
11778 int port = BP_PORT(bp);
11779
11780 /* Zero primary MAC configuration */
11781 eth_zero_addr(bp->dev->dev_addr);
11782
11783 if (BP_NOMCP(bp)) {
11784 BNX2X_ERROR("warning: random MAC workaround active\n");
11785 eth_hw_addr_random(bp->dev);
11786 } else if (IS_MF(bp)) {
11787 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11788 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11789 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11790 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11791 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11792
11793 if (CNIC_SUPPORT(bp))
11794 bnx2x_get_cnic_mac_hwinfo(bp);
11795 } else {
11796 /* in SF read MACs from port configuration */
11797 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11798 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11799 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11800
11801 if (CNIC_SUPPORT(bp))
11802 bnx2x_get_cnic_mac_hwinfo(bp);
11803 }
11804
11805 if (!BP_NOMCP(bp)) {
11806 /* Read physical port identifier from shmem */
11807 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11808 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11809 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11810 bp->flags |= HAS_PHYS_PORT_ID;
11811 }
11812
11813 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11814
11815 if (!is_valid_ether_addr(bp->dev->dev_addr))
11816 dev_err(&bp->pdev->dev,
11817 "bad Ethernet MAC address configuration: %pM\n"
11818 "change it manually before bringing up the appropriate network interface\n",
11819 bp->dev->dev_addr);
11820 }
11821
11822 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11823 {
11824 int tmp;
11825 u32 cfg;
11826
11827 if (IS_VF(bp))
11828 return false;
11829
11830 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11831 /* Take function: tmp = func */
11832 tmp = BP_ABS_FUNC(bp);
11833 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11834 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11835 } else {
11836 /* Take port: tmp = port */
11837 tmp = BP_PORT(bp);
11838 cfg = SHMEM_RD(bp,
11839 dev_info.port_hw_config[tmp].generic_features);
11840 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11841 }
11842 return cfg;
11843 }
11844
11845 static void validate_set_si_mode(struct bnx2x *bp)
11846 {
11847 u8 func = BP_ABS_FUNC(bp);
11848 u32 val;
11849
11850 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11851
11852 /* check for legal mac (upper bytes) */
11853 if (val != 0xffff) {
11854 bp->mf_mode = MULTI_FUNCTION_SI;
11855 bp->mf_config[BP_VN(bp)] =
11856 MF_CFG_RD(bp, func_mf_config[func].config);
11857 } else
11858 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11859 }
11860
11861 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11862 {
11863 int /*abs*/func = BP_ABS_FUNC(bp);
11864 int vn, mfw_vn;
11865 u32 val = 0, val2 = 0;
11866 int rc = 0;
11867
11868 /* Validate that chip access is feasible */
11869 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11870 dev_err(&bp->pdev->dev,
11871 "Chip read returns all Fs. Preventing probe from continuing\n");
11872 return -EINVAL;
11873 }
11874
11875 bnx2x_get_common_hwinfo(bp);
11876
11877 /*
11878 * initialize IGU parameters
11879 */
11880 if (CHIP_IS_E1x(bp)) {
11881 bp->common.int_block = INT_BLOCK_HC;
11882
11883 bp->igu_dsb_id = DEF_SB_IGU_ID;
11884 bp->igu_base_sb = 0;
11885 } else {
11886 bp->common.int_block = INT_BLOCK_IGU;
11887
11888 /* do not allow device reset during IGU info processing */
11889 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11890
11891 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11892
11893 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11894 int tout = 5000;
11895
11896 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11897
11898 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11899 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11900 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11901
11902 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11903 tout--;
11904 usleep_range(1000, 2000);
11905 }
11906
11907 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11908 dev_err(&bp->pdev->dev,
11909 "FORCING Normal Mode failed!!!\n");
11910 bnx2x_release_hw_lock(bp,
11911 HW_LOCK_RESOURCE_RESET);
11912 return -EPERM;
11913 }
11914 }
11915
11916 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11917 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11918 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11919 } else
11920 BNX2X_DEV_INFO("IGU Normal Mode\n");
11921
11922 rc = bnx2x_get_igu_cam_info(bp);
11923 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11924 if (rc)
11925 return rc;
11926 }
11927
11928 /*
11929 * set base FW non-default (fast path) status block id, this value is
11930 * used to initialize the fw_sb_id saved on the fp/queue structure to
11931 * determine the id used by the FW.
11932 */
11933 if (CHIP_IS_E1x(bp))
11934 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11935 else /*
11936 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11937 * the same queue are indicated on the same IGU SB). So we prefer
11938 * FW and IGU SBs to be the same value.
11939 */
11940 bp->base_fw_ndsb = bp->igu_base_sb;
11941
11942 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11943 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11944 bp->igu_sb_cnt, bp->base_fw_ndsb);
11945
11946 /*
11947 * Initialize MF configuration
11948 */
11949
11950 bp->mf_ov = 0;
11951 bp->mf_mode = 0;
11952 bp->mf_sub_mode = 0;
11953 vn = BP_VN(bp);
11954 mfw_vn = BP_FW_MB_IDX(bp);
11955
11956 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11957 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11958 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11959 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11960
11961 if (SHMEM2_HAS(bp, mf_cfg_addr))
11962 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11963 else
11964 bp->common.mf_cfg_base = bp->common.shmem_base +
11965 offsetof(struct shmem_region, func_mb) +
11966 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11967 /*
11968 * get mf configuration:
11969 * 1. Existence of MF configuration
11970 * 2. MAC address must be legal (check only upper bytes)
11971 * for Switch-Independent mode;
11972 * OVLAN must be legal for Switch-Dependent mode
11973 * 3. SF_MODE configures specific MF mode
11974 */
11975 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11976 /* get mf configuration */
11977 val = SHMEM_RD(bp,
11978 dev_info.shared_feature_config.config);
11979 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11980
11981 switch (val) {
11982 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11983 validate_set_si_mode(bp);
11984 break;
11985 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11986 if ((!CHIP_IS_E1x(bp)) &&
11987 (MF_CFG_RD(bp, func_mf_config[func].
11988 mac_upper) != 0xffff) &&
11989 (SHMEM2_HAS(bp,
11990 afex_driver_support))) {
11991 bp->mf_mode = MULTI_FUNCTION_AFEX;
11992 bp->mf_config[vn] = MF_CFG_RD(bp,
11993 func_mf_config[func].config);
11994 } else {
11995 BNX2X_DEV_INFO("can not configure afex mode\n");
11996 }
11997 break;
11998 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11999 /* get OV configuration */
12000 val = MF_CFG_RD(bp,
12001 func_mf_config[FUNC_0].e1hov_tag);
12002 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12003
12004 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12005 bp->mf_mode = MULTI_FUNCTION_SD;
12006 bp->mf_config[vn] = MF_CFG_RD(bp,
12007 func_mf_config[func].config);
12008 } else
12009 BNX2X_DEV_INFO("illegal OV for SD\n");
12010 break;
12011 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12012 bp->mf_mode = MULTI_FUNCTION_SD;
12013 bp->mf_sub_mode = SUB_MF_MODE_BD;
12014 bp->mf_config[vn] =
12015 MF_CFG_RD(bp,
12016 func_mf_config[func].config);
12017
12018 if (SHMEM2_HAS(bp, mtu_size)) {
12019 int mtu_idx = BP_FW_MB_IDX(bp);
12020 u16 mtu_size;
12021 u32 mtu;
12022
12023 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12024 mtu_size = (u16)mtu;
12025 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12026 mtu_size, mtu);
12027
12028 /* if valid: update device mtu */
12029 if (((mtu_size + ETH_HLEN) >=
12030 ETH_MIN_PACKET_SIZE) &&
12031 (mtu_size <=
12032 ETH_MAX_JUMBO_PACKET_SIZE))
12033 bp->dev->mtu = mtu_size;
12034 }
12035 break;
12036 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12037 bp->mf_mode = MULTI_FUNCTION_SD;
12038 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12039 bp->mf_config[vn] =
12040 MF_CFG_RD(bp,
12041 func_mf_config[func].config);
12042 break;
12043 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12044 bp->mf_config[vn] = 0;
12045 break;
12046 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12047 val2 = SHMEM_RD(bp,
12048 dev_info.shared_hw_config.config_3);
12049 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12050 switch (val2) {
12051 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12052 validate_set_si_mode(bp);
12053 bp->mf_sub_mode =
12054 SUB_MF_MODE_NPAR1_DOT_5;
12055 break;
12056 default:
12057 /* Unknown configuration */
12058 bp->mf_config[vn] = 0;
12059 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12060 val);
12061 }
12062 break;
12063 default:
12064 /* Unknown configuration: reset mf_config */
12065 bp->mf_config[vn] = 0;
12066 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12067 }
12068 }
12069
12070 BNX2X_DEV_INFO("%s function mode\n",
12071 IS_MF(bp) ? "multi" : "single");
12072
12073 switch (bp->mf_mode) {
12074 case MULTI_FUNCTION_SD:
12075 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12076 FUNC_MF_CFG_E1HOV_TAG_MASK;
12077 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12078 bp->mf_ov = val;
12079 bp->path_has_ovlan = true;
12080
12081 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12082 func, bp->mf_ov, bp->mf_ov);
12083 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12084 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12085 dev_err(&bp->pdev->dev,
12086 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12087 func);
12088 bp->path_has_ovlan = true;
12089 } else {
12090 dev_err(&bp->pdev->dev,
12091 "No valid MF OV for func %d, aborting\n",
12092 func);
12093 return -EPERM;
12094 }
12095 break;
12096 case MULTI_FUNCTION_AFEX:
12097 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12098 break;
12099 case MULTI_FUNCTION_SI:
12100 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12101 func);
12102 break;
12103 default:
12104 if (vn) {
12105 dev_err(&bp->pdev->dev,
12106 "VN %d is in a single function mode, aborting\n",
12107 vn);
12108 return -EPERM;
12109 }
12110 break;
12111 }
12112
12113 /* check if other port on the path needs ovlan:
12114 * Since MF configuration is shared between ports
12115 * Possible mixed modes are only
12116 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12117 */
12118 if (CHIP_MODE_IS_4_PORT(bp) &&
12119 !bp->path_has_ovlan &&
12120 !IS_MF(bp) &&
12121 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12122 u8 other_port = !BP_PORT(bp);
12123 u8 other_func = BP_PATH(bp) + 2*other_port;
12124 val = MF_CFG_RD(bp,
12125 func_mf_config[other_func].e1hov_tag);
12126 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12127 bp->path_has_ovlan = true;
12128 }
12129 }
12130
12131 /* adjust igu_sb_cnt to MF for E1H */
12132 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12133 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12134
12135 /* port info */
12136 bnx2x_get_port_hwinfo(bp);
12137
12138 /* Get MAC addresses */
12139 bnx2x_get_mac_hwinfo(bp);
12140
12141 bnx2x_get_cnic_info(bp);
12142
12143 return rc;
12144 }
12145
12146 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12147 {
12148 int cnt, i, block_end, rodi;
12149 char vpd_start[BNX2X_VPD_LEN+1];
12150 char str_id_reg[VENDOR_ID_LEN+1];
12151 char str_id_cap[VENDOR_ID_LEN+1];
12152 char *vpd_data;
12153 char *vpd_extended_data = NULL;
12154 u8 len;
12155
12156 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12157 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12158
12159 if (cnt < BNX2X_VPD_LEN)
12160 goto out_not_found;
12161
12162 /* VPD RO tag should be first tag after identifier string, hence
12163 * we should be able to find it in first BNX2X_VPD_LEN chars
12164 */
12165 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12166 PCI_VPD_LRDT_RO_DATA);
12167 if (i < 0)
12168 goto out_not_found;
12169
12170 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12171 pci_vpd_lrdt_size(&vpd_start[i]);
12172
12173 i += PCI_VPD_LRDT_TAG_SIZE;
12174
12175 if (block_end > BNX2X_VPD_LEN) {
12176 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12177 if (vpd_extended_data == NULL)
12178 goto out_not_found;
12179
12180 /* read rest of vpd image into vpd_extended_data */
12181 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12182 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12183 block_end - BNX2X_VPD_LEN,
12184 vpd_extended_data + BNX2X_VPD_LEN);
12185 if (cnt < (block_end - BNX2X_VPD_LEN))
12186 goto out_not_found;
12187 vpd_data = vpd_extended_data;
12188 } else
12189 vpd_data = vpd_start;
12190
12191 /* now vpd_data holds full vpd content in both cases */
12192
12193 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12194 PCI_VPD_RO_KEYWORD_MFR_ID);
12195 if (rodi < 0)
12196 goto out_not_found;
12197
12198 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12199
12200 if (len != VENDOR_ID_LEN)
12201 goto out_not_found;
12202
12203 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12204
12205 /* vendor specific info */
12206 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12207 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12208 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12209 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12210
12211 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12212 PCI_VPD_RO_KEYWORD_VENDOR0);
12213 if (rodi >= 0) {
12214 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12215
12216 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12217
12218 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12219 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12220 bp->fw_ver[len] = ' ';
12221 }
12222 }
12223 kfree(vpd_extended_data);
12224 return;
12225 }
12226 out_not_found:
12227 kfree(vpd_extended_data);
12228 return;
12229 }
12230
12231 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12232 {
12233 u32 flags = 0;
12234
12235 if (CHIP_REV_IS_FPGA(bp))
12236 SET_FLAGS(flags, MODE_FPGA);
12237 else if (CHIP_REV_IS_EMUL(bp))
12238 SET_FLAGS(flags, MODE_EMUL);
12239 else
12240 SET_FLAGS(flags, MODE_ASIC);
12241
12242 if (CHIP_MODE_IS_4_PORT(bp))
12243 SET_FLAGS(flags, MODE_PORT4);
12244 else
12245 SET_FLAGS(flags, MODE_PORT2);
12246
12247 if (CHIP_IS_E2(bp))
12248 SET_FLAGS(flags, MODE_E2);
12249 else if (CHIP_IS_E3(bp)) {
12250 SET_FLAGS(flags, MODE_E3);
12251 if (CHIP_REV(bp) == CHIP_REV_Ax)
12252 SET_FLAGS(flags, MODE_E3_A0);
12253 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12254 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12255 }
12256
12257 if (IS_MF(bp)) {
12258 SET_FLAGS(flags, MODE_MF);
12259 switch (bp->mf_mode) {
12260 case MULTI_FUNCTION_SD:
12261 SET_FLAGS(flags, MODE_MF_SD);
12262 break;
12263 case MULTI_FUNCTION_SI:
12264 SET_FLAGS(flags, MODE_MF_SI);
12265 break;
12266 case MULTI_FUNCTION_AFEX:
12267 SET_FLAGS(flags, MODE_MF_AFEX);
12268 break;
12269 }
12270 } else
12271 SET_FLAGS(flags, MODE_SF);
12272
12273 #if defined(__LITTLE_ENDIAN)
12274 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12275 #else /*(__BIG_ENDIAN)*/
12276 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12277 #endif
12278 INIT_MODE_FLAGS(bp) = flags;
12279 }
12280
12281 static int bnx2x_init_bp(struct bnx2x *bp)
12282 {
12283 int func;
12284 int rc;
12285
12286 mutex_init(&bp->port.phy_mutex);
12287 mutex_init(&bp->fw_mb_mutex);
12288 mutex_init(&bp->drv_info_mutex);
12289 sema_init(&bp->stats_lock, 1);
12290 bp->drv_info_mng_owner = false;
12291 INIT_LIST_HEAD(&bp->vlan_reg);
12292
12293 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12294 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12295 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12296 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12297 if (IS_PF(bp)) {
12298 rc = bnx2x_get_hwinfo(bp);
12299 if (rc)
12300 return rc;
12301 } else {
12302 eth_zero_addr(bp->dev->dev_addr);
12303 }
12304
12305 bnx2x_set_modes_bitmap(bp);
12306
12307 rc = bnx2x_alloc_mem_bp(bp);
12308 if (rc)
12309 return rc;
12310
12311 bnx2x_read_fwinfo(bp);
12312
12313 func = BP_FUNC(bp);
12314
12315 /* need to reset chip if undi was active */
12316 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12317 /* init fw_seq */
12318 bp->fw_seq =
12319 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12320 DRV_MSG_SEQ_NUMBER_MASK;
12321 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12322
12323 rc = bnx2x_prev_unload(bp);
12324 if (rc) {
12325 bnx2x_free_mem_bp(bp);
12326 return rc;
12327 }
12328 }
12329
12330 if (CHIP_REV_IS_FPGA(bp))
12331 dev_err(&bp->pdev->dev, "FPGA detected\n");
12332
12333 if (BP_NOMCP(bp) && (func == 0))
12334 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12335
12336 bp->disable_tpa = disable_tpa;
12337 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12338 /* Reduce memory usage in kdump environment by disabling TPA */
12339 bp->disable_tpa |= is_kdump_kernel();
12340
12341 /* Set TPA flags */
12342 if (bp->disable_tpa) {
12343 bp->dev->hw_features &= ~NETIF_F_LRO;
12344 bp->dev->features &= ~NETIF_F_LRO;
12345 }
12346
12347 if (CHIP_IS_E1(bp))
12348 bp->dropless_fc = 0;
12349 else
12350 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12351
12352 bp->mrrs = mrrs;
12353
12354 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12355 if (IS_VF(bp))
12356 bp->rx_ring_size = MAX_RX_AVAIL;
12357
12358 /* make sure that the numbers are in the right granularity */
12359 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12360 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12361
12362 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12363
12364 init_timer(&bp->timer);
12365 bp->timer.expires = jiffies + bp->current_interval;
12366 bp->timer.data = (unsigned long) bp;
12367 bp->timer.function = bnx2x_timer;
12368
12369 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12370 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12371 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12372 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12373 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12374 bnx2x_dcbx_init_params(bp);
12375 } else {
12376 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12377 }
12378
12379 if (CHIP_IS_E1x(bp))
12380 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12381 else
12382 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12383
12384 /* multiple tx priority */
12385 if (IS_VF(bp))
12386 bp->max_cos = 1;
12387 else if (CHIP_IS_E1x(bp))
12388 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12389 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12390 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12391 else if (CHIP_IS_E3B0(bp))
12392 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12393 else
12394 BNX2X_ERR("unknown chip %x revision %x\n",
12395 CHIP_NUM(bp), CHIP_REV(bp));
12396 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12397
12398 /* We need at least one default status block for slow-path events,
12399 * second status block for the L2 queue, and a third status block for
12400 * CNIC if supported.
12401 */
12402 if (IS_VF(bp))
12403 bp->min_msix_vec_cnt = 1;
12404 else if (CNIC_SUPPORT(bp))
12405 bp->min_msix_vec_cnt = 3;
12406 else /* PF w/o cnic */
12407 bp->min_msix_vec_cnt = 2;
12408 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12409
12410 bp->dump_preset_idx = 1;
12411
12412 if (CHIP_IS_E3B0(bp))
12413 bp->flags |= PTP_SUPPORTED;
12414
12415 return rc;
12416 }
12417
12418 /****************************************************************************
12419 * General service functions
12420 ****************************************************************************/
12421
12422 /*
12423 * net_device service functions
12424 */
12425
12426 /* called with rtnl_lock */
12427 static int bnx2x_open(struct net_device *dev)
12428 {
12429 struct bnx2x *bp = netdev_priv(dev);
12430 int rc;
12431
12432 bp->stats_init = true;
12433
12434 netif_carrier_off(dev);
12435
12436 bnx2x_set_power_state(bp, PCI_D0);
12437
12438 /* If parity had happen during the unload, then attentions
12439 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12440 * want the first function loaded on the current engine to
12441 * complete the recovery.
12442 * Parity recovery is only relevant for PF driver.
12443 */
12444 if (IS_PF(bp)) {
12445 int other_engine = BP_PATH(bp) ? 0 : 1;
12446 bool other_load_status, load_status;
12447 bool global = false;
12448
12449 other_load_status = bnx2x_get_load_status(bp, other_engine);
12450 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12451 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12452 bnx2x_chk_parity_attn(bp, &global, true)) {
12453 do {
12454 /* If there are attentions and they are in a
12455 * global blocks, set the GLOBAL_RESET bit
12456 * regardless whether it will be this function
12457 * that will complete the recovery or not.
12458 */
12459 if (global)
12460 bnx2x_set_reset_global(bp);
12461
12462 /* Only the first function on the current
12463 * engine should try to recover in open. In case
12464 * of attentions in global blocks only the first
12465 * in the chip should try to recover.
12466 */
12467 if ((!load_status &&
12468 (!global || !other_load_status)) &&
12469 bnx2x_trylock_leader_lock(bp) &&
12470 !bnx2x_leader_reset(bp)) {
12471 netdev_info(bp->dev,
12472 "Recovered in open\n");
12473 break;
12474 }
12475
12476 /* recovery has failed... */
12477 bnx2x_set_power_state(bp, PCI_D3hot);
12478 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12479
12480 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12481 "If you still see this message after a few retries then power cycle is required.\n");
12482
12483 return -EAGAIN;
12484 } while (0);
12485 }
12486 }
12487
12488 bp->recovery_state = BNX2X_RECOVERY_DONE;
12489 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12490 if (rc)
12491 return rc;
12492
12493 #ifdef CONFIG_BNX2X_VXLAN
12494 if (IS_PF(bp))
12495 vxlan_get_rx_port(dev);
12496 #endif
12497
12498 return 0;
12499 }
12500
12501 /* called with rtnl_lock */
12502 static int bnx2x_close(struct net_device *dev)
12503 {
12504 struct bnx2x *bp = netdev_priv(dev);
12505
12506 /* Unload the driver, release IRQs */
12507 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12508
12509 return 0;
12510 }
12511
12512 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12513 struct bnx2x_mcast_ramrod_params *p)
12514 {
12515 int mc_count = netdev_mc_count(bp->dev);
12516 struct bnx2x_mcast_list_elem *mc_mac =
12517 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12518 struct netdev_hw_addr *ha;
12519
12520 if (!mc_mac)
12521 return -ENOMEM;
12522
12523 INIT_LIST_HEAD(&p->mcast_list);
12524
12525 netdev_for_each_mc_addr(ha, bp->dev) {
12526 mc_mac->mac = bnx2x_mc_addr(ha);
12527 list_add_tail(&mc_mac->link, &p->mcast_list);
12528 mc_mac++;
12529 }
12530
12531 p->mcast_list_len = mc_count;
12532
12533 return 0;
12534 }
12535
12536 static void bnx2x_free_mcast_macs_list(
12537 struct bnx2x_mcast_ramrod_params *p)
12538 {
12539 struct bnx2x_mcast_list_elem *mc_mac =
12540 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12541 link);
12542
12543 WARN_ON(!mc_mac);
12544 kfree(mc_mac);
12545 }
12546
12547 /**
12548 * bnx2x_set_uc_list - configure a new unicast MACs list.
12549 *
12550 * @bp: driver handle
12551 *
12552 * We will use zero (0) as a MAC type for these MACs.
12553 */
12554 static int bnx2x_set_uc_list(struct bnx2x *bp)
12555 {
12556 int rc;
12557 struct net_device *dev = bp->dev;
12558 struct netdev_hw_addr *ha;
12559 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12560 unsigned long ramrod_flags = 0;
12561
12562 /* First schedule a cleanup up of old configuration */
12563 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12564 if (rc < 0) {
12565 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12566 return rc;
12567 }
12568
12569 netdev_for_each_uc_addr(ha, dev) {
12570 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12571 BNX2X_UC_LIST_MAC, &ramrod_flags);
12572 if (rc == -EEXIST) {
12573 DP(BNX2X_MSG_SP,
12574 "Failed to schedule ADD operations: %d\n", rc);
12575 /* do not treat adding same MAC as error */
12576 rc = 0;
12577
12578 } else if (rc < 0) {
12579
12580 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12581 rc);
12582 return rc;
12583 }
12584 }
12585
12586 /* Execute the pending commands */
12587 __set_bit(RAMROD_CONT, &ramrod_flags);
12588 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12589 BNX2X_UC_LIST_MAC, &ramrod_flags);
12590 }
12591
12592 static int bnx2x_set_mc_list(struct bnx2x *bp)
12593 {
12594 struct net_device *dev = bp->dev;
12595 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12596 int rc = 0;
12597
12598 rparam.mcast_obj = &bp->mcast_obj;
12599
12600 /* first, clear all configured multicast MACs */
12601 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12602 if (rc < 0) {
12603 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12604 return rc;
12605 }
12606
12607 /* then, configure a new MACs list */
12608 if (netdev_mc_count(dev)) {
12609 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12610 if (rc) {
12611 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12612 rc);
12613 return rc;
12614 }
12615
12616 /* Now add the new MACs */
12617 rc = bnx2x_config_mcast(bp, &rparam,
12618 BNX2X_MCAST_CMD_ADD);
12619 if (rc < 0)
12620 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12621 rc);
12622
12623 bnx2x_free_mcast_macs_list(&rparam);
12624 }
12625
12626 return rc;
12627 }
12628
12629 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12630 static void bnx2x_set_rx_mode(struct net_device *dev)
12631 {
12632 struct bnx2x *bp = netdev_priv(dev);
12633
12634 if (bp->state != BNX2X_STATE_OPEN) {
12635 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12636 return;
12637 } else {
12638 /* Schedule an SP task to handle rest of change */
12639 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12640 NETIF_MSG_IFUP);
12641 }
12642 }
12643
12644 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12645 {
12646 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12647
12648 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12649
12650 netif_addr_lock_bh(bp->dev);
12651
12652 if (bp->dev->flags & IFF_PROMISC) {
12653 rx_mode = BNX2X_RX_MODE_PROMISC;
12654 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12655 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12656 CHIP_IS_E1(bp))) {
12657 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12658 } else {
12659 if (IS_PF(bp)) {
12660 /* some multicasts */
12661 if (bnx2x_set_mc_list(bp) < 0)
12662 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12663
12664 /* release bh lock, as bnx2x_set_uc_list might sleep */
12665 netif_addr_unlock_bh(bp->dev);
12666 if (bnx2x_set_uc_list(bp) < 0)
12667 rx_mode = BNX2X_RX_MODE_PROMISC;
12668 netif_addr_lock_bh(bp->dev);
12669 } else {
12670 /* configuring mcast to a vf involves sleeping (when we
12671 * wait for the pf's response).
12672 */
12673 bnx2x_schedule_sp_rtnl(bp,
12674 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12675 }
12676 }
12677
12678 bp->rx_mode = rx_mode;
12679 /* handle ISCSI SD mode */
12680 if (IS_MF_ISCSI_ONLY(bp))
12681 bp->rx_mode = BNX2X_RX_MODE_NONE;
12682
12683 /* Schedule the rx_mode command */
12684 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12685 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12686 netif_addr_unlock_bh(bp->dev);
12687 return;
12688 }
12689
12690 if (IS_PF(bp)) {
12691 bnx2x_set_storm_rx_mode(bp);
12692 netif_addr_unlock_bh(bp->dev);
12693 } else {
12694 /* VF will need to request the PF to make this change, and so
12695 * the VF needs to release the bottom-half lock prior to the
12696 * request (as it will likely require sleep on the VF side)
12697 */
12698 netif_addr_unlock_bh(bp->dev);
12699 bnx2x_vfpf_storm_rx_mode(bp);
12700 }
12701 }
12702
12703 /* called with rtnl_lock */
12704 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12705 int devad, u16 addr)
12706 {
12707 struct bnx2x *bp = netdev_priv(netdev);
12708 u16 value;
12709 int rc;
12710
12711 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12712 prtad, devad, addr);
12713
12714 /* The HW expects different devad if CL22 is used */
12715 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12716
12717 bnx2x_acquire_phy_lock(bp);
12718 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12719 bnx2x_release_phy_lock(bp);
12720 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12721
12722 if (!rc)
12723 rc = value;
12724 return rc;
12725 }
12726
12727 /* called with rtnl_lock */
12728 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12729 u16 addr, u16 value)
12730 {
12731 struct bnx2x *bp = netdev_priv(netdev);
12732 int rc;
12733
12734 DP(NETIF_MSG_LINK,
12735 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12736 prtad, devad, addr, value);
12737
12738 /* The HW expects different devad if CL22 is used */
12739 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12740
12741 bnx2x_acquire_phy_lock(bp);
12742 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12743 bnx2x_release_phy_lock(bp);
12744 return rc;
12745 }
12746
12747 /* called with rtnl_lock */
12748 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12749 {
12750 struct bnx2x *bp = netdev_priv(dev);
12751 struct mii_ioctl_data *mdio = if_mii(ifr);
12752
12753 if (!netif_running(dev))
12754 return -EAGAIN;
12755
12756 switch (cmd) {
12757 case SIOCSHWTSTAMP:
12758 return bnx2x_hwtstamp_ioctl(bp, ifr);
12759 default:
12760 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12761 mdio->phy_id, mdio->reg_num, mdio->val_in);
12762 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12763 }
12764 }
12765
12766 #ifdef CONFIG_NET_POLL_CONTROLLER
12767 static void poll_bnx2x(struct net_device *dev)
12768 {
12769 struct bnx2x *bp = netdev_priv(dev);
12770 int i;
12771
12772 for_each_eth_queue(bp, i) {
12773 struct bnx2x_fastpath *fp = &bp->fp[i];
12774 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12775 }
12776 }
12777 #endif
12778
12779 static int bnx2x_validate_addr(struct net_device *dev)
12780 {
12781 struct bnx2x *bp = netdev_priv(dev);
12782
12783 /* query the bulletin board for mac address configured by the PF */
12784 if (IS_VF(bp))
12785 bnx2x_sample_bulletin(bp);
12786
12787 if (!is_valid_ether_addr(dev->dev_addr)) {
12788 BNX2X_ERR("Non-valid Ethernet address\n");
12789 return -EADDRNOTAVAIL;
12790 }
12791 return 0;
12792 }
12793
12794 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12795 struct netdev_phys_item_id *ppid)
12796 {
12797 struct bnx2x *bp = netdev_priv(netdev);
12798
12799 if (!(bp->flags & HAS_PHYS_PORT_ID))
12800 return -EOPNOTSUPP;
12801
12802 ppid->id_len = sizeof(bp->phys_port_id);
12803 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12804
12805 return 0;
12806 }
12807
12808 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12809 struct net_device *dev,
12810 netdev_features_t features)
12811 {
12812 features = vlan_features_check(skb, features);
12813 return vxlan_features_check(skb, features);
12814 }
12815
12816 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12817 {
12818 int rc;
12819
12820 if (IS_PF(bp)) {
12821 unsigned long ramrod_flags = 0;
12822
12823 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12824 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12825 add, &ramrod_flags);
12826 } else {
12827 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12828 }
12829
12830 return rc;
12831 }
12832
12833 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12834 {
12835 struct bnx2x_vlan_entry *vlan;
12836 int rc = 0;
12837
12838 if (!bp->vlan_cnt) {
12839 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12840 return 0;
12841 }
12842
12843 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12844 /* Prepare for cleanup in case of errors */
12845 if (rc) {
12846 vlan->hw = false;
12847 continue;
12848 }
12849
12850 if (!vlan->hw)
12851 continue;
12852
12853 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12854
12855 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12856 if (rc) {
12857 BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12858 vlan->hw = false;
12859 rc = -EINVAL;
12860 continue;
12861 }
12862 }
12863
12864 return rc;
12865 }
12866
12867 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12868 {
12869 struct bnx2x *bp = netdev_priv(dev);
12870 struct bnx2x_vlan_entry *vlan;
12871 bool hw = false;
12872 int rc = 0;
12873
12874 if (!netif_running(bp->dev)) {
12875 DP(NETIF_MSG_IFUP,
12876 "Ignoring VLAN configuration the interface is down\n");
12877 return -EFAULT;
12878 }
12879
12880 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12881
12882 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12883 if (!vlan)
12884 return -ENOMEM;
12885
12886 bp->vlan_cnt++;
12887 if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12888 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12889 bp->accept_any_vlan = true;
12890 if (IS_PF(bp))
12891 bnx2x_set_rx_mode_inner(bp);
12892 else
12893 bnx2x_vfpf_storm_rx_mode(bp);
12894 } else if (bp->vlan_cnt <= bp->vlan_credit) {
12895 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12896 hw = true;
12897 }
12898
12899 vlan->vid = vid;
12900 vlan->hw = hw;
12901
12902 if (!rc) {
12903 list_add(&vlan->link, &bp->vlan_reg);
12904 } else {
12905 bp->vlan_cnt--;
12906 kfree(vlan);
12907 }
12908
12909 DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12910
12911 return rc;
12912 }
12913
12914 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12915 {
12916 struct bnx2x *bp = netdev_priv(dev);
12917 struct bnx2x_vlan_entry *vlan;
12918 int rc = 0;
12919
12920 if (!netif_running(bp->dev)) {
12921 DP(NETIF_MSG_IFUP,
12922 "Ignoring VLAN configuration the interface is down\n");
12923 return -EFAULT;
12924 }
12925
12926 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12927
12928 if (!bp->vlan_cnt) {
12929 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12930 return -EINVAL;
12931 }
12932
12933 list_for_each_entry(vlan, &bp->vlan_reg, link)
12934 if (vlan->vid == vid)
12935 break;
12936
12937 if (vlan->vid != vid) {
12938 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
12939 return -EINVAL;
12940 }
12941
12942 if (vlan->hw)
12943 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
12944
12945 list_del(&vlan->link);
12946 kfree(vlan);
12947
12948 bp->vlan_cnt--;
12949
12950 if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
12951 /* Configure all non-configured entries */
12952 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12953 if (vlan->hw)
12954 continue;
12955
12956 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12957 if (rc) {
12958 BNX2X_ERR("Unable to config VLAN %d\n",
12959 vlan->vid);
12960 continue;
12961 }
12962 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
12963 vlan->vid);
12964 vlan->hw = true;
12965 }
12966 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
12967 bp->accept_any_vlan = false;
12968 if (IS_PF(bp))
12969 bnx2x_set_rx_mode_inner(bp);
12970 else
12971 bnx2x_vfpf_storm_rx_mode(bp);
12972 }
12973
12974 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
12975
12976 return rc;
12977 }
12978
12979 static const struct net_device_ops bnx2x_netdev_ops = {
12980 .ndo_open = bnx2x_open,
12981 .ndo_stop = bnx2x_close,
12982 .ndo_start_xmit = bnx2x_start_xmit,
12983 .ndo_select_queue = bnx2x_select_queue,
12984 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12985 .ndo_set_mac_address = bnx2x_change_mac_addr,
12986 .ndo_validate_addr = bnx2x_validate_addr,
12987 .ndo_do_ioctl = bnx2x_ioctl,
12988 .ndo_change_mtu = bnx2x_change_mtu,
12989 .ndo_fix_features = bnx2x_fix_features,
12990 .ndo_set_features = bnx2x_set_features,
12991 .ndo_tx_timeout = bnx2x_tx_timeout,
12992 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
12993 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
12994 #ifdef CONFIG_NET_POLL_CONTROLLER
12995 .ndo_poll_controller = poll_bnx2x,
12996 #endif
12997 .ndo_setup_tc = bnx2x_setup_tc,
12998 #ifdef CONFIG_BNX2X_SRIOV
12999 .ndo_set_vf_mac = bnx2x_set_vf_mac,
13000 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
13001 .ndo_get_vf_config = bnx2x_get_vf_config,
13002 #endif
13003 #ifdef NETDEV_FCOE_WWNN
13004 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
13005 #endif
13006
13007 #ifdef CONFIG_NET_RX_BUSY_POLL
13008 .ndo_busy_poll = bnx2x_low_latency_recv,
13009 #endif
13010 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
13011 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
13012 .ndo_features_check = bnx2x_features_check,
13013 #ifdef CONFIG_BNX2X_VXLAN
13014 .ndo_add_vxlan_port = bnx2x_add_vxlan_port,
13015 .ndo_del_vxlan_port = bnx2x_del_vxlan_port,
13016 #endif
13017 };
13018
13019 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13020 {
13021 struct device *dev = &bp->pdev->dev;
13022
13023 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13024 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13025 dev_err(dev, "System does not support DMA, aborting\n");
13026 return -EIO;
13027 }
13028
13029 return 0;
13030 }
13031
13032 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13033 {
13034 if (bp->flags & AER_ENABLED) {
13035 pci_disable_pcie_error_reporting(bp->pdev);
13036 bp->flags &= ~AER_ENABLED;
13037 }
13038 }
13039
13040 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13041 struct net_device *dev, unsigned long board_type)
13042 {
13043 int rc;
13044 u32 pci_cfg_dword;
13045 bool chip_is_e1x = (board_type == BCM57710 ||
13046 board_type == BCM57711 ||
13047 board_type == BCM57711E);
13048
13049 SET_NETDEV_DEV(dev, &pdev->dev);
13050
13051 bp->dev = dev;
13052 bp->pdev = pdev;
13053
13054 rc = pci_enable_device(pdev);
13055 if (rc) {
13056 dev_err(&bp->pdev->dev,
13057 "Cannot enable PCI device, aborting\n");
13058 goto err_out;
13059 }
13060
13061 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13062 dev_err(&bp->pdev->dev,
13063 "Cannot find PCI device base address, aborting\n");
13064 rc = -ENODEV;
13065 goto err_out_disable;
13066 }
13067
13068 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13069 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13070 rc = -ENODEV;
13071 goto err_out_disable;
13072 }
13073
13074 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13075 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13076 PCICFG_REVESION_ID_ERROR_VAL) {
13077 pr_err("PCI device error, probably due to fan failure, aborting\n");
13078 rc = -ENODEV;
13079 goto err_out_disable;
13080 }
13081
13082 if (atomic_read(&pdev->enable_cnt) == 1) {
13083 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13084 if (rc) {
13085 dev_err(&bp->pdev->dev,
13086 "Cannot obtain PCI resources, aborting\n");
13087 goto err_out_disable;
13088 }
13089
13090 pci_set_master(pdev);
13091 pci_save_state(pdev);
13092 }
13093
13094 if (IS_PF(bp)) {
13095 if (!pdev->pm_cap) {
13096 dev_err(&bp->pdev->dev,
13097 "Cannot find power management capability, aborting\n");
13098 rc = -EIO;
13099 goto err_out_release;
13100 }
13101 }
13102
13103 if (!pci_is_pcie(pdev)) {
13104 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13105 rc = -EIO;
13106 goto err_out_release;
13107 }
13108
13109 rc = bnx2x_set_coherency_mask(bp);
13110 if (rc)
13111 goto err_out_release;
13112
13113 dev->mem_start = pci_resource_start(pdev, 0);
13114 dev->base_addr = dev->mem_start;
13115 dev->mem_end = pci_resource_end(pdev, 0);
13116
13117 dev->irq = pdev->irq;
13118
13119 bp->regview = pci_ioremap_bar(pdev, 0);
13120 if (!bp->regview) {
13121 dev_err(&bp->pdev->dev,
13122 "Cannot map register space, aborting\n");
13123 rc = -ENOMEM;
13124 goto err_out_release;
13125 }
13126
13127 /* In E1/E1H use pci device function given by kernel.
13128 * In E2/E3 read physical function from ME register since these chips
13129 * support Physical Device Assignment where kernel BDF maybe arbitrary
13130 * (depending on hypervisor).
13131 */
13132 if (chip_is_e1x) {
13133 bp->pf_num = PCI_FUNC(pdev->devfn);
13134 } else {
13135 /* chip is E2/3*/
13136 pci_read_config_dword(bp->pdev,
13137 PCICFG_ME_REGISTER, &pci_cfg_dword);
13138 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13139 ME_REG_ABS_PF_NUM_SHIFT);
13140 }
13141 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13142
13143 /* clean indirect addresses */
13144 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13145 PCICFG_VENDOR_ID_OFFSET);
13146
13147 /* Set PCIe reset type to fundamental for EEH recovery */
13148 pdev->needs_freset = 1;
13149
13150 /* AER (Advanced Error reporting) configuration */
13151 rc = pci_enable_pcie_error_reporting(pdev);
13152 if (!rc)
13153 bp->flags |= AER_ENABLED;
13154 else
13155 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13156
13157 /*
13158 * Clean the following indirect addresses for all functions since it
13159 * is not used by the driver.
13160 */
13161 if (IS_PF(bp)) {
13162 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13163 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13164 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13165 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13166
13167 if (chip_is_e1x) {
13168 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13169 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13170 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13171 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13172 }
13173
13174 /* Enable internal target-read (in case we are probed after PF
13175 * FLR). Must be done prior to any BAR read access. Only for
13176 * 57712 and up
13177 */
13178 if (!chip_is_e1x)
13179 REG_WR(bp,
13180 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13181 }
13182
13183 dev->watchdog_timeo = TX_TIMEOUT;
13184
13185 dev->netdev_ops = &bnx2x_netdev_ops;
13186 bnx2x_set_ethtool_ops(bp, dev);
13187
13188 dev->priv_flags |= IFF_UNICAST_FLT;
13189
13190 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13191 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13192 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13193 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13194 if (!chip_is_e1x) {
13195 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
13196 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
13197 dev->hw_enc_features =
13198 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13199 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13200 NETIF_F_GSO_IPIP |
13201 NETIF_F_GSO_SIT |
13202 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
13203 }
13204
13205 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13206 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13207
13208 /* VF with OLD Hypervisor or old PF do not support filtering */
13209 if (IS_PF(bp)) {
13210 if (chip_is_e1x)
13211 bp->accept_any_vlan = true;
13212 else
13213 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13214 #ifdef CONFIG_BNX2X_SRIOV
13215 } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13216 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13217 #endif
13218 }
13219
13220 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13221 dev->features |= NETIF_F_HIGHDMA;
13222
13223 /* Add Loopback capability to the device */
13224 dev->hw_features |= NETIF_F_LOOPBACK;
13225
13226 #ifdef BCM_DCBNL
13227 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13228 #endif
13229
13230 /* get_port_hwinfo() will set prtad and mmds properly */
13231 bp->mdio.prtad = MDIO_PRTAD_NONE;
13232 bp->mdio.mmds = 0;
13233 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13234 bp->mdio.dev = dev;
13235 bp->mdio.mdio_read = bnx2x_mdio_read;
13236 bp->mdio.mdio_write = bnx2x_mdio_write;
13237
13238 return 0;
13239
13240 err_out_release:
13241 if (atomic_read(&pdev->enable_cnt) == 1)
13242 pci_release_regions(pdev);
13243
13244 err_out_disable:
13245 pci_disable_device(pdev);
13246
13247 err_out:
13248 return rc;
13249 }
13250
13251 static int bnx2x_check_firmware(struct bnx2x *bp)
13252 {
13253 const struct firmware *firmware = bp->firmware;
13254 struct bnx2x_fw_file_hdr *fw_hdr;
13255 struct bnx2x_fw_file_section *sections;
13256 u32 offset, len, num_ops;
13257 __be16 *ops_offsets;
13258 int i;
13259 const u8 *fw_ver;
13260
13261 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13262 BNX2X_ERR("Wrong FW size\n");
13263 return -EINVAL;
13264 }
13265
13266 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13267 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13268
13269 /* Make sure none of the offsets and sizes make us read beyond
13270 * the end of the firmware data */
13271 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13272 offset = be32_to_cpu(sections[i].offset);
13273 len = be32_to_cpu(sections[i].len);
13274 if (offset + len > firmware->size) {
13275 BNX2X_ERR("Section %d length is out of bounds\n", i);
13276 return -EINVAL;
13277 }
13278 }
13279
13280 /* Likewise for the init_ops offsets */
13281 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
13282 ops_offsets = (__force __be16 *)(firmware->data + offset);
13283 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13284
13285 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13286 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
13287 BNX2X_ERR("Section offset %d is out of bounds\n", i);
13288 return -EINVAL;
13289 }
13290 }
13291
13292 /* Check FW version */
13293 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13294 fw_ver = firmware->data + offset;
13295 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13296 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13297 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13298 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
13299 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13300 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13301 BCM_5710_FW_MAJOR_VERSION,
13302 BCM_5710_FW_MINOR_VERSION,
13303 BCM_5710_FW_REVISION_VERSION,
13304 BCM_5710_FW_ENGINEERING_VERSION);
13305 return -EINVAL;
13306 }
13307
13308 return 0;
13309 }
13310
13311 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13312 {
13313 const __be32 *source = (const __be32 *)_source;
13314 u32 *target = (u32 *)_target;
13315 u32 i;
13316
13317 for (i = 0; i < n/4; i++)
13318 target[i] = be32_to_cpu(source[i]);
13319 }
13320
13321 /*
13322 Ops array is stored in the following format:
13323 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13324 */
13325 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13326 {
13327 const __be32 *source = (const __be32 *)_source;
13328 struct raw_op *target = (struct raw_op *)_target;
13329 u32 i, j, tmp;
13330
13331 for (i = 0, j = 0; i < n/8; i++, j += 2) {
13332 tmp = be32_to_cpu(source[j]);
13333 target[i].op = (tmp >> 24) & 0xff;
13334 target[i].offset = tmp & 0xffffff;
13335 target[i].raw_data = be32_to_cpu(source[j + 1]);
13336 }
13337 }
13338
13339 /* IRO array is stored in the following format:
13340 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13341 */
13342 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13343 {
13344 const __be32 *source = (const __be32 *)_source;
13345 struct iro *target = (struct iro *)_target;
13346 u32 i, j, tmp;
13347
13348 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13349 target[i].base = be32_to_cpu(source[j]);
13350 j++;
13351 tmp = be32_to_cpu(source[j]);
13352 target[i].m1 = (tmp >> 16) & 0xffff;
13353 target[i].m2 = tmp & 0xffff;
13354 j++;
13355 tmp = be32_to_cpu(source[j]);
13356 target[i].m3 = (tmp >> 16) & 0xffff;
13357 target[i].size = tmp & 0xffff;
13358 j++;
13359 }
13360 }
13361
13362 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13363 {
13364 const __be16 *source = (const __be16 *)_source;
13365 u16 *target = (u16 *)_target;
13366 u32 i;
13367
13368 for (i = 0; i < n/2; i++)
13369 target[i] = be16_to_cpu(source[i]);
13370 }
13371
13372 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13373 do { \
13374 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13375 bp->arr = kmalloc(len, GFP_KERNEL); \
13376 if (!bp->arr) \
13377 goto lbl; \
13378 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13379 (u8 *)bp->arr, len); \
13380 } while (0)
13381
13382 static int bnx2x_init_firmware(struct bnx2x *bp)
13383 {
13384 const char *fw_file_name;
13385 struct bnx2x_fw_file_hdr *fw_hdr;
13386 int rc;
13387
13388 if (bp->firmware)
13389 return 0;
13390
13391 if (CHIP_IS_E1(bp))
13392 fw_file_name = FW_FILE_NAME_E1;
13393 else if (CHIP_IS_E1H(bp))
13394 fw_file_name = FW_FILE_NAME_E1H;
13395 else if (!CHIP_IS_E1x(bp))
13396 fw_file_name = FW_FILE_NAME_E2;
13397 else {
13398 BNX2X_ERR("Unsupported chip revision\n");
13399 return -EINVAL;
13400 }
13401 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13402
13403 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13404 if (rc) {
13405 BNX2X_ERR("Can't load firmware file %s\n",
13406 fw_file_name);
13407 goto request_firmware_exit;
13408 }
13409
13410 rc = bnx2x_check_firmware(bp);
13411 if (rc) {
13412 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13413 goto request_firmware_exit;
13414 }
13415
13416 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13417
13418 /* Initialize the pointers to the init arrays */
13419 /* Blob */
13420 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13421
13422 /* Opcodes */
13423 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13424
13425 /* Offsets */
13426 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13427 be16_to_cpu_n);
13428
13429 /* STORMs firmware */
13430 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13431 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13432 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13433 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13434 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13435 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13436 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13437 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13438 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13439 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13440 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13441 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13442 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13443 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13444 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13445 be32_to_cpu(fw_hdr->csem_pram_data.offset);
13446 /* IRO */
13447 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13448
13449 return 0;
13450
13451 iro_alloc_err:
13452 kfree(bp->init_ops_offsets);
13453 init_offsets_alloc_err:
13454 kfree(bp->init_ops);
13455 init_ops_alloc_err:
13456 kfree(bp->init_data);
13457 request_firmware_exit:
13458 release_firmware(bp->firmware);
13459 bp->firmware = NULL;
13460
13461 return rc;
13462 }
13463
13464 static void bnx2x_release_firmware(struct bnx2x *bp)
13465 {
13466 kfree(bp->init_ops_offsets);
13467 kfree(bp->init_ops);
13468 kfree(bp->init_data);
13469 release_firmware(bp->firmware);
13470 bp->firmware = NULL;
13471 }
13472
13473 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13474 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13475 .init_hw_cmn = bnx2x_init_hw_common,
13476 .init_hw_port = bnx2x_init_hw_port,
13477 .init_hw_func = bnx2x_init_hw_func,
13478
13479 .reset_hw_cmn = bnx2x_reset_common,
13480 .reset_hw_port = bnx2x_reset_port,
13481 .reset_hw_func = bnx2x_reset_func,
13482
13483 .gunzip_init = bnx2x_gunzip_init,
13484 .gunzip_end = bnx2x_gunzip_end,
13485
13486 .init_fw = bnx2x_init_firmware,
13487 .release_fw = bnx2x_release_firmware,
13488 };
13489
13490 void bnx2x__init_func_obj(struct bnx2x *bp)
13491 {
13492 /* Prepare DMAE related driver resources */
13493 bnx2x_setup_dmae(bp);
13494
13495 bnx2x_init_func_obj(bp, &bp->func_obj,
13496 bnx2x_sp(bp, func_rdata),
13497 bnx2x_sp_mapping(bp, func_rdata),
13498 bnx2x_sp(bp, func_afex_rdata),
13499 bnx2x_sp_mapping(bp, func_afex_rdata),
13500 &bnx2x_func_sp_drv);
13501 }
13502
13503 /* must be called after sriov-enable */
13504 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13505 {
13506 int cid_count = BNX2X_L2_MAX_CID(bp);
13507
13508 if (IS_SRIOV(bp))
13509 cid_count += BNX2X_VF_CIDS;
13510
13511 if (CNIC_SUPPORT(bp))
13512 cid_count += CNIC_CID_MAX;
13513
13514 return roundup(cid_count, QM_CID_ROUND);
13515 }
13516
13517 /**
13518 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13519 *
13520 * @dev: pci device
13521 *
13522 */
13523 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13524 {
13525 int index;
13526 u16 control = 0;
13527
13528 /*
13529 * If MSI-X is not supported - return number of SBs needed to support
13530 * one fast path queue: one FP queue + SB for CNIC
13531 */
13532 if (!pdev->msix_cap) {
13533 dev_info(&pdev->dev, "no msix capability found\n");
13534 return 1 + cnic_cnt;
13535 }
13536 dev_info(&pdev->dev, "msix capability found\n");
13537
13538 /*
13539 * The value in the PCI configuration space is the index of the last
13540 * entry, namely one less than the actual size of the table, which is
13541 * exactly what we want to return from this function: number of all SBs
13542 * without the default SB.
13543 * For VFs there is no default SB, then we return (index+1).
13544 */
13545 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13546
13547 index = control & PCI_MSIX_FLAGS_QSIZE;
13548
13549 return index;
13550 }
13551
13552 static int set_max_cos_est(int chip_id)
13553 {
13554 switch (chip_id) {
13555 case BCM57710:
13556 case BCM57711:
13557 case BCM57711E:
13558 return BNX2X_MULTI_TX_COS_E1X;
13559 case BCM57712:
13560 case BCM57712_MF:
13561 return BNX2X_MULTI_TX_COS_E2_E3A0;
13562 case BCM57800:
13563 case BCM57800_MF:
13564 case BCM57810:
13565 case BCM57810_MF:
13566 case BCM57840_4_10:
13567 case BCM57840_2_20:
13568 case BCM57840_O:
13569 case BCM57840_MFO:
13570 case BCM57840_MF:
13571 case BCM57811:
13572 case BCM57811_MF:
13573 return BNX2X_MULTI_TX_COS_E3B0;
13574 case BCM57712_VF:
13575 case BCM57800_VF:
13576 case BCM57810_VF:
13577 case BCM57840_VF:
13578 case BCM57811_VF:
13579 return 1;
13580 default:
13581 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13582 return -ENODEV;
13583 }
13584 }
13585
13586 static int set_is_vf(int chip_id)
13587 {
13588 switch (chip_id) {
13589 case BCM57712_VF:
13590 case BCM57800_VF:
13591 case BCM57810_VF:
13592 case BCM57840_VF:
13593 case BCM57811_VF:
13594 return true;
13595 default:
13596 return false;
13597 }
13598 }
13599
13600 /* nig_tsgen registers relative address */
13601 #define tsgen_ctrl 0x0
13602 #define tsgen_freecount 0x10
13603 #define tsgen_synctime_t0 0x20
13604 #define tsgen_offset_t0 0x28
13605 #define tsgen_drift_t0 0x30
13606 #define tsgen_synctime_t1 0x58
13607 #define tsgen_offset_t1 0x60
13608 #define tsgen_drift_t1 0x68
13609
13610 /* FW workaround for setting drift */
13611 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13612 int best_val, int best_period)
13613 {
13614 struct bnx2x_func_state_params func_params = {NULL};
13615 struct bnx2x_func_set_timesync_params *set_timesync_params =
13616 &func_params.params.set_timesync;
13617
13618 /* Prepare parameters for function state transitions */
13619 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13620 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13621
13622 func_params.f_obj = &bp->func_obj;
13623 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13624
13625 /* Function parameters */
13626 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13627 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13628 set_timesync_params->add_sub_drift_adjust_value =
13629 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13630 set_timesync_params->drift_adjust_value = best_val;
13631 set_timesync_params->drift_adjust_period = best_period;
13632
13633 return bnx2x_func_state_change(bp, &func_params);
13634 }
13635
13636 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13637 {
13638 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13639 int rc;
13640 int drift_dir = 1;
13641 int val, period, period1, period2, dif, dif1, dif2;
13642 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13643
13644 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13645
13646 if (!netif_running(bp->dev)) {
13647 DP(BNX2X_MSG_PTP,
13648 "PTP adjfreq called while the interface is down\n");
13649 return -EFAULT;
13650 }
13651
13652 if (ppb < 0) {
13653 ppb = -ppb;
13654 drift_dir = 0;
13655 }
13656
13657 if (ppb == 0) {
13658 best_val = 1;
13659 best_period = 0x1FFFFFF;
13660 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13661 best_val = 31;
13662 best_period = 1;
13663 } else {
13664 /* Changed not to allow val = 8, 16, 24 as these values
13665 * are not supported in workaround.
13666 */
13667 for (val = 0; val <= 31; val++) {
13668 if ((val & 0x7) == 0)
13669 continue;
13670 period1 = val * 1000000 / ppb;
13671 period2 = period1 + 1;
13672 if (period1 != 0)
13673 dif1 = ppb - (val * 1000000 / period1);
13674 else
13675 dif1 = BNX2X_MAX_PHC_DRIFT;
13676 if (dif1 < 0)
13677 dif1 = -dif1;
13678 dif2 = ppb - (val * 1000000 / period2);
13679 if (dif2 < 0)
13680 dif2 = -dif2;
13681 dif = (dif1 < dif2) ? dif1 : dif2;
13682 period = (dif1 < dif2) ? period1 : period2;
13683 if (dif < best_dif) {
13684 best_dif = dif;
13685 best_val = val;
13686 best_period = period;
13687 }
13688 }
13689 }
13690
13691 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13692 best_period);
13693 if (rc) {
13694 BNX2X_ERR("Failed to set drift\n");
13695 return -EFAULT;
13696 }
13697
13698 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13699 best_period);
13700
13701 return 0;
13702 }
13703
13704 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13705 {
13706 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13707
13708 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13709
13710 timecounter_adjtime(&bp->timecounter, delta);
13711
13712 return 0;
13713 }
13714
13715 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13716 {
13717 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13718 u64 ns;
13719
13720 ns = timecounter_read(&bp->timecounter);
13721
13722 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13723
13724 *ts = ns_to_timespec64(ns);
13725
13726 return 0;
13727 }
13728
13729 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13730 const struct timespec64 *ts)
13731 {
13732 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13733 u64 ns;
13734
13735 ns = timespec64_to_ns(ts);
13736
13737 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13738
13739 /* Re-init the timecounter */
13740 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13741
13742 return 0;
13743 }
13744
13745 /* Enable (or disable) ancillary features of the phc subsystem */
13746 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13747 struct ptp_clock_request *rq, int on)
13748 {
13749 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13750
13751 BNX2X_ERR("PHC ancillary features are not supported\n");
13752 return -ENOTSUPP;
13753 }
13754
13755 static void bnx2x_register_phc(struct bnx2x *bp)
13756 {
13757 /* Fill the ptp_clock_info struct and register PTP clock*/
13758 bp->ptp_clock_info.owner = THIS_MODULE;
13759 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13760 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13761 bp->ptp_clock_info.n_alarm = 0;
13762 bp->ptp_clock_info.n_ext_ts = 0;
13763 bp->ptp_clock_info.n_per_out = 0;
13764 bp->ptp_clock_info.pps = 0;
13765 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13766 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13767 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13768 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13769 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13770
13771 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13772 if (IS_ERR(bp->ptp_clock)) {
13773 bp->ptp_clock = NULL;
13774 BNX2X_ERR("PTP clock registeration failed\n");
13775 }
13776 }
13777
13778 static int bnx2x_init_one(struct pci_dev *pdev,
13779 const struct pci_device_id *ent)
13780 {
13781 struct net_device *dev = NULL;
13782 struct bnx2x *bp;
13783 enum pcie_link_width pcie_width;
13784 enum pci_bus_speed pcie_speed;
13785 int rc, max_non_def_sbs;
13786 int rx_count, tx_count, rss_count, doorbell_size;
13787 int max_cos_est;
13788 bool is_vf;
13789 int cnic_cnt;
13790
13791 /* Management FW 'remembers' living interfaces. Allow it some time
13792 * to forget previously living interfaces, allowing a proper re-load.
13793 */
13794 if (is_kdump_kernel()) {
13795 ktime_t now = ktime_get_boottime();
13796 ktime_t fw_ready_time = ktime_set(5, 0);
13797
13798 if (ktime_before(now, fw_ready_time))
13799 msleep(ktime_ms_delta(fw_ready_time, now));
13800 }
13801
13802 /* An estimated maximum supported CoS number according to the chip
13803 * version.
13804 * We will try to roughly estimate the maximum number of CoSes this chip
13805 * may support in order to minimize the memory allocated for Tx
13806 * netdev_queue's. This number will be accurately calculated during the
13807 * initialization of bp->max_cos based on the chip versions AND chip
13808 * revision in the bnx2x_init_bp().
13809 */
13810 max_cos_est = set_max_cos_est(ent->driver_data);
13811 if (max_cos_est < 0)
13812 return max_cos_est;
13813 is_vf = set_is_vf(ent->driver_data);
13814 cnic_cnt = is_vf ? 0 : 1;
13815
13816 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13817
13818 /* add another SB for VF as it has no default SB */
13819 max_non_def_sbs += is_vf ? 1 : 0;
13820
13821 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13822 rss_count = max_non_def_sbs - cnic_cnt;
13823
13824 if (rss_count < 1)
13825 return -EINVAL;
13826
13827 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13828 rx_count = rss_count + cnic_cnt;
13829
13830 /* Maximum number of netdev Tx queues:
13831 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13832 */
13833 tx_count = rss_count * max_cos_est + cnic_cnt;
13834
13835 /* dev zeroed in init_etherdev */
13836 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13837 if (!dev)
13838 return -ENOMEM;
13839
13840 bp = netdev_priv(dev);
13841
13842 bp->flags = 0;
13843 if (is_vf)
13844 bp->flags |= IS_VF_FLAG;
13845
13846 bp->igu_sb_cnt = max_non_def_sbs;
13847 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13848 bp->msg_enable = debug;
13849 bp->cnic_support = cnic_cnt;
13850 bp->cnic_probe = bnx2x_cnic_probe;
13851
13852 pci_set_drvdata(pdev, dev);
13853
13854 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13855 if (rc < 0) {
13856 free_netdev(dev);
13857 return rc;
13858 }
13859
13860 BNX2X_DEV_INFO("This is a %s function\n",
13861 IS_PF(bp) ? "physical" : "virtual");
13862 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13863 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13864 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13865 tx_count, rx_count);
13866
13867 rc = bnx2x_init_bp(bp);
13868 if (rc)
13869 goto init_one_exit;
13870
13871 /* Map doorbells here as we need the real value of bp->max_cos which
13872 * is initialized in bnx2x_init_bp() to determine the number of
13873 * l2 connections.
13874 */
13875 if (IS_VF(bp)) {
13876 bp->doorbells = bnx2x_vf_doorbells(bp);
13877 rc = bnx2x_vf_pci_alloc(bp);
13878 if (rc)
13879 goto init_one_exit;
13880 } else {
13881 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13882 if (doorbell_size > pci_resource_len(pdev, 2)) {
13883 dev_err(&bp->pdev->dev,
13884 "Cannot map doorbells, bar size too small, aborting\n");
13885 rc = -ENOMEM;
13886 goto init_one_exit;
13887 }
13888 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13889 doorbell_size);
13890 }
13891 if (!bp->doorbells) {
13892 dev_err(&bp->pdev->dev,
13893 "Cannot map doorbell space, aborting\n");
13894 rc = -ENOMEM;
13895 goto init_one_exit;
13896 }
13897
13898 if (IS_VF(bp)) {
13899 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13900 if (rc)
13901 goto init_one_exit;
13902 }
13903
13904 /* Enable SRIOV if capability found in configuration space */
13905 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13906 if (rc)
13907 goto init_one_exit;
13908
13909 /* calc qm_cid_count */
13910 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13911 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13912
13913 /* disable FCOE L2 queue for E1x*/
13914 if (CHIP_IS_E1x(bp))
13915 bp->flags |= NO_FCOE_FLAG;
13916
13917 /* Set bp->num_queues for MSI-X mode*/
13918 bnx2x_set_num_queues(bp);
13919
13920 /* Configure interrupt mode: try to enable MSI-X/MSI if
13921 * needed.
13922 */
13923 rc = bnx2x_set_int_mode(bp);
13924 if (rc) {
13925 dev_err(&pdev->dev, "Cannot set interrupts\n");
13926 goto init_one_exit;
13927 }
13928 BNX2X_DEV_INFO("set interrupts successfully\n");
13929
13930 /* register the net device */
13931 rc = register_netdev(dev);
13932 if (rc) {
13933 dev_err(&pdev->dev, "Cannot register net device\n");
13934 goto init_one_exit;
13935 }
13936 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13937
13938 if (!NO_FCOE(bp)) {
13939 /* Add storage MAC address */
13940 rtnl_lock();
13941 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13942 rtnl_unlock();
13943 }
13944 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13945 pcie_speed == PCI_SPEED_UNKNOWN ||
13946 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13947 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13948 else
13949 BNX2X_DEV_INFO(
13950 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13951 board_info[ent->driver_data].name,
13952 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13953 pcie_width,
13954 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13955 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13956 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13957 "Unknown",
13958 dev->base_addr, bp->pdev->irq, dev->dev_addr);
13959
13960 bnx2x_register_phc(bp);
13961
13962 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13963 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13964
13965 return 0;
13966
13967 init_one_exit:
13968 bnx2x_disable_pcie_error_reporting(bp);
13969
13970 if (bp->regview)
13971 iounmap(bp->regview);
13972
13973 if (IS_PF(bp) && bp->doorbells)
13974 iounmap(bp->doorbells);
13975
13976 free_netdev(dev);
13977
13978 if (atomic_read(&pdev->enable_cnt) == 1)
13979 pci_release_regions(pdev);
13980
13981 pci_disable_device(pdev);
13982
13983 return rc;
13984 }
13985
13986 static void __bnx2x_remove(struct pci_dev *pdev,
13987 struct net_device *dev,
13988 struct bnx2x *bp,
13989 bool remove_netdev)
13990 {
13991 if (bp->ptp_clock) {
13992 ptp_clock_unregister(bp->ptp_clock);
13993 bp->ptp_clock = NULL;
13994 }
13995
13996 /* Delete storage MAC address */
13997 if (!NO_FCOE(bp)) {
13998 rtnl_lock();
13999 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14000 rtnl_unlock();
14001 }
14002
14003 #ifdef BCM_DCBNL
14004 /* Delete app tlvs from dcbnl */
14005 bnx2x_dcbnl_update_applist(bp, true);
14006 #endif
14007
14008 if (IS_PF(bp) &&
14009 !BP_NOMCP(bp) &&
14010 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14011 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14012
14013 /* Close the interface - either directly or implicitly */
14014 if (remove_netdev) {
14015 unregister_netdev(dev);
14016 } else {
14017 rtnl_lock();
14018 dev_close(dev);
14019 rtnl_unlock();
14020 }
14021
14022 bnx2x_iov_remove_one(bp);
14023
14024 /* Power on: we can't let PCI layer write to us while we are in D3 */
14025 if (IS_PF(bp)) {
14026 bnx2x_set_power_state(bp, PCI_D0);
14027 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14028
14029 /* Set endianity registers to reset values in case next driver
14030 * boots in different endianty environment.
14031 */
14032 bnx2x_reset_endianity(bp);
14033 }
14034
14035 /* Disable MSI/MSI-X */
14036 bnx2x_disable_msi(bp);
14037
14038 /* Power off */
14039 if (IS_PF(bp))
14040 bnx2x_set_power_state(bp, PCI_D3hot);
14041
14042 /* Make sure RESET task is not scheduled before continuing */
14043 cancel_delayed_work_sync(&bp->sp_rtnl_task);
14044
14045 /* send message via vfpf channel to release the resources of this vf */
14046 if (IS_VF(bp))
14047 bnx2x_vfpf_release(bp);
14048
14049 /* Assumes no further PCIe PM changes will occur */
14050 if (system_state == SYSTEM_POWER_OFF) {
14051 pci_wake_from_d3(pdev, bp->wol);
14052 pci_set_power_state(pdev, PCI_D3hot);
14053 }
14054
14055 bnx2x_disable_pcie_error_reporting(bp);
14056 if (remove_netdev) {
14057 if (bp->regview)
14058 iounmap(bp->regview);
14059
14060 /* For vfs, doorbells are part of the regview and were unmapped
14061 * along with it. FW is only loaded by PF.
14062 */
14063 if (IS_PF(bp)) {
14064 if (bp->doorbells)
14065 iounmap(bp->doorbells);
14066
14067 bnx2x_release_firmware(bp);
14068 } else {
14069 bnx2x_vf_pci_dealloc(bp);
14070 }
14071 bnx2x_free_mem_bp(bp);
14072
14073 free_netdev(dev);
14074
14075 if (atomic_read(&pdev->enable_cnt) == 1)
14076 pci_release_regions(pdev);
14077
14078 pci_disable_device(pdev);
14079 }
14080 }
14081
14082 static void bnx2x_remove_one(struct pci_dev *pdev)
14083 {
14084 struct net_device *dev = pci_get_drvdata(pdev);
14085 struct bnx2x *bp;
14086
14087 if (!dev) {
14088 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14089 return;
14090 }
14091 bp = netdev_priv(dev);
14092
14093 __bnx2x_remove(pdev, dev, bp, true);
14094 }
14095
14096 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14097 {
14098 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14099
14100 bp->rx_mode = BNX2X_RX_MODE_NONE;
14101
14102 if (CNIC_LOADED(bp))
14103 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14104
14105 /* Stop Tx */
14106 bnx2x_tx_disable(bp);
14107 /* Delete all NAPI objects */
14108 bnx2x_del_all_napi(bp);
14109 if (CNIC_LOADED(bp))
14110 bnx2x_del_all_napi_cnic(bp);
14111 netdev_reset_tc(bp->dev);
14112
14113 del_timer_sync(&bp->timer);
14114 cancel_delayed_work_sync(&bp->sp_task);
14115 cancel_delayed_work_sync(&bp->period_task);
14116
14117 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14118 bp->stats_state = STATS_STATE_DISABLED;
14119 up(&bp->stats_lock);
14120 }
14121
14122 bnx2x_save_statistics(bp);
14123
14124 netif_carrier_off(bp->dev);
14125
14126 return 0;
14127 }
14128
14129 /**
14130 * bnx2x_io_error_detected - called when PCI error is detected
14131 * @pdev: Pointer to PCI device
14132 * @state: The current pci connection state
14133 *
14134 * This function is called after a PCI bus error affecting
14135 * this device has been detected.
14136 */
14137 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14138 pci_channel_state_t state)
14139 {
14140 struct net_device *dev = pci_get_drvdata(pdev);
14141 struct bnx2x *bp = netdev_priv(dev);
14142
14143 rtnl_lock();
14144
14145 BNX2X_ERR("IO error detected\n");
14146
14147 netif_device_detach(dev);
14148
14149 if (state == pci_channel_io_perm_failure) {
14150 rtnl_unlock();
14151 return PCI_ERS_RESULT_DISCONNECT;
14152 }
14153
14154 if (netif_running(dev))
14155 bnx2x_eeh_nic_unload(bp);
14156
14157 bnx2x_prev_path_mark_eeh(bp);
14158
14159 pci_disable_device(pdev);
14160
14161 rtnl_unlock();
14162
14163 /* Request a slot reset */
14164 return PCI_ERS_RESULT_NEED_RESET;
14165 }
14166
14167 /**
14168 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14169 * @pdev: Pointer to PCI device
14170 *
14171 * Restart the card from scratch, as if from a cold-boot.
14172 */
14173 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14174 {
14175 struct net_device *dev = pci_get_drvdata(pdev);
14176 struct bnx2x *bp = netdev_priv(dev);
14177 int i;
14178
14179 rtnl_lock();
14180 BNX2X_ERR("IO slot reset initializing...\n");
14181 if (pci_enable_device(pdev)) {
14182 dev_err(&pdev->dev,
14183 "Cannot re-enable PCI device after reset\n");
14184 rtnl_unlock();
14185 return PCI_ERS_RESULT_DISCONNECT;
14186 }
14187
14188 pci_set_master(pdev);
14189 pci_restore_state(pdev);
14190 pci_save_state(pdev);
14191
14192 if (netif_running(dev))
14193 bnx2x_set_power_state(bp, PCI_D0);
14194
14195 if (netif_running(dev)) {
14196 BNX2X_ERR("IO slot reset --> driver unload\n");
14197
14198 /* MCP should have been reset; Need to wait for validity */
14199 bnx2x_init_shmem(bp);
14200
14201 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14202 u32 v;
14203
14204 v = SHMEM2_RD(bp,
14205 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14206 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14207 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14208 }
14209 bnx2x_drain_tx_queues(bp);
14210 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14211 bnx2x_netif_stop(bp, 1);
14212 bnx2x_free_irq(bp);
14213
14214 /* Report UNLOAD_DONE to MCP */
14215 bnx2x_send_unload_done(bp, true);
14216
14217 bp->sp_state = 0;
14218 bp->port.pmf = 0;
14219
14220 bnx2x_prev_unload(bp);
14221
14222 /* We should have reseted the engine, so It's fair to
14223 * assume the FW will no longer write to the bnx2x driver.
14224 */
14225 bnx2x_squeeze_objects(bp);
14226 bnx2x_free_skbs(bp);
14227 for_each_rx_queue(bp, i)
14228 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14229 bnx2x_free_fp_mem(bp);
14230 bnx2x_free_mem(bp);
14231
14232 bp->state = BNX2X_STATE_CLOSED;
14233 }
14234
14235 rtnl_unlock();
14236
14237 /* If AER, perform cleanup of the PCIe registers */
14238 if (bp->flags & AER_ENABLED) {
14239 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14240 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14241 else
14242 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14243 }
14244
14245 return PCI_ERS_RESULT_RECOVERED;
14246 }
14247
14248 /**
14249 * bnx2x_io_resume - called when traffic can start flowing again
14250 * @pdev: Pointer to PCI device
14251 *
14252 * This callback is called when the error recovery driver tells us that
14253 * its OK to resume normal operation.
14254 */
14255 static void bnx2x_io_resume(struct pci_dev *pdev)
14256 {
14257 struct net_device *dev = pci_get_drvdata(pdev);
14258 struct bnx2x *bp = netdev_priv(dev);
14259
14260 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14261 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14262 return;
14263 }
14264
14265 rtnl_lock();
14266
14267 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14268 DRV_MSG_SEQ_NUMBER_MASK;
14269
14270 if (netif_running(dev))
14271 bnx2x_nic_load(bp, LOAD_NORMAL);
14272
14273 netif_device_attach(dev);
14274
14275 rtnl_unlock();
14276 }
14277
14278 static const struct pci_error_handlers bnx2x_err_handler = {
14279 .error_detected = bnx2x_io_error_detected,
14280 .slot_reset = bnx2x_io_slot_reset,
14281 .resume = bnx2x_io_resume,
14282 };
14283
14284 static void bnx2x_shutdown(struct pci_dev *pdev)
14285 {
14286 struct net_device *dev = pci_get_drvdata(pdev);
14287 struct bnx2x *bp;
14288
14289 if (!dev)
14290 return;
14291
14292 bp = netdev_priv(dev);
14293 if (!bp)
14294 return;
14295
14296 rtnl_lock();
14297 netif_device_detach(dev);
14298 rtnl_unlock();
14299
14300 /* Don't remove the netdevice, as there are scenarios which will cause
14301 * the kernel to hang, e.g., when trying to remove bnx2i while the
14302 * rootfs is mounted from SAN.
14303 */
14304 __bnx2x_remove(pdev, dev, bp, false);
14305 }
14306
14307 static struct pci_driver bnx2x_pci_driver = {
14308 .name = DRV_MODULE_NAME,
14309 .id_table = bnx2x_pci_tbl,
14310 .probe = bnx2x_init_one,
14311 .remove = bnx2x_remove_one,
14312 .suspend = bnx2x_suspend,
14313 .resume = bnx2x_resume,
14314 .err_handler = &bnx2x_err_handler,
14315 #ifdef CONFIG_BNX2X_SRIOV
14316 .sriov_configure = bnx2x_sriov_configure,
14317 #endif
14318 .shutdown = bnx2x_shutdown,
14319 };
14320
14321 static int __init bnx2x_init(void)
14322 {
14323 int ret;
14324
14325 pr_info("%s", version);
14326
14327 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14328 if (bnx2x_wq == NULL) {
14329 pr_err("Cannot create workqueue\n");
14330 return -ENOMEM;
14331 }
14332 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14333 if (!bnx2x_iov_wq) {
14334 pr_err("Cannot create iov workqueue\n");
14335 destroy_workqueue(bnx2x_wq);
14336 return -ENOMEM;
14337 }
14338
14339 ret = pci_register_driver(&bnx2x_pci_driver);
14340 if (ret) {
14341 pr_err("Cannot register driver\n");
14342 destroy_workqueue(bnx2x_wq);
14343 destroy_workqueue(bnx2x_iov_wq);
14344 }
14345 return ret;
14346 }
14347
14348 static void __exit bnx2x_cleanup(void)
14349 {
14350 struct list_head *pos, *q;
14351
14352 pci_unregister_driver(&bnx2x_pci_driver);
14353
14354 destroy_workqueue(bnx2x_wq);
14355 destroy_workqueue(bnx2x_iov_wq);
14356
14357 /* Free globally allocated resources */
14358 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14359 struct bnx2x_prev_path_list *tmp =
14360 list_entry(pos, struct bnx2x_prev_path_list, list);
14361 list_del(pos);
14362 kfree(tmp);
14363 }
14364 }
14365
14366 void bnx2x_notify_link_changed(struct bnx2x *bp)
14367 {
14368 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14369 }
14370
14371 module_init(bnx2x_init);
14372 module_exit(bnx2x_cleanup);
14373
14374 /**
14375 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14376 *
14377 * @bp: driver handle
14378 * @set: set or clear the CAM entry
14379 *
14380 * This function will wait until the ramrod completion returns.
14381 * Return 0 if success, -ENODEV if ramrod doesn't return.
14382 */
14383 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14384 {
14385 unsigned long ramrod_flags = 0;
14386
14387 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14388 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14389 &bp->iscsi_l2_mac_obj, true,
14390 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14391 }
14392
14393 /* count denotes the number of new completions we have seen */
14394 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14395 {
14396 struct eth_spe *spe;
14397 int cxt_index, cxt_offset;
14398
14399 #ifdef BNX2X_STOP_ON_ERROR
14400 if (unlikely(bp->panic))
14401 return;
14402 #endif
14403
14404 spin_lock_bh(&bp->spq_lock);
14405 BUG_ON(bp->cnic_spq_pending < count);
14406 bp->cnic_spq_pending -= count;
14407
14408 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14409 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14410 & SPE_HDR_CONN_TYPE) >>
14411 SPE_HDR_CONN_TYPE_SHIFT;
14412 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14413 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14414
14415 /* Set validation for iSCSI L2 client before sending SETUP
14416 * ramrod
14417 */
14418 if (type == ETH_CONNECTION_TYPE) {
14419 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14420 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14421 ILT_PAGE_CIDS;
14422 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14423 (cxt_index * ILT_PAGE_CIDS);
14424 bnx2x_set_ctx_validation(bp,
14425 &bp->context[cxt_index].
14426 vcxt[cxt_offset].eth,
14427 BNX2X_ISCSI_ETH_CID(bp));
14428 }
14429 }
14430
14431 /*
14432 * There may be not more than 8 L2, not more than 8 L5 SPEs
14433 * and in the air. We also check that number of outstanding
14434 * COMMON ramrods is not more than the EQ and SPQ can
14435 * accommodate.
14436 */
14437 if (type == ETH_CONNECTION_TYPE) {
14438 if (!atomic_read(&bp->cq_spq_left))
14439 break;
14440 else
14441 atomic_dec(&bp->cq_spq_left);
14442 } else if (type == NONE_CONNECTION_TYPE) {
14443 if (!atomic_read(&bp->eq_spq_left))
14444 break;
14445 else
14446 atomic_dec(&bp->eq_spq_left);
14447 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14448 (type == FCOE_CONNECTION_TYPE)) {
14449 if (bp->cnic_spq_pending >=
14450 bp->cnic_eth_dev.max_kwqe_pending)
14451 break;
14452 else
14453 bp->cnic_spq_pending++;
14454 } else {
14455 BNX2X_ERR("Unknown SPE type: %d\n", type);
14456 bnx2x_panic();
14457 break;
14458 }
14459
14460 spe = bnx2x_sp_get_next(bp);
14461 *spe = *bp->cnic_kwq_cons;
14462
14463 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14464 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14465
14466 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14467 bp->cnic_kwq_cons = bp->cnic_kwq;
14468 else
14469 bp->cnic_kwq_cons++;
14470 }
14471 bnx2x_sp_prod_update(bp);
14472 spin_unlock_bh(&bp->spq_lock);
14473 }
14474
14475 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14476 struct kwqe_16 *kwqes[], u32 count)
14477 {
14478 struct bnx2x *bp = netdev_priv(dev);
14479 int i;
14480
14481 #ifdef BNX2X_STOP_ON_ERROR
14482 if (unlikely(bp->panic)) {
14483 BNX2X_ERR("Can't post to SP queue while panic\n");
14484 return -EIO;
14485 }
14486 #endif
14487
14488 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14489 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14490 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14491 return -EAGAIN;
14492 }
14493
14494 spin_lock_bh(&bp->spq_lock);
14495
14496 for (i = 0; i < count; i++) {
14497 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14498
14499 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14500 break;
14501
14502 *bp->cnic_kwq_prod = *spe;
14503
14504 bp->cnic_kwq_pending++;
14505
14506 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14507 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14508 spe->data.update_data_addr.hi,
14509 spe->data.update_data_addr.lo,
14510 bp->cnic_kwq_pending);
14511
14512 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14513 bp->cnic_kwq_prod = bp->cnic_kwq;
14514 else
14515 bp->cnic_kwq_prod++;
14516 }
14517
14518 spin_unlock_bh(&bp->spq_lock);
14519
14520 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14521 bnx2x_cnic_sp_post(bp, 0);
14522
14523 return i;
14524 }
14525
14526 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14527 {
14528 struct cnic_ops *c_ops;
14529 int rc = 0;
14530
14531 mutex_lock(&bp->cnic_mutex);
14532 c_ops = rcu_dereference_protected(bp->cnic_ops,
14533 lockdep_is_held(&bp->cnic_mutex));
14534 if (c_ops)
14535 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14536 mutex_unlock(&bp->cnic_mutex);
14537
14538 return rc;
14539 }
14540
14541 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14542 {
14543 struct cnic_ops *c_ops;
14544 int rc = 0;
14545
14546 rcu_read_lock();
14547 c_ops = rcu_dereference(bp->cnic_ops);
14548 if (c_ops)
14549 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14550 rcu_read_unlock();
14551
14552 return rc;
14553 }
14554
14555 /*
14556 * for commands that have no data
14557 */
14558 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14559 {
14560 struct cnic_ctl_info ctl = {0};
14561
14562 ctl.cmd = cmd;
14563
14564 return bnx2x_cnic_ctl_send(bp, &ctl);
14565 }
14566
14567 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14568 {
14569 struct cnic_ctl_info ctl = {0};
14570
14571 /* first we tell CNIC and only then we count this as a completion */
14572 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14573 ctl.data.comp.cid = cid;
14574 ctl.data.comp.error = err;
14575
14576 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14577 bnx2x_cnic_sp_post(bp, 0);
14578 }
14579
14580 /* Called with netif_addr_lock_bh() taken.
14581 * Sets an rx_mode config for an iSCSI ETH client.
14582 * Doesn't block.
14583 * Completion should be checked outside.
14584 */
14585 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14586 {
14587 unsigned long accept_flags = 0, ramrod_flags = 0;
14588 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14589 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14590
14591 if (start) {
14592 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14593 * because it's the only way for UIO Queue to accept
14594 * multicasts (in non-promiscuous mode only one Queue per
14595 * function will receive multicast packets (leading in our
14596 * case).
14597 */
14598 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14599 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14600 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14601 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14602
14603 /* Clear STOP_PENDING bit if START is requested */
14604 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14605
14606 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14607 } else
14608 /* Clear START_PENDING bit if STOP is requested */
14609 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14610
14611 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14612 set_bit(sched_state, &bp->sp_state);
14613 else {
14614 __set_bit(RAMROD_RX, &ramrod_flags);
14615 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14616 ramrod_flags);
14617 }
14618 }
14619
14620 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14621 {
14622 struct bnx2x *bp = netdev_priv(dev);
14623 int rc = 0;
14624
14625 switch (ctl->cmd) {
14626 case DRV_CTL_CTXTBL_WR_CMD: {
14627 u32 index = ctl->data.io.offset;
14628 dma_addr_t addr = ctl->data.io.dma_addr;
14629
14630 bnx2x_ilt_wr(bp, index, addr);
14631 break;
14632 }
14633
14634 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14635 int count = ctl->data.credit.credit_count;
14636
14637 bnx2x_cnic_sp_post(bp, count);
14638 break;
14639 }
14640
14641 /* rtnl_lock is held. */
14642 case DRV_CTL_START_L2_CMD: {
14643 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14644 unsigned long sp_bits = 0;
14645
14646 /* Configure the iSCSI classification object */
14647 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14648 cp->iscsi_l2_client_id,
14649 cp->iscsi_l2_cid, BP_FUNC(bp),
14650 bnx2x_sp(bp, mac_rdata),
14651 bnx2x_sp_mapping(bp, mac_rdata),
14652 BNX2X_FILTER_MAC_PENDING,
14653 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14654 &bp->macs_pool);
14655
14656 /* Set iSCSI MAC address */
14657 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14658 if (rc)
14659 break;
14660
14661 mmiowb();
14662 barrier();
14663
14664 /* Start accepting on iSCSI L2 ring */
14665
14666 netif_addr_lock_bh(dev);
14667 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14668 netif_addr_unlock_bh(dev);
14669
14670 /* bits to wait on */
14671 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14672 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14673
14674 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14675 BNX2X_ERR("rx_mode completion timed out!\n");
14676
14677 break;
14678 }
14679
14680 /* rtnl_lock is held. */
14681 case DRV_CTL_STOP_L2_CMD: {
14682 unsigned long sp_bits = 0;
14683
14684 /* Stop accepting on iSCSI L2 ring */
14685 netif_addr_lock_bh(dev);
14686 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14687 netif_addr_unlock_bh(dev);
14688
14689 /* bits to wait on */
14690 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14691 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14692
14693 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14694 BNX2X_ERR("rx_mode completion timed out!\n");
14695
14696 mmiowb();
14697 barrier();
14698
14699 /* Unset iSCSI L2 MAC */
14700 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14701 BNX2X_ISCSI_ETH_MAC, true);
14702 break;
14703 }
14704 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14705 int count = ctl->data.credit.credit_count;
14706
14707 smp_mb__before_atomic();
14708 atomic_add(count, &bp->cq_spq_left);
14709 smp_mb__after_atomic();
14710 break;
14711 }
14712 case DRV_CTL_ULP_REGISTER_CMD: {
14713 int ulp_type = ctl->data.register_data.ulp_type;
14714
14715 if (CHIP_IS_E3(bp)) {
14716 int idx = BP_FW_MB_IDX(bp);
14717 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14718 int path = BP_PATH(bp);
14719 int port = BP_PORT(bp);
14720 int i;
14721 u32 scratch_offset;
14722 u32 *host_addr;
14723
14724 /* first write capability to shmem2 */
14725 if (ulp_type == CNIC_ULP_ISCSI)
14726 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14727 else if (ulp_type == CNIC_ULP_FCOE)
14728 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14729 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14730
14731 if ((ulp_type != CNIC_ULP_FCOE) ||
14732 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14733 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14734 break;
14735
14736 /* if reached here - should write fcoe capabilities */
14737 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14738 if (!scratch_offset)
14739 break;
14740 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14741 fcoe_features[path][port]);
14742 host_addr = (u32 *) &(ctl->data.register_data.
14743 fcoe_features);
14744 for (i = 0; i < sizeof(struct fcoe_capabilities);
14745 i += 4)
14746 REG_WR(bp, scratch_offset + i,
14747 *(host_addr + i/4));
14748 }
14749 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14750 break;
14751 }
14752
14753 case DRV_CTL_ULP_UNREGISTER_CMD: {
14754 int ulp_type = ctl->data.ulp_type;
14755
14756 if (CHIP_IS_E3(bp)) {
14757 int idx = BP_FW_MB_IDX(bp);
14758 u32 cap;
14759
14760 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14761 if (ulp_type == CNIC_ULP_ISCSI)
14762 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14763 else if (ulp_type == CNIC_ULP_FCOE)
14764 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14765 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14766 }
14767 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14768 break;
14769 }
14770
14771 default:
14772 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14773 rc = -EINVAL;
14774 }
14775
14776 /* For storage-only interfaces, change driver state */
14777 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14778 switch (ctl->drv_state) {
14779 case DRV_NOP:
14780 break;
14781 case DRV_ACTIVE:
14782 bnx2x_set_os_driver_state(bp,
14783 OS_DRIVER_STATE_ACTIVE);
14784 break;
14785 case DRV_INACTIVE:
14786 bnx2x_set_os_driver_state(bp,
14787 OS_DRIVER_STATE_DISABLED);
14788 break;
14789 case DRV_UNLOADED:
14790 bnx2x_set_os_driver_state(bp,
14791 OS_DRIVER_STATE_NOT_LOADED);
14792 break;
14793 default:
14794 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14795 }
14796 }
14797
14798 return rc;
14799 }
14800
14801 static int bnx2x_get_fc_npiv(struct net_device *dev,
14802 struct cnic_fc_npiv_tbl *cnic_tbl)
14803 {
14804 struct bnx2x *bp = netdev_priv(dev);
14805 struct bdn_fc_npiv_tbl *tbl = NULL;
14806 u32 offset, entries;
14807 int rc = -EINVAL;
14808 int i;
14809
14810 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14811 goto out;
14812
14813 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14814
14815 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14816 if (!tbl) {
14817 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14818 goto out;
14819 }
14820
14821 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14822 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14823
14824 /* Read the table contents from nvram */
14825 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14826 BNX2X_ERR("Failed to read FC-NPIV table\n");
14827 goto out;
14828 }
14829
14830 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14831 * the number of entries back to cpu endianness.
14832 */
14833 entries = tbl->fc_npiv_cfg.num_of_npiv;
14834 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14835 tbl->fc_npiv_cfg.num_of_npiv = entries;
14836
14837 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14838 DP(BNX2X_MSG_MCP,
14839 "No FC-NPIV table [valid, simply not present]\n");
14840 goto out;
14841 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14842 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14843 tbl->fc_npiv_cfg.num_of_npiv);
14844 goto out;
14845 } else {
14846 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14847 tbl->fc_npiv_cfg.num_of_npiv);
14848 }
14849
14850 /* Copy the data into cnic-provided struct */
14851 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14852 for (i = 0; i < cnic_tbl->count; i++) {
14853 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14854 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14855 }
14856
14857 rc = 0;
14858 out:
14859 kfree(tbl);
14860 return rc;
14861 }
14862
14863 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14864 {
14865 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14866
14867 if (bp->flags & USING_MSIX_FLAG) {
14868 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14869 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14870 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14871 } else {
14872 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14873 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14874 }
14875 if (!CHIP_IS_E1x(bp))
14876 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14877 else
14878 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14879
14880 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14881 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14882 cp->irq_arr[1].status_blk = bp->def_status_blk;
14883 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14884 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14885
14886 cp->num_irq = 2;
14887 }
14888
14889 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14890 {
14891 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14892
14893 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14894 bnx2x_cid_ilt_lines(bp);
14895 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14896 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14897 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14898
14899 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14900 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14901 cp->iscsi_l2_cid);
14902
14903 if (NO_ISCSI_OOO(bp))
14904 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14905 }
14906
14907 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14908 void *data)
14909 {
14910 struct bnx2x *bp = netdev_priv(dev);
14911 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14912 int rc;
14913
14914 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14915
14916 if (ops == NULL) {
14917 BNX2X_ERR("NULL ops received\n");
14918 return -EINVAL;
14919 }
14920
14921 if (!CNIC_SUPPORT(bp)) {
14922 BNX2X_ERR("Can't register CNIC when not supported\n");
14923 return -EOPNOTSUPP;
14924 }
14925
14926 if (!CNIC_LOADED(bp)) {
14927 rc = bnx2x_load_cnic(bp);
14928 if (rc) {
14929 BNX2X_ERR("CNIC-related load failed\n");
14930 return rc;
14931 }
14932 }
14933
14934 bp->cnic_enabled = true;
14935
14936 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14937 if (!bp->cnic_kwq)
14938 return -ENOMEM;
14939
14940 bp->cnic_kwq_cons = bp->cnic_kwq;
14941 bp->cnic_kwq_prod = bp->cnic_kwq;
14942 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14943
14944 bp->cnic_spq_pending = 0;
14945 bp->cnic_kwq_pending = 0;
14946
14947 bp->cnic_data = data;
14948
14949 cp->num_irq = 0;
14950 cp->drv_state |= CNIC_DRV_STATE_REGD;
14951 cp->iro_arr = bp->iro_arr;
14952
14953 bnx2x_setup_cnic_irq_info(bp);
14954
14955 rcu_assign_pointer(bp->cnic_ops, ops);
14956
14957 /* Schedule driver to read CNIC driver versions */
14958 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14959
14960 return 0;
14961 }
14962
14963 static int bnx2x_unregister_cnic(struct net_device *dev)
14964 {
14965 struct bnx2x *bp = netdev_priv(dev);
14966 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14967
14968 mutex_lock(&bp->cnic_mutex);
14969 cp->drv_state = 0;
14970 RCU_INIT_POINTER(bp->cnic_ops, NULL);
14971 mutex_unlock(&bp->cnic_mutex);
14972 synchronize_rcu();
14973 bp->cnic_enabled = false;
14974 kfree(bp->cnic_kwq);
14975 bp->cnic_kwq = NULL;
14976
14977 return 0;
14978 }
14979
14980 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14981 {
14982 struct bnx2x *bp = netdev_priv(dev);
14983 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14984
14985 /* If both iSCSI and FCoE are disabled - return NULL in
14986 * order to indicate CNIC that it should not try to work
14987 * with this device.
14988 */
14989 if (NO_ISCSI(bp) && NO_FCOE(bp))
14990 return NULL;
14991
14992 cp->drv_owner = THIS_MODULE;
14993 cp->chip_id = CHIP_ID(bp);
14994 cp->pdev = bp->pdev;
14995 cp->io_base = bp->regview;
14996 cp->io_base2 = bp->doorbells;
14997 cp->max_kwqe_pending = 8;
14998 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14999 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15000 bnx2x_cid_ilt_lines(bp);
15001 cp->ctx_tbl_len = CNIC_ILT_LINES;
15002 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15003 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15004 cp->drv_ctl = bnx2x_drv_ctl;
15005 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15006 cp->drv_register_cnic = bnx2x_register_cnic;
15007 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15008 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15009 cp->iscsi_l2_client_id =
15010 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15011 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15012
15013 if (NO_ISCSI_OOO(bp))
15014 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15015
15016 if (NO_ISCSI(bp))
15017 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15018
15019 if (NO_FCOE(bp))
15020 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15021
15022 BNX2X_DEV_INFO(
15023 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15024 cp->ctx_blk_size,
15025 cp->ctx_tbl_offset,
15026 cp->ctx_tbl_len,
15027 cp->starting_cid);
15028 return cp;
15029 }
15030
15031 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15032 {
15033 struct bnx2x *bp = fp->bp;
15034 u32 offset = BAR_USTRORM_INTMEM;
15035
15036 if (IS_VF(bp))
15037 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15038 else if (!CHIP_IS_E1x(bp))
15039 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15040 else
15041 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15042
15043 return offset;
15044 }
15045
15046 /* called only on E1H or E2.
15047 * When pretending to be PF, the pretend value is the function number 0...7
15048 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15049 * combination
15050 */
15051 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15052 {
15053 u32 pretend_reg;
15054
15055 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15056 return -1;
15057
15058 /* get my own pretend register */
15059 pretend_reg = bnx2x_get_pretend_reg(bp);
15060 REG_WR(bp, pretend_reg, pretend_func_val);
15061 REG_RD(bp, pretend_reg);
15062 return 0;
15063 }
15064
15065 static void bnx2x_ptp_task(struct work_struct *work)
15066 {
15067 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15068 int port = BP_PORT(bp);
15069 u32 val_seq;
15070 u64 timestamp, ns;
15071 struct skb_shared_hwtstamps shhwtstamps;
15072
15073 /* Read Tx timestamp registers */
15074 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15075 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15076 if (val_seq & 0x10000) {
15077 /* There is a valid timestamp value */
15078 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15079 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15080 timestamp <<= 32;
15081 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15082 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15083 /* Reset timestamp register to allow new timestamp */
15084 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15085 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15086 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15087
15088 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15089 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15090 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15091 dev_kfree_skb_any(bp->ptp_tx_skb);
15092 bp->ptp_tx_skb = NULL;
15093
15094 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15095 timestamp, ns);
15096 } else {
15097 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15098 /* Reschedule to keep checking for a valid timestamp value */
15099 schedule_work(&bp->ptp_task);
15100 }
15101 }
15102
15103 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15104 {
15105 int port = BP_PORT(bp);
15106 u64 timestamp, ns;
15107
15108 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15109 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15110 timestamp <<= 32;
15111 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15112 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15113
15114 /* Reset timestamp register to allow new timestamp */
15115 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15116 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15117
15118 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15119
15120 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15121
15122 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15123 timestamp, ns);
15124 }
15125
15126 /* Read the PHC */
15127 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15128 {
15129 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15130 int port = BP_PORT(bp);
15131 u32 wb_data[2];
15132 u64 phc_cycles;
15133
15134 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15135 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15136 phc_cycles = wb_data[1];
15137 phc_cycles = (phc_cycles << 32) + wb_data[0];
15138
15139 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15140
15141 return phc_cycles;
15142 }
15143
15144 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15145 {
15146 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15147 bp->cyclecounter.read = bnx2x_cyclecounter_read;
15148 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15149 bp->cyclecounter.shift = 1;
15150 bp->cyclecounter.mult = 1;
15151 }
15152
15153 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15154 {
15155 struct bnx2x_func_state_params func_params = {NULL};
15156 struct bnx2x_func_set_timesync_params *set_timesync_params =
15157 &func_params.params.set_timesync;
15158
15159 /* Prepare parameters for function state transitions */
15160 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15161 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15162
15163 func_params.f_obj = &bp->func_obj;
15164 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15165
15166 /* Function parameters */
15167 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15168 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15169
15170 return bnx2x_func_state_change(bp, &func_params);
15171 }
15172
15173 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15174 {
15175 struct bnx2x_queue_state_params q_params;
15176 int rc, i;
15177
15178 /* send queue update ramrod to enable PTP packets */
15179 memset(&q_params, 0, sizeof(q_params));
15180 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15181 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15182 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15183 &q_params.params.update.update_flags);
15184 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15185 &q_params.params.update.update_flags);
15186
15187 /* send the ramrod on all the queues of the PF */
15188 for_each_eth_queue(bp, i) {
15189 struct bnx2x_fastpath *fp = &bp->fp[i];
15190
15191 /* Set the appropriate Queue object */
15192 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15193
15194 /* Update the Queue state */
15195 rc = bnx2x_queue_state_change(bp, &q_params);
15196 if (rc) {
15197 BNX2X_ERR("Failed to enable PTP packets\n");
15198 return rc;
15199 }
15200 }
15201
15202 return 0;
15203 }
15204
15205 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15206 {
15207 int port = BP_PORT(bp);
15208 int rc;
15209
15210 if (!bp->hwtstamp_ioctl_called)
15211 return 0;
15212
15213 switch (bp->tx_type) {
15214 case HWTSTAMP_TX_ON:
15215 bp->flags |= TX_TIMESTAMPING_EN;
15216 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15217 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15218 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15219 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15220 break;
15221 case HWTSTAMP_TX_ONESTEP_SYNC:
15222 BNX2X_ERR("One-step timestamping is not supported\n");
15223 return -ERANGE;
15224 }
15225
15226 switch (bp->rx_filter) {
15227 case HWTSTAMP_FILTER_NONE:
15228 break;
15229 case HWTSTAMP_FILTER_ALL:
15230 case HWTSTAMP_FILTER_SOME:
15231 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15232 break;
15233 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15234 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15235 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15236 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15237 /* Initialize PTP detection for UDP/IPv4 events */
15238 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15239 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15240 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15241 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15242 break;
15243 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15244 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15245 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15246 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15247 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15249 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15251 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15252 break;
15253 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15254 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15255 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15256 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15257 /* Initialize PTP detection L2 events */
15258 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15259 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15260 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15261 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15262
15263 break;
15264 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15265 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15266 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15267 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15268 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15269 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15270 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15271 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15272 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15273 break;
15274 }
15275
15276 /* Indicate to FW that this PF expects recorded PTP packets */
15277 rc = bnx2x_enable_ptp_packets(bp);
15278 if (rc)
15279 return rc;
15280
15281 /* Enable sending PTP packets to host */
15282 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15283 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15284
15285 return 0;
15286 }
15287
15288 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15289 {
15290 struct hwtstamp_config config;
15291 int rc;
15292
15293 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15294
15295 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15296 return -EFAULT;
15297
15298 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15299 config.tx_type, config.rx_filter);
15300
15301 if (config.flags) {
15302 BNX2X_ERR("config.flags is reserved for future use\n");
15303 return -EINVAL;
15304 }
15305
15306 bp->hwtstamp_ioctl_called = 1;
15307 bp->tx_type = config.tx_type;
15308 bp->rx_filter = config.rx_filter;
15309
15310 rc = bnx2x_configure_ptp_filters(bp);
15311 if (rc)
15312 return rc;
15313
15314 config.rx_filter = bp->rx_filter;
15315
15316 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15317 -EFAULT : 0;
15318 }
15319
15320 /* Configures HW for PTP */
15321 static int bnx2x_configure_ptp(struct bnx2x *bp)
15322 {
15323 int rc, port = BP_PORT(bp);
15324 u32 wb_data[2];
15325
15326 /* Reset PTP event detection rules - will be configured in the IOCTL */
15327 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15328 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15329 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15330 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15331 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15332 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15333 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15334 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15335
15336 /* Disable PTP packets to host - will be configured in the IOCTL*/
15337 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15338 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15339
15340 /* Enable the PTP feature */
15341 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15342 NIG_REG_P0_PTP_EN, 0x3F);
15343
15344 /* Enable the free-running counter */
15345 wb_data[0] = 0;
15346 wb_data[1] = 0;
15347 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15348
15349 /* Reset drift register (offset register is not reset) */
15350 rc = bnx2x_send_reset_timesync_ramrod(bp);
15351 if (rc) {
15352 BNX2X_ERR("Failed to reset PHC drift register\n");
15353 return -EFAULT;
15354 }
15355
15356 /* Reset possibly old timestamps */
15357 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15358 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15359 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15360 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15361
15362 return 0;
15363 }
15364
15365 /* Called during load, to initialize PTP-related stuff */
15366 void bnx2x_init_ptp(struct bnx2x *bp)
15367 {
15368 int rc;
15369
15370 /* Configure PTP in HW */
15371 rc = bnx2x_configure_ptp(bp);
15372 if (rc) {
15373 BNX2X_ERR("Stopping PTP initialization\n");
15374 return;
15375 }
15376
15377 /* Init work queue for Tx timestamping */
15378 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15379
15380 /* Init cyclecounter and timecounter. This is done only in the first
15381 * load. If done in every load, PTP application will fail when doing
15382 * unload / load (e.g. MTU change) while it is running.
15383 */
15384 if (!bp->timecounter_init_done) {
15385 bnx2x_init_cyclecounter(bp);
15386 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15387 ktime_to_ns(ktime_get_real()));
15388 bp->timecounter_init_done = 1;
15389 }
15390
15391 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15392 }
Michael's Linux tree.