drivers/net/ethernet/cavium/thunder/thunder_bgx.h

   1 /*
   2  * Copyright (C) 2015 Cavium, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef THUNDER_BGX_H
  10 #define THUNDER_BGX_H
  11
  12 #define    MAX_BGX_THUNDER                      8 /* Max 4 nodes, 2 per node */
  13 #define    MAX_BGX_PER_CN88XX                   2
  14 #define    MAX_LMAC_PER_BGX                     4
  15 #define    MAX_BGX_CHANS_PER_LMAC               16
  16 #define    MAX_DMAC_PER_LMAC                    8
  17 #define    MAX_FRAME_SIZE                       9216
  18
  19 #define    MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE    2
  20
  21 #define    MAX_LMAC     (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX)
  22
  23 /* Registers */
  24 #define BGX_CMRX_CFG                    0x00
  25 #define  CMR_PKT_TX_EN                          BIT_ULL(13)
  26 #define  CMR_PKT_RX_EN                          BIT_ULL(14)
  27 #define  CMR_EN                                 BIT_ULL(15)
  28 #define BGX_CMR_GLOBAL_CFG              0x08
  29 #define  CMR_GLOBAL_CFG_FCS_STRIP               BIT_ULL(6)
  30 #define BGX_CMRX_RX_ID_MAP              0x60
  31 #define BGX_CMRX_RX_STAT0               0x70
  32 #define BGX_CMRX_RX_STAT1               0x78
  33 #define BGX_CMRX_RX_STAT2               0x80
  34 #define BGX_CMRX_RX_STAT3               0x88
  35 #define BGX_CMRX_RX_STAT4               0x90
  36 #define BGX_CMRX_RX_STAT5               0x98
  37 #define BGX_CMRX_RX_STAT6               0xA0
  38 #define BGX_CMRX_RX_STAT7               0xA8
  39 #define BGX_CMRX_RX_STAT8               0xB0
  40 #define BGX_CMRX_RX_STAT9               0xB8
  41 #define BGX_CMRX_RX_STAT10              0xC0
  42 #define BGX_CMRX_RX_BP_DROP             0xC8
  43 #define BGX_CMRX_RX_DMAC_CTL            0x0E8
  44 #define BGX_CMR_RX_DMACX_CAM            0x200
  45 #define  RX_DMACX_CAM_EN                        BIT_ULL(48)
  46 #define  RX_DMACX_CAM_LMACID(x)                 (x << 49)
  47 #define  RX_DMAC_COUNT                          32
  48 #define BGX_CMR_RX_STREERING            0x300
  49 #define  RX_TRAFFIC_STEER_RULE_COUNT            8
  50 #define BGX_CMR_CHAN_MSK_AND            0x450
  51 #define BGX_CMR_BIST_STATUS             0x460
  52 #define BGX_CMR_RX_LMACS                0x468
  53 #define BGX_CMRX_TX_STAT0               0x600
  54 #define BGX_CMRX_TX_STAT1               0x608
  55 #define BGX_CMRX_TX_STAT2               0x610
  56 #define BGX_CMRX_TX_STAT3               0x618
  57 #define BGX_CMRX_TX_STAT4               0x620
  58 #define BGX_CMRX_TX_STAT5               0x628
  59 #define BGX_CMRX_TX_STAT6               0x630
  60 #define BGX_CMRX_TX_STAT7               0x638
  61 #define BGX_CMRX_TX_STAT8               0x640
  62 #define BGX_CMRX_TX_STAT9               0x648
  63 #define BGX_CMRX_TX_STAT10              0x650
  64 #define BGX_CMRX_TX_STAT11              0x658
  65 #define BGX_CMRX_TX_STAT12              0x660
  66 #define BGX_CMRX_TX_STAT13              0x668
  67 #define BGX_CMRX_TX_STAT14              0x670
  68 #define BGX_CMRX_TX_STAT15              0x678
  69 #define BGX_CMRX_TX_STAT16              0x680
  70 #define BGX_CMRX_TX_STAT17              0x688
  71 #define BGX_CMR_TX_LMACS                0x1000
  72
  73 #define BGX_SPUX_CONTROL1               0x10000
  74 #define  SPU_CTL_LOW_POWER                      BIT_ULL(11)
  75 #define  SPU_CTL_LOOPBACK                       BIT_ULL(14)
  76 #define  SPU_CTL_RESET                          BIT_ULL(15)
  77 #define BGX_SPUX_STATUS1                0x10008
  78 #define  SPU_STATUS1_RCV_LNK                    BIT_ULL(2)
  79 #define BGX_SPUX_STATUS2                0x10020
  80 #define  SPU_STATUS2_RCVFLT                     BIT_ULL(10)
  81 #define BGX_SPUX_BX_STATUS              0x10028
  82 #define  SPU_BX_STATUS_RX_ALIGN                 BIT_ULL(12)
  83 #define BGX_SPUX_BR_STATUS1             0x10030
  84 #define  SPU_BR_STATUS_BLK_LOCK                 BIT_ULL(0)
  85 #define  SPU_BR_STATUS_RCV_LNK                  BIT_ULL(12)
  86 #define BGX_SPUX_BR_PMD_CRTL            0x10068
  87 #define  SPU_PMD_CRTL_TRAIN_EN                  BIT_ULL(1)
  88 #define BGX_SPUX_BR_PMD_LP_CUP          0x10078
  89 #define BGX_SPUX_BR_PMD_LD_CUP          0x10088
  90 #define BGX_SPUX_BR_PMD_LD_REP          0x10090
  91 #define BGX_SPUX_FEC_CONTROL            0x100A0
  92 #define  SPU_FEC_CTL_FEC_EN                     BIT_ULL(0)
  93 #define  SPU_FEC_CTL_ERR_EN                     BIT_ULL(1)
  94 #define BGX_SPUX_AN_CONTROL             0x100C8
  95 #define  SPU_AN_CTL_AN_EN                       BIT_ULL(12)
  96 #define  SPU_AN_CTL_XNP_EN                      BIT_ULL(13)
  97 #define BGX_SPUX_AN_ADV                 0x100D8
  98 #define BGX_SPUX_MISC_CONTROL           0x10218
  99 #define  SPU_MISC_CTL_INTLV_RDISP               BIT_ULL(10)
 100 #define  SPU_MISC_CTL_RX_DIS                    BIT_ULL(12)
 101 #define BGX_SPUX_INT                    0x10220 /* +(0..3) << 20 */
 102 #define BGX_SPUX_INT_W1S                0x10228
 103 #define BGX_SPUX_INT_ENA_W1C            0x10230
 104 #define BGX_SPUX_INT_ENA_W1S            0x10238
 105 #define BGX_SPU_DBG_CONTROL             0x10300
 106 #define  SPU_DBG_CTL_AN_ARB_LINK_CHK_EN         BIT_ULL(18)
 107 #define  SPU_DBG_CTL_AN_NONCE_MCT_DIS           BIT_ULL(29)
 108
 109 #define BGX_SMUX_RX_INT                 0x20000
 110 #define BGX_SMUX_RX_JABBER              0x20030
 111 #define BGX_SMUX_RX_CTL                 0x20048
 112 #define  SMU_RX_CTL_STATUS                      (3ull << 0)
 113 #define BGX_SMUX_TX_APPEND              0x20100
 114 #define  SMU_TX_APPEND_FCS_D                    BIT_ULL(2)
 115 #define BGX_SMUX_TX_MIN_PKT             0x20118
 116 #define BGX_SMUX_TX_INT                 0x20140
 117 #define BGX_SMUX_TX_CTL                 0x20178
 118 #define  SMU_TX_CTL_DIC_EN                      BIT_ULL(0)
 119 #define  SMU_TX_CTL_UNI_EN                      BIT_ULL(1)
 120 #define  SMU_TX_CTL_LNK_STATUS                  (3ull << 4)
 121 #define BGX_SMUX_TX_THRESH              0x20180
 122 #define BGX_SMUX_CTL                    0x20200
 123 #define  SMU_CTL_RX_IDLE                        BIT_ULL(0)
 124 #define  SMU_CTL_TX_IDLE                        BIT_ULL(1)
 125
 126 #define BGX_GMP_PCS_MRX_CTL             0x30000
 127 #define  PCS_MRX_CTL_RST_AN                     BIT_ULL(9)
 128 #define  PCS_MRX_CTL_PWR_DN                     BIT_ULL(11)
 129 #define  PCS_MRX_CTL_AN_EN                      BIT_ULL(12)
 130 #define  PCS_MRX_CTL_LOOPBACK1                  BIT_ULL(14)
 131 #define  PCS_MRX_CTL_RESET                      BIT_ULL(15)
 132 #define BGX_GMP_PCS_MRX_STATUS          0x30008
 133 #define  PCS_MRX_STATUS_AN_CPT                  BIT_ULL(5)
 134 #define BGX_GMP_PCS_ANX_AN_RESULTS      0x30020
 135 #define BGX_GMP_PCS_SGM_AN_ADV          0x30068
 136 #define BGX_GMP_PCS_MISCX_CTL           0x30078
 137 #define  PCS_MISC_CTL_GMX_ENO                   BIT_ULL(11)
 138 #define  PCS_MISC_CTL_SAMP_PT_MASK      0x7Full
 139 #define BGX_GMP_GMI_PRTX_CFG            0x38020
 140 #define  GMI_PORT_CFG_SPEED                     BIT_ULL(1)
 141 #define  GMI_PORT_CFG_DUPLEX                    BIT_ULL(2)
 142 #define  GMI_PORT_CFG_SLOT_TIME                 BIT_ULL(3)
 143 #define  GMI_PORT_CFG_SPEED_MSB                 BIT_ULL(8)
 144 #define BGX_GMP_GMI_RXX_JABBER          0x38038
 145 #define BGX_GMP_GMI_TXX_THRESH          0x38210
 146 #define BGX_GMP_GMI_TXX_APPEND          0x38218
 147 #define BGX_GMP_GMI_TXX_SLOT            0x38220
 148 #define BGX_GMP_GMI_TXX_BURST           0x38228
 149 #define BGX_GMP_GMI_TXX_MIN_PKT         0x38240
 150 #define BGX_GMP_GMI_TXX_SGMII_CTL       0x38300
 151
 152 #define BGX_MSIX_VEC_0_29_ADDR          0x400000 /* +(0..29) << 4 */
 153 #define BGX_MSIX_VEC_0_29_CTL           0x400008
 154 #define BGX_MSIX_PBA_0                  0x4F0000
 155
 156 /* MSI-X interrupts */
 157 #define BGX_MSIX_VECTORS        30
 158 #define BGX_LMAC_VEC_OFFSET     7
 159 #define BGX_MSIX_VEC_SHIFT      4
 160
 161 #define CMRX_INT                0
 162 #define SPUX_INT                1
 163 #define SMUX_RX_INT             2
 164 #define SMUX_TX_INT             3
 165 #define GMPX_PCS_INT            4
 166 #define GMPX_GMI_RX_INT         5
 167 #define GMPX_GMI_TX_INT         6
 168 #define CMR_MEM_INT             28
 169 #define SPU_MEM_INT             29
 170
 171 #define LMAC_INTR_LINK_UP       BIT(0)
 172 #define LMAC_INTR_LINK_DOWN     BIT(1)
 173
 174 /*  RX_DMAC_CTL configuration*/
 175 enum MCAST_MODE {
 176                 MCAST_MODE_REJECT,
 177                 MCAST_MODE_ACCEPT,
 178                 MCAST_MODE_CAM_FILTER,
 179                 RSVD
 180 };
 181
 182 #define BCAST_ACCEPT    1
 183 #define CAM_ACCEPT      1
 184
 185 void octeon_mdiobus_force_mod_depencency(void);
 186 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable);
 187 void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac);
 188 unsigned bgx_get_map(int node);
 189 int bgx_get_lmac_count(int node, int bgx);
 190 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid);
 191 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac);
 192 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status);
 193 void bgx_lmac_internal_loopback(int node, int bgx_idx,
 194                                 int lmac_idx, bool enable);
 195 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx);
 196 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx);
 197 #define BGX_RX_STATS_COUNT 11
 198 #define BGX_TX_STATS_COUNT 18
 199
 200 struct bgx_stats {
 201         u64 rx_stats[BGX_RX_STATS_COUNT];
 202         u64 tx_stats[BGX_TX_STATS_COUNT];
 203 };
 204
 205 enum LMAC_TYPE {
 206         BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */
 207         BGX_MODE_XAUI = 1,  /* 4 lanes, 3.125 Gbaud */
 208         BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */
 209         BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */
 210         BGX_MODE_XFI = 3,   /* 1 lane, 10.3125 Gbaud */
 211         BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */
 212         BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */
 213         BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */
 214 };
 215
 216 enum qlm_mode {
 217         QLM_MODE_SGMII,         /* SGMII, each lane independent */
 218         QLM_MODE_XAUI_1X4,      /* 1 XAUI or DXAUI, 4 lanes */
 219         QLM_MODE_RXAUI_2X2,     /* 2 RXAUI, 2 lanes each */
 220         QLM_MODE_XFI_4X1,       /* 4 XFI, 1 lane each */
 221         QLM_MODE_XLAUI_1X4,     /* 1 XLAUI, 4 lanes each */
 222         QLM_MODE_10G_KR_4X1,    /* 4 10GBASE-KR, 1 lane each */
 223         QLM_MODE_40G_KR4_1X4,   /* 1 40GBASE-KR4, 4 lanes each */
 224 };
 225
 226 #endif /* THUNDER_BGX_H */