drivers/pci/host/pcie-altera.c

   1 /*
   2  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irqchip/chained_irq.h>
  20 #include <linux/module.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_pci.h>
  24 #include <linux/pci.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27
  28 #define RP_TX_REG0                      0x2000
  29 #define RP_TX_REG1                      0x2004
  30 #define RP_TX_CNTRL                     0x2008
  31 #define RP_TX_EOP                       0x2
  32 #define RP_TX_SOP                       0x1
  33 #define RP_RXCPL_STATUS                 0x2010
  34 #define RP_RXCPL_EOP                    0x2
  35 #define RP_RXCPL_SOP                    0x1
  36 #define RP_RXCPL_REG0                   0x2014
  37 #define RP_RXCPL_REG1                   0x2018
  38 #define P2A_INT_STATUS                  0x3060
  39 #define P2A_INT_STS_ALL                 0xf
  40 #define P2A_INT_ENABLE                  0x3070
  41 #define P2A_INT_ENA_ALL                 0xf
  42 #define RP_LTSSM                        0x3c64
  43 #define LTSSM_L0                        0xf
  44
  45 /* TLP configuration type 0 and 1 */
  46 #define TLP_FMTTYPE_CFGRD0              0x04    /* Configuration Read Type 0 */
  47 #define TLP_FMTTYPE_CFGWR0              0x44    /* Configuration Write Type 0 */
  48 #define TLP_FMTTYPE_CFGRD1              0x05    /* Configuration Read Type 1 */
  49 #define TLP_FMTTYPE_CFGWR1              0x45    /* Configuration Write Type 1 */
  50 #define TLP_PAYLOAD_SIZE                0x01
  51 #define TLP_READ_TAG                    0x1d
  52 #define TLP_WRITE_TAG                   0x10
  53 #define TLP_CFG_DW0(fmttype)            (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
  54 #define TLP_CFG_DW1(reqid, tag, be)     (((reqid) << 16) | (tag << 8) | (be))
  55 #define TLP_CFG_DW2(bus, devfn, offset) \
  56                                 (((bus) << 24) | ((devfn) << 16) | (offset))
  57 #define TLP_REQ_ID(bus, devfn)          (((bus) << 8) | (devfn))
  58 #define TLP_HDR_SIZE                    3
  59 #define TLP_LOOP                        500
  60 #define RP_DEVFN                        0
  61
  62 #define INTX_NUM                        4
  63
  64 #define DWORD_MASK                      3
  65
  66 struct altera_pcie {
  67         struct platform_device  *pdev;
  68         void __iomem            *cra_base;
  69         int                     irq;
  70         u8                      root_bus_nr;
  71         struct irq_domain       *irq_domain;
  72         struct resource         bus_range;
  73         struct list_head        resources;
  74 };
  75
  76 struct tlp_rp_regpair_t {
  77         u32 ctrl;
  78         u32 reg0;
  79         u32 reg1;
  80 };
  81
  82 static void altera_pcie_retrain(struct pci_dev *dev)
  83 {
  84         u16 linkcap, linkstat;
  85
  86         /*
  87          * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
  88          * current speed is 2.5 GB/s.
  89          */
  90         pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
  91
  92         if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
  93                 return;
  94
  95         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
  96         if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
  97                 pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
  98                                          PCI_EXP_LNKCTL_RL);
  99 }
 100 DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
 101
 102 /*
 103  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 104  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 105  * using these registers, so it can be reached by DMA from EP devices.
 106  * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 107  * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 108  * should be hidden during enumeration to avoid the sizing and resource
 109  * allocation by PCIe core.
 110  */
 111 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
 112                                     int offset)
 113 {
 114         if (pci_is_root_bus(bus) && (devfn == 0) &&
 115             (offset == PCI_BASE_ADDRESS_0))
 116                 return true;
 117
 118         return false;
 119 }
 120
 121 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
 122                               const u32 reg)
 123 {
 124         writel_relaxed(value, pcie->cra_base + reg);
 125 }
 126
 127 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
 128 {
 129         return readl_relaxed(pcie->cra_base + reg);
 130 }
 131
 132 static void tlp_write_tx(struct altera_pcie *pcie,
 133                          struct tlp_rp_regpair_t *tlp_rp_regdata)
 134 {
 135         cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
 136         cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
 137         cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
 138 }
 139
 140 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
 141 {
 142         return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0);
 143 }
 144
 145 static bool altera_pcie_valid_config(struct altera_pcie *pcie,
 146                                      struct pci_bus *bus, int dev)
 147 {
 148         /* If there is no link, then there is no device */
 149         if (bus->number != pcie->root_bus_nr) {
 150                 if (!altera_pcie_link_is_up(pcie))
 151                         return false;
 152         }
 153
 154         /* access only one slot on each root port */
 155         if (bus->number == pcie->root_bus_nr && dev > 0)
 156                 return false;
 157
 158         /*
 159          * Do not read more than one device on the bus directly attached
 160          * to root port, root port can only attach to one downstream port.
 161          */
 162         if (bus->primary == pcie->root_bus_nr && dev > 0)
 163                 return false;
 164
 165          return true;
 166 }
 167
 168 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 169 {
 170         int i;
 171         bool sop = 0;
 172         u32 ctrl;
 173         u32 reg0, reg1;
 174
 175         /*
 176          * Minimum 2 loops to read TLP headers and 1 loop to read data
 177          * payload.
 178          */
 179         for (i = 0; i < TLP_LOOP; i++) {
 180                 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
 181                 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
 182                         reg0 = cra_readl(pcie, RP_RXCPL_REG0);
 183                         reg1 = cra_readl(pcie, RP_RXCPL_REG1);
 184
 185                         if (ctrl & RP_RXCPL_SOP)
 186                                 sop = true;
 187
 188                         if (ctrl & RP_RXCPL_EOP) {
 189                                 if (value)
 190                                         *value = reg0;
 191                                 return PCIBIOS_SUCCESSFUL;
 192                         }
 193                 }
 194                 udelay(5);
 195         }
 196
 197         return -ENOENT;
 198 }
 199
 200 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 201                              u32 data, bool align)
 202 {
 203         struct tlp_rp_regpair_t tlp_rp_regdata;
 204
 205         tlp_rp_regdata.reg0 = headers[0];
 206         tlp_rp_regdata.reg1 = headers[1];
 207         tlp_rp_regdata.ctrl = RP_TX_SOP;
 208         tlp_write_tx(pcie, &tlp_rp_regdata);
 209
 210         if (align) {
 211                 tlp_rp_regdata.reg0 = headers[2];
 212                 tlp_rp_regdata.reg1 = 0;
 213                 tlp_rp_regdata.ctrl = 0;
 214                 tlp_write_tx(pcie, &tlp_rp_regdata);
 215
 216                 tlp_rp_regdata.reg0 = data;
 217                 tlp_rp_regdata.reg1 = 0;
 218         } else {
 219                 tlp_rp_regdata.reg0 = headers[2];
 220                 tlp_rp_regdata.reg1 = data;
 221         }
 222
 223         tlp_rp_regdata.ctrl = RP_TX_EOP;
 224         tlp_write_tx(pcie, &tlp_rp_regdata);
 225 }
 226
 227 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
 228                               int where, u8 byte_en, u32 *value)
 229 {
 230         u32 headers[TLP_HDR_SIZE];
 231
 232         if (bus == pcie->root_bus_nr)
 233                 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
 234         else
 235                 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
 236
 237         headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
 238                                         TLP_READ_TAG, byte_en);
 239         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 240
 241         tlp_write_packet(pcie, headers, 0, false);
 242
 243         return tlp_read_packet(pcie, value);
 244 }
 245
 246 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
 247                                int where, u8 byte_en, u32 value)
 248 {
 249         u32 headers[TLP_HDR_SIZE];
 250         int ret;
 251
 252         if (bus == pcie->root_bus_nr)
 253                 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
 254         else
 255                 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
 256
 257         headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
 258                                         TLP_WRITE_TAG, byte_en);
 259         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 260
 261         /* check alignment to Qword */
 262         if ((where & 0x7) == 0)
 263                 tlp_write_packet(pcie, headers, value, true);
 264         else
 265                 tlp_write_packet(pcie, headers, value, false);
 266
 267         ret = tlp_read_packet(pcie, NULL);
 268         if (ret != PCIBIOS_SUCCESSFUL)
 269                 return ret;
 270
 271         /*
 272          * Monitor changes to PCI_PRIMARY_BUS register on root port
 273          * and update local copy of root bus number accordingly.
 274          */
 275         if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
 276                 pcie->root_bus_nr = (u8)(value);
 277
 278         return PCIBIOS_SUCCESSFUL;
 279 }
 280
 281 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
 282                                 int where, int size, u32 *value)
 283 {
 284         struct altera_pcie *pcie = bus->sysdata;
 285         int ret;
 286         u32 data;
 287         u8 byte_en;
 288
 289         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 290                 return PCIBIOS_BAD_REGISTER_NUMBER;
 291
 292         if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
 293                 *value = 0xffffffff;
 294                 return PCIBIOS_DEVICE_NOT_FOUND;
 295         }
 296
 297         switch (size) {
 298         case 1:
 299                 byte_en = 1 << (where & 3);
 300                 break;
 301         case 2:
 302                 byte_en = 3 << (where & 3);
 303                 break;
 304         default:
 305                 byte_en = 0xf;
 306                 break;
 307         }
 308
 309         ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
 310                                  (where & ~DWORD_MASK), byte_en, &data);
 311         if (ret != PCIBIOS_SUCCESSFUL)
 312                 return ret;
 313
 314         switch (size) {
 315         case 1:
 316                 *value = (data >> (8 * (where & 0x3))) & 0xff;
 317                 break;
 318         case 2:
 319                 *value = (data >> (8 * (where & 0x2))) & 0xffff;
 320                 break;
 321         default:
 322                 *value = data;
 323                 break;
 324         }
 325
 326         return PCIBIOS_SUCCESSFUL;
 327 }
 328
 329 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
 330                                  int where, int size, u32 value)
 331 {
 332         struct altera_pcie *pcie = bus->sysdata;
 333         u32 data32;
 334         u32 shift = 8 * (where & 3);
 335         u8 byte_en;
 336
 337         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 338                 return PCIBIOS_BAD_REGISTER_NUMBER;
 339
 340         if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
 341                 return PCIBIOS_DEVICE_NOT_FOUND;
 342
 343         switch (size) {
 344         case 1:
 345                 data32 = (value & 0xff) << shift;
 346                 byte_en = 1 << (where & 3);
 347                 break;
 348         case 2:
 349                 data32 = (value & 0xffff) << shift;
 350                 byte_en = 3 << (where & 3);
 351                 break;
 352         default:
 353                 data32 = value;
 354                 byte_en = 0xf;
 355                 break;
 356         }
 357
 358         return tlp_cfg_dword_write(pcie, bus->number, devfn,
 359                 (where & ~DWORD_MASK), byte_en, data32);
 360 }
 361
 362 static struct pci_ops altera_pcie_ops = {
 363         .read = altera_pcie_cfg_read,
 364         .write = altera_pcie_cfg_write,
 365 };
 366
 367 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 368                                 irq_hw_number_t hwirq)
 369 {
 370         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 371         irq_set_chip_data(irq, domain->host_data);
 372
 373         return 0;
 374 }
 375
 376 static const struct irq_domain_ops intx_domain_ops = {
 377         .map = altera_pcie_intx_map,
 378 };
 379
 380 static void altera_pcie_isr(struct irq_desc *desc)
 381 {
 382         struct irq_chip *chip = irq_desc_get_chip(desc);
 383         struct altera_pcie *pcie;
 384         unsigned long status;
 385         u32 bit;
 386         u32 virq;
 387
 388         chained_irq_enter(chip, desc);
 389         pcie = irq_desc_get_handler_data(desc);
 390
 391         while ((status = cra_readl(pcie, P2A_INT_STATUS)
 392                 & P2A_INT_STS_ALL) != 0) {
 393                 for_each_set_bit(bit, &status, INTX_NUM) {
 394                         /* clear interrupts */
 395                         cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
 396
 397                         virq = irq_find_mapping(pcie->irq_domain, bit + 1);
 398                         if (virq)
 399                                 generic_handle_irq(virq);
 400                         else
 401                                 dev_err(&pcie->pdev->dev,
 402                                         "unexpected IRQ, INT%d\n", bit);
 403                 }
 404         }
 405
 406         chained_irq_exit(chip, desc);
 407 }
 408
 409 static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie)
 410 {
 411         pci_free_resource_list(&pcie->resources);
 412 }
 413
 414 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
 415 {
 416         int err, res_valid = 0;
 417         struct device *dev = &pcie->pdev->dev;
 418         struct device_node *np = dev->of_node;
 419         struct resource_entry *win;
 420
 421         err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
 422                                                NULL);
 423         if (err)
 424                 return err;
 425
 426         resource_list_for_each_entry(win, &pcie->resources) {
 427                 struct resource *parent, *res = win->res;
 428
 429                 switch (resource_type(res)) {
 430                 case IORESOURCE_MEM:
 431                         parent = &iomem_resource;
 432                         res_valid |= !(res->flags & IORESOURCE_PREFETCH);
 433                         break;
 434                 default:
 435                         continue;
 436                 }
 437
 438                 err = devm_request_resource(dev, parent, res);
 439                 if (err)
 440                         goto out_release_res;
 441         }
 442
 443         if (!res_valid) {
 444                 dev_err(dev, "non-prefetchable memory resource required\n");
 445                 err = -EINVAL;
 446                 goto out_release_res;
 447         }
 448
 449         return 0;
 450
 451 out_release_res:
 452         altera_pcie_release_of_pci_ranges(pcie);
 453         return err;
 454 }
 455
 456 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
 457 {
 458         struct device *dev = &pcie->pdev->dev;
 459         struct device_node *node = dev->of_node;
 460
 461         /* Setup INTx */
 462         pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM,
 463                                         &intx_domain_ops, pcie);
 464         if (!pcie->irq_domain) {
 465                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 466                 return -ENOMEM;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 473 {
 474         struct resource *cra;
 475         struct platform_device *pdev = pcie->pdev;
 476
 477         cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
 478         if (!cra) {
 479                 dev_err(&pdev->dev, "no Cra memory resource defined\n");
 480                 return -ENODEV;
 481         }
 482
 483         pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
 484         if (IS_ERR(pcie->cra_base)) {
 485                 dev_err(&pdev->dev, "failed to map cra memory\n");
 486                 return PTR_ERR(pcie->cra_base);
 487         }
 488
 489         /* setup IRQ */
 490         pcie->irq = platform_get_irq(pdev, 0);
 491         if (pcie->irq <= 0) {
 492                 dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
 493                 return -EINVAL;
 494         }
 495
 496         irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
 497
 498         return 0;
 499 }
 500
 501 static int altera_pcie_probe(struct platform_device *pdev)
 502 {
 503         struct altera_pcie *pcie;
 504         struct pci_bus *bus;
 505         struct pci_bus *child;
 506         int ret;
 507
 508         pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
 509         if (!pcie)
 510                 return -ENOMEM;
 511
 512         pcie->pdev = pdev;
 513
 514         ret = altera_pcie_parse_dt(pcie);
 515         if (ret) {
 516                 dev_err(&pdev->dev, "Parsing DT failed\n");
 517                 return ret;
 518         }
 519
 520         INIT_LIST_HEAD(&pcie->resources);
 521
 522         ret = altera_pcie_parse_request_of_pci_ranges(pcie);
 523         if (ret) {
 524                 dev_err(&pdev->dev, "Failed add resources\n");
 525                 return ret;
 526         }
 527
 528         ret = altera_pcie_init_irq_domain(pcie);
 529         if (ret) {
 530                 dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
 531                 return ret;
 532         }
 533
 534         /* clear all interrupts */
 535         cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
 536         /* enable all interrupts */
 537         cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
 538
 539         bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
 540                                 pcie, &pcie->resources);
 541         if (!bus)
 542                 return -ENOMEM;
 543
 544         pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
 545         pci_assign_unassigned_bus_resources(bus);
 546
 547         /* Configure PCI Express setting. */
 548         list_for_each_entry(child, &bus->children, node)
 549                 pcie_bus_configure_settings(child);
 550
 551         pci_bus_add_devices(bus);
 552
 553         platform_set_drvdata(pdev, pcie);
 554         return ret;
 555 }
 556
 557 static const struct of_device_id altera_pcie_of_match[] = {
 558         { .compatible = "altr,pcie-root-port-1.0", },
 559         {},
 560 };
 561 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
 562
 563 static struct platform_driver altera_pcie_driver = {
 564         .probe          = altera_pcie_probe,
 565         .driver = {
 566                 .name   = "altera-pcie",
 567                 .of_match_table = altera_pcie_of_match,
 568                 .suppress_bind_attrs = true,
 569         },
 570 };
 571
 572 static int altera_pcie_init(void)
 573 {
 574         return platform_driver_register(&altera_pcie_driver);
 575 }
 576 module_init(altera_pcie_init);
 577
 578 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
 579 MODULE_DESCRIPTION("Altera PCIe host controller driver");
 580 MODULE_LICENSE("GPL v2");