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[people/ms/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include "8250.h"
29
30 /*
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
34 * < 0 - error
35 */
36 struct pci_serial_quirk {
37 u32 vendor;
38 u32 device;
39 u32 subvendor;
40 u32 subdevice;
41 int (*probe)(struct pci_dev *dev);
42 int (*init)(struct pci_dev *dev);
43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
45 struct uart_8250_port *, int);
46 void (*exit)(struct pci_dev *dev);
47 };
48
49 #define PCI_NUM_BAR_RESOURCES 6
50
51 struct serial_private {
52 struct pci_dev *dev;
53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57 };
58
59 static int pci_default_setup(struct serial_private*,
60 const struct pciserial_board*, struct uart_8250_port *, int);
61
62 static void moan_device(const char *str, struct pci_dev *dev)
63 {
64 dev_err(&dev->dev,
65 "%s: %s\n"
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to <linux-serial@vger.kernel.org>.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72 }
73
74 static int
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 int bar, int offset, int regshift)
77 {
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
84 base = pci_resource_start(dev, bar);
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap_nocache(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
96 port->port.mapbase = base + offset;
97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
99 } else {
100 port->port.iotype = UPIO_PORT;
101 port->port.iobase = base + offset;
102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
105 }
106 return 0;
107 }
108
109 /*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112 static int addidata_apci7800_setup(struct serial_private *priv,
113 const struct pciserial_board *board,
114 struct uart_8250_port *port, int idx)
115 {
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133 }
134
135 /*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139 static int
140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
141 struct uart_8250_port *port, int idx)
142 {
143 unsigned int bar, offset = board->first_offset;
144
145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
153 return setup_port(priv, port, bar, offset, board->reg_shift);
154 }
155
156 /*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
163 static int pci_hp_diva_init(struct pci_dev *dev)
164 {
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
182 rc = 1;
183 break;
184 }
185
186 return rc;
187 }
188
189 /*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193 static int
194 pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
196 struct uart_8250_port *port, int idx)
197 {
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
201 switch (priv->dev->subsystem_device) {
202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
218 return setup_port(priv, port, bar, offset, board->reg_shift);
219 }
220
221 /*
222 * Added for EKF Intel i960 serial boards
223 */
224 static int pci_inteli960ni_init(struct pci_dev *dev)
225 {
226 unsigned long oldval;
227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
232 pci_read_config_dword(dev, 0x44, (void *)&oldval);
233 if (oldval == 0x00001000L) { /* RESET value */
234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
235 return -ENODEV;
236 }
237 return 0;
238 }
239
240 /*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
246 static int pci_plx9050_init(struct pci_dev *dev)
247 {
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
259 irq_config = 0x43;
260
261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
272 /*
273 * enable/disable interrupts
274 */
275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287 }
288
289 static void pci_plx9050_exit(struct pci_dev *dev)
290 {
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309 }
310
311 #define NI8420_INT_ENABLE_REG 0x38
312 #define NI8420_INT_ENABLE_BIT 0x2000
313
314 static void pci_ni8420_exit(struct pci_dev *dev)
315 {
316 void __iomem *p;
317 unsigned long base, len;
318 unsigned int bar = 0;
319
320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
321 moan_device("no memory in bar", dev);
322 return;
323 }
324
325 base = pci_resource_start(dev, bar);
326 len = pci_resource_len(dev, bar);
327 p = ioremap_nocache(base, len);
328 if (p == NULL)
329 return;
330
331 /* Disable the CPU Interrupt */
332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
333 p + NI8420_INT_ENABLE_REG);
334 iounmap(p);
335 }
336
337
338 /* MITE registers */
339 #define MITE_IOWBSR1 0xc4
340 #define MITE_IOWCR1 0xf4
341 #define MITE_LCIMR1 0x08
342 #define MITE_LCIMR2 0x10
343
344 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
345
346 static void pci_ni8430_exit(struct pci_dev *dev)
347 {
348 void __iomem *p;
349 unsigned long base, len;
350 unsigned int bar = 0;
351
352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
353 moan_device("no memory in bar", dev);
354 return;
355 }
356
357 base = pci_resource_start(dev, bar);
358 len = pci_resource_len(dev, bar);
359 p = ioremap_nocache(base, len);
360 if (p == NULL)
361 return;
362
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
365 iounmap(p);
366 }
367
368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369 static int
370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
371 struct uart_8250_port *port, int idx)
372 {
373 unsigned int bar, offset = board->first_offset;
374
375 bar = 0;
376
377 if (idx < 4) {
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
384 return 1;
385
386 return setup_port(priv, port, bar, offset, board->reg_shift);
387 }
388
389 /*
390 * This does initialization for PMC OCTALPRO cards:
391 * maps the device memory, resets the UARTs (needed, bc
392 * if the module is removed and inserted again, the card
393 * is in the sleep mode) and enables global interrupt.
394 */
395
396 /* global control register offset for SBS PMC-OctalPro */
397 #define OCT_REG_CR_OFF 0x500
398
399 static int sbs_init(struct pci_dev *dev)
400 {
401 u8 __iomem *p;
402
403 p = pci_ioremap_bar(dev, 0);
404
405 if (p == NULL)
406 return -ENOMEM;
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
408 writeb(0x10, p + OCT_REG_CR_OFF);
409 udelay(50);
410 writeb(0x0, p + OCT_REG_CR_OFF);
411
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
414 iounmap(p);
415
416 return 0;
417 }
418
419 /*
420 * Disables the global interrupt of PMC-OctalPro
421 */
422
423 static void sbs_exit(struct pci_dev *dev)
424 {
425 u8 __iomem *p;
426
427 p = pci_ioremap_bar(dev, 0);
428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
430 writeb(0, p + OCT_REG_CR_OFF);
431 iounmap(p);
432 }
433
434 /*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equipped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
446 *
447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
464 static int pci_siig10x_init(struct pci_dev *dev)
465 {
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489 }
490
491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
494 static int pci_siig20x_init(struct pci_dev *dev)
495 {
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509 }
510
511 static int pci_siig_init(struct pci_dev *dev)
512 {
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522 }
523
524 static int pci_siig_setup(struct serial_private *priv,
525 const struct pciserial_board *board,
526 struct uart_8250_port *port, int idx)
527 {
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536 }
537
538 /*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
543 static const unsigned short timedia_single_port[] = {
544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545 };
546
547 static const unsigned short timedia_dual_port[] = {
548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553 };
554
555 static const unsigned short timedia_quad_port[] = {
556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560 };
561
562 static const unsigned short timedia_eight_port[] = {
563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565 };
566
567 static const struct timedia_struct {
568 int num;
569 const unsigned short *ids;
570 } timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
574 { 8, timedia_eight_port }
575 };
576
577 /*
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
582 */
583 static int pci_timedia_probe(struct pci_dev *dev)
584 {
585 /*
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 */
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 dev_info(&dev->dev,
591 "ignoring Timedia subdevice %04x for parport_serial\n",
592 dev->subsystem_device);
593 return -ENODEV;
594 }
595
596 return 0;
597 }
598
599 static int pci_timedia_init(struct pci_dev *dev)
600 {
601 const unsigned short *ids;
602 int i, j;
603
604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
605 ids = timedia_data[i].ids;
606 for (j = 0; ids[j]; j++)
607 if (dev->subsystem_device == ids[j])
608 return timedia_data[i].num;
609 }
610 return 0;
611 }
612
613 /*
614 * Timedia/SUNIX uses a mixture of BARs and offsets
615 * Ugh, this is ugly as all hell --- TYT
616 */
617 static int
618 pci_timedia_setup(struct serial_private *priv,
619 const struct pciserial_board *board,
620 struct uart_8250_port *port, int idx)
621 {
622 unsigned int bar = 0, offset = board->first_offset;
623
624 switch (idx) {
625 case 0:
626 bar = 0;
627 break;
628 case 1:
629 offset = board->uart_offset;
630 bar = 0;
631 break;
632 case 2:
633 bar = 1;
634 break;
635 case 3:
636 offset = board->uart_offset;
637 /* FALLTHROUGH */
638 case 4: /* BAR 2 */
639 case 5: /* BAR 3 */
640 case 6: /* BAR 4 */
641 case 7: /* BAR 5 */
642 bar = idx - 2;
643 }
644
645 return setup_port(priv, port, bar, offset, board->reg_shift);
646 }
647
648 /*
649 * Some Titan cards are also a little weird
650 */
651 static int
652 titan_400l_800l_setup(struct serial_private *priv,
653 const struct pciserial_board *board,
654 struct uart_8250_port *port, int idx)
655 {
656 unsigned int bar, offset = board->first_offset;
657
658 switch (idx) {
659 case 0:
660 bar = 1;
661 break;
662 case 1:
663 bar = 2;
664 break;
665 default:
666 bar = 4;
667 offset = (idx - 2) * board->uart_offset;
668 }
669
670 return setup_port(priv, port, bar, offset, board->reg_shift);
671 }
672
673 static int pci_xircom_init(struct pci_dev *dev)
674 {
675 msleep(100);
676 return 0;
677 }
678
679 static int pci_ni8420_init(struct pci_dev *dev)
680 {
681 void __iomem *p;
682 unsigned long base, len;
683 unsigned int bar = 0;
684
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
687 return 0;
688 }
689
690 base = pci_resource_start(dev, bar);
691 len = pci_resource_len(dev, bar);
692 p = ioremap_nocache(base, len);
693 if (p == NULL)
694 return -ENOMEM;
695
696 /* Enable CPU Interrupt */
697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
698 p + NI8420_INT_ENABLE_REG);
699
700 iounmap(p);
701 return 0;
702 }
703
704 #define MITE_IOWBSR1_WSIZE 0xa
705 #define MITE_IOWBSR1_WIN_OFFSET 0x800
706 #define MITE_IOWBSR1_WENAB (1 << 7)
707 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
708 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
709 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
710
711 static int pci_ni8430_init(struct pci_dev *dev)
712 {
713 void __iomem *p;
714 unsigned long base, len;
715 u32 device_window;
716 unsigned int bar = 0;
717
718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
719 moan_device("no memory in bar", dev);
720 return 0;
721 }
722
723 base = pci_resource_start(dev, bar);
724 len = pci_resource_len(dev, bar);
725 p = ioremap_nocache(base, len);
726 if (p == NULL)
727 return -ENOMEM;
728
729 /* Set device window address and size in BAR0 */
730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
732 writel(device_window, p + MITE_IOWBSR1);
733
734 /* Set window access to go to RAMSEL IO address space */
735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
736 p + MITE_IOWCR1);
737
738 /* Enable IO Bus Interrupt 0 */
739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
740
741 /* Enable CPU Interrupt */
742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
743
744 iounmap(p);
745 return 0;
746 }
747
748 /* UART Port Control Register */
749 #define NI8430_PORTCON 0x0f
750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
751
752 static int
753 pci_ni8430_setup(struct serial_private *priv,
754 const struct pciserial_board *board,
755 struct uart_8250_port *port, int idx)
756 {
757 void __iomem *p;
758 unsigned long base, len;
759 unsigned int bar, offset = board->first_offset;
760
761 if (idx >= board->num_ports)
762 return 1;
763
764 bar = FL_GET_BASE(board->flags);
765 offset += idx * board->uart_offset;
766
767 base = pci_resource_start(priv->dev, bar);
768 len = pci_resource_len(priv->dev, bar);
769 p = ioremap_nocache(base, len);
770
771 /* enable the transceiver */
772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
773 p + offset + NI8430_PORTCON);
774
775 iounmap(p);
776
777 return setup_port(priv, port, bar, offset, board->reg_shift);
778 }
779
780 static int pci_netmos_9900_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
782 struct uart_8250_port *port, int idx)
783 {
784 unsigned int bar;
785
786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
787 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797 }
798
799 /* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807 static int pci_netmos_9900_numports(struct pci_dev *dev)
808 {
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836 }
837
838 static int pci_netmos_init(struct pci_dev *dev)
839 {
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845 return 0;
846
847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
865 if (num_serial == 0)
866 return -ENODEV;
867
868 return num_serial;
869 }
870
871 /*
872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881 /* registers */
882 #define ITE_887x_MISCR 0x9c
883 #define ITE_887x_INTCBAR 0x78
884 #define ITE_887x_UARTBAR 0x7c
885 #define ITE_887x_PS0BAR 0x10
886 #define ITE_887x_POSIO0 0x60
887
888 /* I/O space size */
889 #define ITE_887x_IOSIZE 32
890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
891 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
893 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895 #define ITE_887x_POSIO_SPEED (3 << 29)
896 /* enable IO_Space bit */
897 #define ITE_887x_POSIO_ENABLE (1 << 31)
898
899 static int pci_ite887x_init(struct pci_dev *dev)
900 {
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 dev_err(&dev->dev, "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991 }
992
993 static void pci_ite887x_exit(struct pci_dev *dev)
994 {
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 dev_dbg(&dev->dev,
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032 }
1033
1034 static int pci_asix_setup(struct serial_private *priv,
1035 const struct pciserial_board *board,
1036 struct uart_8250_port *port, int idx)
1037 {
1038 port->bugs |= UART_BUG_PARITY;
1039 return pci_default_setup(priv, board, port, idx);
1040 }
1041
1042 /* Quatech devices have their own extra interface features */
1043
1044 struct quatech_feature {
1045 u16 devid;
1046 bool amcc;
1047 };
1048
1049 #define QPCR_TEST_FOR1 0x3F
1050 #define QPCR_TEST_GET1 0x00
1051 #define QPCR_TEST_FOR2 0x40
1052 #define QPCR_TEST_GET2 0x40
1053 #define QPCR_TEST_FOR3 0x80
1054 #define QPCR_TEST_GET3 0x40
1055 #define QPCR_TEST_FOR4 0xC0
1056 #define QPCR_TEST_GET4 0x80
1057
1058 #define QOPR_CLOCK_X1 0x0000
1059 #define QOPR_CLOCK_X2 0x0001
1060 #define QOPR_CLOCK_X4 0x0002
1061 #define QOPR_CLOCK_X8 0x0003
1062 #define QOPR_CLOCK_RATE_MASK 0x0003
1063
1064
1065 static struct quatech_feature quatech_cards[] = {
1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1085 { 0, }
1086 };
1087
1088 static int pci_quatech_amcc(u16 devid)
1089 {
1090 struct quatech_feature *qf = &quatech_cards[0];
1091 while (qf->devid) {
1092 if (qf->devid == devid)
1093 return qf->amcc;
1094 qf++;
1095 }
1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1097 return 0;
1098 };
1099
1100 static int pci_quatech_rqopr(struct uart_8250_port *port)
1101 {
1102 unsigned long base = port->port.iobase;
1103 u8 LCR, val;
1104
1105 LCR = inb(base + UART_LCR);
1106 outb(0xBF, base + UART_LCR);
1107 val = inb(base + UART_SCR);
1108 outb(LCR, base + UART_LCR);
1109 return val;
1110 }
1111
1112 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1113 {
1114 unsigned long base = port->port.iobase;
1115 u8 LCR, val;
1116
1117 LCR = inb(base + UART_LCR);
1118 outb(0xBF, base + UART_LCR);
1119 val = inb(base + UART_SCR);
1120 outb(qopr, base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1122 }
1123
1124 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1125 {
1126 unsigned long base = port->port.iobase;
1127 u8 LCR, val, qmcr;
1128
1129 LCR = inb(base + UART_LCR);
1130 outb(0xBF, base + UART_LCR);
1131 val = inb(base + UART_SCR);
1132 outb(val | 0x10, base + UART_SCR);
1133 qmcr = inb(base + UART_MCR);
1134 outb(val, base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1136
1137 return qmcr;
1138 }
1139
1140 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1141 {
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(val | 0x10, base + UART_SCR);
1149 outb(qmcr, base + UART_MCR);
1150 outb(val, base + UART_SCR);
1151 outb(LCR, base + UART_LCR);
1152 }
1153
1154 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1155 {
1156 unsigned long base = port->port.iobase;
1157 u8 LCR, val;
1158
1159 LCR = inb(base + UART_LCR);
1160 outb(0xBF, base + UART_LCR);
1161 val = inb(base + UART_SCR);
1162 if (val & 0x20) {
1163 outb(0x80, UART_LCR);
1164 if (!(inb(UART_SCR) & 0x20)) {
1165 outb(LCR, base + UART_LCR);
1166 return 1;
1167 }
1168 }
1169 return 0;
1170 }
1171
1172 static int pci_quatech_test(struct uart_8250_port *port)
1173 {
1174 u8 reg;
1175 u8 qopr = pci_quatech_rqopr(port);
1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177 reg = pci_quatech_rqopr(port) & 0xC0;
1178 if (reg != QPCR_TEST_GET1)
1179 return -EINVAL;
1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181 reg = pci_quatech_rqopr(port) & 0xC0;
1182 if (reg != QPCR_TEST_GET2)
1183 return -EINVAL;
1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185 reg = pci_quatech_rqopr(port) & 0xC0;
1186 if (reg != QPCR_TEST_GET3)
1187 return -EINVAL;
1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189 reg = pci_quatech_rqopr(port) & 0xC0;
1190 if (reg != QPCR_TEST_GET4)
1191 return -EINVAL;
1192
1193 pci_quatech_wqopr(port, qopr);
1194 return 0;
1195 }
1196
1197 static int pci_quatech_clock(struct uart_8250_port *port)
1198 {
1199 u8 qopr, reg, set;
1200 unsigned long clock;
1201
1202 if (pci_quatech_test(port) < 0)
1203 return 1843200;
1204
1205 qopr = pci_quatech_rqopr(port);
1206
1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208 reg = pci_quatech_rqopr(port);
1209 if (reg & QOPR_CLOCK_X8) {
1210 clock = 1843200;
1211 goto out;
1212 }
1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214 reg = pci_quatech_rqopr(port);
1215 if (!(reg & QOPR_CLOCK_X8)) {
1216 clock = 1843200;
1217 goto out;
1218 }
1219 reg &= QOPR_CLOCK_X8;
1220 if (reg == QOPR_CLOCK_X2) {
1221 clock = 3685400;
1222 set = QOPR_CLOCK_X2;
1223 } else if (reg == QOPR_CLOCK_X4) {
1224 clock = 7372800;
1225 set = QOPR_CLOCK_X4;
1226 } else if (reg == QOPR_CLOCK_X8) {
1227 clock = 14745600;
1228 set = QOPR_CLOCK_X8;
1229 } else {
1230 clock = 1843200;
1231 set = QOPR_CLOCK_X1;
1232 }
1233 qopr &= ~QOPR_CLOCK_RATE_MASK;
1234 qopr |= set;
1235
1236 out:
1237 pci_quatech_wqopr(port, qopr);
1238 return clock;
1239 }
1240
1241 static int pci_quatech_rs422(struct uart_8250_port *port)
1242 {
1243 u8 qmcr;
1244 int rs422 = 0;
1245
1246 if (!pci_quatech_has_qmcr(port))
1247 return 0;
1248 qmcr = pci_quatech_rqmcr(port);
1249 pci_quatech_wqmcr(port, 0xFF);
1250 if (pci_quatech_rqmcr(port))
1251 rs422 = 1;
1252 pci_quatech_wqmcr(port, qmcr);
1253 return rs422;
1254 }
1255
1256 static int pci_quatech_init(struct pci_dev *dev)
1257 {
1258 if (pci_quatech_amcc(dev->device)) {
1259 unsigned long base = pci_resource_start(dev, 0);
1260 if (base) {
1261 u32 tmp;
1262 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1263 tmp = inl(base + 0x3c);
1264 outl(tmp | 0x01000000, base + 0x3c);
1265 outl(tmp &= ~0x01000000, base + 0x3c);
1266 }
1267 }
1268 return 0;
1269 }
1270
1271 static int pci_quatech_setup(struct serial_private *priv,
1272 const struct pciserial_board *board,
1273 struct uart_8250_port *port, int idx)
1274 {
1275 /* Needed by pci_quatech calls below */
1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277 /* Set up the clocking */
1278 port->port.uartclk = pci_quatech_clock(port);
1279 /* For now just warn about RS422 */
1280 if (pci_quatech_rs422(port))
1281 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282 return pci_default_setup(priv, board, port, idx);
1283 }
1284
1285 static void pci_quatech_exit(struct pci_dev *dev)
1286 {
1287 }
1288
1289 static int pci_default_setup(struct serial_private *priv,
1290 const struct pciserial_board *board,
1291 struct uart_8250_port *port, int idx)
1292 {
1293 unsigned int bar, offset = board->first_offset, maxnr;
1294
1295 bar = FL_GET_BASE(board->flags);
1296 if (board->flags & FL_BASE_BARS)
1297 bar += idx;
1298 else
1299 offset += idx * board->uart_offset;
1300
1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302 (board->reg_shift + 3);
1303
1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1305 return 1;
1306
1307 return setup_port(priv, port, bar, offset, board->reg_shift);
1308 }
1309
1310 static int pci_pericom_setup(struct serial_private *priv,
1311 const struct pciserial_board *board,
1312 struct uart_8250_port *port, int idx)
1313 {
1314 unsigned int bar, offset = board->first_offset, maxnr;
1315
1316 bar = FL_GET_BASE(board->flags);
1317 if (board->flags & FL_BASE_BARS)
1318 bar += idx;
1319 else
1320 offset += idx * board->uart_offset;
1321
1322 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1323 (board->reg_shift + 3);
1324
1325 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1326 return 1;
1327
1328 port->port.uartclk = 14745600;
1329
1330 return setup_port(priv, port, bar, offset, board->reg_shift);
1331 }
1332
1333 static int
1334 ce4100_serial_setup(struct serial_private *priv,
1335 const struct pciserial_board *board,
1336 struct uart_8250_port *port, int idx)
1337 {
1338 int ret;
1339
1340 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1341 port->port.iotype = UPIO_MEM32;
1342 port->port.type = PORT_XSCALE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 port->port.regshift = 2;
1345
1346 return ret;
1347 }
1348
1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1351
1352 #define BYT_PRV_CLK 0x800
1353 #define BYT_PRV_CLK_EN (1 << 0)
1354 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1355 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1356 #define BYT_PRV_CLK_UPDATE (1 << 31)
1357
1358 #define BYT_GENERAL_REG 0x808
1359 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1360
1361 #define BYT_TX_OVF_INT 0x820
1362 #define BYT_TX_OVF_INT_MASK (1 << 1)
1363
1364 static void
1365 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1366 struct ktermios *old)
1367 {
1368 unsigned int baud = tty_termios_baud_rate(termios);
1369 unsigned int m = 6912;
1370 unsigned int n = 15625;
1371 u32 reg;
1372
1373 /* For baud rates 1M, 2M, 3M and 4M the dividers must be adjusted. */
1374 if (baud == 1000000 || baud == 2000000 || baud == 4000000) {
1375 m = 64;
1376 n = 100;
1377
1378 p->uartclk = 64000000;
1379 } else if (baud == 3000000) {
1380 m = 48;
1381 n = 100;
1382
1383 p->uartclk = 48000000;
1384 } else {
1385 p->uartclk = 44236800;
1386 }
1387
1388 /* Reset the clock */
1389 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1390 writel(reg, p->membase + BYT_PRV_CLK);
1391 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1392 writel(reg, p->membase + BYT_PRV_CLK);
1393
1394 /*
1395 * If auto-handshake mechanism is not enabled,
1396 * disable rts_n override
1397 */
1398 reg = readl(p->membase + BYT_GENERAL_REG);
1399 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1400 if (termios->c_cflag & CRTSCTS)
1401 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1402 writel(reg, p->membase + BYT_GENERAL_REG);
1403
1404 serial8250_do_set_termios(p, termios, old);
1405 }
1406
1407 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1408 {
1409 return chan->chan_id == *(int *)param;
1410 }
1411
1412 static int
1413 byt_serial_setup(struct serial_private *priv,
1414 const struct pciserial_board *board,
1415 struct uart_8250_port *port, int idx)
1416 {
1417 struct uart_8250_dma *dma;
1418 int ret;
1419
1420 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1421 if (!dma)
1422 return -ENOMEM;
1423
1424 switch (priv->dev->device) {
1425 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1426 dma->rx_chan_id = 3;
1427 dma->tx_chan_id = 2;
1428 break;
1429 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1430 dma->rx_chan_id = 5;
1431 dma->tx_chan_id = 4;
1432 break;
1433 default:
1434 return -EINVAL;
1435 }
1436
1437 dma->rxconf.slave_id = dma->rx_chan_id;
1438 dma->rxconf.src_maxburst = 16;
1439
1440 dma->txconf.slave_id = dma->tx_chan_id;
1441 dma->txconf.dst_maxburst = 16;
1442
1443 dma->fn = byt_dma_filter;
1444 dma->rx_param = &dma->rx_chan_id;
1445 dma->tx_param = &dma->tx_chan_id;
1446
1447 ret = pci_default_setup(priv, board, port, idx);
1448 port->port.iotype = UPIO_MEM;
1449 port->port.type = PORT_16550A;
1450 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1451 port->port.set_termios = byt_set_termios;
1452 port->port.fifosize = 64;
1453 port->tx_loadsz = 64;
1454 port->dma = dma;
1455 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1456
1457 /* Disable Tx counter interrupts */
1458 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1459
1460 return ret;
1461 }
1462
1463 static int
1464 pci_omegapci_setup(struct serial_private *priv,
1465 const struct pciserial_board *board,
1466 struct uart_8250_port *port, int idx)
1467 {
1468 return setup_port(priv, port, 2, idx * 8, 0);
1469 }
1470
1471 static int
1472 pci_brcm_trumanage_setup(struct serial_private *priv,
1473 const struct pciserial_board *board,
1474 struct uart_8250_port *port, int idx)
1475 {
1476 int ret = pci_default_setup(priv, board, port, idx);
1477
1478 port->port.type = PORT_BRCM_TRUMANAGE;
1479 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1480 return ret;
1481 }
1482
1483 static int pci_fintek_setup(struct serial_private *priv,
1484 const struct pciserial_board *board,
1485 struct uart_8250_port *port, int idx)
1486 {
1487 struct pci_dev *pdev = priv->dev;
1488 unsigned long base;
1489 unsigned long iobase;
1490 unsigned long ciobase = 0;
1491 u8 config_base;
1492
1493 /*
1494 * We are supposed to be able to read these from the PCI config space,
1495 * but the values there don't seem to match what we need to use, so
1496 * just use these hard-coded values for now, as they are correct.
1497 */
1498 switch (idx) {
1499 case 0: iobase = 0xe000; config_base = 0x40; break;
1500 case 1: iobase = 0xe008; config_base = 0x48; break;
1501 case 2: iobase = 0xe010; config_base = 0x50; break;
1502 case 3: iobase = 0xe018; config_base = 0x58; break;
1503 case 4: iobase = 0xe020; config_base = 0x60; break;
1504 case 5: iobase = 0xe028; config_base = 0x68; break;
1505 case 6: iobase = 0xe030; config_base = 0x70; break;
1506 case 7: iobase = 0xe038; config_base = 0x78; break;
1507 case 8: iobase = 0xe040; config_base = 0x80; break;
1508 case 9: iobase = 0xe048; config_base = 0x88; break;
1509 case 10: iobase = 0xe050; config_base = 0x90; break;
1510 case 11: iobase = 0xe058; config_base = 0x98; break;
1511 default:
1512 /* Unknown number of ports, get out of here */
1513 return -EINVAL;
1514 }
1515
1516 if (idx < 4) {
1517 base = pci_resource_start(priv->dev, 3);
1518 ciobase = (int)(base + (0x8 * idx));
1519 }
1520
1521 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1522 __func__, idx, iobase, ciobase, config_base);
1523
1524 /* Enable UART I/O port */
1525 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1526
1527 /* Select 128-byte FIFO and 8x FIFO threshold */
1528 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1529
1530 /* LSB UART */
1531 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1532
1533 /* MSB UART */
1534 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1535
1536 /* irq number, this usually fails, but the spec says to do it anyway. */
1537 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1538
1539 port->port.iotype = UPIO_PORT;
1540 port->port.iobase = iobase;
1541 port->port.mapbase = 0;
1542 port->port.membase = NULL;
1543 port->port.regshift = 0;
1544
1545 return 0;
1546 }
1547
1548 static int skip_tx_en_setup(struct serial_private *priv,
1549 const struct pciserial_board *board,
1550 struct uart_8250_port *port, int idx)
1551 {
1552 port->port.flags |= UPF_NO_TXEN_TEST;
1553 dev_dbg(&priv->dev->dev,
1554 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1555 priv->dev->vendor, priv->dev->device,
1556 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1557
1558 return pci_default_setup(priv, board, port, idx);
1559 }
1560
1561 static void kt_handle_break(struct uart_port *p)
1562 {
1563 struct uart_8250_port *up =
1564 container_of(p, struct uart_8250_port, port);
1565 /*
1566 * On receipt of a BI, serial device in Intel ME (Intel
1567 * management engine) needs to have its fifos cleared for sane
1568 * SOL (Serial Over Lan) output.
1569 */
1570 serial8250_clear_and_reinit_fifos(up);
1571 }
1572
1573 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1574 {
1575 struct uart_8250_port *up =
1576 container_of(p, struct uart_8250_port, port);
1577 unsigned int val;
1578
1579 /*
1580 * When the Intel ME (management engine) gets reset its serial
1581 * port registers could return 0 momentarily. Functions like
1582 * serial8250_console_write, read and save the IER, perform
1583 * some operation and then restore it. In order to avoid
1584 * setting IER register inadvertently to 0, if the value read
1585 * is 0, double check with ier value in uart_8250_port and use
1586 * that instead. up->ier should be the same value as what is
1587 * currently configured.
1588 */
1589 val = inb(p->iobase + offset);
1590 if (offset == UART_IER) {
1591 if (val == 0)
1592 val = up->ier;
1593 }
1594 return val;
1595 }
1596
1597 static int kt_serial_setup(struct serial_private *priv,
1598 const struct pciserial_board *board,
1599 struct uart_8250_port *port, int idx)
1600 {
1601 port->port.flags |= UPF_BUG_THRE;
1602 port->port.serial_in = kt_serial_in;
1603 port->port.handle_break = kt_handle_break;
1604 return skip_tx_en_setup(priv, board, port, idx);
1605 }
1606
1607 static int pci_eg20t_init(struct pci_dev *dev)
1608 {
1609 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1610 return -ENODEV;
1611 #else
1612 return 0;
1613 #endif
1614 }
1615
1616 static int
1617 pci_xr17c154_setup(struct serial_private *priv,
1618 const struct pciserial_board *board,
1619 struct uart_8250_port *port, int idx)
1620 {
1621 port->port.flags |= UPF_EXAR_EFR;
1622 return pci_default_setup(priv, board, port, idx);
1623 }
1624
1625 static int
1626 pci_xr17v35x_setup(struct serial_private *priv,
1627 const struct pciserial_board *board,
1628 struct uart_8250_port *port, int idx)
1629 {
1630 u8 __iomem *p;
1631
1632 p = pci_ioremap_bar(priv->dev, 0);
1633 if (p == NULL)
1634 return -ENOMEM;
1635
1636 port->port.flags |= UPF_EXAR_EFR;
1637
1638 /*
1639 * Setup Multipurpose Input/Output pins.
1640 */
1641 if (idx == 0) {
1642 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1643 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1644 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1645 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1646 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1647 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1648 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1649 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1650 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1651 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1652 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1653 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1654 }
1655 writeb(0x00, p + UART_EXAR_8XMODE);
1656 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1657 writeb(128, p + UART_EXAR_TXTRG);
1658 writeb(128, p + UART_EXAR_RXTRG);
1659 iounmap(p);
1660
1661 return pci_default_setup(priv, board, port, idx);
1662 }
1663
1664 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1665 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1666 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1667 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1668
1669 static int
1670 pci_fastcom335_setup(struct serial_private *priv,
1671 const struct pciserial_board *board,
1672 struct uart_8250_port *port, int idx)
1673 {
1674 u8 __iomem *p;
1675
1676 p = pci_ioremap_bar(priv->dev, 0);
1677 if (p == NULL)
1678 return -ENOMEM;
1679
1680 port->port.flags |= UPF_EXAR_EFR;
1681
1682 /*
1683 * Setup Multipurpose Input/Output pins.
1684 */
1685 if (idx == 0) {
1686 switch (priv->dev->device) {
1687 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1688 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1689 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1690 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1691 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1692 break;
1693 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1694 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1695 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1696 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1697 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1698 break;
1699 }
1700 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1701 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1702 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1703 }
1704 writeb(0x00, p + UART_EXAR_8XMODE);
1705 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1706 writeb(32, p + UART_EXAR_TXTRG);
1707 writeb(32, p + UART_EXAR_RXTRG);
1708 iounmap(p);
1709
1710 return pci_default_setup(priv, board, port, idx);
1711 }
1712
1713 static int
1714 pci_wch_ch353_setup(struct serial_private *priv,
1715 const struct pciserial_board *board,
1716 struct uart_8250_port *port, int idx)
1717 {
1718 port->port.flags |= UPF_FIXED_TYPE;
1719 port->port.type = PORT_16550A;
1720 return pci_default_setup(priv, board, port, idx);
1721 }
1722
1723 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1724 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1725 #define PCI_DEVICE_ID_OCTPRO 0x0001
1726 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1727 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1728 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1729 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1730 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1731 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1732 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1733 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1734 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1735 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1736 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1737 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1738 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1739 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1740 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1741 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1742 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1743 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1744 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1745 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1746 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1747 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1748 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1749 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1750 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1751 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1752 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1753 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1754 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1755 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1756 #define PCI_VENDOR_ID_WCH 0x4348
1757 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1758 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1759 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1760 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1761 #define PCI_VENDOR_ID_AGESTAR 0x5372
1762 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1763 #define PCI_VENDOR_ID_ASIX 0x9710
1764 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1765 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1766 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1767 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1768 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1769 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1770
1771 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1772 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1773
1774
1775 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1776
1777 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1778 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1779 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1780
1781 /*
1782 * Master list of serial port init/setup/exit quirks.
1783 * This does not describe the general nature of the port.
1784 * (ie, baud base, number and location of ports, etc)
1785 *
1786 * This list is ordered alphabetically by vendor then device.
1787 * Specific entries must come before more generic entries.
1788 */
1789 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1790 /*
1791 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1792 */
1793 {
1794 .vendor = PCI_VENDOR_ID_AMCC,
1795 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1796 .subvendor = PCI_ANY_ID,
1797 .subdevice = PCI_ANY_ID,
1798 .setup = addidata_apci7800_setup,
1799 },
1800 /*
1801 * AFAVLAB cards - these may be called via parport_serial
1802 * It is not clear whether this applies to all products.
1803 */
1804 {
1805 .vendor = PCI_VENDOR_ID_AFAVLAB,
1806 .device = PCI_ANY_ID,
1807 .subvendor = PCI_ANY_ID,
1808 .subdevice = PCI_ANY_ID,
1809 .setup = afavlab_setup,
1810 },
1811 /*
1812 * HP Diva
1813 */
1814 {
1815 .vendor = PCI_VENDOR_ID_HP,
1816 .device = PCI_DEVICE_ID_HP_DIVA,
1817 .subvendor = PCI_ANY_ID,
1818 .subdevice = PCI_ANY_ID,
1819 .init = pci_hp_diva_init,
1820 .setup = pci_hp_diva_setup,
1821 },
1822 /*
1823 * Intel
1824 */
1825 {
1826 .vendor = PCI_VENDOR_ID_INTEL,
1827 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1828 .subvendor = 0xe4bf,
1829 .subdevice = PCI_ANY_ID,
1830 .init = pci_inteli960ni_init,
1831 .setup = pci_default_setup,
1832 },
1833 {
1834 .vendor = PCI_VENDOR_ID_INTEL,
1835 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1836 .subvendor = PCI_ANY_ID,
1837 .subdevice = PCI_ANY_ID,
1838 .setup = skip_tx_en_setup,
1839 },
1840 {
1841 .vendor = PCI_VENDOR_ID_INTEL,
1842 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1843 .subvendor = PCI_ANY_ID,
1844 .subdevice = PCI_ANY_ID,
1845 .setup = skip_tx_en_setup,
1846 },
1847 {
1848 .vendor = PCI_VENDOR_ID_INTEL,
1849 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1850 .subvendor = PCI_ANY_ID,
1851 .subdevice = PCI_ANY_ID,
1852 .setup = skip_tx_en_setup,
1853 },
1854 {
1855 .vendor = PCI_VENDOR_ID_INTEL,
1856 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1857 .subvendor = PCI_ANY_ID,
1858 .subdevice = PCI_ANY_ID,
1859 .setup = ce4100_serial_setup,
1860 },
1861 {
1862 .vendor = PCI_VENDOR_ID_INTEL,
1863 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1864 .subvendor = PCI_ANY_ID,
1865 .subdevice = PCI_ANY_ID,
1866 .setup = kt_serial_setup,
1867 },
1868 {
1869 .vendor = PCI_VENDOR_ID_INTEL,
1870 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1871 .subvendor = PCI_ANY_ID,
1872 .subdevice = PCI_ANY_ID,
1873 .setup = byt_serial_setup,
1874 },
1875 {
1876 .vendor = PCI_VENDOR_ID_INTEL,
1877 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1878 .subvendor = PCI_ANY_ID,
1879 .subdevice = PCI_ANY_ID,
1880 .setup = byt_serial_setup,
1881 },
1882 {
1883 .vendor = PCI_VENDOR_ID_INTEL,
1884 .device = PCI_DEVICE_ID_INTEL_QRK_UART,
1885 .subvendor = PCI_ANY_ID,
1886 .subdevice = PCI_ANY_ID,
1887 .setup = pci_default_setup,
1888 },
1889 /*
1890 * ITE
1891 */
1892 {
1893 .vendor = PCI_VENDOR_ID_ITE,
1894 .device = PCI_DEVICE_ID_ITE_8872,
1895 .subvendor = PCI_ANY_ID,
1896 .subdevice = PCI_ANY_ID,
1897 .init = pci_ite887x_init,
1898 .setup = pci_default_setup,
1899 .exit = pci_ite887x_exit,
1900 },
1901 /*
1902 * National Instruments
1903 */
1904 {
1905 .vendor = PCI_VENDOR_ID_NI,
1906 .device = PCI_DEVICE_ID_NI_PCI23216,
1907 .subvendor = PCI_ANY_ID,
1908 .subdevice = PCI_ANY_ID,
1909 .init = pci_ni8420_init,
1910 .setup = pci_default_setup,
1911 .exit = pci_ni8420_exit,
1912 },
1913 {
1914 .vendor = PCI_VENDOR_ID_NI,
1915 .device = PCI_DEVICE_ID_NI_PCI2328,
1916 .subvendor = PCI_ANY_ID,
1917 .subdevice = PCI_ANY_ID,
1918 .init = pci_ni8420_init,
1919 .setup = pci_default_setup,
1920 .exit = pci_ni8420_exit,
1921 },
1922 {
1923 .vendor = PCI_VENDOR_ID_NI,
1924 .device = PCI_DEVICE_ID_NI_PCI2324,
1925 .subvendor = PCI_ANY_ID,
1926 .subdevice = PCI_ANY_ID,
1927 .init = pci_ni8420_init,
1928 .setup = pci_default_setup,
1929 .exit = pci_ni8420_exit,
1930 },
1931 {
1932 .vendor = PCI_VENDOR_ID_NI,
1933 .device = PCI_DEVICE_ID_NI_PCI2322,
1934 .subvendor = PCI_ANY_ID,
1935 .subdevice = PCI_ANY_ID,
1936 .init = pci_ni8420_init,
1937 .setup = pci_default_setup,
1938 .exit = pci_ni8420_exit,
1939 },
1940 {
1941 .vendor = PCI_VENDOR_ID_NI,
1942 .device = PCI_DEVICE_ID_NI_PCI2324I,
1943 .subvendor = PCI_ANY_ID,
1944 .subdevice = PCI_ANY_ID,
1945 .init = pci_ni8420_init,
1946 .setup = pci_default_setup,
1947 .exit = pci_ni8420_exit,
1948 },
1949 {
1950 .vendor = PCI_VENDOR_ID_NI,
1951 .device = PCI_DEVICE_ID_NI_PCI2322I,
1952 .subvendor = PCI_ANY_ID,
1953 .subdevice = PCI_ANY_ID,
1954 .init = pci_ni8420_init,
1955 .setup = pci_default_setup,
1956 .exit = pci_ni8420_exit,
1957 },
1958 {
1959 .vendor = PCI_VENDOR_ID_NI,
1960 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1961 .subvendor = PCI_ANY_ID,
1962 .subdevice = PCI_ANY_ID,
1963 .init = pci_ni8420_init,
1964 .setup = pci_default_setup,
1965 .exit = pci_ni8420_exit,
1966 },
1967 {
1968 .vendor = PCI_VENDOR_ID_NI,
1969 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1970 .subvendor = PCI_ANY_ID,
1971 .subdevice = PCI_ANY_ID,
1972 .init = pci_ni8420_init,
1973 .setup = pci_default_setup,
1974 .exit = pci_ni8420_exit,
1975 },
1976 {
1977 .vendor = PCI_VENDOR_ID_NI,
1978 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1979 .subvendor = PCI_ANY_ID,
1980 .subdevice = PCI_ANY_ID,
1981 .init = pci_ni8420_init,
1982 .setup = pci_default_setup,
1983 .exit = pci_ni8420_exit,
1984 },
1985 {
1986 .vendor = PCI_VENDOR_ID_NI,
1987 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1988 .subvendor = PCI_ANY_ID,
1989 .subdevice = PCI_ANY_ID,
1990 .init = pci_ni8420_init,
1991 .setup = pci_default_setup,
1992 .exit = pci_ni8420_exit,
1993 },
1994 {
1995 .vendor = PCI_VENDOR_ID_NI,
1996 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1997 .subvendor = PCI_ANY_ID,
1998 .subdevice = PCI_ANY_ID,
1999 .init = pci_ni8420_init,
2000 .setup = pci_default_setup,
2001 .exit = pci_ni8420_exit,
2002 },
2003 {
2004 .vendor = PCI_VENDOR_ID_NI,
2005 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2006 .subvendor = PCI_ANY_ID,
2007 .subdevice = PCI_ANY_ID,
2008 .init = pci_ni8420_init,
2009 .setup = pci_default_setup,
2010 .exit = pci_ni8420_exit,
2011 },
2012 {
2013 .vendor = PCI_VENDOR_ID_NI,
2014 .device = PCI_ANY_ID,
2015 .subvendor = PCI_ANY_ID,
2016 .subdevice = PCI_ANY_ID,
2017 .init = pci_ni8430_init,
2018 .setup = pci_ni8430_setup,
2019 .exit = pci_ni8430_exit,
2020 },
2021 /* Quatech */
2022 {
2023 .vendor = PCI_VENDOR_ID_QUATECH,
2024 .device = PCI_ANY_ID,
2025 .subvendor = PCI_ANY_ID,
2026 .subdevice = PCI_ANY_ID,
2027 .init = pci_quatech_init,
2028 .setup = pci_quatech_setup,
2029 .exit = pci_quatech_exit,
2030 },
2031 /*
2032 * Panacom
2033 */
2034 {
2035 .vendor = PCI_VENDOR_ID_PANACOM,
2036 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2037 .subvendor = PCI_ANY_ID,
2038 .subdevice = PCI_ANY_ID,
2039 .init = pci_plx9050_init,
2040 .setup = pci_default_setup,
2041 .exit = pci_plx9050_exit,
2042 },
2043 {
2044 .vendor = PCI_VENDOR_ID_PANACOM,
2045 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2046 .subvendor = PCI_ANY_ID,
2047 .subdevice = PCI_ANY_ID,
2048 .init = pci_plx9050_init,
2049 .setup = pci_default_setup,
2050 .exit = pci_plx9050_exit,
2051 },
2052 /*
2053 * Pericom
2054 */
2055 {
2056 .vendor = 0x12d8,
2057 .device = 0x7952,
2058 .subvendor = PCI_ANY_ID,
2059 .subdevice = PCI_ANY_ID,
2060 .setup = pci_pericom_setup,
2061 },
2062 {
2063 .vendor = 0x12d8,
2064 .device = 0x7954,
2065 .subvendor = PCI_ANY_ID,
2066 .subdevice = PCI_ANY_ID,
2067 .setup = pci_pericom_setup,
2068 },
2069 {
2070 .vendor = 0x12d8,
2071 .device = 0x7958,
2072 .subvendor = PCI_ANY_ID,
2073 .subdevice = PCI_ANY_ID,
2074 .setup = pci_pericom_setup,
2075 },
2076
2077 /*
2078 * PLX
2079 */
2080 {
2081 .vendor = PCI_VENDOR_ID_PLX,
2082 .device = PCI_DEVICE_ID_PLX_9030,
2083 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2084 .subdevice = PCI_ANY_ID,
2085 .setup = pci_default_setup,
2086 },
2087 {
2088 .vendor = PCI_VENDOR_ID_PLX,
2089 .device = PCI_DEVICE_ID_PLX_9050,
2090 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2091 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2092 .init = pci_plx9050_init,
2093 .setup = pci_default_setup,
2094 .exit = pci_plx9050_exit,
2095 },
2096 {
2097 .vendor = PCI_VENDOR_ID_PLX,
2098 .device = PCI_DEVICE_ID_PLX_9050,
2099 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2100 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2101 .init = pci_plx9050_init,
2102 .setup = pci_default_setup,
2103 .exit = pci_plx9050_exit,
2104 },
2105 {
2106 .vendor = PCI_VENDOR_ID_PLX,
2107 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2108 .subvendor = PCI_VENDOR_ID_PLX,
2109 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2110 .init = pci_plx9050_init,
2111 .setup = pci_default_setup,
2112 .exit = pci_plx9050_exit,
2113 },
2114 /*
2115 * SBS Technologies, Inc., PMC-OCTALPRO 232
2116 */
2117 {
2118 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2119 .device = PCI_DEVICE_ID_OCTPRO,
2120 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2121 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2122 .init = sbs_init,
2123 .setup = sbs_setup,
2124 .exit = sbs_exit,
2125 },
2126 /*
2127 * SBS Technologies, Inc., PMC-OCTALPRO 422
2128 */
2129 {
2130 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2131 .device = PCI_DEVICE_ID_OCTPRO,
2132 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2133 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2134 .init = sbs_init,
2135 .setup = sbs_setup,
2136 .exit = sbs_exit,
2137 },
2138 /*
2139 * SBS Technologies, Inc., P-Octal 232
2140 */
2141 {
2142 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2143 .device = PCI_DEVICE_ID_OCTPRO,
2144 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2145 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2146 .init = sbs_init,
2147 .setup = sbs_setup,
2148 .exit = sbs_exit,
2149 },
2150 /*
2151 * SBS Technologies, Inc., P-Octal 422
2152 */
2153 {
2154 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2155 .device = PCI_DEVICE_ID_OCTPRO,
2156 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2157 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2158 .init = sbs_init,
2159 .setup = sbs_setup,
2160 .exit = sbs_exit,
2161 },
2162 /*
2163 * SIIG cards - these may be called via parport_serial
2164 */
2165 {
2166 .vendor = PCI_VENDOR_ID_SIIG,
2167 .device = PCI_ANY_ID,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .init = pci_siig_init,
2171 .setup = pci_siig_setup,
2172 },
2173 /*
2174 * Titan cards
2175 */
2176 {
2177 .vendor = PCI_VENDOR_ID_TITAN,
2178 .device = PCI_DEVICE_ID_TITAN_400L,
2179 .subvendor = PCI_ANY_ID,
2180 .subdevice = PCI_ANY_ID,
2181 .setup = titan_400l_800l_setup,
2182 },
2183 {
2184 .vendor = PCI_VENDOR_ID_TITAN,
2185 .device = PCI_DEVICE_ID_TITAN_800L,
2186 .subvendor = PCI_ANY_ID,
2187 .subdevice = PCI_ANY_ID,
2188 .setup = titan_400l_800l_setup,
2189 },
2190 /*
2191 * Timedia cards
2192 */
2193 {
2194 .vendor = PCI_VENDOR_ID_TIMEDIA,
2195 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2196 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2197 .subdevice = PCI_ANY_ID,
2198 .probe = pci_timedia_probe,
2199 .init = pci_timedia_init,
2200 .setup = pci_timedia_setup,
2201 },
2202 {
2203 .vendor = PCI_VENDOR_ID_TIMEDIA,
2204 .device = PCI_ANY_ID,
2205 .subvendor = PCI_ANY_ID,
2206 .subdevice = PCI_ANY_ID,
2207 .setup = pci_timedia_setup,
2208 },
2209 /*
2210 * SUNIX (Timedia) cards
2211 * Do not "probe" for these cards as there is at least one combination
2212 * card that should be handled by parport_pc that doesn't match the
2213 * rule in pci_timedia_probe.
2214 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2215 * There are some boards with part number SER5037AL that report
2216 * subdevice ID 0x0002.
2217 */
2218 {
2219 .vendor = PCI_VENDOR_ID_SUNIX,
2220 .device = PCI_DEVICE_ID_SUNIX_1999,
2221 .subvendor = PCI_VENDOR_ID_SUNIX,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_timedia_init,
2224 .setup = pci_timedia_setup,
2225 },
2226 /*
2227 * Exar cards
2228 */
2229 {
2230 .vendor = PCI_VENDOR_ID_EXAR,
2231 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .setup = pci_xr17c154_setup,
2235 },
2236 {
2237 .vendor = PCI_VENDOR_ID_EXAR,
2238 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .setup = pci_xr17c154_setup,
2242 },
2243 {
2244 .vendor = PCI_VENDOR_ID_EXAR,
2245 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = pci_xr17c154_setup,
2249 },
2250 {
2251 .vendor = PCI_VENDOR_ID_EXAR,
2252 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = pci_xr17v35x_setup,
2256 },
2257 {
2258 .vendor = PCI_VENDOR_ID_EXAR,
2259 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2260 .subvendor = PCI_ANY_ID,
2261 .subdevice = PCI_ANY_ID,
2262 .setup = pci_xr17v35x_setup,
2263 },
2264 {
2265 .vendor = PCI_VENDOR_ID_EXAR,
2266 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2267 .subvendor = PCI_ANY_ID,
2268 .subdevice = PCI_ANY_ID,
2269 .setup = pci_xr17v35x_setup,
2270 },
2271 {
2272 .vendor = PCI_VENDOR_ID_EXAR,
2273 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2274 .subvendor = PCI_ANY_ID,
2275 .subdevice = PCI_ANY_ID,
2276 .setup = pci_xr17v35x_setup,
2277 },
2278 /*
2279 * Xircom cards
2280 */
2281 {
2282 .vendor = PCI_VENDOR_ID_XIRCOM,
2283 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .init = pci_xircom_init,
2287 .setup = pci_default_setup,
2288 },
2289 /*
2290 * Netmos cards - these may be called via parport_serial
2291 */
2292 {
2293 .vendor = PCI_VENDOR_ID_NETMOS,
2294 .device = PCI_ANY_ID,
2295 .subvendor = PCI_ANY_ID,
2296 .subdevice = PCI_ANY_ID,
2297 .init = pci_netmos_init,
2298 .setup = pci_netmos_9900_setup,
2299 },
2300 /*
2301 * For Oxford Semiconductor Tornado based devices
2302 */
2303 {
2304 .vendor = PCI_VENDOR_ID_OXSEMI,
2305 .device = PCI_ANY_ID,
2306 .subvendor = PCI_ANY_ID,
2307 .subdevice = PCI_ANY_ID,
2308 .init = pci_oxsemi_tornado_init,
2309 .setup = pci_default_setup,
2310 },
2311 {
2312 .vendor = PCI_VENDOR_ID_MAINPINE,
2313 .device = PCI_ANY_ID,
2314 .subvendor = PCI_ANY_ID,
2315 .subdevice = PCI_ANY_ID,
2316 .init = pci_oxsemi_tornado_init,
2317 .setup = pci_default_setup,
2318 },
2319 {
2320 .vendor = PCI_VENDOR_ID_DIGI,
2321 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2322 .subvendor = PCI_SUBVENDOR_ID_IBM,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_oxsemi_tornado_init,
2325 .setup = pci_default_setup,
2326 },
2327 {
2328 .vendor = PCI_VENDOR_ID_INTEL,
2329 .device = 0x8811,
2330 .subvendor = PCI_ANY_ID,
2331 .subdevice = PCI_ANY_ID,
2332 .init = pci_eg20t_init,
2333 .setup = pci_default_setup,
2334 },
2335 {
2336 .vendor = PCI_VENDOR_ID_INTEL,
2337 .device = 0x8812,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .init = pci_eg20t_init,
2341 .setup = pci_default_setup,
2342 },
2343 {
2344 .vendor = PCI_VENDOR_ID_INTEL,
2345 .device = 0x8813,
2346 .subvendor = PCI_ANY_ID,
2347 .subdevice = PCI_ANY_ID,
2348 .init = pci_eg20t_init,
2349 .setup = pci_default_setup,
2350 },
2351 {
2352 .vendor = PCI_VENDOR_ID_INTEL,
2353 .device = 0x8814,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .init = pci_eg20t_init,
2357 .setup = pci_default_setup,
2358 },
2359 {
2360 .vendor = 0x10DB,
2361 .device = 0x8027,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .init = pci_eg20t_init,
2365 .setup = pci_default_setup,
2366 },
2367 {
2368 .vendor = 0x10DB,
2369 .device = 0x8028,
2370 .subvendor = PCI_ANY_ID,
2371 .subdevice = PCI_ANY_ID,
2372 .init = pci_eg20t_init,
2373 .setup = pci_default_setup,
2374 },
2375 {
2376 .vendor = 0x10DB,
2377 .device = 0x8029,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .init = pci_eg20t_init,
2381 .setup = pci_default_setup,
2382 },
2383 {
2384 .vendor = 0x10DB,
2385 .device = 0x800C,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .init = pci_eg20t_init,
2389 .setup = pci_default_setup,
2390 },
2391 {
2392 .vendor = 0x10DB,
2393 .device = 0x800D,
2394 .subvendor = PCI_ANY_ID,
2395 .subdevice = PCI_ANY_ID,
2396 .init = pci_eg20t_init,
2397 .setup = pci_default_setup,
2398 },
2399 /*
2400 * Cronyx Omega PCI (PLX-chip based)
2401 */
2402 {
2403 .vendor = PCI_VENDOR_ID_PLX,
2404 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2405 .subvendor = PCI_ANY_ID,
2406 .subdevice = PCI_ANY_ID,
2407 .setup = pci_omegapci_setup,
2408 },
2409 /* WCH CH353 2S1P card (16550 clone) */
2410 {
2411 .vendor = PCI_VENDOR_ID_WCH,
2412 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2413 .subvendor = PCI_ANY_ID,
2414 .subdevice = PCI_ANY_ID,
2415 .setup = pci_wch_ch353_setup,
2416 },
2417 /* WCH CH353 4S card (16550 clone) */
2418 {
2419 .vendor = PCI_VENDOR_ID_WCH,
2420 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = pci_wch_ch353_setup,
2424 },
2425 /* WCH CH353 2S1PF card (16550 clone) */
2426 {
2427 .vendor = PCI_VENDOR_ID_WCH,
2428 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2429 .subvendor = PCI_ANY_ID,
2430 .subdevice = PCI_ANY_ID,
2431 .setup = pci_wch_ch353_setup,
2432 },
2433 /* WCH CH352 2S card (16550 clone) */
2434 {
2435 .vendor = PCI_VENDOR_ID_WCH,
2436 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2437 .subvendor = PCI_ANY_ID,
2438 .subdevice = PCI_ANY_ID,
2439 .setup = pci_wch_ch353_setup,
2440 },
2441 /*
2442 * ASIX devices with FIFO bug
2443 */
2444 {
2445 .vendor = PCI_VENDOR_ID_ASIX,
2446 .device = PCI_ANY_ID,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_asix_setup,
2450 },
2451 /*
2452 * Commtech, Inc. Fastcom adapters
2453 *
2454 */
2455 {
2456 .vendor = PCI_VENDOR_ID_COMMTECH,
2457 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2458 .subvendor = PCI_ANY_ID,
2459 .subdevice = PCI_ANY_ID,
2460 .setup = pci_fastcom335_setup,
2461 },
2462 {
2463 .vendor = PCI_VENDOR_ID_COMMTECH,
2464 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2465 .subvendor = PCI_ANY_ID,
2466 .subdevice = PCI_ANY_ID,
2467 .setup = pci_fastcom335_setup,
2468 },
2469 {
2470 .vendor = PCI_VENDOR_ID_COMMTECH,
2471 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2472 .subvendor = PCI_ANY_ID,
2473 .subdevice = PCI_ANY_ID,
2474 .setup = pci_fastcom335_setup,
2475 },
2476 {
2477 .vendor = PCI_VENDOR_ID_COMMTECH,
2478 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2479 .subvendor = PCI_ANY_ID,
2480 .subdevice = PCI_ANY_ID,
2481 .setup = pci_fastcom335_setup,
2482 },
2483 {
2484 .vendor = PCI_VENDOR_ID_COMMTECH,
2485 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2486 .subvendor = PCI_ANY_ID,
2487 .subdevice = PCI_ANY_ID,
2488 .setup = pci_xr17v35x_setup,
2489 },
2490 {
2491 .vendor = PCI_VENDOR_ID_COMMTECH,
2492 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2493 .subvendor = PCI_ANY_ID,
2494 .subdevice = PCI_ANY_ID,
2495 .setup = pci_xr17v35x_setup,
2496 },
2497 {
2498 .vendor = PCI_VENDOR_ID_COMMTECH,
2499 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2500 .subvendor = PCI_ANY_ID,
2501 .subdevice = PCI_ANY_ID,
2502 .setup = pci_xr17v35x_setup,
2503 },
2504 /*
2505 * Broadcom TruManage (NetXtreme)
2506 */
2507 {
2508 .vendor = PCI_VENDOR_ID_BROADCOM,
2509 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .setup = pci_brcm_trumanage_setup,
2513 },
2514 {
2515 .vendor = 0x1c29,
2516 .device = 0x1104,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .setup = pci_fintek_setup,
2520 },
2521 {
2522 .vendor = 0x1c29,
2523 .device = 0x1108,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .setup = pci_fintek_setup,
2527 },
2528 {
2529 .vendor = 0x1c29,
2530 .device = 0x1112,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .setup = pci_fintek_setup,
2534 },
2535
2536 /*
2537 * Default "match everything" terminator entry
2538 */
2539 {
2540 .vendor = PCI_ANY_ID,
2541 .device = PCI_ANY_ID,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .setup = pci_default_setup,
2545 }
2546 };
2547
2548 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2549 {
2550 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2551 }
2552
2553 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2554 {
2555 struct pci_serial_quirk *quirk;
2556
2557 for (quirk = pci_serial_quirks; ; quirk++)
2558 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2559 quirk_id_matches(quirk->device, dev->device) &&
2560 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2561 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2562 break;
2563 return quirk;
2564 }
2565
2566 static inline int get_pci_irq(struct pci_dev *dev,
2567 const struct pciserial_board *board)
2568 {
2569 if (board->flags & FL_NOIRQ)
2570 return 0;
2571 else
2572 return dev->irq;
2573 }
2574
2575 /*
2576 * This is the configuration table for all of the PCI serial boards
2577 * which we support. It is directly indexed by the pci_board_num_t enum
2578 * value, which is encoded in the pci_device_id PCI probe table's
2579 * driver_data member.
2580 *
2581 * The makeup of these names are:
2582 * pbn_bn{_bt}_n_baud{_offsetinhex}
2583 *
2584 * bn = PCI BAR number
2585 * bt = Index using PCI BARs
2586 * n = number of serial ports
2587 * baud = baud rate
2588 * offsetinhex = offset for each sequential port (in hex)
2589 *
2590 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2591 *
2592 * Please note: in theory if n = 1, _bt infix should make no difference.
2593 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2594 */
2595 enum pci_board_num_t {
2596 pbn_default = 0,
2597
2598 pbn_b0_1_115200,
2599 pbn_b0_2_115200,
2600 pbn_b0_4_115200,
2601 pbn_b0_5_115200,
2602 pbn_b0_8_115200,
2603
2604 pbn_b0_1_921600,
2605 pbn_b0_2_921600,
2606 pbn_b0_4_921600,
2607
2608 pbn_b0_2_1130000,
2609
2610 pbn_b0_4_1152000,
2611
2612 pbn_b0_2_1152000_200,
2613 pbn_b0_4_1152000_200,
2614 pbn_b0_8_1152000_200,
2615
2616 pbn_b0_2_1843200,
2617 pbn_b0_4_1843200,
2618
2619 pbn_b0_2_1843200_200,
2620 pbn_b0_4_1843200_200,
2621 pbn_b0_8_1843200_200,
2622
2623 pbn_b0_1_4000000,
2624
2625 pbn_b0_bt_1_115200,
2626 pbn_b0_bt_2_115200,
2627 pbn_b0_bt_4_115200,
2628 pbn_b0_bt_8_115200,
2629
2630 pbn_b0_bt_1_460800,
2631 pbn_b0_bt_2_460800,
2632 pbn_b0_bt_4_460800,
2633
2634 pbn_b0_bt_1_921600,
2635 pbn_b0_bt_2_921600,
2636 pbn_b0_bt_4_921600,
2637 pbn_b0_bt_8_921600,
2638
2639 pbn_b1_1_115200,
2640 pbn_b1_2_115200,
2641 pbn_b1_4_115200,
2642 pbn_b1_8_115200,
2643 pbn_b1_16_115200,
2644
2645 pbn_b1_1_921600,
2646 pbn_b1_2_921600,
2647 pbn_b1_4_921600,
2648 pbn_b1_8_921600,
2649
2650 pbn_b1_2_1250000,
2651
2652 pbn_b1_bt_1_115200,
2653 pbn_b1_bt_2_115200,
2654 pbn_b1_bt_4_115200,
2655
2656 pbn_b1_bt_2_921600,
2657
2658 pbn_b1_1_1382400,
2659 pbn_b1_2_1382400,
2660 pbn_b1_4_1382400,
2661 pbn_b1_8_1382400,
2662
2663 pbn_b2_1_115200,
2664 pbn_b2_2_115200,
2665 pbn_b2_4_115200,
2666 pbn_b2_8_115200,
2667
2668 pbn_b2_1_460800,
2669 pbn_b2_4_460800,
2670 pbn_b2_8_460800,
2671 pbn_b2_16_460800,
2672
2673 pbn_b2_1_921600,
2674 pbn_b2_4_921600,
2675 pbn_b2_8_921600,
2676
2677 pbn_b2_8_1152000,
2678
2679 pbn_b2_bt_1_115200,
2680 pbn_b2_bt_2_115200,
2681 pbn_b2_bt_4_115200,
2682
2683 pbn_b2_bt_2_921600,
2684 pbn_b2_bt_4_921600,
2685
2686 pbn_b3_2_115200,
2687 pbn_b3_4_115200,
2688 pbn_b3_8_115200,
2689
2690 pbn_b4_bt_2_921600,
2691 pbn_b4_bt_4_921600,
2692 pbn_b4_bt_8_921600,
2693
2694 /*
2695 * Board-specific versions.
2696 */
2697 pbn_panacom,
2698 pbn_panacom2,
2699 pbn_panacom4,
2700 pbn_plx_romulus,
2701 pbn_oxsemi,
2702 pbn_oxsemi_1_4000000,
2703 pbn_oxsemi_2_4000000,
2704 pbn_oxsemi_4_4000000,
2705 pbn_oxsemi_8_4000000,
2706 pbn_intel_i960,
2707 pbn_sgi_ioc3,
2708 pbn_computone_4,
2709 pbn_computone_6,
2710 pbn_computone_8,
2711 pbn_sbsxrsio,
2712 pbn_exar_XR17C152,
2713 pbn_exar_XR17C154,
2714 pbn_exar_XR17C158,
2715 pbn_exar_XR17V352,
2716 pbn_exar_XR17V354,
2717 pbn_exar_XR17V358,
2718 pbn_exar_XR17V8358,
2719 pbn_exar_ibm_saturn,
2720 pbn_pasemi_1682M,
2721 pbn_ni8430_2,
2722 pbn_ni8430_4,
2723 pbn_ni8430_8,
2724 pbn_ni8430_16,
2725 pbn_ADDIDATA_PCIe_1_3906250,
2726 pbn_ADDIDATA_PCIe_2_3906250,
2727 pbn_ADDIDATA_PCIe_4_3906250,
2728 pbn_ADDIDATA_PCIe_8_3906250,
2729 pbn_ce4100_1_115200,
2730 pbn_byt,
2731 pbn_qrk,
2732 pbn_omegapci,
2733 pbn_NETMOS9900_2s_115200,
2734 pbn_brcm_trumanage,
2735 pbn_fintek_4,
2736 pbn_fintek_8,
2737 pbn_fintek_12,
2738 };
2739
2740 /*
2741 * uart_offset - the space between channels
2742 * reg_shift - describes how the UART registers are mapped
2743 * to PCI memory by the card.
2744 * For example IER register on SBS, Inc. PMC-OctPro is located at
2745 * offset 0x10 from the UART base, while UART_IER is defined as 1
2746 * in include/linux/serial_reg.h,
2747 * see first lines of serial_in() and serial_out() in 8250.c
2748 */
2749
2750 static struct pciserial_board pci_boards[] = {
2751 [pbn_default] = {
2752 .flags = FL_BASE0,
2753 .num_ports = 1,
2754 .base_baud = 115200,
2755 .uart_offset = 8,
2756 },
2757 [pbn_b0_1_115200] = {
2758 .flags = FL_BASE0,
2759 .num_ports = 1,
2760 .base_baud = 115200,
2761 .uart_offset = 8,
2762 },
2763 [pbn_b0_2_115200] = {
2764 .flags = FL_BASE0,
2765 .num_ports = 2,
2766 .base_baud = 115200,
2767 .uart_offset = 8,
2768 },
2769 [pbn_b0_4_115200] = {
2770 .flags = FL_BASE0,
2771 .num_ports = 4,
2772 .base_baud = 115200,
2773 .uart_offset = 8,
2774 },
2775 [pbn_b0_5_115200] = {
2776 .flags = FL_BASE0,
2777 .num_ports = 5,
2778 .base_baud = 115200,
2779 .uart_offset = 8,
2780 },
2781 [pbn_b0_8_115200] = {
2782 .flags = FL_BASE0,
2783 .num_ports = 8,
2784 .base_baud = 115200,
2785 .uart_offset = 8,
2786 },
2787 [pbn_b0_1_921600] = {
2788 .flags = FL_BASE0,
2789 .num_ports = 1,
2790 .base_baud = 921600,
2791 .uart_offset = 8,
2792 },
2793 [pbn_b0_2_921600] = {
2794 .flags = FL_BASE0,
2795 .num_ports = 2,
2796 .base_baud = 921600,
2797 .uart_offset = 8,
2798 },
2799 [pbn_b0_4_921600] = {
2800 .flags = FL_BASE0,
2801 .num_ports = 4,
2802 .base_baud = 921600,
2803 .uart_offset = 8,
2804 },
2805
2806 [pbn_b0_2_1130000] = {
2807 .flags = FL_BASE0,
2808 .num_ports = 2,
2809 .base_baud = 1130000,
2810 .uart_offset = 8,
2811 },
2812
2813 [pbn_b0_4_1152000] = {
2814 .flags = FL_BASE0,
2815 .num_ports = 4,
2816 .base_baud = 1152000,
2817 .uart_offset = 8,
2818 },
2819
2820 [pbn_b0_2_1152000_200] = {
2821 .flags = FL_BASE0,
2822 .num_ports = 2,
2823 .base_baud = 1152000,
2824 .uart_offset = 0x200,
2825 },
2826
2827 [pbn_b0_4_1152000_200] = {
2828 .flags = FL_BASE0,
2829 .num_ports = 4,
2830 .base_baud = 1152000,
2831 .uart_offset = 0x200,
2832 },
2833
2834 [pbn_b0_8_1152000_200] = {
2835 .flags = FL_BASE0,
2836 .num_ports = 8,
2837 .base_baud = 1152000,
2838 .uart_offset = 0x200,
2839 },
2840
2841 [pbn_b0_2_1843200] = {
2842 .flags = FL_BASE0,
2843 .num_ports = 2,
2844 .base_baud = 1843200,
2845 .uart_offset = 8,
2846 },
2847 [pbn_b0_4_1843200] = {
2848 .flags = FL_BASE0,
2849 .num_ports = 4,
2850 .base_baud = 1843200,
2851 .uart_offset = 8,
2852 },
2853
2854 [pbn_b0_2_1843200_200] = {
2855 .flags = FL_BASE0,
2856 .num_ports = 2,
2857 .base_baud = 1843200,
2858 .uart_offset = 0x200,
2859 },
2860 [pbn_b0_4_1843200_200] = {
2861 .flags = FL_BASE0,
2862 .num_ports = 4,
2863 .base_baud = 1843200,
2864 .uart_offset = 0x200,
2865 },
2866 [pbn_b0_8_1843200_200] = {
2867 .flags = FL_BASE0,
2868 .num_ports = 8,
2869 .base_baud = 1843200,
2870 .uart_offset = 0x200,
2871 },
2872 [pbn_b0_1_4000000] = {
2873 .flags = FL_BASE0,
2874 .num_ports = 1,
2875 .base_baud = 4000000,
2876 .uart_offset = 8,
2877 },
2878
2879 [pbn_b0_bt_1_115200] = {
2880 .flags = FL_BASE0|FL_BASE_BARS,
2881 .num_ports = 1,
2882 .base_baud = 115200,
2883 .uart_offset = 8,
2884 },
2885 [pbn_b0_bt_2_115200] = {
2886 .flags = FL_BASE0|FL_BASE_BARS,
2887 .num_ports = 2,
2888 .base_baud = 115200,
2889 .uart_offset = 8,
2890 },
2891 [pbn_b0_bt_4_115200] = {
2892 .flags = FL_BASE0|FL_BASE_BARS,
2893 .num_ports = 4,
2894 .base_baud = 115200,
2895 .uart_offset = 8,
2896 },
2897 [pbn_b0_bt_8_115200] = {
2898 .flags = FL_BASE0|FL_BASE_BARS,
2899 .num_ports = 8,
2900 .base_baud = 115200,
2901 .uart_offset = 8,
2902 },
2903
2904 [pbn_b0_bt_1_460800] = {
2905 .flags = FL_BASE0|FL_BASE_BARS,
2906 .num_ports = 1,
2907 .base_baud = 460800,
2908 .uart_offset = 8,
2909 },
2910 [pbn_b0_bt_2_460800] = {
2911 .flags = FL_BASE0|FL_BASE_BARS,
2912 .num_ports = 2,
2913 .base_baud = 460800,
2914 .uart_offset = 8,
2915 },
2916 [pbn_b0_bt_4_460800] = {
2917 .flags = FL_BASE0|FL_BASE_BARS,
2918 .num_ports = 4,
2919 .base_baud = 460800,
2920 .uart_offset = 8,
2921 },
2922
2923 [pbn_b0_bt_1_921600] = {
2924 .flags = FL_BASE0|FL_BASE_BARS,
2925 .num_ports = 1,
2926 .base_baud = 921600,
2927 .uart_offset = 8,
2928 },
2929 [pbn_b0_bt_2_921600] = {
2930 .flags = FL_BASE0|FL_BASE_BARS,
2931 .num_ports = 2,
2932 .base_baud = 921600,
2933 .uart_offset = 8,
2934 },
2935 [pbn_b0_bt_4_921600] = {
2936 .flags = FL_BASE0|FL_BASE_BARS,
2937 .num_ports = 4,
2938 .base_baud = 921600,
2939 .uart_offset = 8,
2940 },
2941 [pbn_b0_bt_8_921600] = {
2942 .flags = FL_BASE0|FL_BASE_BARS,
2943 .num_ports = 8,
2944 .base_baud = 921600,
2945 .uart_offset = 8,
2946 },
2947
2948 [pbn_b1_1_115200] = {
2949 .flags = FL_BASE1,
2950 .num_ports = 1,
2951 .base_baud = 115200,
2952 .uart_offset = 8,
2953 },
2954 [pbn_b1_2_115200] = {
2955 .flags = FL_BASE1,
2956 .num_ports = 2,
2957 .base_baud = 115200,
2958 .uart_offset = 8,
2959 },
2960 [pbn_b1_4_115200] = {
2961 .flags = FL_BASE1,
2962 .num_ports = 4,
2963 .base_baud = 115200,
2964 .uart_offset = 8,
2965 },
2966 [pbn_b1_8_115200] = {
2967 .flags = FL_BASE1,
2968 .num_ports = 8,
2969 .base_baud = 115200,
2970 .uart_offset = 8,
2971 },
2972 [pbn_b1_16_115200] = {
2973 .flags = FL_BASE1,
2974 .num_ports = 16,
2975 .base_baud = 115200,
2976 .uart_offset = 8,
2977 },
2978
2979 [pbn_b1_1_921600] = {
2980 .flags = FL_BASE1,
2981 .num_ports = 1,
2982 .base_baud = 921600,
2983 .uart_offset = 8,
2984 },
2985 [pbn_b1_2_921600] = {
2986 .flags = FL_BASE1,
2987 .num_ports = 2,
2988 .base_baud = 921600,
2989 .uart_offset = 8,
2990 },
2991 [pbn_b1_4_921600] = {
2992 .flags = FL_BASE1,
2993 .num_ports = 4,
2994 .base_baud = 921600,
2995 .uart_offset = 8,
2996 },
2997 [pbn_b1_8_921600] = {
2998 .flags = FL_BASE1,
2999 .num_ports = 8,
3000 .base_baud = 921600,
3001 .uart_offset = 8,
3002 },
3003 [pbn_b1_2_1250000] = {
3004 .flags = FL_BASE1,
3005 .num_ports = 2,
3006 .base_baud = 1250000,
3007 .uart_offset = 8,
3008 },
3009
3010 [pbn_b1_bt_1_115200] = {
3011 .flags = FL_BASE1|FL_BASE_BARS,
3012 .num_ports = 1,
3013 .base_baud = 115200,
3014 .uart_offset = 8,
3015 },
3016 [pbn_b1_bt_2_115200] = {
3017 .flags = FL_BASE1|FL_BASE_BARS,
3018 .num_ports = 2,
3019 .base_baud = 115200,
3020 .uart_offset = 8,
3021 },
3022 [pbn_b1_bt_4_115200] = {
3023 .flags = FL_BASE1|FL_BASE_BARS,
3024 .num_ports = 4,
3025 .base_baud = 115200,
3026 .uart_offset = 8,
3027 },
3028
3029 [pbn_b1_bt_2_921600] = {
3030 .flags = FL_BASE1|FL_BASE_BARS,
3031 .num_ports = 2,
3032 .base_baud = 921600,
3033 .uart_offset = 8,
3034 },
3035
3036 [pbn_b1_1_1382400] = {
3037 .flags = FL_BASE1,
3038 .num_ports = 1,
3039 .base_baud = 1382400,
3040 .uart_offset = 8,
3041 },
3042 [pbn_b1_2_1382400] = {
3043 .flags = FL_BASE1,
3044 .num_ports = 2,
3045 .base_baud = 1382400,
3046 .uart_offset = 8,
3047 },
3048 [pbn_b1_4_1382400] = {
3049 .flags = FL_BASE1,
3050 .num_ports = 4,
3051 .base_baud = 1382400,
3052 .uart_offset = 8,
3053 },
3054 [pbn_b1_8_1382400] = {
3055 .flags = FL_BASE1,
3056 .num_ports = 8,
3057 .base_baud = 1382400,
3058 .uart_offset = 8,
3059 },
3060
3061 [pbn_b2_1_115200] = {
3062 .flags = FL_BASE2,
3063 .num_ports = 1,
3064 .base_baud = 115200,
3065 .uart_offset = 8,
3066 },
3067 [pbn_b2_2_115200] = {
3068 .flags = FL_BASE2,
3069 .num_ports = 2,
3070 .base_baud = 115200,
3071 .uart_offset = 8,
3072 },
3073 [pbn_b2_4_115200] = {
3074 .flags = FL_BASE2,
3075 .num_ports = 4,
3076 .base_baud = 115200,
3077 .uart_offset = 8,
3078 },
3079 [pbn_b2_8_115200] = {
3080 .flags = FL_BASE2,
3081 .num_ports = 8,
3082 .base_baud = 115200,
3083 .uart_offset = 8,
3084 },
3085
3086 [pbn_b2_1_460800] = {
3087 .flags = FL_BASE2,
3088 .num_ports = 1,
3089 .base_baud = 460800,
3090 .uart_offset = 8,
3091 },
3092 [pbn_b2_4_460800] = {
3093 .flags = FL_BASE2,
3094 .num_ports = 4,
3095 .base_baud = 460800,
3096 .uart_offset = 8,
3097 },
3098 [pbn_b2_8_460800] = {
3099 .flags = FL_BASE2,
3100 .num_ports = 8,
3101 .base_baud = 460800,
3102 .uart_offset = 8,
3103 },
3104 [pbn_b2_16_460800] = {
3105 .flags = FL_BASE2,
3106 .num_ports = 16,
3107 .base_baud = 460800,
3108 .uart_offset = 8,
3109 },
3110
3111 [pbn_b2_1_921600] = {
3112 .flags = FL_BASE2,
3113 .num_ports = 1,
3114 .base_baud = 921600,
3115 .uart_offset = 8,
3116 },
3117 [pbn_b2_4_921600] = {
3118 .flags = FL_BASE2,
3119 .num_ports = 4,
3120 .base_baud = 921600,
3121 .uart_offset = 8,
3122 },
3123 [pbn_b2_8_921600] = {
3124 .flags = FL_BASE2,
3125 .num_ports = 8,
3126 .base_baud = 921600,
3127 .uart_offset = 8,
3128 },
3129
3130 [pbn_b2_8_1152000] = {
3131 .flags = FL_BASE2,
3132 .num_ports = 8,
3133 .base_baud = 1152000,
3134 .uart_offset = 8,
3135 },
3136
3137 [pbn_b2_bt_1_115200] = {
3138 .flags = FL_BASE2|FL_BASE_BARS,
3139 .num_ports = 1,
3140 .base_baud = 115200,
3141 .uart_offset = 8,
3142 },
3143 [pbn_b2_bt_2_115200] = {
3144 .flags = FL_BASE2|FL_BASE_BARS,
3145 .num_ports = 2,
3146 .base_baud = 115200,
3147 .uart_offset = 8,
3148 },
3149 [pbn_b2_bt_4_115200] = {
3150 .flags = FL_BASE2|FL_BASE_BARS,
3151 .num_ports = 4,
3152 .base_baud = 115200,
3153 .uart_offset = 8,
3154 },
3155
3156 [pbn_b2_bt_2_921600] = {
3157 .flags = FL_BASE2|FL_BASE_BARS,
3158 .num_ports = 2,
3159 .base_baud = 921600,
3160 .uart_offset = 8,
3161 },
3162 [pbn_b2_bt_4_921600] = {
3163 .flags = FL_BASE2|FL_BASE_BARS,
3164 .num_ports = 4,
3165 .base_baud = 921600,
3166 .uart_offset = 8,
3167 },
3168
3169 [pbn_b3_2_115200] = {
3170 .flags = FL_BASE3,
3171 .num_ports = 2,
3172 .base_baud = 115200,
3173 .uart_offset = 8,
3174 },
3175 [pbn_b3_4_115200] = {
3176 .flags = FL_BASE3,
3177 .num_ports = 4,
3178 .base_baud = 115200,
3179 .uart_offset = 8,
3180 },
3181 [pbn_b3_8_115200] = {
3182 .flags = FL_BASE3,
3183 .num_ports = 8,
3184 .base_baud = 115200,
3185 .uart_offset = 8,
3186 },
3187
3188 [pbn_b4_bt_2_921600] = {
3189 .flags = FL_BASE4,
3190 .num_ports = 2,
3191 .base_baud = 921600,
3192 .uart_offset = 8,
3193 },
3194 [pbn_b4_bt_4_921600] = {
3195 .flags = FL_BASE4,
3196 .num_ports = 4,
3197 .base_baud = 921600,
3198 .uart_offset = 8,
3199 },
3200 [pbn_b4_bt_8_921600] = {
3201 .flags = FL_BASE4,
3202 .num_ports = 8,
3203 .base_baud = 921600,
3204 .uart_offset = 8,
3205 },
3206
3207 /*
3208 * Entries following this are board-specific.
3209 */
3210
3211 /*
3212 * Panacom - IOMEM
3213 */
3214 [pbn_panacom] = {
3215 .flags = FL_BASE2,
3216 .num_ports = 2,
3217 .base_baud = 921600,
3218 .uart_offset = 0x400,
3219 .reg_shift = 7,
3220 },
3221 [pbn_panacom2] = {
3222 .flags = FL_BASE2|FL_BASE_BARS,
3223 .num_ports = 2,
3224 .base_baud = 921600,
3225 .uart_offset = 0x400,
3226 .reg_shift = 7,
3227 },
3228 [pbn_panacom4] = {
3229 .flags = FL_BASE2|FL_BASE_BARS,
3230 .num_ports = 4,
3231 .base_baud = 921600,
3232 .uart_offset = 0x400,
3233 .reg_shift = 7,
3234 },
3235
3236 /* I think this entry is broken - the first_offset looks wrong --rmk */
3237 [pbn_plx_romulus] = {
3238 .flags = FL_BASE2,
3239 .num_ports = 4,
3240 .base_baud = 921600,
3241 .uart_offset = 8 << 2,
3242 .reg_shift = 2,
3243 .first_offset = 0x03,
3244 },
3245
3246 /*
3247 * This board uses the size of PCI Base region 0 to
3248 * signal now many ports are available
3249 */
3250 [pbn_oxsemi] = {
3251 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3252 .num_ports = 32,
3253 .base_baud = 115200,
3254 .uart_offset = 8,
3255 },
3256 [pbn_oxsemi_1_4000000] = {
3257 .flags = FL_BASE0,
3258 .num_ports = 1,
3259 .base_baud = 4000000,
3260 .uart_offset = 0x200,
3261 .first_offset = 0x1000,
3262 },
3263 [pbn_oxsemi_2_4000000] = {
3264 .flags = FL_BASE0,
3265 .num_ports = 2,
3266 .base_baud = 4000000,
3267 .uart_offset = 0x200,
3268 .first_offset = 0x1000,
3269 },
3270 [pbn_oxsemi_4_4000000] = {
3271 .flags = FL_BASE0,
3272 .num_ports = 4,
3273 .base_baud = 4000000,
3274 .uart_offset = 0x200,
3275 .first_offset = 0x1000,
3276 },
3277 [pbn_oxsemi_8_4000000] = {
3278 .flags = FL_BASE0,
3279 .num_ports = 8,
3280 .base_baud = 4000000,
3281 .uart_offset = 0x200,
3282 .first_offset = 0x1000,
3283 },
3284
3285
3286 /*
3287 * EKF addition for i960 Boards form EKF with serial port.
3288 * Max 256 ports.
3289 */
3290 [pbn_intel_i960] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 32,
3293 .base_baud = 921600,
3294 .uart_offset = 8 << 2,
3295 .reg_shift = 2,
3296 .first_offset = 0x10000,
3297 },
3298 [pbn_sgi_ioc3] = {
3299 .flags = FL_BASE0|FL_NOIRQ,
3300 .num_ports = 1,
3301 .base_baud = 458333,
3302 .uart_offset = 8,
3303 .reg_shift = 0,
3304 .first_offset = 0x20178,
3305 },
3306
3307 /*
3308 * Computone - uses IOMEM.
3309 */
3310 [pbn_computone_4] = {
3311 .flags = FL_BASE0,
3312 .num_ports = 4,
3313 .base_baud = 921600,
3314 .uart_offset = 0x40,
3315 .reg_shift = 2,
3316 .first_offset = 0x200,
3317 },
3318 [pbn_computone_6] = {
3319 .flags = FL_BASE0,
3320 .num_ports = 6,
3321 .base_baud = 921600,
3322 .uart_offset = 0x40,
3323 .reg_shift = 2,
3324 .first_offset = 0x200,
3325 },
3326 [pbn_computone_8] = {
3327 .flags = FL_BASE0,
3328 .num_ports = 8,
3329 .base_baud = 921600,
3330 .uart_offset = 0x40,
3331 .reg_shift = 2,
3332 .first_offset = 0x200,
3333 },
3334 [pbn_sbsxrsio] = {
3335 .flags = FL_BASE0,
3336 .num_ports = 8,
3337 .base_baud = 460800,
3338 .uart_offset = 256,
3339 .reg_shift = 4,
3340 },
3341 /*
3342 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3343 * Only basic 16550A support.
3344 * XR17C15[24] are not tested, but they should work.
3345 */
3346 [pbn_exar_XR17C152] = {
3347 .flags = FL_BASE0,
3348 .num_ports = 2,
3349 .base_baud = 921600,
3350 .uart_offset = 0x200,
3351 },
3352 [pbn_exar_XR17C154] = {
3353 .flags = FL_BASE0,
3354 .num_ports = 4,
3355 .base_baud = 921600,
3356 .uart_offset = 0x200,
3357 },
3358 [pbn_exar_XR17C158] = {
3359 .flags = FL_BASE0,
3360 .num_ports = 8,
3361 .base_baud = 921600,
3362 .uart_offset = 0x200,
3363 },
3364 [pbn_exar_XR17V352] = {
3365 .flags = FL_BASE0,
3366 .num_ports = 2,
3367 .base_baud = 7812500,
3368 .uart_offset = 0x400,
3369 .reg_shift = 0,
3370 .first_offset = 0,
3371 },
3372 [pbn_exar_XR17V354] = {
3373 .flags = FL_BASE0,
3374 .num_ports = 4,
3375 .base_baud = 7812500,
3376 .uart_offset = 0x400,
3377 .reg_shift = 0,
3378 .first_offset = 0,
3379 },
3380 [pbn_exar_XR17V358] = {
3381 .flags = FL_BASE0,
3382 .num_ports = 8,
3383 .base_baud = 7812500,
3384 .uart_offset = 0x400,
3385 .reg_shift = 0,
3386 .first_offset = 0,
3387 },
3388 [pbn_exar_XR17V8358] = {
3389 .flags = FL_BASE0,
3390 .num_ports = 16,
3391 .base_baud = 7812500,
3392 .uart_offset = 0x400,
3393 .reg_shift = 0,
3394 .first_offset = 0,
3395 },
3396 [pbn_exar_ibm_saturn] = {
3397 .flags = FL_BASE0,
3398 .num_ports = 1,
3399 .base_baud = 921600,
3400 .uart_offset = 0x200,
3401 },
3402
3403 /*
3404 * PA Semi PWRficient PA6T-1682M on-chip UART
3405 */
3406 [pbn_pasemi_1682M] = {
3407 .flags = FL_BASE0,
3408 .num_ports = 1,
3409 .base_baud = 8333333,
3410 },
3411 /*
3412 * National Instruments 843x
3413 */
3414 [pbn_ni8430_16] = {
3415 .flags = FL_BASE0,
3416 .num_ports = 16,
3417 .base_baud = 3686400,
3418 .uart_offset = 0x10,
3419 .first_offset = 0x800,
3420 },
3421 [pbn_ni8430_8] = {
3422 .flags = FL_BASE0,
3423 .num_ports = 8,
3424 .base_baud = 3686400,
3425 .uart_offset = 0x10,
3426 .first_offset = 0x800,
3427 },
3428 [pbn_ni8430_4] = {
3429 .flags = FL_BASE0,
3430 .num_ports = 4,
3431 .base_baud = 3686400,
3432 .uart_offset = 0x10,
3433 .first_offset = 0x800,
3434 },
3435 [pbn_ni8430_2] = {
3436 .flags = FL_BASE0,
3437 .num_ports = 2,
3438 .base_baud = 3686400,
3439 .uart_offset = 0x10,
3440 .first_offset = 0x800,
3441 },
3442 /*
3443 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3444 */
3445 [pbn_ADDIDATA_PCIe_1_3906250] = {
3446 .flags = FL_BASE0,
3447 .num_ports = 1,
3448 .base_baud = 3906250,
3449 .uart_offset = 0x200,
3450 .first_offset = 0x1000,
3451 },
3452 [pbn_ADDIDATA_PCIe_2_3906250] = {
3453 .flags = FL_BASE0,
3454 .num_ports = 2,
3455 .base_baud = 3906250,
3456 .uart_offset = 0x200,
3457 .first_offset = 0x1000,
3458 },
3459 [pbn_ADDIDATA_PCIe_4_3906250] = {
3460 .flags = FL_BASE0,
3461 .num_ports = 4,
3462 .base_baud = 3906250,
3463 .uart_offset = 0x200,
3464 .first_offset = 0x1000,
3465 },
3466 [pbn_ADDIDATA_PCIe_8_3906250] = {
3467 .flags = FL_BASE0,
3468 .num_ports = 8,
3469 .base_baud = 3906250,
3470 .uart_offset = 0x200,
3471 .first_offset = 0x1000,
3472 },
3473 [pbn_ce4100_1_115200] = {
3474 .flags = FL_BASE_BARS,
3475 .num_ports = 2,
3476 .base_baud = 921600,
3477 .reg_shift = 2,
3478 },
3479 [pbn_byt] = {
3480 .flags = FL_BASE0,
3481 .num_ports = 1,
3482 .base_baud = 2764800,
3483 .uart_offset = 0x80,
3484 .reg_shift = 2,
3485 },
3486 [pbn_qrk] = {
3487 .flags = FL_BASE0,
3488 .num_ports = 1,
3489 .base_baud = 2764800,
3490 .reg_shift = 2,
3491 },
3492 [pbn_omegapci] = {
3493 .flags = FL_BASE0,
3494 .num_ports = 8,
3495 .base_baud = 115200,
3496 .uart_offset = 0x200,
3497 },
3498 [pbn_NETMOS9900_2s_115200] = {
3499 .flags = FL_BASE0,
3500 .num_ports = 2,
3501 .base_baud = 115200,
3502 },
3503 [pbn_brcm_trumanage] = {
3504 .flags = FL_BASE0,
3505 .num_ports = 1,
3506 .reg_shift = 2,
3507 .base_baud = 115200,
3508 },
3509 [pbn_fintek_4] = {
3510 .num_ports = 4,
3511 .uart_offset = 8,
3512 .base_baud = 115200,
3513 .first_offset = 0x40,
3514 },
3515 [pbn_fintek_8] = {
3516 .num_ports = 8,
3517 .uart_offset = 8,
3518 .base_baud = 115200,
3519 .first_offset = 0x40,
3520 },
3521 [pbn_fintek_12] = {
3522 .num_ports = 12,
3523 .uart_offset = 8,
3524 .base_baud = 115200,
3525 .first_offset = 0x40,
3526 },
3527 };
3528
3529 static const struct pci_device_id blacklist[] = {
3530 /* softmodems */
3531 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3532 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3533 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3534
3535 /* multi-io cards handled by parport_serial */
3536 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3537 };
3538
3539 /*
3540 * Given a complete unknown PCI device, try to use some heuristics to
3541 * guess what the configuration might be, based on the pitiful PCI
3542 * serial specs. Returns 0 on success, 1 on failure.
3543 */
3544 static int
3545 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3546 {
3547 const struct pci_device_id *bldev;
3548 int num_iomem, num_port, first_port = -1, i;
3549
3550 /*
3551 * If it is not a communications device or the programming
3552 * interface is greater than 6, give up.
3553 *
3554 * (Should we try to make guesses for multiport serial devices
3555 * later?)
3556 */
3557 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3558 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3559 (dev->class & 0xff) > 6)
3560 return -ENODEV;
3561
3562 /*
3563 * Do not access blacklisted devices that are known not to
3564 * feature serial ports or are handled by other modules.
3565 */
3566 for (bldev = blacklist;
3567 bldev < blacklist + ARRAY_SIZE(blacklist);
3568 bldev++) {
3569 if (dev->vendor == bldev->vendor &&
3570 dev->device == bldev->device)
3571 return -ENODEV;
3572 }
3573
3574 num_iomem = num_port = 0;
3575 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3576 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3577 num_port++;
3578 if (first_port == -1)
3579 first_port = i;
3580 }
3581 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3582 num_iomem++;
3583 }
3584
3585 /*
3586 * If there is 1 or 0 iomem regions, and exactly one port,
3587 * use it. We guess the number of ports based on the IO
3588 * region size.
3589 */
3590 if (num_iomem <= 1 && num_port == 1) {
3591 board->flags = first_port;
3592 board->num_ports = pci_resource_len(dev, first_port) / 8;
3593 return 0;
3594 }
3595
3596 /*
3597 * Now guess if we've got a board which indexes by BARs.
3598 * Each IO BAR should be 8 bytes, and they should follow
3599 * consecutively.
3600 */
3601 first_port = -1;
3602 num_port = 0;
3603 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3604 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3605 pci_resource_len(dev, i) == 8 &&
3606 (first_port == -1 || (first_port + num_port) == i)) {
3607 num_port++;
3608 if (first_port == -1)
3609 first_port = i;
3610 }
3611 }
3612
3613 if (num_port > 1) {
3614 board->flags = first_port | FL_BASE_BARS;
3615 board->num_ports = num_port;
3616 return 0;
3617 }
3618
3619 return -ENODEV;
3620 }
3621
3622 static inline int
3623 serial_pci_matches(const struct pciserial_board *board,
3624 const struct pciserial_board *guessed)
3625 {
3626 return
3627 board->num_ports == guessed->num_ports &&
3628 board->base_baud == guessed->base_baud &&
3629 board->uart_offset == guessed->uart_offset &&
3630 board->reg_shift == guessed->reg_shift &&
3631 board->first_offset == guessed->first_offset;
3632 }
3633
3634 struct serial_private *
3635 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3636 {
3637 struct uart_8250_port uart;
3638 struct serial_private *priv;
3639 struct pci_serial_quirk *quirk;
3640 int rc, nr_ports, i;
3641
3642 nr_ports = board->num_ports;
3643
3644 /*
3645 * Find an init and setup quirks.
3646 */
3647 quirk = find_quirk(dev);
3648
3649 /*
3650 * Run the new-style initialization function.
3651 * The initialization function returns:
3652 * <0 - error
3653 * 0 - use board->num_ports
3654 * >0 - number of ports
3655 */
3656 if (quirk->init) {
3657 rc = quirk->init(dev);
3658 if (rc < 0) {
3659 priv = ERR_PTR(rc);
3660 goto err_out;
3661 }
3662 if (rc)
3663 nr_ports = rc;
3664 }
3665
3666 priv = kzalloc(sizeof(struct serial_private) +
3667 sizeof(unsigned int) * nr_ports,
3668 GFP_KERNEL);
3669 if (!priv) {
3670 priv = ERR_PTR(-ENOMEM);
3671 goto err_deinit;
3672 }
3673
3674 priv->dev = dev;
3675 priv->quirk = quirk;
3676
3677 memset(&uart, 0, sizeof(uart));
3678 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3679 uart.port.uartclk = board->base_baud * 16;
3680 uart.port.irq = get_pci_irq(dev, board);
3681 uart.port.dev = &dev->dev;
3682
3683 for (i = 0; i < nr_ports; i++) {
3684 if (quirk->setup(priv, board, &uart, i))
3685 break;
3686
3687 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3688 uart.port.iobase, uart.port.irq, uart.port.iotype);
3689
3690 priv->line[i] = serial8250_register_8250_port(&uart);
3691 if (priv->line[i] < 0) {
3692 dev_err(&dev->dev,
3693 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3694 uart.port.iobase, uart.port.irq,
3695 uart.port.iotype, priv->line[i]);
3696 break;
3697 }
3698 }
3699 priv->nr = i;
3700 return priv;
3701
3702 err_deinit:
3703 if (quirk->exit)
3704 quirk->exit(dev);
3705 err_out:
3706 return priv;
3707 }
3708 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3709
3710 void pciserial_remove_ports(struct serial_private *priv)
3711 {
3712 struct pci_serial_quirk *quirk;
3713 int i;
3714
3715 for (i = 0; i < priv->nr; i++)
3716 serial8250_unregister_port(priv->line[i]);
3717
3718 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3719 if (priv->remapped_bar[i])
3720 iounmap(priv->remapped_bar[i]);
3721 priv->remapped_bar[i] = NULL;
3722 }
3723
3724 /*
3725 * Find the exit quirks.
3726 */
3727 quirk = find_quirk(priv->dev);
3728 if (quirk->exit)
3729 quirk->exit(priv->dev);
3730
3731 kfree(priv);
3732 }
3733 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3734
3735 void pciserial_suspend_ports(struct serial_private *priv)
3736 {
3737 int i;
3738
3739 for (i = 0; i < priv->nr; i++)
3740 if (priv->line[i] >= 0)
3741 serial8250_suspend_port(priv->line[i]);
3742
3743 /*
3744 * Ensure that every init quirk is properly torn down
3745 */
3746 if (priv->quirk->exit)
3747 priv->quirk->exit(priv->dev);
3748 }
3749 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3750
3751 void pciserial_resume_ports(struct serial_private *priv)
3752 {
3753 int i;
3754
3755 /*
3756 * Ensure that the board is correctly configured.
3757 */
3758 if (priv->quirk->init)
3759 priv->quirk->init(priv->dev);
3760
3761 for (i = 0; i < priv->nr; i++)
3762 if (priv->line[i] >= 0)
3763 serial8250_resume_port(priv->line[i]);
3764 }
3765 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3766
3767 /*
3768 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3769 * to the arrangement of serial ports on a PCI card.
3770 */
3771 static int
3772 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3773 {
3774 struct pci_serial_quirk *quirk;
3775 struct serial_private *priv;
3776 const struct pciserial_board *board;
3777 struct pciserial_board tmp;
3778 int rc;
3779
3780 quirk = find_quirk(dev);
3781 if (quirk->probe) {
3782 rc = quirk->probe(dev);
3783 if (rc)
3784 return rc;
3785 }
3786
3787 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3788 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3789 ent->driver_data);
3790 return -EINVAL;
3791 }
3792
3793 board = &pci_boards[ent->driver_data];
3794
3795 rc = pci_enable_device(dev);
3796 pci_save_state(dev);
3797 if (rc)
3798 return rc;
3799
3800 if (ent->driver_data == pbn_default) {
3801 /*
3802 * Use a copy of the pci_board entry for this;
3803 * avoid changing entries in the table.
3804 */
3805 memcpy(&tmp, board, sizeof(struct pciserial_board));
3806 board = &tmp;
3807
3808 /*
3809 * We matched one of our class entries. Try to
3810 * determine the parameters of this board.
3811 */
3812 rc = serial_pci_guess_board(dev, &tmp);
3813 if (rc)
3814 goto disable;
3815 } else {
3816 /*
3817 * We matched an explicit entry. If we are able to
3818 * detect this boards settings with our heuristic,
3819 * then we no longer need this entry.
3820 */
3821 memcpy(&tmp, &pci_boards[pbn_default],
3822 sizeof(struct pciserial_board));
3823 rc = serial_pci_guess_board(dev, &tmp);
3824 if (rc == 0 && serial_pci_matches(board, &tmp))
3825 moan_device("Redundant entry in serial pci_table.",
3826 dev);
3827 }
3828
3829 priv = pciserial_init_ports(dev, board);
3830 if (!IS_ERR(priv)) {
3831 pci_set_drvdata(dev, priv);
3832 return 0;
3833 }
3834
3835 rc = PTR_ERR(priv);
3836
3837 disable:
3838 pci_disable_device(dev);
3839 return rc;
3840 }
3841
3842 static void pciserial_remove_one(struct pci_dev *dev)
3843 {
3844 struct serial_private *priv = pci_get_drvdata(dev);
3845
3846 pciserial_remove_ports(priv);
3847
3848 pci_disable_device(dev);
3849 }
3850
3851 #ifdef CONFIG_PM
3852 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3853 {
3854 struct serial_private *priv = pci_get_drvdata(dev);
3855
3856 if (priv)
3857 pciserial_suspend_ports(priv);
3858
3859 pci_save_state(dev);
3860 pci_set_power_state(dev, pci_choose_state(dev, state));
3861 return 0;
3862 }
3863
3864 static int pciserial_resume_one(struct pci_dev *dev)
3865 {
3866 int err;
3867 struct serial_private *priv = pci_get_drvdata(dev);
3868
3869 pci_set_power_state(dev, PCI_D0);
3870 pci_restore_state(dev);
3871
3872 if (priv) {
3873 /*
3874 * The device may have been disabled. Re-enable it.
3875 */
3876 err = pci_enable_device(dev);
3877 /* FIXME: We cannot simply error out here */
3878 if (err)
3879 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3880 pciserial_resume_ports(priv);
3881 }
3882 return 0;
3883 }
3884 #endif
3885
3886 static struct pci_device_id serial_pci_tbl[] = {
3887 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3888 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3889 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3890 pbn_b2_8_921600 },
3891 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3892 PCI_SUBVENDOR_ID_CONNECT_TECH,
3893 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3894 pbn_b1_8_1382400 },
3895 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3896 PCI_SUBVENDOR_ID_CONNECT_TECH,
3897 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3898 pbn_b1_4_1382400 },
3899 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3900 PCI_SUBVENDOR_ID_CONNECT_TECH,
3901 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3902 pbn_b1_2_1382400 },
3903 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3904 PCI_SUBVENDOR_ID_CONNECT_TECH,
3905 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3906 pbn_b1_8_1382400 },
3907 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3908 PCI_SUBVENDOR_ID_CONNECT_TECH,
3909 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3910 pbn_b1_4_1382400 },
3911 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3912 PCI_SUBVENDOR_ID_CONNECT_TECH,
3913 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3914 pbn_b1_2_1382400 },
3915 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3916 PCI_SUBVENDOR_ID_CONNECT_TECH,
3917 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3918 pbn_b1_8_921600 },
3919 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3920 PCI_SUBVENDOR_ID_CONNECT_TECH,
3921 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3922 pbn_b1_8_921600 },
3923 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3924 PCI_SUBVENDOR_ID_CONNECT_TECH,
3925 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3926 pbn_b1_4_921600 },
3927 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3928 PCI_SUBVENDOR_ID_CONNECT_TECH,
3929 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3930 pbn_b1_4_921600 },
3931 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3932 PCI_SUBVENDOR_ID_CONNECT_TECH,
3933 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3934 pbn_b1_2_921600 },
3935 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3936 PCI_SUBVENDOR_ID_CONNECT_TECH,
3937 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3938 pbn_b1_8_921600 },
3939 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3940 PCI_SUBVENDOR_ID_CONNECT_TECH,
3941 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3942 pbn_b1_8_921600 },
3943 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3944 PCI_SUBVENDOR_ID_CONNECT_TECH,
3945 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3946 pbn_b1_4_921600 },
3947 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3948 PCI_SUBVENDOR_ID_CONNECT_TECH,
3949 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3950 pbn_b1_2_1250000 },
3951 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3952 PCI_SUBVENDOR_ID_CONNECT_TECH,
3953 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3954 pbn_b0_2_1843200 },
3955 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3956 PCI_SUBVENDOR_ID_CONNECT_TECH,
3957 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3958 pbn_b0_4_1843200 },
3959 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3960 PCI_VENDOR_ID_AFAVLAB,
3961 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3962 pbn_b0_4_1152000 },
3963 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3964 PCI_SUBVENDOR_ID_CONNECT_TECH,
3965 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3966 pbn_b0_2_1843200_200 },
3967 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3968 PCI_SUBVENDOR_ID_CONNECT_TECH,
3969 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3970 pbn_b0_4_1843200_200 },
3971 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3972 PCI_SUBVENDOR_ID_CONNECT_TECH,
3973 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3974 pbn_b0_8_1843200_200 },
3975 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3976 PCI_SUBVENDOR_ID_CONNECT_TECH,
3977 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3978 pbn_b0_2_1843200_200 },
3979 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3980 PCI_SUBVENDOR_ID_CONNECT_TECH,
3981 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3982 pbn_b0_4_1843200_200 },
3983 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3984 PCI_SUBVENDOR_ID_CONNECT_TECH,
3985 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3986 pbn_b0_8_1843200_200 },
3987 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3988 PCI_SUBVENDOR_ID_CONNECT_TECH,
3989 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3990 pbn_b0_2_1843200_200 },
3991 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3992 PCI_SUBVENDOR_ID_CONNECT_TECH,
3993 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3994 pbn_b0_4_1843200_200 },
3995 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3996 PCI_SUBVENDOR_ID_CONNECT_TECH,
3997 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3998 pbn_b0_8_1843200_200 },
3999 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4000 PCI_SUBVENDOR_ID_CONNECT_TECH,
4001 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4002 pbn_b0_2_1843200_200 },
4003 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4004 PCI_SUBVENDOR_ID_CONNECT_TECH,
4005 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4006 pbn_b0_4_1843200_200 },
4007 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4008 PCI_SUBVENDOR_ID_CONNECT_TECH,
4009 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4010 pbn_b0_8_1843200_200 },
4011 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4012 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4013 0, 0, pbn_exar_ibm_saturn },
4014
4015 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4017 pbn_b2_bt_1_115200 },
4018 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4020 pbn_b2_bt_2_115200 },
4021 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4023 pbn_b2_bt_4_115200 },
4024 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4026 pbn_b2_bt_2_115200 },
4027 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4029 pbn_b2_bt_4_115200 },
4030 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4032 pbn_b2_8_115200 },
4033 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4035 pbn_b2_8_460800 },
4036 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4038 pbn_b2_8_115200 },
4039
4040 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4042 pbn_b2_bt_2_115200 },
4043 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4045 pbn_b2_bt_2_921600 },
4046 /*
4047 * VScom SPCOM800, from sl@s.pl
4048 */
4049 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4051 pbn_b2_8_921600 },
4052 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4054 pbn_b2_4_921600 },
4055 /* Unknown card - subdevice 0x1584 */
4056 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4057 PCI_VENDOR_ID_PLX,
4058 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4059 pbn_b2_4_115200 },
4060 /* Unknown card - subdevice 0x1588 */
4061 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4062 PCI_VENDOR_ID_PLX,
4063 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4064 pbn_b2_8_115200 },
4065 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4066 PCI_SUBVENDOR_ID_KEYSPAN,
4067 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4068 pbn_panacom },
4069 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4071 pbn_panacom4 },
4072 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4074 pbn_panacom2 },
4075 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4076 PCI_VENDOR_ID_ESDGMBH,
4077 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4078 pbn_b2_4_115200 },
4079 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4080 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4081 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4082 pbn_b2_4_460800 },
4083 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4084 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4085 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4086 pbn_b2_8_460800 },
4087 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4088 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4089 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4090 pbn_b2_16_460800 },
4091 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4092 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4093 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4094 pbn_b2_16_460800 },
4095 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4096 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4097 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4098 pbn_b2_4_460800 },
4099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4100 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4101 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4102 pbn_b2_8_460800 },
4103 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4104 PCI_SUBVENDOR_ID_EXSYS,
4105 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4106 pbn_b2_4_115200 },
4107 /*
4108 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4109 * (Exoray@isys.ca)
4110 */
4111 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4112 0x10b5, 0x106a, 0, 0,
4113 pbn_plx_romulus },
4114 /*
4115 * Quatech cards. These actually have configurable clocks but for
4116 * now we just use the default.
4117 *
4118 * 100 series are RS232, 200 series RS422,
4119 */
4120 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_b1_4_115200 },
4123 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125 pbn_b1_2_115200 },
4126 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_b2_2_115200 },
4129 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_b1_2_115200 },
4132 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_b2_2_115200 },
4135 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_b1_4_115200 },
4138 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_b1_8_115200 },
4141 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_b1_8_115200 },
4144 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_b1_4_115200 },
4147 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 pbn_b1_2_115200 },
4150 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 pbn_b1_4_115200 },
4153 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 pbn_b1_2_115200 },
4156 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_b2_4_115200 },
4159 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_b2_2_115200 },
4162 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_b2_1_115200 },
4165 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_b2_4_115200 },
4168 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_b2_2_115200 },
4171 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 pbn_b2_1_115200 },
4174 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b0_8_115200 },
4177
4178 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4179 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4180 0, 0,
4181 pbn_b0_4_921600 },
4182 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4183 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4184 0, 0,
4185 pbn_b0_4_1152000 },
4186 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188 pbn_b0_bt_2_921600 },
4189
4190 /*
4191 * The below card is a little controversial since it is the
4192 * subject of a PCI vendor/device ID clash. (See
4193 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4194 * For now just used the hex ID 0x950a.
4195 */
4196 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4197 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4198 0, 0, pbn_b0_2_115200 },
4199 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4200 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4201 0, 0, pbn_b0_2_115200 },
4202 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_b0_2_1130000 },
4205 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4206 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4207 pbn_b0_1_921600 },
4208 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_b0_4_115200 },
4211 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_b0_bt_2_921600 },
4214 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4215 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4216 pbn_b2_8_1152000 },
4217
4218 /*
4219 * Oxford Semiconductor Inc. Tornado PCI express device range.
4220 */
4221 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4223 pbn_b0_1_4000000 },
4224 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226 pbn_b0_1_4000000 },
4227 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229 pbn_oxsemi_1_4000000 },
4230 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232 pbn_oxsemi_1_4000000 },
4233 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 pbn_b0_1_4000000 },
4236 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238 pbn_b0_1_4000000 },
4239 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4241 pbn_oxsemi_1_4000000 },
4242 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244 pbn_oxsemi_1_4000000 },
4245 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247 pbn_b0_1_4000000 },
4248 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250 pbn_b0_1_4000000 },
4251 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4253 pbn_b0_1_4000000 },
4254 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4256 pbn_b0_1_4000000 },
4257 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4259 pbn_oxsemi_2_4000000 },
4260 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262 pbn_oxsemi_2_4000000 },
4263 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265 pbn_oxsemi_4_4000000 },
4266 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268 pbn_oxsemi_4_4000000 },
4269 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271 pbn_oxsemi_8_4000000 },
4272 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274 pbn_oxsemi_8_4000000 },
4275 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277 pbn_oxsemi_1_4000000 },
4278 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280 pbn_oxsemi_1_4000000 },
4281 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283 pbn_oxsemi_1_4000000 },
4284 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_oxsemi_1_4000000 },
4287 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_oxsemi_1_4000000 },
4290 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 pbn_oxsemi_1_4000000 },
4293 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295 pbn_oxsemi_1_4000000 },
4296 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_oxsemi_1_4000000 },
4299 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_oxsemi_1_4000000 },
4302 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304 pbn_oxsemi_1_4000000 },
4305 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 pbn_oxsemi_1_4000000 },
4308 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310 pbn_oxsemi_1_4000000 },
4311 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4313 pbn_oxsemi_1_4000000 },
4314 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 pbn_oxsemi_1_4000000 },
4317 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 pbn_oxsemi_1_4000000 },
4320 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322 pbn_oxsemi_1_4000000 },
4323 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_oxsemi_1_4000000 },
4326 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 pbn_oxsemi_1_4000000 },
4329 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 pbn_oxsemi_1_4000000 },
4332 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 pbn_oxsemi_1_4000000 },
4335 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337 pbn_oxsemi_1_4000000 },
4338 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340 pbn_oxsemi_1_4000000 },
4341 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4343 pbn_oxsemi_1_4000000 },
4344 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346 pbn_oxsemi_1_4000000 },
4347 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349 pbn_oxsemi_1_4000000 },
4350 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4352 pbn_oxsemi_1_4000000 },
4353 /*
4354 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4355 */
4356 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4357 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4358 pbn_oxsemi_1_4000000 },
4359 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4360 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4361 pbn_oxsemi_2_4000000 },
4362 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4363 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4364 pbn_oxsemi_4_4000000 },
4365 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4366 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4367 pbn_oxsemi_8_4000000 },
4368
4369 /*
4370 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4371 */
4372 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4373 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4374 pbn_oxsemi_2_4000000 },
4375
4376 /*
4377 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4378 * from skokodyn@yahoo.com
4379 */
4380 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4381 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4382 pbn_sbsxrsio },
4383 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4384 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4385 pbn_sbsxrsio },
4386 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4387 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4388 pbn_sbsxrsio },
4389 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4390 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4391 pbn_sbsxrsio },
4392
4393 /*
4394 * Digitan DS560-558, from jimd@esoft.com
4395 */
4396 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_b1_1_115200 },
4399
4400 /*
4401 * Titan Electronic cards
4402 * The 400L and 800L have a custom setup quirk.
4403 */
4404 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b0_1_921600 },
4407 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b0_2_921600 },
4410 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b0_4_921600 },
4413 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b0_4_921600 },
4416 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b1_1_921600 },
4419 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b1_bt_2_921600 },
4422 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b0_bt_4_921600 },
4425 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b0_bt_8_921600 },
4428 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_b4_bt_2_921600 },
4431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b4_bt_4_921600 },
4434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b4_bt_8_921600 },
4437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b0_4_921600 },
4440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b0_4_921600 },
4443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_b0_4_921600 },
4446 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_oxsemi_1_4000000 },
4449 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_oxsemi_2_4000000 },
4452 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_oxsemi_4_4000000 },
4455 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_oxsemi_8_4000000 },
4458 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_oxsemi_2_4000000 },
4461 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_oxsemi_2_4000000 },
4464 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_b0_bt_2_921600 },
4467 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_b0_4_921600 },
4470 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_b0_4_921600 },
4473 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_b0_4_921600 },
4476 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b0_4_921600 },
4479
4480 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b2_1_460800 },
4483 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_b2_1_460800 },
4486 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_b2_1_460800 },
4489 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b2_bt_2_921600 },
4492 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_bt_2_921600 },
4495 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b2_bt_2_921600 },
4498 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b2_bt_4_921600 },
4501 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b2_bt_4_921600 },
4504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b2_bt_4_921600 },
4507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_b0_1_921600 },
4510 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b0_1_921600 },
4513 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_b0_1_921600 },
4516 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_b0_bt_2_921600 },
4519 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_b0_bt_2_921600 },
4522 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_b0_bt_2_921600 },
4525 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_b0_bt_4_921600 },
4528 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_b0_bt_4_921600 },
4531 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_b0_bt_4_921600 },
4534 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_b0_bt_8_921600 },
4537 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b0_bt_8_921600 },
4540 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_b0_bt_8_921600 },
4543
4544 /*
4545 * Computone devices submitted by Doug McNash dmcnash@computone.com
4546 */
4547 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4548 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4549 0, 0, pbn_computone_4 },
4550 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4551 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4552 0, 0, pbn_computone_8 },
4553 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4554 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4555 0, 0, pbn_computone_6 },
4556
4557 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_oxsemi },
4560 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4561 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4562 pbn_b0_bt_1_921600 },
4563
4564 /*
4565 * SUNIX (TIMEDIA)
4566 */
4567 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4568 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4569 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4570 pbn_b0_bt_1_921600 },
4571
4572 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4573 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4574 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4575 pbn_b0_bt_1_921600 },
4576
4577 /*
4578 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4579 */
4580 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_b0_bt_8_115200 },
4583 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585 pbn_b0_bt_8_115200 },
4586
4587 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b0_bt_2_115200 },
4590 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b0_bt_2_115200 },
4593 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b0_bt_2_115200 },
4596 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b0_bt_2_115200 },
4599 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b0_bt_2_115200 },
4602 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_b0_bt_4_460800 },
4605 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b0_bt_4_460800 },
4608 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b0_bt_2_460800 },
4611 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b0_bt_2_460800 },
4614 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b0_bt_2_460800 },
4617 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b0_bt_1_115200 },
4620 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b0_bt_1_460800 },
4623
4624 /*
4625 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4626 * Cards are identified by their subsystem vendor IDs, which
4627 * (in hex) match the model number.
4628 *
4629 * Note that JC140x are RS422/485 cards which require ox950
4630 * ACR = 0x10, and as such are not currently fully supported.
4631 */
4632 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4633 0x1204, 0x0004, 0, 0,
4634 pbn_b0_4_921600 },
4635 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4636 0x1208, 0x0004, 0, 0,
4637 pbn_b0_4_921600 },
4638 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4639 0x1402, 0x0002, 0, 0,
4640 pbn_b0_2_921600 }, */
4641 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4642 0x1404, 0x0004, 0, 0,
4643 pbn_b0_4_921600 }, */
4644 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4645 0x1208, 0x0004, 0, 0,
4646 pbn_b0_4_921600 },
4647
4648 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4649 0x1204, 0x0004, 0, 0,
4650 pbn_b0_4_921600 },
4651 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4652 0x1208, 0x0004, 0, 0,
4653 pbn_b0_4_921600 },
4654 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4655 0x1208, 0x0004, 0, 0,
4656 pbn_b0_4_921600 },
4657 /*
4658 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4659 */
4660 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b1_1_1382400 },
4663
4664 /*
4665 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4666 */
4667 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b1_1_1382400 },
4670
4671 /*
4672 * RAStel 2 port modem, gerg@moreton.com.au
4673 */
4674 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_b2_bt_2_115200 },
4677
4678 /*
4679 * EKF addition for i960 Boards form EKF with serial port
4680 */
4681 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4682 0xE4BF, PCI_ANY_ID, 0, 0,
4683 pbn_intel_i960 },
4684
4685 /*
4686 * Xircom Cardbus/Ethernet combos
4687 */
4688 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b0_1_115200 },
4691 /*
4692 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4693 */
4694 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_1_115200 },
4697
4698 /*
4699 * Untested PCI modems, sent in from various folks...
4700 */
4701
4702 /*
4703 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4704 */
4705 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4706 0x1048, 0x1500, 0, 0,
4707 pbn_b1_1_115200 },
4708
4709 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4710 0xFF00, 0, 0, 0,
4711 pbn_sgi_ioc3 },
4712
4713 /*
4714 * HP Diva card
4715 */
4716 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4717 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4718 pbn_b1_1_115200 },
4719 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_b0_5_115200 },
4722 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_b2_1_115200 },
4725
4726 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b3_2_115200 },
4729 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_b3_4_115200 },
4732 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b3_8_115200 },
4735
4736 /*
4737 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4738 */
4739 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4740 PCI_ANY_ID, PCI_ANY_ID,
4741 0,
4742 0, pbn_exar_XR17C152 },
4743 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4744 PCI_ANY_ID, PCI_ANY_ID,
4745 0,
4746 0, pbn_exar_XR17C154 },
4747 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4748 PCI_ANY_ID, PCI_ANY_ID,
4749 0,
4750 0, pbn_exar_XR17C158 },
4751 /*
4752 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
4753 */
4754 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4755 PCI_ANY_ID, PCI_ANY_ID,
4756 0,
4757 0, pbn_exar_XR17V352 },
4758 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4759 PCI_ANY_ID, PCI_ANY_ID,
4760 0,
4761 0, pbn_exar_XR17V354 },
4762 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4763 PCI_ANY_ID, PCI_ANY_ID,
4764 0,
4765 0, pbn_exar_XR17V358 },
4766 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
4767 PCI_ANY_ID, PCI_ANY_ID,
4768 0,
4769 0, pbn_exar_XR17V8358 },
4770 /*
4771 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4772 */
4773 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_b0_1_115200 },
4776 /*
4777 * ITE
4778 */
4779 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4780 PCI_ANY_ID, PCI_ANY_ID,
4781 0, 0,
4782 pbn_b1_bt_1_115200 },
4783
4784 /*
4785 * IntaShield IS-200
4786 */
4787 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4789 pbn_b2_2_115200 },
4790 /*
4791 * IntaShield IS-400
4792 */
4793 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4795 pbn_b2_4_115200 },
4796 /*
4797 * Perle PCI-RAS cards
4798 */
4799 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4800 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4801 0, 0, pbn_b2_4_921600 },
4802 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4803 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4804 0, 0, pbn_b2_8_921600 },
4805
4806 /*
4807 * Mainpine series cards: Fairly standard layout but fools
4808 * parts of the autodetect in some cases and uses otherwise
4809 * unmatched communications subclasses in the PCI Express case
4810 */
4811
4812 { /* RockForceDUO */
4813 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4814 PCI_VENDOR_ID_MAINPINE, 0x0200,
4815 0, 0, pbn_b0_2_115200 },
4816 { /* RockForceQUATRO */
4817 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4818 PCI_VENDOR_ID_MAINPINE, 0x0300,
4819 0, 0, pbn_b0_4_115200 },
4820 { /* RockForceDUO+ */
4821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4822 PCI_VENDOR_ID_MAINPINE, 0x0400,
4823 0, 0, pbn_b0_2_115200 },
4824 { /* RockForceQUATRO+ */
4825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4826 PCI_VENDOR_ID_MAINPINE, 0x0500,
4827 0, 0, pbn_b0_4_115200 },
4828 { /* RockForce+ */
4829 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4830 PCI_VENDOR_ID_MAINPINE, 0x0600,
4831 0, 0, pbn_b0_2_115200 },
4832 { /* RockForce+ */
4833 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4834 PCI_VENDOR_ID_MAINPINE, 0x0700,
4835 0, 0, pbn_b0_4_115200 },
4836 { /* RockForceOCTO+ */
4837 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4838 PCI_VENDOR_ID_MAINPINE, 0x0800,
4839 0, 0, pbn_b0_8_115200 },
4840 { /* RockForceDUO+ */
4841 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4842 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4843 0, 0, pbn_b0_2_115200 },
4844 { /* RockForceQUARTRO+ */
4845 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4846 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4847 0, 0, pbn_b0_4_115200 },
4848 { /* RockForceOCTO+ */
4849 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4850 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4851 0, 0, pbn_b0_8_115200 },
4852 { /* RockForceD1 */
4853 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4854 PCI_VENDOR_ID_MAINPINE, 0x2000,
4855 0, 0, pbn_b0_1_115200 },
4856 { /* RockForceF1 */
4857 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4858 PCI_VENDOR_ID_MAINPINE, 0x2100,
4859 0, 0, pbn_b0_1_115200 },
4860 { /* RockForceD2 */
4861 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4862 PCI_VENDOR_ID_MAINPINE, 0x2200,
4863 0, 0, pbn_b0_2_115200 },
4864 { /* RockForceF2 */
4865 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4866 PCI_VENDOR_ID_MAINPINE, 0x2300,
4867 0, 0, pbn_b0_2_115200 },
4868 { /* RockForceD4 */
4869 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870 PCI_VENDOR_ID_MAINPINE, 0x2400,
4871 0, 0, pbn_b0_4_115200 },
4872 { /* RockForceF4 */
4873 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874 PCI_VENDOR_ID_MAINPINE, 0x2500,
4875 0, 0, pbn_b0_4_115200 },
4876 { /* RockForceD8 */
4877 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4878 PCI_VENDOR_ID_MAINPINE, 0x2600,
4879 0, 0, pbn_b0_8_115200 },
4880 { /* RockForceF8 */
4881 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4882 PCI_VENDOR_ID_MAINPINE, 0x2700,
4883 0, 0, pbn_b0_8_115200 },
4884 { /* IQ Express D1 */
4885 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4886 PCI_VENDOR_ID_MAINPINE, 0x3000,
4887 0, 0, pbn_b0_1_115200 },
4888 { /* IQ Express F1 */
4889 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4890 PCI_VENDOR_ID_MAINPINE, 0x3100,
4891 0, 0, pbn_b0_1_115200 },
4892 { /* IQ Express D2 */
4893 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4894 PCI_VENDOR_ID_MAINPINE, 0x3200,
4895 0, 0, pbn_b0_2_115200 },
4896 { /* IQ Express F2 */
4897 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4898 PCI_VENDOR_ID_MAINPINE, 0x3300,
4899 0, 0, pbn_b0_2_115200 },
4900 { /* IQ Express D4 */
4901 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4902 PCI_VENDOR_ID_MAINPINE, 0x3400,
4903 0, 0, pbn_b0_4_115200 },
4904 { /* IQ Express F4 */
4905 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4906 PCI_VENDOR_ID_MAINPINE, 0x3500,
4907 0, 0, pbn_b0_4_115200 },
4908 { /* IQ Express D8 */
4909 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4910 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4911 0, 0, pbn_b0_8_115200 },
4912 { /* IQ Express F8 */
4913 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4914 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4915 0, 0, pbn_b0_8_115200 },
4916
4917
4918 /*
4919 * PA Semi PA6T-1682M on-chip UART
4920 */
4921 { PCI_VENDOR_ID_PASEMI, 0xa004,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_pasemi_1682M },
4924
4925 /*
4926 * National Instruments
4927 */
4928 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 pbn_b1_16_115200 },
4931 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933 pbn_b1_8_115200 },
4934 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936 pbn_b1_bt_4_115200 },
4937 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 pbn_b1_bt_2_115200 },
4940 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 pbn_b1_bt_4_115200 },
4943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945 pbn_b1_bt_2_115200 },
4946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948 pbn_b1_16_115200 },
4949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b1_8_115200 },
4952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954 pbn_b1_bt_4_115200 },
4955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_b1_bt_2_115200 },
4958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 pbn_b1_bt_4_115200 },
4961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_b1_bt_2_115200 },
4964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_ni8430_2 },
4967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_ni8430_2 },
4970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_ni8430_4 },
4973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_ni8430_4 },
4976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_ni8430_8 },
4979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_ni8430_8 },
4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_ni8430_16 },
4985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 pbn_ni8430_16 },
4988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_ni8430_2 },
4991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_ni8430_2 },
4994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_ni8430_4 },
4997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_ni8430_4 },
5000
5001 /*
5002 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5003 */
5004 { PCI_VENDOR_ID_ADDIDATA,
5005 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5006 PCI_ANY_ID,
5007 PCI_ANY_ID,
5008 0,
5009 0,
5010 pbn_b0_4_115200 },
5011
5012 { PCI_VENDOR_ID_ADDIDATA,
5013 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5014 PCI_ANY_ID,
5015 PCI_ANY_ID,
5016 0,
5017 0,
5018 pbn_b0_2_115200 },
5019
5020 { PCI_VENDOR_ID_ADDIDATA,
5021 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5022 PCI_ANY_ID,
5023 PCI_ANY_ID,
5024 0,
5025 0,
5026 pbn_b0_1_115200 },
5027
5028 { PCI_VENDOR_ID_AMCC,
5029 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5030 PCI_ANY_ID,
5031 PCI_ANY_ID,
5032 0,
5033 0,
5034 pbn_b1_8_115200 },
5035
5036 { PCI_VENDOR_ID_ADDIDATA,
5037 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5038 PCI_ANY_ID,
5039 PCI_ANY_ID,
5040 0,
5041 0,
5042 pbn_b0_4_115200 },
5043
5044 { PCI_VENDOR_ID_ADDIDATA,
5045 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5046 PCI_ANY_ID,
5047 PCI_ANY_ID,
5048 0,
5049 0,
5050 pbn_b0_2_115200 },
5051
5052 { PCI_VENDOR_ID_ADDIDATA,
5053 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5054 PCI_ANY_ID,
5055 PCI_ANY_ID,
5056 0,
5057 0,
5058 pbn_b0_1_115200 },
5059
5060 { PCI_VENDOR_ID_ADDIDATA,
5061 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5062 PCI_ANY_ID,
5063 PCI_ANY_ID,
5064 0,
5065 0,
5066 pbn_b0_4_115200 },
5067
5068 { PCI_VENDOR_ID_ADDIDATA,
5069 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5070 PCI_ANY_ID,
5071 PCI_ANY_ID,
5072 0,
5073 0,
5074 pbn_b0_2_115200 },
5075
5076 { PCI_VENDOR_ID_ADDIDATA,
5077 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5078 PCI_ANY_ID,
5079 PCI_ANY_ID,
5080 0,
5081 0,
5082 pbn_b0_1_115200 },
5083
5084 { PCI_VENDOR_ID_ADDIDATA,
5085 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5086 PCI_ANY_ID,
5087 PCI_ANY_ID,
5088 0,
5089 0,
5090 pbn_b0_8_115200 },
5091
5092 { PCI_VENDOR_ID_ADDIDATA,
5093 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5094 PCI_ANY_ID,
5095 PCI_ANY_ID,
5096 0,
5097 0,
5098 pbn_ADDIDATA_PCIe_4_3906250 },
5099
5100 { PCI_VENDOR_ID_ADDIDATA,
5101 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5102 PCI_ANY_ID,
5103 PCI_ANY_ID,
5104 0,
5105 0,
5106 pbn_ADDIDATA_PCIe_2_3906250 },
5107
5108 { PCI_VENDOR_ID_ADDIDATA,
5109 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5110 PCI_ANY_ID,
5111 PCI_ANY_ID,
5112 0,
5113 0,
5114 pbn_ADDIDATA_PCIe_1_3906250 },
5115
5116 { PCI_VENDOR_ID_ADDIDATA,
5117 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5118 PCI_ANY_ID,
5119 PCI_ANY_ID,
5120 0,
5121 0,
5122 pbn_ADDIDATA_PCIe_8_3906250 },
5123
5124 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5125 PCI_VENDOR_ID_IBM, 0x0299,
5126 0, 0, pbn_b0_bt_2_115200 },
5127
5128 /*
5129 * other NetMos 9835 devices are most likely handled by the
5130 * parport_serial driver, check drivers/parport/parport_serial.c
5131 * before adding them here.
5132 */
5133
5134 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5135 0xA000, 0x1000,
5136 0, 0, pbn_b0_1_115200 },
5137
5138 /* the 9901 is a rebranded 9912 */
5139 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5140 0xA000, 0x1000,
5141 0, 0, pbn_b0_1_115200 },
5142
5143 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5144 0xA000, 0x1000,
5145 0, 0, pbn_b0_1_115200 },
5146
5147 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5148 0xA000, 0x1000,
5149 0, 0, pbn_b0_1_115200 },
5150
5151 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5152 0xA000, 0x1000,
5153 0, 0, pbn_b0_1_115200 },
5154
5155 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5156 0xA000, 0x3002,
5157 0, 0, pbn_NETMOS9900_2s_115200 },
5158
5159 /*
5160 * Best Connectivity and Rosewill PCI Multi I/O cards
5161 */
5162
5163 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5164 0xA000, 0x1000,
5165 0, 0, pbn_b0_1_115200 },
5166
5167 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5168 0xA000, 0x3002,
5169 0, 0, pbn_b0_bt_2_115200 },
5170
5171 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5172 0xA000, 0x3004,
5173 0, 0, pbn_b0_bt_4_115200 },
5174 /* Intel CE4100 */
5175 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5177 pbn_ce4100_1_115200 },
5178 /* Intel BayTrail */
5179 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5180 PCI_ANY_ID, PCI_ANY_ID,
5181 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5182 pbn_byt },
5183 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5184 PCI_ANY_ID, PCI_ANY_ID,
5185 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5186 pbn_byt },
5187
5188 /*
5189 * Intel Quark x1000
5190 */
5191 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5193 pbn_qrk },
5194 /*
5195 * Cronyx Omega PCI
5196 */
5197 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5199 pbn_omegapci },
5200
5201 /*
5202 * Broadcom TruManage
5203 */
5204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 pbn_brcm_trumanage },
5207
5208 /*
5209 * AgeStar as-prs2-009
5210 */
5211 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5212 PCI_ANY_ID, PCI_ANY_ID,
5213 0, 0, pbn_b0_bt_2_115200 },
5214
5215 /*
5216 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5217 * so not listed here.
5218 */
5219 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5220 PCI_ANY_ID, PCI_ANY_ID,
5221 0, 0, pbn_b0_bt_4_115200 },
5222
5223 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5224 PCI_ANY_ID, PCI_ANY_ID,
5225 0, 0, pbn_b0_bt_2_115200 },
5226
5227 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5228 PCI_ANY_ID, PCI_ANY_ID,
5229 0, 0, pbn_b0_bt_2_115200 },
5230
5231 /*
5232 * Commtech, Inc. Fastcom adapters
5233 */
5234 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5235 PCI_ANY_ID, PCI_ANY_ID,
5236 0,
5237 0, pbn_b0_2_1152000_200 },
5238 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5239 PCI_ANY_ID, PCI_ANY_ID,
5240 0,
5241 0, pbn_b0_4_1152000_200 },
5242 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5243 PCI_ANY_ID, PCI_ANY_ID,
5244 0,
5245 0, pbn_b0_4_1152000_200 },
5246 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5247 PCI_ANY_ID, PCI_ANY_ID,
5248 0,
5249 0, pbn_b0_8_1152000_200 },
5250 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5251 PCI_ANY_ID, PCI_ANY_ID,
5252 0,
5253 0, pbn_exar_XR17V352 },
5254 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5255 PCI_ANY_ID, PCI_ANY_ID,
5256 0,
5257 0, pbn_exar_XR17V354 },
5258 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5259 PCI_ANY_ID, PCI_ANY_ID,
5260 0,
5261 0, pbn_exar_XR17V358 },
5262
5263 /* Fintek PCI serial cards */
5264 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5265 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5266 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5267
5268 /*
5269 * These entries match devices with class COMMUNICATION_SERIAL,
5270 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5271 */
5272 { PCI_ANY_ID, PCI_ANY_ID,
5273 PCI_ANY_ID, PCI_ANY_ID,
5274 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5275 0xffff00, pbn_default },
5276 { PCI_ANY_ID, PCI_ANY_ID,
5277 PCI_ANY_ID, PCI_ANY_ID,
5278 PCI_CLASS_COMMUNICATION_MODEM << 8,
5279 0xffff00, pbn_default },
5280 { PCI_ANY_ID, PCI_ANY_ID,
5281 PCI_ANY_ID, PCI_ANY_ID,
5282 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5283 0xffff00, pbn_default },
5284 { 0, }
5285 };
5286
5287 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5288 pci_channel_state_t state)
5289 {
5290 struct serial_private *priv = pci_get_drvdata(dev);
5291
5292 if (state == pci_channel_io_perm_failure)
5293 return PCI_ERS_RESULT_DISCONNECT;
5294
5295 if (priv)
5296 pciserial_suspend_ports(priv);
5297
5298 pci_disable_device(dev);
5299
5300 return PCI_ERS_RESULT_NEED_RESET;
5301 }
5302
5303 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5304 {
5305 int rc;
5306
5307 rc = pci_enable_device(dev);
5308
5309 if (rc)
5310 return PCI_ERS_RESULT_DISCONNECT;
5311
5312 pci_restore_state(dev);
5313 pci_save_state(dev);
5314
5315 return PCI_ERS_RESULT_RECOVERED;
5316 }
5317
5318 static void serial8250_io_resume(struct pci_dev *dev)
5319 {
5320 struct serial_private *priv = pci_get_drvdata(dev);
5321
5322 if (priv)
5323 pciserial_resume_ports(priv);
5324 }
5325
5326 static const struct pci_error_handlers serial8250_err_handler = {
5327 .error_detected = serial8250_io_error_detected,
5328 .slot_reset = serial8250_io_slot_reset,
5329 .resume = serial8250_io_resume,
5330 };
5331
5332 static struct pci_driver serial_pci_driver = {
5333 .name = "serial",
5334 .probe = pciserial_init_one,
5335 .remove = pciserial_remove_one,
5336 #ifdef CONFIG_PM
5337 .suspend = pciserial_suspend_one,
5338 .resume = pciserial_resume_one,
5339 #endif
5340 .id_table = serial_pci_tbl,
5341 .err_handler = &serial8250_err_handler,
5342 };
5343
5344 module_pci_driver(serial_pci_driver);
5345
5346 MODULE_LICENSE("GPL");
5347 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5348 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Michael's Linux tree.