[people/ms/u-boot.git] / arch / arc / include / asm / io.h

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARC_IO_H
#define __ASM_ARC_IO_H

#include <linux/types.h>
#include <asm/byteorder.h>

#ifdef CONFIG_ISA_ARCV2

/*
 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
 * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
 *
 * Explicit barrier provided by DMB instruction
 *  - Operand supports fine grained load/store/load+store semantics
 *  - Ensures that selected memory operation issued before it will complete
 *    before any subsequent memory operation of same type
 *  - DMB guarantees SMP as well as local barrier semantics
 *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
 *    UP: barrier(), SMP: smp_*mb == *mb)
 *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
 *    in the general case. Plus it only provides full barrier.
 */

#define mb()	asm volatile("dmb 3\n" : : : "memory")
#define rmb()	asm volatile("dmb 1\n" : : : "memory")
#define wmb()	asm volatile("dmb 2\n" : : : "memory")

#else

/*
 * ARCompact based cores (ARC700) only have SYNC instruction which is super
 * heavy weight as it flushes the pipeline as well.
 * There are no real SMP implementations of such cores.
 */

#define mb()	asm volatile("sync\n" : : : "memory")
#endif

#ifdef CONFIG_ISA_ARCV2
#define __iormb()		rmb()
#define __iowmb()		wmb()
#else
#define __iormb()		do { } while (0)
#define __iowmb()		do { } while (0)
#endif

static inline void sync(void)
{
	/* Not yet implemented */
}

static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	u8 b;

	__asm__ __volatile__("ldb%U1	%0, %1\n"
			     : "=r" (b)
			     : "m" (*(volatile u8 __force *)addr)
			     : "memory");
	return b;
}

static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	u16 s;

	__asm__ __volatile__("ldw%U1	%0, %1\n"
			     : "=r" (s)
			     : "m" (*(volatile u16 __force *)addr)
			     : "memory");
	return s;
}

static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	u32 w;

	__asm__ __volatile__("ld%U1	%0, %1\n"
			     : "=r" (w)
			     : "m" (*(volatile u32 __force *)addr)
			     : "memory");
	return w;
}

static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
{
	__asm__ __volatile__("stb%U1	%0, %1\n"
			     :
			     : "r" (b), "m" (*(volatile u8 __force *)addr)
			     : "memory");
}

static inline void __raw_writew(u16 s, volatile void __iomem *addr)
{
	__asm__ __volatile__("stw%U1	%0, %1\n"
			     :
			     : "r" (s), "m" (*(volatile u16 __force *)addr)
			     : "memory");
}

static inline void __raw_writel(u32 w, volatile void __iomem *addr)
{
	__asm__ __volatile__("st%U1	%0, %1\n"
			     :
			     : "r" (w), "m" (*(volatile u32 __force *)addr)
			     : "memory");
}

static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
{
	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
			      "sub.f	r2, r2, 1\n"
			      "bnz.d	1b\n"
			      "stb.ab	r8, [r1, 1]\n"
			      :
			      : "r" (addr), "r" (data), "r" (bytelen)
			      : "r8");
	return bytelen;
}

static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
{
	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
			      "sub.f	r2, r2, 1\n"
			      "bnz.d	1b\n"
			      "stw.ab	r8, [r1, 2]\n"
			      :
			      : "r" (addr), "r" (data), "r" (wordlen)
			      : "r8");
	return wordlen;
}

static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
{
	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
			      "sub.f	r2, r2, 1\n"
			      "bnz.d	1b\n"
			      "st.ab	r8, [r1, 4]\n"
			      :
			      : "r" (addr), "r" (data), "r" (longlen)
			      : "r8");
	return longlen;
}

static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
{
	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
			      "sub.f	r2, r2, 1\n"
			      "bnz.d	1b\n"
			      "st.di	r8, [r0, 0]\n"
			      :
			      : "r" (addr), "r" (data), "r" (bytelen)
			      : "r8");
	return bytelen;
}

static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
{
	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
			      "sub.f	r2, r2, 1\n"
			      "bnz.d	1b\n"
			      "st.ab.di	r8, [r0, 0]\n"
			      :
			      : "r" (addr), "r" (data), "r" (wordlen)
			      : "r8");
	return wordlen;
}

static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
{
	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
			      "sub.f	r2, r2, 1\n"
			      "bnz.d	1b\n"
			      "st.ab.di	r8, [r0, 0]\n"
			      :
			      : "r" (addr), "r" (data), "r" (longlen)
			      : "r8");
	return longlen;
}

/*
 * MMIO can also get buffered/optimized in micro-arch, so barriers needed
 * Based on ARM model for the typical use case
 *
 *	<ST [DMA buffer]>
 *	<writel MMIO "go" reg>
 *  or:
 *	<readl MMIO "status" reg>
 *	<LD [DMA buffer]>
 *
 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
 */
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })

#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })
#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })
#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })

/*
 * Relaxed API for drivers which can handle barrier ordering themselves
 *
 * Also these are defined to perform little endian accesses.
 * To provide the typical device register semantics of fixed endian,
 * swap the byte order for Big Endian
 *
 * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
 */
#define readb_relaxed(c)	__raw_readb(c)
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
					__raw_readw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
					__raw_readl(c)); __r; })

#define writeb_relaxed(v,c)	__raw_writeb(v,c)
#define writew_relaxed(v,c)	__raw_writew((__force u16) cpu_to_le16(v),c)
#define writel_relaxed(v,c)	__raw_writel((__force u32) cpu_to_le32(v),c)

#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))

#define out_le32(a, v)	out_arch(l, le32, a, v)
#define out_le16(a, v)	out_arch(w, le16, a, v)

#define in_le32(a)	in_arch(l, le32, a)
#define in_le16(a)	in_arch(w, le16, a)

#define out_be32(a, v)	out_arch(l, be32, a, v)
#define out_be16(a, v)	out_arch(w, be16, a, v)

#define in_be32(a)	in_arch(l, be32, a)
#define in_be16(a)	in_arch(w, be16, a)

#define out_8(a, v)	__raw_writeb(v, a)
#define in_8(a)		__raw_readb(a)

/*
 * Clear and set bits in one shot. These macros can be used to clear and
 * set multiple bits in a register using a single call. These macros can
 * also be used to set a multiple-bit bit pattern using a mask, by
 * specifying the mask in the 'clear' parameter and the new bit pattern
 * in the 'set' parameter.
 */

#define clrbits(type, addr, clear) \
	out_##type((addr), in_##type(addr) & ~(clear))

#define setbits(type, addr, set) \
	out_##type((addr), in_##type(addr) | (set))

#define clrsetbits(type, addr, clear, set) \
	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))

#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)

#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)

#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)

#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)

#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)

#include <asm-generic/io.h>

#endif	/* __ASM_ARC_IO_H */
Commit	Line	Data
288aaacf AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __ASM_ARC_IO_H
	8	#define __ASM_ARC_IO_H
	9
	10	#include <linux/types.h>
	11	#include <asm/byteorder.h>
	12
5bea2bec AB	13	#ifdef CONFIG_ISA_ARCV2
	14
	15	/*
	16	* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
	17	* due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
	18	*
	19	* Explicit barrier provided by DMB instruction
	20	* - Operand supports fine grained load/store/load+store semantics
	21	* - Ensures that selected memory operation issued before it will complete
	22	* before any subsequent memory operation of same type
	23	* - DMB guarantees SMP as well as local barrier semantics
	24	* (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
	25	* UP: barrier(), SMP: smp_mb == mb)
	26	* - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
	27	* in the general case. Plus it only provides full barrier.
	28	*/
	29
	30	#define mb() asm volatile("dmb 3\n" : : : "memory")
	31	#define rmb() asm volatile("dmb 1\n" : : : "memory")
	32	#define wmb() asm volatile("dmb 2\n" : : : "memory")
	33
	34	#else
	35
	36	/*
	37	* ARCompact based cores (ARC700) only have SYNC instruction which is super
	38	* heavy weight as it flushes the pipeline as well.
	39	* There are no real SMP implementations of such cores.
	40	*/
	41
	42	#define mb() asm volatile("sync\n" : : : "memory")
	43	#endif
	44
	45	#ifdef CONFIG_ISA_ARCV2
	46	#define __iormb() rmb()
	47	#define __iowmb() wmb()
	48	#else
	49	#define __iormb() do { } while (0)
	50	#define __iowmb() do { } while (0)
	51	#endif
	52
288aaacf AB	53	static inline void sync(void)
	54	{
	55	/* Not yet implemented */
	56	}
	57
	58	static inline u8 __raw_readb(const volatile void __iomem *addr)
	59	{
	60	u8 b;
	61
	62	__asm__ __volatile__("ldb%U1 %0, %1\n"
	63	: "=r" (b)
	64	: "m" ((volatile u8 __force )addr)
	65	: "memory");
	66	return b;
	67	}
	68
	69	static inline u16 __raw_readw(const volatile void __iomem *addr)
	70	{
	71	u16 s;
	72
	73	__asm__ __volatile__("ldw%U1 %0, %1\n"
	74	: "=r" (s)
	75	: "m" ((volatile u16 __force )addr)
	76	: "memory");
	77	return s;
	78	}
	79
	80	static inline u32 __raw_readl(const volatile void __iomem *addr)
	81	{
	82	u32 w;
	83
	84	__asm__ __volatile__("ld%U1 %0, %1\n"
	85	: "=r" (w)
	86	: "m" ((volatile u32 __force )addr)
	87	: "memory");
	88	return w;
	89	}
	90
288aaacf AB	91	static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
	92	{
	93	__asm__ __volatile__("stb%U1 %0, %1\n"
	94	:
	95	: "r" (b), "m" ((volatile u8 __force )addr)
	96	: "memory");
	97	}
	98
	99	static inline void __raw_writew(u16 s, volatile void __iomem *addr)
	100	{
	101	__asm__ __volatile__("stw%U1 %0, %1\n"
	102	:
	103	: "r" (s), "m" ((volatile u16 __force )addr)
	104	: "memory");
	105	}
	106
	107	static inline void __raw_writel(u32 w, volatile void __iomem *addr)
	108	{
	109	__asm__ __volatile__("st%U1 %0, %1\n"
	110	:
	111	: "r" (w), "m" ((volatile u32 __force )addr)
	112	: "memory");
	113	}
	114
288aaacf AB	115	static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
	116	{
	117	__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
	118	"sub.f r2, r2, 1\n"
	119	"bnz.d 1b\n"
	120	"stb.ab r8, [r1, 1]\n"
	121	:
	122	: "r" (addr), "r" (data), "r" (bytelen)
	123	: "r8");
	124	return bytelen;
	125	}
	126
	127	static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
	128	{
	129	__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
	130	"sub.f r2, r2, 1\n"
	131	"bnz.d 1b\n"
	132	"stw.ab r8, [r1, 2]\n"
	133	:
	134	: "r" (addr), "r" (data), "r" (wordlen)
	135	: "r8");
	136	return wordlen;
	137	}
	138
	139	static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
	140	{
	141	__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
	142	"sub.f r2, r2, 1\n"
	143	"bnz.d 1b\n"
	144	"st.ab r8, [r1, 4]\n"
	145	:
	146	: "r" (addr), "r" (data), "r" (longlen)
	147	: "r8");
	148	return longlen;
	149	}
	150
	151	static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
	152	{
	153	__asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
	154	"sub.f r2, r2, 1\n"
	155	"bnz.d 1b\n"
	156	"st.di r8, [r0, 0]\n"
	157	:
	158	: "r" (addr), "r" (data), "r" (bytelen)
	159	: "r8");
	160	return bytelen;
	161	}
	162
	163	static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
	164	{
	165	__asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
	166	"sub.f r2, r2, 1\n"
	167	"bnz.d 1b\n"
	168	"st.ab.di r8, [r0, 0]\n"
	169	:
	170	: "r" (addr), "r" (data), "r" (wordlen)
	171	: "r8");
	172	return wordlen;
	173	}
	174
	175	static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
	176	{
	177	__asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
	178	"sub.f r2, r2, 1\n"
179	"bnz.d 1b\n"
180	"st.ab.di r8, [r0, 0]\n"
181	:
182	: "r" (addr), "r" (data), "r" (longlen)
183	: "r8");
184	return longlen;
185	}
186
5bea2bec AB	187	/*
	188	* MMIO can also get buffered/optimized in micro-arch, so barriers needed
	189	* Based on ARM model for the typical use case
	190	*
	191	* <ST [DMA buffer]>
	192	* <writel MMIO "go" reg>
	193	* or:
	194	* <readl MMIO "status" reg>
	195	* <LD [DMA buffer]>
	196	*
	197	* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
	198	*/
	199	#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
	200	#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
	201	#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
	202
	203	#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
	204	#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
	205	#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
	206
	207	/*
	208	* Relaxed API for drivers which can handle barrier ordering themselves
	209	*
	210	* Also these are defined to perform little endian accesses.
	211	* To provide the typical device register semantics of fixed endian,
	212	* swap the byte order for Big Endian
	213	*
	214	* http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
	215	*/
	216	#define readb_relaxed(c) __raw_readb(c)
	217	#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
	218	__raw_readw(c)); __r; })
	219	#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
	220	__raw_readl(c)); __r; })
	221
	222	#define writeb_relaxed(v,c) __raw_writeb(v,c)
	223	#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
	224	#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
	225
288aaacf AB	226	#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
	227	#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
	228
	229	#define out_le32(a, v) out_arch(l, le32, a, v)
	230	#define out_le16(a, v) out_arch(w, le16, a, v)
	231
	232	#define in_le32(a) in_arch(l, le32, a)
	233	#define in_le16(a) in_arch(w, le16, a)
	234
	235	#define out_be32(a, v) out_arch(l, be32, a, v)
	236	#define out_be16(a, v) out_arch(w, be16, a, v)
	237
	238	#define in_be32(a) in_arch(l, be32, a)
	239	#define in_be16(a) in_arch(w, be16, a)
	240
	241	#define out_8(a, v) __raw_writeb(v, a)
	242	#define in_8(a) __raw_readb(a)
	243
	244	/*
	245	* Clear and set bits in one shot. These macros can be used to clear and
	246	* set multiple bits in a register using a single call. These macros can
	247	* also be used to set a multiple-bit bit pattern using a mask, by
	248	* specifying the mask in the 'clear' parameter and the new bit pattern
	249	* in the 'set' parameter.
	250	*/
	251
	252	#define clrbits(type, addr, clear) \
	253	out_##type((addr), in_##type(addr) & ~(clear))
	254
	255	#define setbits(type, addr, set) \
	256	out_##type((addr), in_##type(addr) \| (set))
	257
	258	#define clrsetbits(type, addr, clear, set) \
	259	out_##type((addr), (in_##type(addr) & ~(clear)) \| (set))
	260
	261	#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
	262	#define setbits_be32(addr, set) setbits(be32, addr, set)
	263	#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
	264
	265	#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
	266	#define setbits_le32(addr, set) setbits(le32, addr, set)
	267	#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
	268
	269	#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
	270	#define setbits_be16(addr, set) setbits(be16, addr, set)
	271	#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
	272
	273	#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
	274	#define setbits_le16(addr, set) setbits(le16, addr, set)
	275	#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
	276
	277	#define clrbits_8(addr, clear) clrbits(8, addr, clear)
	278	#define setbits_8(addr, set) setbits(8, addr, set)
	279	#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
	280
593477c6	281	#include <asm-generic/io.h>
53637c91	282
288aaacf	283	#endif /* __ASM_ARC_IO_H */