[people/ms/u-boot.git] / arch / arm / cpu / armv7 / am33xx / sys_info.c

/*
 * sys_info.c
 *
 * System information functions
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
#include <linux/compiler.h>

struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;

/**
 * get_cpu_rev(void) - extract rev info
 */
u32 get_cpu_rev(void)
{
	u32 id;
	u32 rev;

	id = readl(DEVICE_ID);
	rev = (id >> 28) & 0xff;

	return rev;
}

/**
 * get_cpu_type(void) - extract cpu info
 */
u32 get_cpu_type(void)
{
	u32 id = 0;
	u32 partnum;

	id = readl(DEVICE_ID);
	partnum = (id >> 12) & 0xffff;

	return partnum;
}

/**
 * get_device_type(): tell if GP/HS/EMU/TST
 */
u32 get_device_type(void)
{
	int mode;
	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
	return mode >>= 8;
}

/**
 * get_sysboot_value(void) - return SYS_BOOT[4:0]
 */
u32 get_sysboot_value(void)
{
	return readl(&cstat->statusreg) & SYSBOOT_MASK;
}

#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
		"1.0",
		"2.0",
		"2.1"};


static char *dev_types[] = {
		"TST",
		"EMU",
		"HS",
		"GP"};

/**
 * Print CPU information
 */
int print_cpuinfo(void)
{
	char *cpu_s, *sec_s, *rev_s;

	switch (get_cpu_type()) {
	case AM335X:
		cpu_s = "AM335X";
		break;
	case TI81XX:
		cpu_s = "TI81XX";
		break;
	default:
		cpu_s = "Unknown CPU type";
		break;
	}

	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
		rev_s = cpu_revs[get_cpu_rev()];
	else
		rev_s = "?";

	if (get_device_type() < ARRAY_SIZE(dev_types))
		sec_s = dev_types[get_device_type()];
	else
		sec_s = "?";

	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);

	return 0;
}
#endif	/* CONFIG_DISPLAY_CPUINFO */

#ifdef CONFIG_AM33XX
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
{
	int sil_rev;

	sil_rev = readl(&cdev->deviceid) >> 28;

	if (sil_rev == 1)
		/* PG 2.0, efuse may not be set. */
		return MPUPLL_M_800;
	else if (sil_rev >= 2) {
		/* Check what the efuse says our max speed is. */
		int efuse_arm_mpu_max_freq;
		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
		case AM335X_ZCZ_1000:
			return MPUPLL_M_1000;
		case AM335X_ZCZ_800:
			return MPUPLL_M_800;
		case AM335X_ZCZ_720:
			return MPUPLL_M_720;
		case AM335X_ZCZ_600:
		case AM335X_ZCE_600:
			return MPUPLL_M_600;
		case AM335X_ZCZ_300:
		case AM335X_ZCE_300:
			return MPUPLL_M_300;
		}
	}

	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
	return MPUPLL_M_720;
}

int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
	/* For PG2.1 and later, we have one set of values. */
	if (sil_rev >= 2) {
		switch (frequency) {
		case MPUPLL_M_1000:
			return TPS65910_OP_REG_SEL_1_3_2_5;
		case MPUPLL_M_800:
			return TPS65910_OP_REG_SEL_1_2_6;
		case MPUPLL_M_720:
			return TPS65910_OP_REG_SEL_1_2_0;
		case MPUPLL_M_600:
		case MPUPLL_M_300:
			return TPS65910_OP_REG_SEL_1_1_3;
		}
	}

	/* Default to PG1.0/PG2.0 values. */
	return TPS65910_OP_REG_SEL_1_1_3;
}
#endif
Commit	Line	Data
5655108a CN	1	/*
	2	* sys_info.c
	3	*
	4	* System information functions
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
5655108a CN	13	*/
	14
	15	#include <common.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/sys_proto.h>
	18	#include <asm/arch/cpu.h>
	19	#include <asm/arch/clock.h>
9721027a	20	#include <power/tps65910.h>
52d84869	21	#include <linux/compiler.h>
5655108a CN	22
	23	struct ctrl_stat cstat = (struct ctrl_stat )CTRL_BASE;
	24
	25	/**
	26	* get_cpu_rev(void) - extract rev info
	27	*/
	28	u32 get_cpu_rev(void)
	29	{
	30	u32 id;
	31	u32 rev;
	32
	33	id = readl(DEVICE_ID);
	34	rev = (id >> 28) & 0xff;
	35
	36	return rev;
	37	}
	38
	39	/**
	40	* get_cpu_type(void) - extract cpu info
	41	*/
	42	u32 get_cpu_type(void)
	43	{
	44	u32 id = 0;
	45	u32 partnum;
	46
	47	id = readl(DEVICE_ID);
	48	partnum = (id >> 12) & 0xffff;
	49
	50	return partnum;
	51	}
	52
5655108a CN	53	/**
	54	* get_device_type(): tell if GP/HS/EMU/TST
	55	*/
	56	u32 get_device_type(void)
	57	{
	58	int mode;
	59	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
	60	return mode >>= 8;
	61	}
	62
	63	/**
	64	* get_sysboot_value(void) - return SYS_BOOT[4:0]
	65	*/
	66	u32 get_sysboot_value(void)
	67	{
63a7578e	68	return readl(&cstat->statusreg) & SYSBOOT_MASK;
5655108a CN	69	}
	70
	71	#ifdef CONFIG_DISPLAY_CPUINFO
21254713 SA	72	static char *cpu_revs[] = {
	73	"1.0",
	74	"2.0",
	75	"2.1"};
	76
	77
	78	static char *dev_types[] = {
	79	"TST",
	80	"EMU",
	81	"HS",
	82	"GP"};
	83
5655108a CN	84	/**
	85	* Print CPU information
	86	*/
	87	int print_cpuinfo(void)
	88	{
21254713	89	char cpu_s, sec_s, *rev_s;
5655108a CN	90
	91	switch (get_cpu_type()) {
	92	case AM335X:
	93	cpu_s = "AM335X";
	94	break;
8b029f22 MP	95	case TI81XX:
	96	cpu_s = "TI81XX";
	97	break;
5655108a	98	default:
21254713	99	cpu_s = "Unknown CPU type";
5655108a CN	100	break;
	101	}
	102
21254713 SA	103	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
	104	rev_s = cpu_revs[get_cpu_rev()];
	105	else
	106	rev_s = "?";
	107
	108	if (get_device_type() < ARRAY_SIZE(dev_types))
	109	sec_s = dev_types[get_device_type()];
	110	else
5655108a	111	sec_s = "?";
5655108a	112
21254713	113	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
5655108a CN	114
	115	return 0;
	116	}
	117	#endif /* CONFIG_DISPLAY_CPUINFO */
9721027a TR	118
	119	#ifdef CONFIG_AM33XX
	120	int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
	121	{
	122	int sil_rev;
	123
	124	sil_rev = readl(&cdev->deviceid) >> 28;
	125
	126	if (sil_rev == 1)
	127	/* PG 2.0, efuse may not be set. */
	128	return MPUPLL_M_800;
	129	else if (sil_rev >= 2) {
	130	/* Check what the efuse says our max speed is. */
	131	int efuse_arm_mpu_max_freq;
	132	efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
	133	switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
	134	case AM335X_ZCZ_1000:
	135	return MPUPLL_M_1000;
	136	case AM335X_ZCZ_800:
	137	return MPUPLL_M_800;
	138	case AM335X_ZCZ_720:
	139	return MPUPLL_M_720;
	140	case AM335X_ZCZ_600:
	141	case AM335X_ZCE_600:
	142	return MPUPLL_M_600;
	143	case AM335X_ZCZ_300:
	144	case AM335X_ZCE_300:
	145	return MPUPLL_M_300;
	146	}
	147	}
	148
	149	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
	150	return MPUPLL_M_720;
	151	}
	152
	153	int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
	154	{
	155	/* For PG2.1 and later, we have one set of values. */
	156	if (sil_rev >= 2) {
	157	switch (frequency) {
	158	case MPUPLL_M_1000:
	159	return TPS65910_OP_REG_SEL_1_3_2_5;
	160	case MPUPLL_M_800:
	161	return TPS65910_OP_REG_SEL_1_2_6;
	162	case MPUPLL_M_720:
	163	return TPS65910_OP_REG_SEL_1_2_0;
	164	case MPUPLL_M_600:
	165	case MPUPLL_M_300:
	166	return TPS65910_OP_REG_SEL_1_1_3;
	167	}
	168	}
	169
	170	/* Default to PG1.0/PG2.0 values. */
	171	return TPS65910_OP_REG_SEL_1_1_3;
	172	}
	173	#endif